Embedded multilayer printed circuit

FIELD OF THE INVENTION

0001The present invention is generally in the field of passive electronic components that are formed from metal patterns in a layer of a printed circuit board, and in particular to combinations of passive components that can be formed within an inner layer of a printed circuit board.

BACKGROUND

0002A significant portion of the design effort for transceivers operating above 1 GHz is in the design of frequency filtering circuits, subcircuits, and filters. Low temperature co-fired cermics (LTCCs) have been used to implement these circuits due to desirable dielectric characteristics of LTCC, and vertical (between layer) capacitors have typically been used to achieve needed capacitances. However, LTCC is more expensive than organic multilayer printed circuit boards.

BRIEF DESCRIPTION OF THE DRAWINGS

0003The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:

0004<figref idref="DRAWINGS">FIG. 1</figref> shows a plan view of two patterned metal layers of a multilayer printed circuit, in accordance with some embodiments of the present invention;

0005<figref idref="DRAWINGS">FIG. 2</figref> shows an electrical schematic of a bandpass filter that includes electrical components illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, in accordance with some embodiments of the present invention;

0006<figref idref="DRAWINGS">FIGS. 3 and 4</figref> are plan views that show layers of the multilayer printed circuit, in accordance with some embodiments of the present invention;

0007<figref idref="DRAWINGS">FIG. 5</figref> is a cross sectional view of the portion of the multilayer printed circuit board illustrated in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>3</b>, and <b>4</b>, in accordance with some embodiments of the present invention;

0008<figref idref="DRAWINGS">FIG. 6</figref> is a cross sectional view of a portion of a multilayer printed circuit board, in accordance with some embodiments of the present invention;

0009<figref idref="DRAWINGS">FIGS. 7</figref>, <b>8</b> and <b>9</b>, are cross sectional views of the portion of the multilayer printed circuit board illustrated in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>3</b>, and <b>4</b>, in accordance with some embodiments of the present invention;

0010<figref idref="DRAWINGS">FIG. 10</figref> is a schematic of other embedded multilayer printed circuits, in accordance with some embodiments of the present invention;

0011<figref idref="DRAWINGS">FIG. 11</figref> is a plan view that shows layers of the multilayer printed circuits illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, in accordance with some embodiments of the present invention;

0012<figref idref="DRAWINGS">FIGS. 12 and 14</figref> each show two patterned metal layers of a multilayer printed circuit fabricated in a portion of a multi-layer printed circuit board, in accordance with some embodiments of the present invention; and

0013<figref idref="DRAWINGS">FIGS. 13 and 15</figref> show electrical schematics of filters that include electrical components illustrated in <figref idref="DRAWINGS">FIGS. 12 and 14</figref>, in accordance with some embodiments of the present invention; and

0014<figref idref="DRAWINGS">FIG. 16</figref> shows an electrical clock diagram of an electronic device, in accordance with some embodiments of the present invention.

0015Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

0016Before describing in detail the particular multilayer electronic circuit in accordance with the present invention, it should be observed that the present invention resides primarily in combinations of method steps and apparatus components related to multilayer printed circuits. Accordingly, the apparatus components and method steps have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

0017In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

0018The terms “including” and/or “having”, as used herein, are defined as comprising. The term “coupled”, as used herein with reference to electro-optical technology, is defined as connected, although not necessarily directly, and not necessarily mechanically.

0019Referring to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, a plan view in <figref idref="DRAWINGS">FIG. 1</figref> shows two patterned metal layers of a multilayer printed circuit fabricated in a portion of a multi-layer printed circuit board, and <figref idref="DRAWINGS">FIG. 2</figref> shows an electrical schematic of a bandpass filter <b>200</b> that includes electrical components illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, in accordance with some embodiments of the present invention. In terms of directions normally associated with plan views, a layer comprising (among other items), a co-planar capacitor <b>110</b> that itself comprises two multi-fingered patterns <b>115</b>, <b>120</b>, overlies a ground plane <b>105</b>, which is called herein a first ground plane. The metal pattern of the first ground plane generally covers all of the area of a layer of the multilayer printed circuit board except for features such as isolated pads. (In the plan view drawings of this document, the material that separates the metal layers is omitted from the drawings. This material is a printed circuit dielectric, such as glass filled epoxy). The capacitance of the co-planar capacitor <b>110</b> is determined largely by the separation between the edges of the two multi-fingered patterns <b>115</b>, <b>120</b>, and the total length of the separation, as well as the dielectric constant of the material in the separation, as is known in the art. The layer comprising the co-planar capacitor <b>110</b> also may comprise a first plate pattern <b>135</b> (also called a first capacitive plate) and a second plate pattern <b>140</b> (also called a second capacitive plate), each of which forms one part of two vertical capacitors. A first vertical capacitor <b>250</b> (<figref idref="DRAWINGS">FIG. 2</figref>) is essentially formed by the first plate pattern <b>135</b> and a portion of the ground plane <b>105</b> that forms an opposing plate of the first vertical capacitor <b>250</b>. A second vertical capacitor <b>260</b>, (<figref idref="DRAWINGS">FIG. 2</figref>) is essentially formed by the second plate pattern <b>140</b> and a portion of the ground plane <b>105</b> that forms an opposing plate of the second vertical capacitor <b>260</b>. The multilayer printed circuit in accordance with these embodiments may include the bandpass filter, which can be modeled by a schematic such as that shown in <figref idref="DRAWINGS">FIG. 2</figref>. Referring to both <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, the bandpass filter may further comprise two distributed inductors <b>125</b>, <b>130</b> that may be embodied in the same layer as the co-planar capacitor <b>110</b> and which may be designed to electromagnetically couple with each other over a frequency range. A desired capacitive value of the co-planar capacitor <b>110</b>, a desired inductive value, and a mutual inductance <b>211</b> of the distributed inductors <b>125</b>, <b>130</b> are typically determined during a design process. Dimensions of the co-planar capacitor are then determined to achieve those desired values using conventional modeling techniques, such as computer aided design, simulation, prototype analysis, etc. Thus, the physical dimensions and such things as the number of capacitive fingers will vary according to characteristics needed for the resulting bandpass filter, such as a resonant frequency and bandwidth. A resonant frequency (center frequency) of the bandpass filter is typically determined largely by the values of the distributed inductors <b>125</b>, <b>130</b> and the first and second vertical capacitors. A transmission zero (or null) in the bandpass filter frequency response at a rejection frequency that is other than the resonant frequency is typically determined largely by the value of the co-planar capacitor <b>110</b> and the mutual inductance <b>211</b> of the distributed inductors <b>125</b>, <b>130</b>. The layer comprising the co-planar capacitor <b>110</b> and the distributed inductors <b>125</b>, <b>130</b> is called for convenience herein the co-planar layer, even though this layer may in general include parts of vertical components and/or components used for purposes other than the circuits described herein, in a multilayer printed circuit board that contains other circuit functions. One of the distributed inductors <b>125</b> is called herein, for convenience, the first distributed inductor, and may be connected by a first terminal of the first distributed inductor <b>125</b> to a first terminal of the co-planar capacitor <b>110</b> at a node <b>111</b>. Similarly, the second distributed inductor <b>130</b> may be connected by a first terminal of the second distributed inductor <b>130</b> to a second terminal of the co-planar capacitor <b>110</b> at a node <b>112</b>. The first node <b>111</b> may be further connected to the first plate pattern <b>135</b>, and the second node <b>112</b> may be further connected to the second plate pattern <b>140</b>. Second terminals <b>145</b>, <b>150</b> of the first and second distributed inductors <b>125</b>, <b>130</b> may be connected to the first ground plane <b>105</b> by vias. The vias may be blind vias or through vias that contact one or more grounds, as will be further described with reference to <figref idref="DRAWINGS">FIGS. 7–9</figref>, below.

0020Referring to <figref idref="DRAWINGS">FIG. 3</figref>, a plan view shows layers of the multilayer printed circuit fabricated in the portion of the multiplayer printed circuit board, in accordance with some embodiments of the present invention. The layers include a layer called herein the input/output (I/O) capacitor coupling layer, having metal patterns that are outlined by solid lines in <figref idref="DRAWINGS">FIG. 3</figref>. The I/O capacitor coupling layer overlies the two layers described above with reference to <figref idref="DRAWINGS">FIG. 1</figref>, which are outlined in dotted lines. Referring also to <figref idref="DRAWINGS">FIG. 2</figref>, the schematic of the bandpass filter <b>200</b> is shown, in accordance with some embodiments of the present invention. The I/O capacitor coupling layer may comprise an opposing plate pattern <b>305</b> of a third vertical capacitor <b>270</b> (<figref idref="DRAWINGS">FIG. 2</figref>), and an opposing plate pattern <b>310</b> of a fourth vertical capacitor <b>280</b> (<figref idref="DRAWINGS">FIG. 2</figref>). The opposing plate pattern of the third vertical capacitor <b>270</b> is on a side of the first plate pattern <b>135</b> opposite the first ground plane <b>105</b>. Thus, the first plate pattern <b>135</b> is shared by the first and third vertical capacitors <b>270</b>. Likewise, the opposing plate pattern of the fourth vertical capacitor <b>280</b> is on a side of the second plate pattern <b>140</b> opposite the first ground plane <b>105</b>. Thus, the second plate pattern <b>140</b> is shared by the second and fourth vertical capacitors <b>260</b>, <b>280</b>. The third and fourth vertical capacitors <b>270</b>, <b>280</b>, are I/O capacitors that are designed to form desired input and output impedances, such as 50 ohms, at nodes <b>285</b> and <b>290</b>, with reference to ground <b>105</b>.

0021The I/O coupling capacitor layer may further comprise an isolated float plate <b>330</b>, which is a metal pattern that may be essentially co-extensive with the co-planar capacitor. The float plate <b>330</b> may be positioned in the I/O coupling capacitor layer or another layer above, below, or above and below the co-planar layer, preferably with no metal patterns existing in any layer between the co-planar layer and the layer or layers containing the float plate <b>330</b>. The float plate <b>330</b> is preferably not conductively connected to other circuits in the multilayer printed circuit board. The float plate <b>330</b> has been demonstrated to improve the depth of the transmission null of the bandpass filter at the rejection frequency by more than 10 dB, in a bandpass filter that resonates at a frequency of approximately 2.5 GHz in a design that has the float plate <b>330</b> located in the I/O coupling capacitor layer, and for which a layer over the I/O coupling capacitor layer is a second ground plane layer. The float plate <b>330</b> is described further with reference to <figref idref="DRAWINGS">FIGS. 5 and 6</figref>, below.

0022Referring to <figref idref="DRAWINGS">FIG. 4</figref>, a plan view shows layers of the multilayer printed circuit fabricated in the portion of a multiplayer printed circuit board, in accordance with some embodiments of the present invention. The layers include a layer called herein the second ground plane layer <b>415</b>, having metal patterns that are outlined by solid lines in <figref idref="DRAWINGS">FIG. 4</figref>. The second ground plane layer <b>415</b> overlies the three layers described above with reference to <figref idref="DRAWINGS">FIGS. 1 and 3</figref>, which are outlined in dotted lines. Referring to both <figref idref="DRAWINGS">FIG. 4</figref>, the second ground plane layer <b>415</b> is a layer having an area that largely comprises metal. There may be cutouts that have isolated patterns <b>405</b>, <b>410</b> to which the opposing plate patterns <b>305</b>, <b>310</b> may be connected by blind or through vias to layers or components at the second ground plane layer <b>415</b> (or to a layer or layers above the second ground plane). The isolated patterns <b>405</b>, <b>410</b>, form nodes <b>285</b>, <b>290</b> when connected to the opposing plate patterns <b>305</b>, <b>310</b>. When through vias are used, the first and second plate patterns will have a hole in them. The cutouts that include the isolated patterns <b>405</b>, <b>410</b> may be of a size that is co-extensive with the opposing plate patterns <b>305</b>, <b>310</b>, to improve the performance of the bandpass filter. Nodes <b>285</b>, <b>290</b> (<figref idref="DRAWINGS">FIG. 2</figref>) may be used to couple a radio frequency signal into and out of the bandpass filter <b>200</b>. The second ground plane layer <b>415</b> may have some other cutouts for other functions.

0023In some embodiments, the values of the distributed inductors <b>125</b>, <b>130</b> are approximately the same, the values of the first and second capacitors <b>250</b>, <b>260</b> are approximately the same, and the values of the third and fourth capacitors <b>270</b>, <b>280</b> are approximately the same; that is, the bandpass filter is a symmetrical bandpass filter.

0024Referring to <figref idref="DRAWINGS">FIG. 5</figref>, a cross sectional view of the portion of the multilayer printed circuit board illustrated in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>3</b>, and <b>4</b> is shown, in accordance with some embodiments of the present invention. This view is shown without interlayer connections, and illustrates the float plate <b>330</b> located “above” the co-planar capacitor <b>110</b>.

0025Referring to <figref idref="DRAWINGS">FIG. 6</figref>, a cross sectional view of a portion of a multilayer printed circuit board is shown, in accordance with some embodiments of the present invention. This view is shown without interlayer connections. In these embodiments, the layer that includes the opposing plate pattern <b>310</b> does not include the float plate <b>330</b>, but rather the float plate <b>330</b> is instead located between the co-planar capacitor <b>110</b> and the first ground plane <b>105</b>. In yet another embodiment (not shown in the figures), two float plates are used, one “above” and one “below” the co-planar capacitor.

0026Referring to <figref idref="DRAWINGS">FIGS. 7</figref>, <b>8</b> and <b>9</b>, three cross sectional views of the portion of the multilayer printed circuit board illustrated in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>3</b>, and <b>4</b> are shown, in accordance with some embodiments of the present invention. The views illustrate three methods of connecting the second capacitive plates <b>305</b>, <b>310</b> of the vertical capacitors <b>270</b>, <b>280</b> to the signal nodes <b>285</b>, <b>290</b>, which are at pads <b>405</b>,<b>410</b>, and connecting second terminals <b>145</b>, <b>150</b> of the first and second distributed inductors <b>125</b>, <b>130</b> to one of the first and second ground planes <b>105</b>, <b>415</b>. Because the views in <figref idref="DRAWINGS">FIGS. 7–9</figref> are cross sections, only the connections of the second capacitive plate <b>310</b> and second terminal <b>150</b> are visible. In <figref idref="DRAWINGS">FIG. 7</figref>, blind vias <b>705</b>, <b>710</b> are used for these connections. In <figref idref="DRAWINGS">FIGS. 8 and 9</figref>, through vias <b>805</b>, <b>810</b>, <b>905</b>, <b>910</b> are used. In <figref idref="DRAWINGS">FIG. 8</figref> through vias are used (via <b>805</b> is visible in <figref idref="DRAWINGS">FIG. 8</figref>) that connect the second terminals <b>145</b>, <b>150</b> of the distributed inductors <b>125</b>, <b>130</b> to both ground planes <b>105</b>, <b>415</b>. In <figref idref="DRAWINGS">FIG. 9</figref>, through vias are used (via <b>905</b> is visible in <figref idref="DRAWINGS">FIG. 9</figref>) that connect the second terminals <b>145</b>, <b>150</b> of the distributed inductors <b>125</b>, <b>130</b> to the second ground plane <b>415</b>, but terminate in isolated pads (isolated pad <b>915</b> is visible in <figref idref="DRAWINGS">FIG. 9</figref>) that are not connected to the first ground plane <b>105</b>. The second capacitive plates <b>305</b>, <b>310</b> are connected by through vias to isolated pads in the layers that include the first and second ground planes <b>105</b>, <b>415</b> in both <figref idref="DRAWINGS">FIGS. 8 and 9</figref> (through vias <b>810</b>, <b>910</b> are visible in <figref idref="DRAWINGS">FIGS. 8 and 9</figref>). The connection technique illustrated in <figref idref="DRAWINGS">FIG. 8</figref> is less expensive to fabricate than those in <figref idref="DRAWINGS">FIGS. 7 and 9</figref>, but has reduced electrical performance compared to those in those illustrated in <figref idref="DRAWINGS">FIGS. 7 and 9</figref>.

0027Referring to <figref idref="DRAWINGS">FIG. 10</figref>, a schematic of other embedded multilayer printed circuits <b>1000</b> is shown, in accordance with some embodiments of the present invention. While an essentially symmetrical bandpass filter has been described above with reference to <figref idref="DRAWINGS">FIGS. 1–4</figref>, the present invention can provide benefits for asymmetric filters or other reactive circuits. As can be observed in <figref idref="DRAWINGS">FIG. 10</figref>, these embedded multiplayer printed circuits <b>1000</b> comprise the first distributed inductor <b>125</b>, the co-planar capacitor <b>110</b>, and the first vertical capacitor <b>250</b> described above with reference to <figref idref="DRAWINGS">FIGS. 1–4</figref>, but do not include the second distributed inductor <b>130</b> nor the third vertical capacitor <b>260</b>. In <figref idref="DRAWINGS">FIG. 10</figref>, the first distributed inductor <b>125</b> is connected to the first ground plane <b>105</b>, the co-planar capacitor <b>110</b> is coupled to a signal node <b>1010</b>, and a reactance <b>1015</b> is coupled to the signal node <b>285</b>. Although both the third vertical capacitor <b>270</b> and an inductor <b>1005</b> are shown in <figref idref="DRAWINGS">FIG. 10</figref>, it will be appreciated that the present invention comprises any embedded reactance coupled between the nodes <b>111</b> and. The reactance <b>1015</b> may be used to couple a signal between node <b>285</b> and node <b>1010</b>. When the inductor <b>1005</b> is included, it may be a single layer distributed type inductor or an embedded multi-layer type inductor, as are known in the art.

0028Referring to <figref idref="DRAWINGS">FIG. 11</figref>, a plan view shows layers of the multilayer printed circuits <b>1000</b> fabricated in the portion of a multiplayer printed circuit board, in accordance with some embodiments of the present invention. The layers illustrated include the co-planar layer and the layer of the first ground plane <b>105</b>, each having metal patterns that are outlined by solid lines in <figref idref="DRAWINGS">FIG. 11</figref>. The plan view illustrates a description of a basic form of the embedded multilayer printed circuits <b>1000</b>, which comprises the first ground plane <b>105</b>, the co-planar capacitor <b>110</b>, the first distributed inductor <b>125</b>, the first capacitive plate <b>135</b>, and the first node <b>111</b>. The first node is formed from a connection of a first terminal of the co-planar capacitor <b>110</b>, a first terminal of the first distributed inductor <b>125</b>, and the first capacitive plate <b>135</b>. The first capacitive plate <b>135</b> is a capacitive plate of a vertical capacitor that may be the vertical capacitor <b>250</b> or the vertical capacitor <b>270</b>, or it can be a capacitive plate for both, as illustrated with reference to <figref idref="DRAWINGS">FIGS. 1–4</figref>.

0029In this basic embodiment, one of a second terminal <b>1105</b> of the co-planar capacitor <b>110</b> and a second terminal <b>145</b> of the first distributed inductor <b>125</b> nay be connected to the first ground plane <b>105</b>. The first node <b>111</b> of the embedded multilayer printed circuit may be coupled to one or more other layers of the multilayer printed circuit board by a first reactance <b>1015</b>.

0030When the second terminal <b>145</b> of the first distributed inductor <b>125</b> is connected to the first ground plane <b>105</b> (as shown in <figref idref="DRAWINGS">FIG. 10</figref>), the second terminal <b>1105</b> of the co-planar capacitor <b>110</b> may be coupled to node <b>1010</b>, which is a signal node. When the second terminal <b>1105</b> of the co-planar capacitor <b>110</b> is connected to the first ground plane <b>105</b> (which is not shown in a figure), the second terminal <b>145</b> of the distributed inductor <b>125</b> may be coupled to node <b>1010</b>, which is again a signal node. In this configuration, the capacitance <b>250</b> will be formed between the first node <b>111</b> and the first ground plane <b>105</b>. When this capacitance is undesirable, the metal in the area co-extensive with the first capacitive plate <b>135</b> on the first ground plane <b>105</b> may be removed, essentially eliminating capacitance <b>250</b>.

0031These embodiments, like the ones described with reference to <figref idref="DRAWINGS">FIGS. 1–9</figref>, provide a very inexpensive and effective filter circuit for use in embedded printed circuits.

0032The metal plating of the layers that includes the co-planar capacitor <b>110</b>, the first ground plane <b>105</b>, the layer that includes the second capacitive plates <b>305</b>, <b>310</b> of the vertical capacitors <b>270</b>, <b>280</b>, the float plate <b>330</b>, and the second ground plane layer <b>415</b> may be any conductive metal typically used for multi-layer printed circuit board fabrication, such as copper, gold, silver, nickel, or any alloy thereof. The present invention has been demonstrated to work well using conventional organic multilayer printed circuit board material, such as the well known FR-4 type, but could be used with other materials such as low temperature co-fired ceramics. The co-planar capacitor <b>110</b>, when embodied in an organic multilayer printed circuit board, may have a value that ranges from about 0.1 pF to about 2.0 pF, and the distributed inductors may have values that range from about 0.1 nH to about 5 nH. The first, second, third, and fourth vertical capacitors, <b>250</b>, <b>260</b>, <b>270</b>, <b>280</b> may have values that range from about 0.1 pF to about 2.0 pF when the printed circuit dielectric between their plates is FR-4 and the printed circuit nominal dielectric layer thickness between their plates ranges from about 100 to about 250 micrometers.

0033Referring to <figref idref="DRAWINGS">FIGS. 12–15</figref>, plan views in <figref idref="DRAWINGS">FIGS. 12 and 14</figref> each show two patterned metal layers of a multilayer printed circuit fabricated in a portion of a multi-layer printed circuit board, and <figref idref="DRAWINGS">FIGS. 13 and 15</figref> show electrical schematics of filters <b>1300</b>, <b>1500</b> that include electrical components illustrated in <figref idref="DRAWINGS">FIGS. 12 and 14</figref>, in accordance with some embodiments of the present invention. The filters <b>1300</b>, <b>1500</b> described with reference to <figref idref="DRAWINGS">FIGS. 12 and 13</figref> are similar in many respects to the filters described with reference to <figref idref="DRAWINGS">FIGS. 13 and 15</figref>, so they common aspects are first described, together. As in <figref idref="DRAWINGS">FIG. 1</figref>, a co-planar capacitor <b>1210</b>, <b>1410</b> that itself comprises two multi-fingered patterns, overlies a ground plane layer <b>1205</b>, <b>1405</b>, which is called herein a first ground plane layer. The co-planar capacitor <b>1210</b>, <b>1410</b>, a distributed inductor <b>1215</b>, <b>1415</b>, and a first capacitive plate <b>1220</b>, <b>1420</b> are embedded within an inner layer of the multilayer printed circuit board. The first capacitive plate <b>1220</b>, <b>1420</b> is a plate of a vertical capacitor <b>1305</b>, <b>1505</b>. A first node <b>1225</b>, <b>1425</b> is formed by a connection of a first terminal of the distributed inductor <b>1215</b>, <b>1415</b> and a first terminal of the co-planar capacitor <b>1210</b>, <b>1410</b>. In the embodiments described with reference to <figref idref="DRAWINGS">FIGS. 12 and 13</figref>, a second terminal of the first distributed inductor <b>1215</b> is connected to the first ground plane <b>1205</b>. The second terminal of the co-planar capacitor <b>1210</b> is coupled to one or more other layers of the multilayer printed circuit board by a reactance <b>1315</b> that includes the vertical capacitor <b>1305</b>. In the embodiments described with reference to <figref idref="DRAWINGS">FIGS. 14 and 15</figref>, a second terminal of the co-planar capacitor <b>1410</b> is connected to the first ground plane <b>1405</b>. The second terminal of the first distributed inductor <b>1415</b> is coupled to one or more other layers of the multilayer printed circuit board by a reactance <b>1515</b> that includes the vertical capacitor <b>1505</b>. The filters <b>1300</b>, <b>1500</b> may further comprise one or two float plates, which may be fabricated relative to the co-planar capacitor <b>1210</b>, <b>1410</b> in the same manner as described with reference to <figref idref="DRAWINGS">FIGS. 1–9</figref> for the float plate <b>330</b> relative to co-planar capacitor <b>110</b>. The first capacitive plate <b>1220</b>, <b>1420</b> may form a vertical capacitor with a second capacitive plate fabricated in a layer between the layer that includes the co-planar capacitor <b>1210</b>, <b>1410</b> and a second ground plane layer, in the same manner as the vertical capacitor <b>270</b> described with reference to <figref idref="DRAWINGS">FIGS. 1–9</figref>. The second plate may be coupled to an input/output signal node <b>1320</b>, <b>1520</b>. In some embodiments, he first capacitive plate <b>1220</b>, <b>1420</b> may also form a second vertical capacitance with a co-extensive area of the first ground plane <b>1205</b>, <b>1405</b>. In the embodiments shown in <figref idref="DRAWINGS">FIGS. 12–15</figref>, the metal in the co-extensive area of the first ground plane <b>1205</b>, <b>1405</b> is removed so that essentially no capacitance exists between the first capacitive plate <b>1220</b>, <b>1420</b> and the first ground plane <b>1205</b>, <b>1405</b>. The electrical components described herein have the same range of values as those described for the corresponding components described with reference to <figref idref="DRAWINGS">FIGS. 1–9</figref>.

0034It will be appreciated that the present invention can be beneficially included in complicated systems that include, for example, a wireless telephone, an essentially complete optical or radio frequency receiver, transmitter, or transceiver, and can be included in any of a very wide variety of optoelectronic assemblies (i.e., those including either electronic or photonic circuits, or both), including consumer products such as portable music players and automobiles; military products such as communication units and communication control systems; and commercial equipment ranging from extremely complicated computers to robots to simple pieces of test equipment and “throwaway” wireless nodes for ad hoc systems, just to name a few types and classes of optoelectronic equipment.

0035Referring to <figref idref="DRAWINGS">FIG. 16</figref>, an electrical clock diagram shows an electronic device <b>1600</b>, in accordance with some embodiments of the present invention. The electronic device <b>1600</b> in this example is a personal communication device <b>1600</b> which may be a cellular telephone or a personal digital assistant that includes a cellular telephone, and which is but one example of the systems and equipment described above. The electronic device <b>1600</b> comprises an antenna <b>1605</b> that may intercept and radiate radio signals, and which may be as simple as a conductive runner printed on a multilayer printed circuit board. Intercepted radio signals are coupled to a receiver <b>1610</b> which receives the intercepted signal and couples demodulated information to a control section <b>1615</b>. The control section comprises one or more processors and user interface devices (displays, buttons, speakers, etc.) and presents and manipulations information, and controls the formation of messages that may be encoded, modulated and transmitted by a transmitter <b>1620</b> that is also coupled to the antenna <b>1605</b>. The intercepted signal is coupled to a down conversion circuit <b>1635</b>. A local oscillator (LO) signal is generated by a local oscillator <b>1630</b> and the LO signal is filtered by filter <b>1630</b>, which is a filter formed in a multilayer printed circuit board in accordance with the present invention, and may be a symmetric filter as described above with reference to <figref idref="DRAWINGS">FIGS. 1–9</figref>. The filtered LO signal is coupled to the down conversion circuit <b>1635</b>, which generates an intermediate frequency signal that is coupled to a demodulator <b>1640</b>. The demodulator <b>1640</b> generates a demodulated signal that is coupled to the control section, which extracts information from the demodulated signal. Filters according to the present invention may be used in other places within the receiver <b>1610</b>, such as for intermediate frequency and front end filtering, decoupling filters, etc., as well as for filters in the transmitter <b>1620</b> and control section <b>1615</b>. It will be appreciated that as a result of the space efficiency of the embedded circuits of the present invention, it may be practical to incorporate all the radio frequency filters for the electronic device <b>1600</b> in one printed circuit board, using a common co-planar layer. Although the present invention has been described in this paragraph as being used in an electronic device that manipulates radio frequency signals and has an antenna, it will be appreciated that the present invention may be useful in any electronic device having signals with radio frequencies, whether desired or undesired. For example, the present invention may be used to filter out undesirable RF frequencies from a signal at a signal node in equipment that has no antenna, such as a computer.

0036In the foregoing specification, the invention and its benefits and advantages have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims.

0037It is further understood that the use of relational terms, if any, such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.