Interconnected high speed electron tunneling devices

RELATED APPLICATION

0001This application is a CIP of U.S. Ser. No. 09/860,988 now U.S. Pat. No. 6,534,784, and is a CIP of Ser. No. 09/860,972 filed May 21, 2001 now U.S. Pat. No. 6,563,185 and is CIP of Ser. No. 10/103,054, filed Mar. 20, 2002, abandoned and CIP of Ser. No. 10/140,535 filed May 6, 2002, all of which application are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

0002The present invention relates generally to optoelectronic devices and, more particularly, to interconnection of optoelectronic devices including electron tunneling devices.

0003Increased amounts and speed of data transfer in communication and computing systems pose a challenge to the current state of device technology. Large quantities of information must be transferred quickly across distances ranging from very short distances, from between chips as well as between boards containing chips, to longer distances between racks of devices, very short reach (VSR)/optical Ethernet and beyond. Even with the development of high-speed communications switches and routers, the data must be taken in and out of such high-speed devices at compatibly high rates in order for the entire system to function efficiently.

0004Radio frequency (RF) inter-chip and intra-chip connections have been developed as a possible way of transferring data within and between chips. However, RF interconnects use large antennae and/or waveguides on or connected to chips, thus requiring valuable on-chip and device “real estate.” Also, RF interconnects are limited in data transfer speed due to the use of radio frequencies.

0005Other researchers have suggested the use of optical signals as an alternative to electrical signals in providing inter- and intra-chip connections.¹For instance, parallel fiber-optic interconnects which are edge-connected to semiconductor devices have been developed for use within systems with a large number of electronic components (e.g., computers).²Although optical interconnect technology promises the possibility of higher rate data transfer than electrical interconnects, optical interconnect technology, as heretofore suggested, is still cost prohibitive in comparison. There is potentially a huge market for high speed interconnect arrangements because all desktop computers and local area networks would benefit from the use of high speed interconnects between components on chips, between chips, etc.

0006As will be seen hereinafter, the present invention provides a significant improvement over the prior art as discussed above by virtue of its ability to provide the increased performance while, at the same time, having significant advantages in its manufacturability. This assertion is true for electromagnetic devices generally, which take advantage of the present invention, as well as data communication and computing devices in particular.

BRIEF SUMMARY OF THE INVENTION

0007As will be described in more detail hereinafter, there is disclosed herein an integrated circuit chip including a formation of integrated layers. The integrated layers are configured so as to define at least one integrated electronic component as well as an integrated electron tunneling device. The integrated electron tunneling device includes first and second non-insulating layers spaced apart from one another such that a given voltage can be provided across the first and second non-insulating layers. The integrated electron tunneling device further includes an arrangement disposed between the first and second non-insulating layers and configured to serve as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The integrated electron tunneling device further includes an antenna structure connected with the first and second non-insulating layers, and the integrated electron tunneling device is electrically connected with the integrated electronic component.

0008In one aspect of the invention, a method for fabricating an integrated circuit chip is disclosed. The method includes forming a plurality of integrated layers, where the forming step includes the steps of defining at least one integrated electronic component and defining an integrated electron tunneling device. The integrated electron tunneling device includes first and second non-insulating layers spaced apart from one another such that a given voltage can be provided across the first and second non-insulating layers. The integrated electron tunneling device further includes an arrangement disposed between the first and second non-insulating layers and configured to serve as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The integrated electron tunneling device further includes an antenna structure connected with the first and second non-insulating layers. The method further includes electrically connecting the integrated electron tunneling device with the integrated electronic component.

0009In another aspect of the invention, an integrated circuit chip includes a formation of integrated layers, which integrated layers are configured so as to define at least one integrated electronic component. The integrated circuit chip also includes an electron tunneling device including first and second non-insulating layers spaced apart from one another such that a given voltage can be provided across the first and second non-insulating layers. The electron tunneling device further includes an arrangement disposed between the first and second non-insulating layers and configured to serve as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The electron tunneling device further includes an antenna structure connected with the first and second non-insulating layers, and the electron tunneling device is formed on top of and separately from the formation of integrated layers without interference with an intended function of the integrated electronic component and its spatial location while being electrically connected with the integrated electronic component.

0010In still another aspect of the invention, an integrated circuit chip includes a formation of integrated layers, which formation of integrated layers is configured to define at least one integrated electronic component and is further configured to define an integrated optoelectronic device having an antenna. The antenna is configured to receive an optical signal. The integrated optoelectronic device is electrically connected with the integrated electronic component.

0011In yet another aspect of the invention, an integrated circuit chip includes a formation of integrated layers defining at least one integrated electronic component. The integrated circuit chip also includes an optoelectronic device having an antenna, which antenna is configured to receive an optical signal incident thereon. The optoelectronic device is formed on top of and separately from the formation of integrated layers without interference with an intended function of the integrated electronic component and its spatial location while being electrically connected with the integrated electronic component. In an alternative embodiment, the optoelectronic device is configured to provide an optical signal while the antenna is configured instead to transmit the optical signal.

0012In a further aspect of the invention, an integrated circuit chip includes at least one substrate and circuitry formed on the substrate, which circuitry includes at least first and second integrated electronic components. The integrated circuit chip also includes a first optoelectronic device for providing an optical signal. The first optoelectronic device includes a first antenna, which first antenna is configured to emit the optical signal, and the first optoelectronic device is supported on the substrate while being electrically connected with the first integrated electronic component. The integrated circuit chip further includes a second optoelectronic device. The second optoelectronic device includes a second antenna, which second antenna is configured to receive the optical signal from the first antenna such that first and second optoelectronic devices are in optical communication with one another, while the second optoelectronic device is also supported on the substrate and is electrically connected with the second integrated electronic component.

0013In a still further aspect of the invention, an integrated circuit assembly includes first and second substrates. First circuitry, including at least a first integrated electronic component, is formed on the first substrate, and second circuitry, including at least a second integrated electronic component, is formed on the second substrate. The integrated circuit assembly also includes a first optoelectronic device for providing an optical signal. The first optoelectronic device includes a first antenna, which is configured to emit the optical signal, and is supported on the first substrate while being electrically connected with the first integrated electronic component. The integrated circuit assembly further includes a second optoelectronic device including a second antenna. The second optoelectronic device is supported on the second substrate and is electrically connected with the second integrated electronic component. The second antenna is configured to receive the optical signal from the first antenna such that the first and second optoelectronic devices are in optical communication with one another.

0014In another aspect of the invention, an assembly includes an optoelectronic system, in which an optical signal is present and which includes at least one optoelectronic device configured to act on the optical signal. The assembly also includes an electron tunneling device also configured to act on the optical signal. The electron tunneling device includes first and second non-insulating layers, which are spaced apart from one another such that a given voltage can be provided across the first and second non-insulating layers, and an arrangement disposed between the first and second non-insulating layers, which arrangement is configured serve as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes a first amorphous layer configured such that using only the first amorphous layer in the arrangement would result in a given value of nonlinearity in the transport of electrons, with respect to the given voltage. The arrangement also includes a different, second layer disposed directly adjacent to and configured to cooperate with the first amorphous layer such that the transport of electrons includes, at least in part, transport by means of tunneling through the first amorphous layer and the second layer, and such that the nonlinearity, with respect to the given voltage, is increased over and above the given value of nonlinearity by the inclusion of the second layer without the necessity for any additional layer. The assembly further includes an optical configuration cooperating with the electron tunneling device and with the optoelectronic device such that the optical signal is transmitted therebetween.

0015In a still another aspect of the invention, a device includes a waveguide, which waveguide in turn includes an optical input port. The optical input port is configured for receiving an input light. The waveguide also includes an optical output port and is configured for directing the input light from the optical input port toward the optical output port. The device also includes an optoelectronic assembly, which includes an electron tunneling device. The electron tunneling device includes first and second non-insulating layers, which are spaced apart from one another such that a given voltage can be provided thereacross, and an arrangement disposed between the first and second non-insulating layers and configured to serve as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The optoelectronic assembly also includes a coupling arrangement configured to cooperate with the electron tunneling device and the waveguide for coupling at least a portion of the input light from the waveguide into the electron tunneling device.

0016In yet another aspect of the invention, an arrangement includes an optical waveguide with an optical input port, which optical input port is configured for receiving an input light, and an optical output port. The optical waveguide is configured for directing the input light from the optical input port toward the optical output port. The arrangement further includes an optoelectronic assembly with a surface plasmon device, which is configured to act on an input signal. The surface plasmon device includes a device input port, which is configured to receive the input signal, a device output port and a structure including a tunneling junction connected with the device input port and the device output port. The tunneling junction is configured in a way (i) which provides electrons in a particular energy state within the structure, (ii) which produces surface plasmons in response to the input signal, (iii) which causes the structure to act as a surface plasmon waveguide for directing at least a portion of the surface plasmons along a predetermined path toward the device output port such that the surface plasmons so directed interact with the electrons in a particular way, and (iv) which produces at the device output port an output signal resulting from the particular interaction between the electrons and the surface plasmons. The optoelectronic assembly further includes a coupling arrangement, which is configured to cooperate with the surface plasmon device and the optical waveguide for coupling at least a portion of the input light from the waveguide into the surface plasmon device as the input signal.

0017In a further aspect of the invention, an integrated circuit chip includes a substrate and a formation of integrated layers supported on the substrate, which integrated layers are configured so as to define at least one integrated electronic component. The integrated circuit chip also includes an optical waveguide, which is also supported on the substrate and includes an optical input port configured for receiving an input light including a clock signal encoded thereon. The integrated circuit chip further includes at least one optoelectronic assembly electrically connected with the integrated electronic component and including an electron tunneling device. The electron tunneling device includes first and second non-insulating layers spaced apart from one another such that a given voltage can be provided thereacross. The electron tunneling device also includes an arrangement disposed between the first and second non-insulating layers and configured to serve as a transport of electrons between and to the first and second non-insulting layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The optoelectronic assembly also includes a coupling arrangement configured to cooperate with the electron tunneling device and the optical waveguide for coupling at least a portion of the input light including the clock signal from the waveguide into the electron tunneling device. The electron tunneling device is configured to (i) receive the portion of the input light, (ii) produce an electric signal and (iii) transmit the electric signal toward the integrated electronic component electrically connected with the optoelectronic assembly for use by the integrated electronic component.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

0018The present invention may be understood by reference to the following detailed description taken in conjunction with the drawings briefly described below. It is noted that, for purposes of illustrative clarity, certain elements in the drawings may not be drawn to scale.

0019<figref idref="DRAWINGS">FIG. 1A</figref> is a diagrammatic illustration, in perspective view, of an interconnected electron tunneling device of the present invention, shown here to illustrate an embodiment including a planar waveguide on a chip as the interconnection.

0020<figref idref="DRAWINGS">FIGS. 1B and 1C</figref> are diagrammatic illustrations, in cross-section, showing details of electron tunneling devices suitable for use in the interconnected electron tunneling device of the present invention.

0021<figref idref="DRAWINGS">FIG. 1D</figref> is a diagrammatic illustration, in perspective view, of an alternative embodiment of an interconnected electron tunneling device of the present invention, shown here to illustrate the use of a double antenna electron tunneling device.

0022<figref idref="DRAWINGS">FIGS. 1E and 1F</figref> are diagrammatic illustrations, in perspective view, of additional embodiments of an interconnected electron tunneling device of the present invention, shown here to illustrate the use of surface plasmon devices.

0023<figref idref="DRAWINGS">FIGS. 2A and 2B</figref> are diagrammatic illustrations, in cross-section, of embodiments of an edge-fed, optical clock distribution scheme of the present invention.

0024<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are diagrammatic illustrations of a top-fed, optical clock distribution scheme of the present invention.

0025<figref idref="DRAWINGS">FIGS. 4A–4D</figref> are diagrammatic illustrations of another interconnected electron tunneling device of the present invention, shown here to illustrate embodiments including optical fiber as the interconnection between devices on separate chips.

0026<figref idref="DRAWINGS">FIG. 5</figref> is a diagrammatic illustration of still another interconnected electron tunneling device in accordance with the present invention, shown here to illustrate the use of free-space optical interconnection between electron tunneling devices on separate chips.

0027<figref idref="DRAWINGS">FIGS. 6A–6E</figref> are diagrammatic illustrations of a waveguide-coupled device of the present invention, shown here to illustrate various embodiments of the coupling of electron tunneling devices with a waveguide, as used in the aforementioned interconnected electron tunneling devices.

0028<figref idref="DRAWINGS">FIGS. 7A–7D</figref> are diagrammatic illustrations of an alternative waveguide-coupled device of the present invention and applications.

0029<figref idref="DRAWINGS">FIGS. 8A–8C</figref> are diagrammatic illustrations, in perspective view, of examples of packaging options and applications for the waveguide-coupled device of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

0030The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.

0031As described in the Background section, there is a growing need for high speed interconnection between devices over short distances, such as between racks, boards, chips, as well as between components located on a single chip. These interconnection arrangements must be capable of high speed transmission of data and should be low cost. The interconnection arrangements and systems need to be competitive and compatible with current state-of-the-art electrical interconnects in terms of cost, speed, power, distance, requirement for signal processing and allowance of plug-n-play. For low cost, high speed and highest level of integration, the interconnect components may be integrated directly onto silicon integrated circuitry. The interconnect should ideally be compatible with standardized systems and interfaces provided by existing suppliers. In order to accommodate the current state of the technology, the interconnect should be compatible with multi-mode fibers and be time division multiplexing (TDM) or coarse wavelength division multiplexing (CWDM) compatible. Alternatively, depending on the application in which the interconnect is to be used, single-mode fibers might also be used. Polarization-insensitivity is desirable in order to reduce signal loss. VCSEL devices are the mainstay light sources in the current art; therefore the interconnection arrangement should be compatible with VCSEL devices. Currently-available VCSEL devices operate at 850 nm and, potentially, at 1300 and 1550 nm wavelengths. Furthermore, current VCSELs operate at 2.5 Gbps, while 10 Gbps and, in the future, 80 Gbps devices may be available. The interconnect should also be temperature-insensitive in order for the interconnect to be incorporated onto silicon integrated circuitry. For example, as will be described in detail hereinafter, the interconnect may be top-side coupled onto CMOS-integrated components.

0032Recent progress in tunneling junction technology by the assignee of the present application has greatly increased the flexibility in fabrication and design of electron tunneling devices based on metal-insulator(s)-metal structures, thus allowing the fabrication of high speed electron tunneling devices (See, copending U.S. patent applications Ser. No. 09/860,988 (hereinafter, '988 application), Ser. No. 09/860,972 (hereinafter, '972 application), Ser. No. 10/103,054 (hereinafter, '054 application), Ser. No. 10,140,545 (hereinafter '535 application) and Ser. No. 10/265,935 (hereinafter '935 application), all of which applications are incorporated herein by reference).

0033The electron tunneling devices as disclosed in the aforementioned '988, '972, '054, '535 and '935 applications are particularly suited for integration onto existing chips because combination of metal and insulating layers forming each electron tunneling device may be deposited directly on the chips without the need for additional semiconductor processing steps. That is, the electron tunneling devices of the aforementioned applications may be formed monolithically on existing semiconductor devices without high temperature or crystalline growth procedures. Additionally, unlike hybrid integration assemblies, in which separately-fabricated devices are surface mounted or flip-chip bonded onto existing chips, the electron tunneling devices developed by the assignee of the present invention may be formed directly on the chips themselves. Furthermore, as described in detail in the '988, '972, '054, '535 and '935 applications, the electron tunneling devices as disclosed in these applications are capable of operating at high speeds, thus enabling these devices to function in optical regimes and at high data rates. Still further, the electron tunneling devices may be integrated into the circuitry itself (i.e., formed during the fabrication procedure of the circuitry as a part of the circuitry components), if so desired. Therefore, by incorporating the electron tunneling devices of the aforementioned '988, '972, '054, '535 and '935 applications as part of an optical interconnect assembly, a high speed interconnection solution for use between components on chips, between chips and so on may be attained.

0034Moreover, the electron tunneling devices developed by the assignee of the present invention may be fabricated directly adjacent to a waveguide and be configured to cooperate with the waveguide so as to absorb an evanescent field portion of a lightwave traveling through the waveguide. For example, the electron tunneling device may include an antenna designed to couple light of a particular wavelength (e.g., optical wavelengths) out of the waveguide and into a tunneling junction region of the electron tunneling device. Alternatively, the electron tunneling devices may be fabricated within a waveguide so as to absorb the propagating field portion of the a lightwave traveling through the waveguide. As will be discussed in detail at an appropriate point in the text below, the concept of combining the electron tunneling devices with a waveguide is significant in that it allows the coupling of light energy into and out of the waveguide as well as the directing of light energy to electronic devices as electrical energy. This concept may be utilized to provide high speed interconnections between optical and electronic components, as will be discussed in detail immediately hereinafter.

0035Turning now to the drawings, wherein like components are indicated by like reference numbers throughout the various figures, attention is immediately directed to <figref idref="DRAWINGS">FIG. 1A</figref>, which illustrates an approach to the interconnection of two electron tunneling structures on a chip in accordance with the present invention. <figref idref="DRAWINGS">FIG. 1A</figref> is a diagrammatic illustration, in perspective view, of an interconnect assembly <b>10</b>. Interconnect assembly <b>10</b> includes a chip <b>11</b>, which includes circuitry <b>12</b> formed on top of a substrate <b>13</b>. A waveguide region <b>14</b> is defined on chip <b>11</b>, and a first electron tunneling device <b>16</b> and a second electron tunneling device <b>18</b> are formed on top of waveguide region <b>14</b>. First and second electron tunneling devices <b>16</b> and <b>18</b> may be, for instance, high speed electron tunneling devices and variants as disclosed in the aforementioned '988, '972, '054, '535 and '935 applications, which high speed electron tunneling devices are formed of thin film layers of non-insulating and insulating materials. Waveguide region <b>14</b> may be formed, for example, of polymers, dielectric materials such as glass, fused silica and silicon-on-insulator, photonic crystals, lithium niobate, organic materials and photonic bandgap materials. In the embodiment illustrated in <figref idref="DRAWINGS">FIG. 1A</figref>, first and second electron tunneling devices <b>16</b> and <b>18</b> include antenna arms <b>20</b>A–<b>20</b>B and <b>22</b>A–<b>22</b>B, respectively, defining bowtie antennae. Other antenna designs such as, but not limited to, Vivaldi, Vee, and those designs described in the '935 application, may also be used. First and second electron tunneling devices <b>16</b> and <b>18</b> may be connected to integrated electronic components in the existing electronic circuitry (represented by squares <b>24</b> and <b>26</b>) on the chip by, for example, pairs of metal lines <b>28</b>A and <b>28</b>B and <b>30</b>A and <b>30</b>B, respectively. The integrated electronic components <b>24</b> and <b>26</b> may be, for example, driver transistors or amplifier transistors.

0036Still referring to <figref idref="DRAWINGS">FIG. 1A</figref>, a number of different configurations of the interconnect assembly of the present invention are contemplated. As an example, first electron tunneling device <b>16</b> may be a modulator, as described in the '972 or '054 or '535 application, and second electron tunneling device <b>18</b> may be a detector, as described in the aforementioned '988, '972, '054, '535 and '935 applications. In this case, an external continuous wave (CW) light source (not shown) may feed a CW light, indicated by an arrow <b>40</b>, into waveguide <b>14</b>, then the circuitry on the chip may cause first electron tunneling device <b>16</b> (modulator) to modulate the CW light in the waveguide so as to produce a modulated light, indicated by a wavy arrow <b>42</b>. The manner in which the first electron tunneling device may act as a modulator is described in detail in the aforementioned '972 and '054 applications. Waveguide region <b>14</b> may be further configured to act as an interconnect between the first electron tunneling device <b>16</b> and second electron tunneling device <b>18</b> such that second electron tunneling device <b>18</b> (detector) detects modulated light <b>42</b> to generate an electrical signal, indicated by an arrow <b>44</b>. Electrical signal <b>44</b> can then be directed back into the existing circuitry on the chip or be coupled out to integrated electronic component <b>26</b>. Alternatively, second electron tunneling device <b>18</b> may be configured to detect only a portion of modulated light <b>42</b> such that a slightly attenuated, output light, indicated by a wavy arrow <b>46</b>, is further directed through waveguide <b>14</b> to be coupled out of the chip. As yet another alternative, second electron tunneling device <b>18</b> may be replaced by a conventional detector which is not based on electron tunneling such as, for example, a semiconductor-based detector.

0037Continuing to refer to <figref idref="DRAWINGS">FIG. 1A</figref>, interconnect assembly <b>10</b> is advantageous in that an optical means of interconnecting various devices on-chip as well as off-chip is provided without additional complications in the chip circuitry itself. As described in detail in the aforementioned '988, '972 and '056 applications, the electron tunneling devices disclosed by the assignee of the present invention may be formed of readily depositable materials, such as metals and insulators. As a result, first electron tunneling device <b>16</b> may be formed directly on top of a chip, as shown in <figref idref="DRAWINGS">FIG. 1A</figref>, without interference with the intended function of the integrated electronic components in the chip circuitry or displacing existing circuitry on the chip, using relatively simple, deposition and lithography, rather than semiconductor crystalline growth techniques. Also, rather than relying upon a direct, hardwire electrical connection from the portion of the chip circuitry near component <b>24</b> to that near component <b>26</b>, data may be transferred between the two regions on the chip by the optical interconnection between the first electron tunneling device and the second electron tunneling device. Furthermore, modulated light <b>46</b>, which contains information as encoded onto first electron tunneling device <b>16</b> acting as a modulator, may be directed onto a site away from chip <b>11</b> such that the encoded information is transmitted off-chip at optical speeds.

0038Referring now to <figref idref="DRAWINGS">FIGS. 1B and 1C</figref>, possible configurations for the electron tunneling devices shown in <figref idref="DRAWINGS">FIG. 1A</figref> are described. <figref idref="DRAWINGS">FIG. 1B</figref> illustrates a cross-sectional view of one embodiment of an electron tunneling device suitable for use in the interconnect assembly of the present invention as shown in <figref idref="DRAWINGS">FIG. 1A</figref>. This electron tunneling device is similar in design to those shown in the aforementioned '988 and '972 applications. An electron tunneling device <b>16</b>B includes a first non-insulating layer <b>50</b>, which forms one of the antenna arms (e.g., antenna arm <b>20</b> in <figref idref="DRAWINGS">FIG. 1A</figref>) of the first electron tunneling device. In the embodiment shown in <figref idref="DRAWINGS">FIG. 1B</figref>, first non-insulating layer <b>50</b> is deposited on top of waveguide <b>14</b>, which in turn has been formed on top of circuitry <b>12</b>. First non-insulating layer <b>50</b> may be, for example, a metal, semi-metal, semiconductor or superconductor. A first layer <b>52</b> is deposited also on top of waveguide <b>14</b> such that first layer <b>52</b> partially overlaps first non-insulating layer <b>50</b>. First layer <b>52</b> may be, for example, an amorphous or crystalline insulating material. The portion which overlaps with first non-insulating layer <b>50</b> may be, for instance, an oxide of the first non-insulating layer or a separately deposited, amorphous insulating layer. A second non-insulating layer <b>54</b> is deposited on top of first layer <b>52</b> such that a tunneling junction region <b>60</b>B is formed by the overlapping portions of first non-insulating layer <b>50</b>, first layer <b>52</b> and second non-insulating layer <b>54</b>. Second insulating layer <b>54</b> defines the other of the antenna arms (e.g., antenna arm <b>21</b> in <figref idref="DRAWINGS">FIG. 1A</figref>) of first electron tunneling device <b>16</b>B, and may be formed of, for example, a metal, semi-metal, semiconductor or superconductor. In a tunneling junction region (indicated by a dashed box <b>60</b>B), first and second non-insulating layers are spaced apart from one another such that a voltage (not shown) may be applied thereacross. First layer <b>52</b> is further configured to cooperate with the materials forming the first and second non-insulating layers such that electrons are allowed to travel therethrough by means of tunneling depending on the voltage placed across the first and second non-insulating layers. That is, the thickness of first layer <b>52</b> as well as the material from which the first layer is formed are selected such that first electron tunneling device exhibits the desired electron tunneling characteristics. For instance, the first non-insulating layer may be 40 nm of nickel, and the second non-insulating material may also be 40 nm of nickel, both deposited by sputtering. The first layer may consist of, for example, a layer of nickel oxide, 4 nm thick, formed by thermal oxidation.

0039Referring now to <figref idref="DRAWINGS">FIG. 1C</figref>, a variation of the electron tunneling device of <figref idref="DRAWINGS">FIG. 1B</figref> is illustrated. An electron tunneling device <b>16</b>C is based on the structures described in the co-assigned '988 application mentioned earlier. Like electron tunneling device <b>16</b>B shown in <figref idref="DRAWINGS">FIG. 1B</figref>, electron tunneling device <b>16</b>C includes first and second non-insulating layers <b>50</b> and <b>54</b>, respectively, with a first layer <b>52</b> disposed therebetween. Additionally, a tunneling region <b>60</b>C of electron tunneling device <b>16</b>C includes a second layer <b>62</b>. As described in detail in the '988 application, the addition of second layer <b>62</b> serves to increase the nonlinearity in the current-voltage characteristics of the electron tunneling device. Moreover, the inclusion of the second layer allows the possibility of resonant tunneling as the electron transport mechanism through the electron tunneling device. Second layer <b>62</b> may be, for example, an amorphous or crystalline insulating layer. For instance, the first non-insulating layer may be 40 nm of niobium, and the second non-insulating material may be 40 nm of tantalum, both deposited by sputtering. The first layer may consist of amorphous niobium oxide, 1.5 nm thick, on top of which is deposited amorphous tantalum oxide, also 1.5 nm thick, both deposited by atomic layer deposition.

0040It should be noted that, the modifications shown in <figref idref="DRAWINGS">FIGS. 1B and 1C</figref> may be applied to one or both of first and second electron tunneling devices <b>16</b> and <b>18</b> of <figref idref="DRAWINGS">FIG. 1A</figref>. Additional modifications, such as the addition of three or more adjacent insulating layers or a combination of metal and insulating layers between the first and second non-insulating layers as shown in <figref idref="DRAWINGS">FIGS. 1B and 1C</figref>, are also contemplated and discussed in the aforementioned co-assigned U.S. patent applications.

0041Additional variations on the interconnect assembly of the present invention are shown in <figref idref="DRAWINGS">FIGS. 1D–1F</figref>. <figref idref="DRAWINGS">FIG. 1D</figref> is similar to the interconnect assembly shown in <figref idref="DRAWINGS">FIG. 1A</figref>, but first electron tunneling device <b>16</b> has been replaced with an electron tunneling modulator <b>72</b>. Electron tunneling modulator <b>72</b> includes first and second pairs of antenna arms. First pair of antenna arms <b>20</b> and <b>21</b> is essentially the same as that shown in, for example, <figref idref="DRAWINGS">FIG. 1A</figref>, and is designed to receive input light <b>40</b> and modulate it so as to produce modulated light <b>42</b>. As discussed in reference to <figref idref="DRAWINGS">FIGS. 1B and 1C</figref>, antenna arms <b>20</b> and <b>21</b> may be configured to overlap such that a tunneling junction region (not shown) is formed. Electrical signals <b>71</b>A and/or <b>71</b>B may be provided via wires <b>28</b>A and <b>28</b>B, respectively, as a modulation signal so as to vary the electron transport characteristics of the tunneling junction region, thus yielding the modulated light in accordance with the modulation signal. Electron tunneling device <b>72</b> further includes a second pair of antenna arms <b>73</b> and <b>74</b>, which may be configured to receive an optical modulation input <b>75</b>. Optical modulation input <b>75</b> acts as an optical modulation signal to vary the electron transport characteristics of the tunneling junction region, thus, again, such that electron tunneling device <b>72</b> yields modulated light <b>42</b> in accordance with the optical modulation signal. Details of such a crossed-bowtie antenna modulator are disclosed in the aforementioned '972 application. Additionally, second pair of antenna arms <b>73</b> and <b>74</b> may be connected with an integrated electronic component <b>78</b> in circuitry <b>12</b> via wires <b>76</b>A and <b>76</b>B.

0042<figref idref="DRAWINGS">FIG. 1E</figref> shows yet another alternative embodiment of an interconnect assembly <b>80</b>, this time using a surface plasmon device of the '054 application as a detector device, in place of second electron tunneling device <b>18</b> in interconnect assembly <b>10</b> of <figref idref="DRAWINGS">FIG. 1A</figref>. A surface plasmon device <b>82</b> includes a pair of antenna arms <b>84</b> and <b>86</b>, which are configured to receive modulated light <b>42</b> from first electron tunneling device <b>16</b>. Antenna arms <b>84</b> and <b>86</b> direct the modulated light so received into a surface plasmon waveguide region <b>88</b> as surface plasmon waves. Surface plasmon waveguide region <b>88</b> then provides electrical signal <b>44</b> in accordance with the received modulated light.

0043As yet another alternative, an interconnect assembly <b>90</b>, as shown in <figref idref="DRAWINGS">FIG. 1F</figref>, may include a surface plasmon device <b>92</b> acting as an emitter, such as described in the '054 application. For instance, in interconnect assembly <b>90</b> as shown in <figref idref="DRAWINGS">FIG. 1F</figref>, surface plasmon device <b>92</b> receives an electrical signal <b>93</b> from integrated electrical component <b>28</b>, which is a part of the chip circuitry. The received electrical signal generates surface plasmon waves (not shown) in a surface plasmon waveguide region <b>94</b>. A pair of antenna arms <b>96</b> and <b>98</b> of surface plasmon device <b>92</b> acts as an emitter antenna to emit the generated surface plasmon waves as an output light <b>46</b>.

0044<figref idref="DRAWINGS">FIGS. 1A–1F</figref> illustrate interconnect assemblies in which light coupling from the waveguide into and out of electron tunneling devices and surface plasmon devices is performed using antennae. It should be noted that other light coupling schemes are also possible. For example, as disclosed in the '054 application, surface plasmon evanescent couplers and grating couplers may also be used in the interconnect assembly of the present invention.

0045An application of the interconnect assembly of the present invention is shown in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref>. <figref idref="DRAWINGS">FIG. 2A</figref> illustrates a cross-sectional view of an integrated circuit chip <b>100</b>A including an optical clock distribution configuration. Integrated circuit chip <b>100</b>A includes circuitry <b>12</b> disposed on substrate <b>13</b> as discussed earlier. Integrated circuit chip <b>100</b>A also includes a tunneling device layer <b>102</b> based on an insulator <b>104</b> with a waveguide layer <b>110</b> disposed thereon. Tunneling device layer <b>102</b> includes two or more electron tunneling devices <b>116</b>, which are connected to circuitry <b>12</b> through, for example, vias <b>118</b>. Each one of the electron tunneling devices may be configured as a detector as described, for example, in the '988, '972 and '054 applications. In the integrated circuit chip shown in <figref idref="DRAWINGS">FIG. 2A</figref>, an optical signal <b>120</b>, carrying a clock signal shown as a waveform <b>122</b>, is edge-coupled into waveguide layer <b>110</b>. Optical signal <b>120</b> may have a sufficiently long wavelength (e.g., 1550 nm) such that the optical signal is not absorbed by, for example, a silicon substrate or silicon components in the circuitry but only by the electron tunneling devices. As optical signal <b>120</b> is guided through waveguide layer <b>110</b>, each one of electron tunneling devices <b>116</b> detects a portion of the optical signal, converts the optical signal into an electrical signal (not shown) and communicates the electrical signal to circuitry <b>12</b>. In this way, the clock signal encoded onto optical signal <b>120</b> is very quickly distributed across the entire chip with minimal clock phase skew.

0046A variation of the optical distribution configuration of <figref idref="DRAWINGS">FIG. 2A</figref> is illustrated in <figref idref="DRAWINGS">FIG. 2B</figref>, showing a cross-sectional view of an integrated circuit chip <b>100</b>B. Like integrated circuit chip <b>100</b>A of <figref idref="DRAWINGS">FIG. 2A</figref>, integrated circuit chip <b>100</b>B includes substrate <b>13</b> and waveguide <b>110</b>, but the electronic circuitry and electron tunneling device layers have been combined. A combination layer <b>130</b> includes circuitry <b>132</b> with electron tunneling devices <b>116</b> monolithically integrated thereon such that electron tunneling devices <b>116</b>B are disposed alongside electrical components (not individually shown) in the circuitry layer. Electron tunneling devices <b>116</b>B may be formed during the same fabrication steps as those used to form circuitry <b>132</b> or may be formed separately following the fabrication of circuitry <b>132</b>.

0047The optical clock distribution configurations shown in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref> present an improvement over the conventional, electrical clock distribution schemes, in which clock signals are provided as electrical signal through electrical lines that take up chip real estate, produce significant clock skew and produce electromagnetic pickup. The optical clock distribution configurations of <figref idref="DRAWINGS">FIGS. 2A and 2B</figref> avoid these problems inherent to electrical clock signals by taking advantage of the fact that the interconnect assembly of the present invention, including the electron tunneling devices and waveguide, may be added on top of an existing integrated circuitry chip. It is often a difficult task in chip layout design to ensure that the clock signal reaches all parts of the chip simultaneously without degradation and while maintaining a constant phase across the chip. Since optical signals in waveguides travel much more quickly and more directly than electrical signals in electrical lines, an optical clock signal may be distributed over the chip much more quickly than an electrical clock signal. The optical clock signal broadcast into the waveguide layer may be picked up by the electron tunneling devices through, for instance, vias where needed.

0048Various modifications to the optical clock distribution configuration of <figref idref="DRAWINGS">FIGS. 2A and 2B</figref> are contemplated. One such example is shown in <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>. Like previously discussed embodiments of the present invention, an integrated circuit chip <b>150</b> shown in <figref idref="DRAWINGS">FIG. 3A</figref> includes circuitry <b>12</b> on top of a substrate <b>13</b>. Like integrated circuit chip <b>100</b>A of <figref idref="DRAWINGS">FIG. 2A</figref>, integrated circuit chip <b>150</b> also includes tunneling device layer <b>102</b>. Integrated circuit chip <b>150</b> further includes a modified waveguide layer <b>152</b>, which is designed to receive optical signal <b>120</b> carrying a clock signal <b>122</b> when the optical signal is incident normally on modified waveguide layer <b>152</b>. A grating coupler <b>154</b>, which is integrated into modified waveguide layer <b>152</b>, couples optical signal <b>120</b> into modified waveguide layer <b>152</b> such that optical signal <b>120</b> is radially broadcast throughout modified waveguide layer <b>152</b> as an optical clock signal (represented by arrows <b>156</b>).

0049Details of modified waveguide layer <b>152</b> as well as tunneling device layer <b>102</b> are more readily apparent in <figref idref="DRAWINGS">FIG. 3B</figref>, which illustrates integrated circuit chip <b>150</b> in cross section. As shown in <figref idref="DRAWINGS">FIG. 3B</figref>, modified waveguide layer <b>152</b> includes grating coupler <b>154</b>, which is designed to receive optical signal <b>120</b> and to direct the optical signal so received throughout modified waveguide layer <b>152</b> as optical clock signal <b>156</b>. Optical clock signal <b>156</b> is picked up by electron tunneling devices <b>116</b> at desired points across the integrated circuit chip. Electron tunneling devices <b>116</b> then communicate the optical clock signal to electrical components in the circuitry wherever needed.

0050As in the case of integrated circuit chip <b>100</b>A of <figref idref="DRAWINGS">FIG. 2A</figref>, the optical clock distribution scheme used in integrated circuit chip <b>150</b> is advantageous because the optical clock signal is distributed over the entire chip within picoseconds without being hampered by electrical delays. As a result, the clock signal received at the chip circuitry does not experience significant delay that may cause phase differences in different part of the chip. Also, since the optical clock signal is transmitted optically and is converted to an electrical signal by an electron tunneling device only where needed, electromagnetic pickup is reduced in comparison to conventional, electrical clock distribution through electrical transmission lines.

0051Various modifications to the optical clock distribution schemes shown in <figref idref="DRAWINGS">FIGS. 2A–2B</figref> and <b>3</b>A–<b>3</b>B are possible. For example, the optical clock signal may be broadcast over the integrated circuit chip through free-space and subsequently picked up by the electron tunneling devices at various locations on the integrated circuit chip. Such a free-space transmission scheme may include, for instance, additional optical components such as lenses, holographic optical elements and filters. Other modifications may be apparent to those skilled in the art while remaining within the spirit of the present invention.

0052Turning now to <figref idref="DRAWINGS">FIGS. 4A and 4B</figref>, still other alternative embodiments of an interconnect assembly of the present invention using optical fibers are illustrated. <figref idref="DRAWINGS">FIG. 4A</figref> shows an interconnect assembly <b>200</b>. Interconnect assembly <b>200</b> includes first and second chips <b>202</b> and <b>204</b>, respectively. First chip <b>202</b> includes a substrate <b>206</b>, on which circuitry <b>208</b> is formed. Similarly, second chip <b>204</b> includes a substrate <b>210</b> with circuitry <b>212</b> formed thereon. The first and second chips further include a first electron tunneling device <b>216</b> and a second electron tunneling device <b>218</b>, respectively, formed thereon. In the embodiment as shown in <figref idref="DRAWINGS">FIG. 4A</figref>, first electron tunneling device <b>216</b> is configured to act as an emitter, such as those disclosed in the patent applications referenced above. First electron tunneling device <b>216</b> emits a light beam <b>220</b>, which is focused by a first lens arrangement <b>222</b> onto an optical fiber input <b>224</b>. Light beam <b>220</b> is then transmitted through an optical fiber <b>226</b> in the direction indicated by an arrow <b>228</b> toward an optical fiber output <b>230</b>. At optical fiber output <b>230</b>, light beam <b>220</b> is then focused by a second lens arrangement <b>232</b> onto second electron tunneling device <b>218</b>. For instance, second electron tunneling device <b>218</b> may be an electron tunneling device, as disclosed in the '988, '972, '054, '535 and '935 applications, which is configured to act as a detector so as to receive light beam <b>220</b>. Alternatively, a conventional detector, such as a silicon-based detector, may be used as second electron tunneling device <b>218</b>. In this way, an optical interconnection is established between devices on first and second chips <b>202</b> and <b>204</b>, thereby allowing transfer of data therebetween. Such an optical interconnection is advantageous over, for example, electrical interconnections in terms of speed, signal loss, propagation distance and drive power.

0053<figref idref="DRAWINGS">FIG. 4B</figref> shows an alternative embodiment of an interconnect assembly using optical fiber. An interconnect assembly <b>250</b> is similar to interconnect assembly <b>200</b> of <figref idref="DRAWINGS">FIG. 4A</figref> with a number of key differences. Interconnect assembly <b>250</b> includes a laser <b>252</b> configured to direct an input laser light (not shown) through an input optical fiber <b>254</b> in the direction indicated by an arrow <b>256</b>. Input optical fiber <b>254</b> directs the input laser light into an optical circulator <b>258</b>, which then directs the input laser light through a fiber segment <b>260</b> toward first electron tunneling device <b>216</b>. In the embodiment shown in <figref idref="DRAWINGS">FIG. 4B</figref>, first electron tunneling device <b>216</b> is configured to act as a reflective modulator, which receives and modulates the input laser light. As a result, a light beam <b>262</b> as shown in <figref idref="DRAWINGS">FIG. 4B</figref> includes both the input laser light and a modulated light (not shown) as reflected from first electron tunneling device <b>216</b> such that fiber segment <b>260</b> contains light traveling into and out of circulator <b>258</b>, as indicated by a double-headed arrow <b>263</b>. Circulator <b>258</b> is configured such that any light entering the circulator from input optical fiber <b>254</b> is directed into fiber segment <b>260</b> while light entering the circulator from fiber segment <b>260</b> is directed toward optical fiber <b>226</b> in direction <b>228</b>. In this way, modulated light from first electron tunneling device <b>216</b> is directed through optical fiber <b>226</b> and detected at second electron tunneling device <b>218</b>. It is noted that multi-mode optical circulators are not commercially available at the current state of technology. Therefore, input optical fiber <b>254</b> and fiber segment <b>260</b> shown in <figref idref="DRAWINGS">FIG. 4B</figref> would be required to be single mode fibers if single mode circulators are used. However, it is anticipated that future development of a multi-mode optical circulator would enable the interconnect scheme of <figref idref="DRAWINGS">FIG. 4B</figref> to be compatible with multi-mode optical signal transmission, therefore the use of single mode optical fiber as well as the use of multi-mode optical fiber in the configuration shown in <figref idref="DRAWINGS">FIG. 4B</figref> are considered to be within the spirit of the present invention. Alternatively, the optical circulator may be replaced by an optical coupler, albeit with loss of optical power into fiber <b>226</b>.

0054Still referring to <figref idref="DRAWINGS">FIG. 4B</figref>, first electron tunneling device <b>216</b> may be configured to receive a modulation signal from on-chip circuitry <b>208</b>. Consequently, data from circuitry <b>208</b> may be encoded onto the modulated light produced at first electron tunneling device <b>216</b> and optically transmitted at high speeds to devices on chip <b>204</b> by way of second electron tunneling device <b>218</b>. Also, second electron tunneling device <b>218</b> may be configured with a second optical circulator such that light reflected by second electron tunneling device <b>218</b> may be passed down a chain or around a token ring.

0055Alternative optical interconnect configurations using optical fiber are shown in <figref idref="DRAWINGS">FIGS. 4C and 4D</figref>. As shown in <figref idref="DRAWINGS">FIG. 4C</figref>, an interconnect assembly <b>270</b> includes first and second chips <b>202</b> and <b>204</b>, respectively. In addition, interconnect assembly <b>270</b> includes first and second waveguides <b>272</b> and <b>274</b>, which are connected with first and second electron tunneling devices <b>216</b> and <b>218</b>, respectively. First and second waveguides <b>272</b> and <b>274</b> couple light into or out of the electron tunneling devices such that light from the electron tunneling devices may be fed into optical fiber <b>226</b> and vice versa. For instance, if first electron tunneling device <b>216</b> is configured as an emitter (as described, for example, in the '972 or 'the '054 application), light emitted by first electron tunneling device <b>216</b> is coupled through first waveguide <b>272</b> and into one end of optical fiber <b>226</b>. The light then travels through optical fiber <b>226</b> and, at an opposing end of the optical fiber, is coupled through second waveguide <b>274</b> and into second electron tunneling device <b>218</b>, which receives the transmitted light. Optical fiber <b>226</b> may be, for example, butt-coupled to first and second waveguides <b>272</b> and <b>274</b>, which are disposed on top of circuitry <b>208</b> and <b>212</b>, respectively, as shown in FIG. <b>4</b>C. Instead, the waveguides may be embedded in the chip circuitry, as shown in <figref idref="DRAWINGS">FIG. 4D</figref> as first and second waveguides <b>282</b> and <b>284</b>. Additionally, alignment aids, such as first and second v-grooves <b>286</b> and <b>288</b>, may be included in the chips to assist in the alignment of the optical fiber with respect to the waveguides.

0056Yet another alternative embodiment of an interconnect assembly is shown in <figref idref="DRAWINGS">FIG. 5</figref>. <figref idref="DRAWINGS">FIG. 5</figref> illustrates an interconnect assembly <b>300</b> in a free space optical interconnect scheme. Interconnect assembly <b>300</b> includes a first chip <b>310</b>, which includes a first substrate <b>312</b> and first circuitry <b>314</b>. A first plurality of electron tunneling devices <b>316</b><i>a</i>–<b>316</b><i>e </i>are disposed on first circuitry <b>314</b>. Interconnect assembly <b>300</b> also includes a complementary, second chip <b>320</b>, which includes a second substrate <b>322</b>, second circuitry <b>324</b> and a second plurality of electron tunneling devices <b>326</b><i>a</i>–<b>326</b><i>e </i>formed thereon. In the embodiment shown in <figref idref="DRAWINGS">FIG. 5</figref>, first chip <b>310</b> and second chip <b>320</b> are positioned such that first plurality of electron tunneling devices <b>316</b><i>a</i>–<b>316</b><i>e </i>on chip <b>310</b> are spaced apart from and in opposing relationship with second plurality of electron tunneling devices <b>326</b><i>a</i>–<b>326</b><i>e </i>on chip <b>322</b>. For instance, first plurality of electron tunneling devices <b>316</b><i>a–e </i>are configured to each emit a light beam of at least a given frequency, indicated by arrows <b>328</b> and second plurality of electron tunneling devices <b>326</b><i>a</i>–<b>326</b><i>e </i>are configured to detect light of at least the given frequency. Interconnect assembly <b>300</b> further includes a lens arrangement <b>330</b>, which is configured to direct light from each of first plurality of electron tunneling devices <b>316</b><i>a</i>–<b>316</b><i>e </i>to a corresponding one of second plurality of electron tunneling devices <b>326</b><i>a</i>–<b>326</b><i>e</i>. For instance, as shown in <figref idref="DRAWINGS">FIG. 5</figref>, lens <b>330</b> is designed such that light beam <b>328</b> emitted by electron tunneling device <b>316</b><i>b </i>on chip <b>310</b> is directed to electron tunneling device <b>326</b><i>b </i>on chip <b>320</b>. Moreover, one or more additional optical components, as represented by a component <b>332</b>, may also be included to perform additional optical operations. For example, component <b>332</b> may be another lens, filter, holographic optical element, reflector, grating, transmissive spatial light modulator, etc. In this way, data may be transferred optically from chip <b>310</b> to chip <b>320</b> through a free space optical interconnect scheme.

0057Various modifications to the free space, interconnect assembly of <figref idref="DRAWINGS">FIG. 5</figref>. Optical components, such as mirrors and beamsplitters, may be added to enable a non-parallel configuration of the chips. Also, lens arrangement <b>330</b> may be configured to cooperate with the electron tunneling devices on chips <b>310</b> and <b>320</b> such that operation of the interconnect assembly in the reverse direction is possible. That is, it is possible to configure the second plurality of electron tunneling devices on chip <b>320</b> to act as emitters and configure the first plurality of electron tunneling devices on chip <b>310</b> to act as detectors so as to enable the transfer of data from chip <b>320</b> to chip <b>310</b>. Also, component <b>332</b> may be configured as, for instance, a waveguide including a grating or evanescent coupler such that at least portions of light beams <b>328</b> and <b>328</b>′ may be transferred out of interconnect assembly <b>300</b>. In this case, an additional light beam (not shown) may also be inserted into the interconnect assembly at component <b>332</b> configured as a waveguide. Furthermore, the free space interconnect assembly of <figref idref="DRAWINGS">FIG. 5</figref> may be combined, for instance, with the optical clock distribution schemes illustrated in <figref idref="DRAWINGS">FIGS. 2</figref>, <b>3</b>A and <b>3</b>B such that, rather than having an optical clock signal be indiscriminately broadcast over the entire chip, the optical clock signal may be selectively imaged onto specific electron tunneling devices on the chip.

0058As described above, the interconnect assembly of the present invention, including electron tunneling devices, is advantageous due to the high speed and integrability with silicon devices (such as chips). The interconnect assembly of the present invention allows high speed interconnection between components on a chip, between chips, between boards and racks, etc., by taking advantage of high speeds possible in the optical regime. It should be noted that an important benefit of the approach of the present invention involving the use of electron tunneling devices in optical interconnect arrangements is the fact that the present invention takes advantage of the ability of the electron tunneling devices to detect, modulate or emit light directly into or out of a waveguide or optical fiber. That is, the electron tunneling device technology developed by the assignee of the present invention allows efficient coupling and conversion between optical and electrical signals in a compact configuration which is compatible with existing integrated circuit chip technology. This feature is in contrast to conventional silicon devices with waveguides, in which light traveling through the waveguide must be redirected away from the waveguide and into the silicon in order to be detected or otherwise acted upon.

0059It is notable that the electron tunneling devices, for example as shown in <figref idref="DRAWINGS">FIGS. 1A–1F</figref>, <b>2</b>A–<b>2</b>B and <b>3</b>A–<b>3</b>B, may be fabricated directly adjacent to a waveguide to allow fast, guided transmission of optical signals from one electron tunneling device to another. Furthermore, the electron tunneling devices may be used to couple light energy into and out of the waveguide as well as to direct light energy to electronic devices as electrical energy. Further details of such waveguide-coupled assemblies are discussed in further detail immediately hereinafter.

0060Turning now to <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, a waveguide-coupled assembly <b>400</b> fabricated in accordance with the present invention is illustrated. Waveguide-coupled assembly <b>400</b> includes a substrate <b>402</b>, which supports a first insulating layer <b>404</b>. For example, substrate <b>402</b> may be formed of silicon, while insulating layer <b>404</b> is formed of silicon dioxide. Waveguide-coupled assembly <b>400</b> further includes an optical waveguide layer <b>406</b> and a second insulating layer <b>408</b>. Optical waveguide layer <b>406</b> and second insulating layer <b>408</b> cooperate to define a raised, rib waveguide section <b>410</b>. Rib waveguide section <b>410</b> includes an optical input end <b>412</b>, which directs input light incident thereon (indicated by an arrow <b>414</b>) into the rib waveguide section. Waveguide-coupled assembly <b>400</b> further includes at least one electron tunneling device <b>416</b>, which is formed on top of rib waveguide section <b>410</b>. Electron tunneling device <b>416</b> is designed to receive a portion of input light <b>414</b>, modulate the received portion of the input light, and produce a modulated, output light (indicated by an arrow <b>418</b>), which output light <b>418</b> is directed toward an optical output end <b>420</b>. For instance, bowtie antenna arms <b>422</b> and <b>424</b> of electron tunneling device <b>416</b> may be formed in a particular shape and size so as to pick up a portion of the input light of a given wavelength. Different antenna designs may also be used to optimize coupling to particular waveguide modes, such as transverse-magnetic and transverse-electric modes. Alternatively, other coupling arrangements, such as grating couplers, may be used in place of an antenna in electron tunneling device <b>416</b>. Also, a coupling arrangement and an electron tunneling component may be formed at physically separate locations while still being connected with each other such that an optical or electrical signal may be communicated therebetween. Electron tunneling device <b>416</b> may be a modulator fabricated in accordance with the disclosure in the aforementioned '988, '972, '054, '535 and '935 applications. As a possible variation, waveguide-coupled assembly <b>400</b> of <figref idref="DRAWINGS">FIG. 6A</figref> is shown to include a linear array of four electron tunneling devices <b>416</b> to provide additional interaction with an evanescent light field portion of the input light so as to provide output light <b>418</b> having a desired degree of modulation. More or fewer electron tunneling devices may be used in a linear or two-dimensional array such that the resulting waveguide-coupled assembly provides a particular function. That is, by using more than one electron tunneling devices in the waveguide-coupled assembly, the interaction length between the input light and the electron tunneling devices may be effectively increased. Coupling between the antenna and waveguide may also be controlled by varying the spacing or cladding thickness between antenna and waveguide core. Any combination of the aforedescribed variations is also considered to be within the scope of the present invention.

0061It should be noted that, although waveguide-coupled assembly <b>400</b> of <figref idref="DRAWINGS">FIG. 6A</figref> is shown to include a silicon-on-insulator rib waveguide, other waveguide types, such as buried waveguides, fully etched waveguides, or photonic crystal waveguides, and different waveguide materials, such as glass or polymer, may also be used. In many instances, higher index and thinner waveguides couple more efficiently to the antenna and also take up less space on chip.

0062An example of the interaction of the electron tunneling devices with the input light is discussed in reference to <figref idref="DRAWINGS">FIG. 6B</figref>, showing a cross-sectional view of waveguide-coupled assembly <b>400</b> of <figref idref="DRAWINGS">FIG. 6A</figref>. As shown in <figref idref="DRAWINGS">FIG. 6B</figref>, electron tunneling devices <b>416</b><i>a</i>–<b>416</b><i>d </i>pick up evanescent field portions of input light <b>414</b> (shown as arrows <b>430</b><i>a</i>–<b>430</b><i>d</i>), modulate the received portions, then re-transmit modulated light (indicated by arrows <b>432</b><i>a</i>–<b>432</b><i>d</i>) back into waveguide layer <b>406</b> so as to provide modulated, output light <b>418</b>. Evanescent coupling between the rib waveguide region and the electron tunneling devices is particularly efficient for thin, high index waveguides.³

0063Continuing to refer to <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, it is noted that further modifications to waveguide-coupled assembly <b>400</b> are possible. For example, each of electron tunneling devices <b>416</b><i>a</i>–<b>416</b><i>d </i>may be configured to pick up a different wavelength of input light such that waveguide-coupled assembly <b>400</b> acts as a wavelength-dependent modulator of input light, which input light may include a variety of wavelengths. Alternatively, one or more of electron tunneling devices <b>416</b><i>a</i>–<b>416</b><i>d </i>may be configured as a detector (see, for example, aforementioned '988, '972 and '054 applications) so as to receive a portion of the input light and generate an electrical signal in accordance with the input light so received, which electrical signal may be directed to an electronic device located off of substrate <b>402</b> or also supported on the substrate. As yet another alternative, one or more of electron tunneling devices <b>416</b><i>a</i>–<b>416</b><i>d </i>may be configured as an amplifier (see, for instance, aforementioned '972 and '054 applications) so as to receive a portion of the input light or a portion of modulated light, as produced by another of the electron tunneling devices, and produce an amplified output light. In still another alternative, one or more of the electron tunneling devices may be configured as an emitter (see, for example, aforementioned '972 and '054 applications) so as to emit additional light into the rib waveguide region to contribute to the output light. Still further, one or more of the electron tunneling devices may be configured to re-emit the portion of input light received at that electron tunneling device, for example, in a direction away from the waveguide and the substrate so as to produce a free-space optical signal in accordance with the input light. As yet another option, one or more of the electron tunneling devices may be configured to receive free-space illumination and re-transmit the received optical energy into the waveguide.

0064<figref idref="DRAWINGS">FIGS. 6C and 6D</figref> illustrate still more alternative configurations to waveguide-coupled assembly <b>400</b> shown in <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>. For example, as shown in <figref idref="DRAWINGS">FIG. 6C</figref>, modified electron tunneling devices <b>416</b><i>a</i>′–<b>416</b><i>d</i>′ are integrated into a modified insulating layer <b>404</b>′, rather than being formed on top of rib waveguide section <b>410</b>. As in the embodiment illustrated in <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, the modified electron tunneling devices also couple to evanescent field portions of input light <b>414</b> (shown as arrows <b>430</b><i>a</i>′–<b>430</b><i>d</i>′), modulate the received portions, then re-transmit modulated light (indicated by arrows <b>432</b><i>a</i>′–<b>432</b><i>d</i>′) back into waveguide layer <b>406</b> so as to provide modulated, output light <b>418</b>. In contrast, modified electron tunneling devices <b>416</b><i>a</i>″–<b>416</b><i>d</i>″, shown in <figref idref="DRAWINGS">FIG. 6D</figref>, are integrated into a modified optical waveguide layer <b>406</b>″. In this case, input light <b>414</b> directly couples into modified electron tunneling device <b>416</b><i>a</i>″, which re-emits a modulated light <b>432</b><i>a</i>″. Modulated light <b>432</b><i>a</i>″ then couples into modified electron tunneling device <b>416</b><i>b</i>″, and so on until the output from the last device in the series, in this case modified electron tunneling device <b>416</b><i>d</i>″, becomes output light <b>418</b>. Thus, each one of the configurations shown in <figref idref="DRAWINGS">FIGS. 6B–6D</figref> is advantageous in different situations, depending on the level of integration required. For example, although the electron tunneling devices are most readily fabricated on top of the rib waveguide region, it may be desirable in certain cases to have the direct coupling of the principal portion of the input light with the electron tunneling devices as allowed by the configuration shown in <figref idref="DRAWINGS">FIG. 6D</figref>. Alternatively, closer coupling of the evanescent field portions of input light <b>414</b> may be enabled by the positioning of the electron tunneling regions as shown in <figref idref="DRAWINGS">FIG. 6C</figref> without drastically altering the lightwave-guiding characteristics of the rib waveguide region.

0065Attention is now directed to <figref idref="DRAWINGS">FIG. 6E</figref>, which illustrates an end-fire variation of the waveguide-coupled assembly of <figref idref="DRAWINGS">FIG. 6A</figref>, generally indicated by a reference number <b>450</b>. To the extent that waveguide-coupled assembly <b>450</b> resembles previously described waveguide-coupled assembly <b>400</b>, for example, with respect to its layered structure and the location of the electron tunneling devices, such descriptions are not repeated for purposes of brevity. A substrate <b>451</b> of waveguide-coupled assembly <b>450</b> includes first and second v-grooves <b>452</b> and <b>453</b>, respectively, for accommodating an input optical fiber <b>454</b> and an output optical fiber <b>456</b>, respectively. For example, input optical fiber <b>454</b> includes a fiber core <b>458</b> surrounded by a cladding <b>460</b>, and is designed to direct an input optical signal <b>462</b> therethrough and into rib waveguide region <b>410</b> as input light <b>414</b>. Output light <b>418</b> provided at optical output end <b>420</b> is then coupled into output optical fiber <b>456</b>. As shown in <figref idref="DRAWINGS">FIG. 6E</figref>, output optical fiber <b>456</b> includes a fiber core <b>464</b> surrounded by a cladding <b>466</b> so as to direct at least a portion (indicated by an arrow <b>468</b>) of output light <b>418</b> away from optical output end <b>420</b>. The coupling of optical fiber to the rib waveguide region enables ready insertion of waveguide-coupled assembly <b>450</b> into optical fiber-based systems, such as long distance communication systems. This end-fire embodiment allows higher coupling efficiency for single-mode fibers. Furthermore, inclusion of alignment aids, such as v-grooves <b>452</b> and <b>453</b> in substrate <b>451</b> allows self-alignment of optical fiber with the waveguide-coupled assembly of the present invention.

0066Referring now to <figref idref="DRAWINGS">FIGS. 7A–7D</figref>, still further variations of the waveguide-coupled assembly of the present invention are discussed. <figref idref="DRAWINGS">FIG. 7A</figref> shows a waveguide-coupled assembly <b>500</b>, which includes a shaped waveguide <b>502</b>. Shaped waveguide <b>502</b> includes first and second tapered sections <b>504</b> and <b>506</b>, respectively, on either side of a middle section <b>507</b>. First and second chirped, focusing grating couplers (surrounded by dashed lines <b>508</b> and <b>510</b>, respectively) are formed near opposite ends of shaped waveguide <b>502</b> such that first chirped, focusing grating coupler <b>508</b> receives an input optical signal <b>512</b> and couples the optical signal so received into shaped waveguide <b>502</b> as an input light (indicated by an arrow <b>514</b>). Input light <b>514</b> is then directed through first tapered section <b>504</b> into middle section <b>507</b>. One or more electron tunneling devices (three are shown, indicated by reference numerals <b>516</b><i>a</i>–<b>516</b><i>c</i>) are disposed on top of middle section <b>507</b> and are configured for, for example, modulating the input light then producing a modulated, output light (indicated by an arrow <b>518</b>). Modulated, output light <b>518</b> is then directed through second tapered section <b>506</b> and coupled out of shaped waveguide <b>502</b> through second chirped, focusing grating coupler <b>510</b> as an output optical signal <b>520</b>.

0067<figref idref="DRAWINGS">FIG. 7B</figref> is an illustration of an integrated optical transceiver chip including the waveguide-coupled assembly of <figref idref="DRAWINGS">FIG. 7A</figref>. The integrated optical transceiver chip, generally indicated by reference numeral <b>550</b>, includes a substrate <b>552</b> on which various components are supported, as will be described in detail immediately hereinafter. Substrate <b>552</b> includes an etched-out section <b>554</b>, in which a modified waveguide-coupled assembly <b>500</b>′, which is similar in design to waveguide-coupled assembly <b>500</b> as shown in <figref idref="DRAWINGS">FIG. 7A</figref>. To the extent that waveguide-coupled assembly <b>500</b>′ resembles previously described waveguide-coupled assembly <b>500</b>, for example, with respect to its tapered waveguide structure, focused grating couplers and the location of the electron tunneling devices, such descriptions are not repeated for purposes of brevity. An array of electron tunneling devices <b>516</b>′ of waveguide-coupled assembly <b>500</b>′ are connected with modulation inputs <b>556</b><i>a </i>and <b>556</b><i>b</i>, which lead from circuitry <b>558</b> supported on substrate <b>552</b>. Circuitry <b>558</b> is also connected with a detector <b>560</b>, which is also supported on substrate <b>552</b>, via leads <b>562</b><i>a </i>and <b>562</b><i>b</i>. Power may be supplied to circuitry <b>558</b> through DC power lines <b>564</b><i>a </i>and <b>564</b><i>b. </i>

0068Referring now to <figref idref="DRAWINGS">FIG. 7B</figref> in conjunction with <figref idref="DRAWINGS">FIG. 7C</figref>, one example of the operation of integrated optical transceiver chip <b>550</b> is described in reference to a schematic <b>580</b> as shown in <figref idref="DRAWINGS">FIG. 7C</figref>. It is noted that corresponding components in the two figures are labeled with the same reference numbers for clarity. In one possible configuration, detector <b>560</b> may be designed to receive an optical signal <b>582</b>, including data encoded thereon, and to provide an electrical, detector signal (not shown), also including the data, via leads <b>562</b><i>a </i>and <b>562</b><i>b </i>to circuitry <b>558</b>. Circuitry <b>558</b> may include, for example, electrical components such as bias control/automatic gain control (AGC) <b>584</b>, a pre-amplifier <b>586</b>, a clock recovery circuit <b>588</b> as well as a modulator driver <b>590</b>. Modulator driver <b>590</b> generates a modulation signal in accordance with the detector signal and directs the modulation to the array of electron tunneling devices of waveguide-coupled assembly <b>500</b>′. As a result, when a continuous wave (CW) light input <b>592</b> is incident on first chirped, focusing grating coupler <b>508</b>′, the array of electron tunneling devices modulate the CW light input and, consequently, waveguide-coupled assembly <b>500</b>′ provides a modulated light output <b>594</b>.

0069<figref idref="DRAWINGS">FIG. 7D</figref> illustrates a further variation on the waveguide-coupled assembly of the present invention as illustrated in <figref idref="DRAWINGS">FIG. 7A</figref>. <figref idref="DRAWINGS">FIG. 7D</figref> is a diagrammatic view, in cross section, of a modified waveguide-coupled assembly <b>600</b>. Modified waveguide-coupled assembly <b>600</b> includes waveguide-coupled assembly <b>500</b>, as shown in <figref idref="DRAWINGS">FIG. 7A</figref>, supported on a substrate <b>602</b> with an insulating layer <b>604</b> disposed therebetween. Input light <b>512</b> is provided through an input optical fiber <b>610</b>, which includes a fiber core <b>612</b> surrounded by a cladding <b>614</b>. As described previously in reference to <figref idref="DRAWINGS">FIG. 7A</figref>, waveguide-coupled assembly <b>500</b> provides a modulated, output light <b>520</b>. In the case of modified waveguide-coupled assembly <b>600</b>, output light <b>520</b> is received by an output optical fiber <b>620</b>, which also includes a fiber core <b>622</b> surrounded by a cladding <b>624</b> for guiding the output light away from the modified waveguide-coupled assembly.

0070Turning now to <figref idref="DRAWINGS">FIGS. 8A–8C</figref>, several packaging options for integrated optical transceiver chip <b>550</b> as shown in <figref idref="DRAWINGS">FIG. 7B</figref> are described. <figref idref="DRAWINGS">FIG. 8A</figref> shows a parallel optical transceiver <b>650</b> including a transceiver module <b>652</b> containing a plurality of integrated optical transceiver chips <b>550</b> therein (not visible). A single mode fiber <b>654</b> serves as a CW input for modulation. A plurality of pin-outs (indicated by dashed bracket <b>656</b>) serves to provide the various RF inputs/outputs as well as DC power input. Transceiver module <b>652</b> includes an input receptacle <b>658</b><i>a </i>and an output receptacle <b>658</b><i>b</i>, both of which are designed to accept multi-mode fiber (MMF) ribbons. For example, a first MMF ribbon <b>660</b><i>a </i>may provide a plurality of optical data inputs for the plurality of integrated optical transceiver chips, while a second MMF ribbon <b>660</b><i>b </i>may serve to extract the plurality of optical data outputs produced by the integrated optical transceiver chips.

0071<figref idref="DRAWINGS">FIG. 8B</figref> illustrates a scheme in which two or more chips may be optically interconnected. A chip-to-chip optical backplane <b>700</b> is designed to accept a lead frame-mounted chip <b>702</b>. Lead frame-mounted chip <b>702</b> includes a die <b>704</b> containing circuitry and connected to a lead frame <b>706</b> including a plurality of pin-outs (indicated by a dashed bracket <b>708</b>). Optical backplane <b>700</b> includes an integrated circuit socket <b>710</b> including a plurality of receptacles (indicated by a dashed bracket <b>712</b>) corresponding to the pin-outs of the lead frame-mounted chip. Optical backplane <b>700</b> further includes a MMF ribbon input <b>714</b>, a MMF ribbon output <b>716</b>, CW input <b>718</b> and DC power input through leads <b>720</b><i>a </i>and <b>720</b><i>b</i>. Integrated circuit socket <b>710</b> includes a plurality of the aforedescribed optical transceiver chips so as to directly connect a chip in a standard lead frame package with the optical transceivers.

0072<figref idref="DRAWINGS">FIG. 8C</figref> illustrates yet another packaging option for the optical transceiver chip of the present invention. An optical processor chip <b>750</b> includes a package <b>752</b> containing a plurality of optical transceiver chips (not visible). Package <b>752</b> includes an optical window <b>754</b>, which allows direct, optical connection of the optical processor chip with other optical components through a parallel optical bus (indicated by arrows bracketed by a dashed bracket <b>756</b>). Package <b>752</b> also includes the usual inputs for CW optical input (an optical fiber <b>758</b>) and DC power input (leads <b>760</b><i>a </i>and <b>760</b><i>b</i>).

0073Although each of the aforedescribed embodiments have been illustrated with various components having particular respective orientations, it should be understood that the present invention may take on a variety of specific configurations with the various components being located in a wide variety of positions and mutual orientations and still remain within the spirit and scope of the present invention. Furthermore, suitable equivalents may be used in place of or in addition to the various components, the function and use of such substitute or additional components being held to be familiar to those skilled in the art and are therefore regarded as falling within the scope of the present invention. For example, a reflective layer may be disposed between the circuitry layer and the waveguide layer for better isolation of the waveguide layer from the circuitry as well as for improved coupling of optical signals from the waveguide into the electron tunneling devices (see, for example, the '935 application). Also, the waveguide layer shown, for example, in <figref idref="DRAWINGS">FIG. 1A</figref> may be a separately deposited waveguide or a silicon-on-insulator (SOI) integrated waveguide. Furthermore, the substrate itself may be optically transmissive or guiding such that the optical signal may be provided from the substrate side of the interconnect arrangement rather than being edge-fed or incident from the top side. Still further, a variety of light coupling arrangements may be included in the embodiments of the present invention such as, and not limited to, antennas (as shown in, for instance, <figref idref="DRAWINGS">FIGS. 1A and 6A</figref>), grating couplers and surface plasmon evanescent couplers, all of which are discussed in detail in the aforementioned '988, '972, '054, '535 and '935 applications.

0074Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein but may be modified within the scope of the appended claims.

REFERENCES

0000<ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0075">1. Neil Savage, “Linking with Light,” <i>IEEE Spectrum</i>, vol. 39, Issue 8, pp. 32–36 (2002).</li><li id="ul0001-0002" num="0076">2. A. F. J. Levi, “Optical Interconnects in Systems,” <i>Proceedings of the IEEE</i>, vol. 88, pp. 750–757 (2002).</li><li id="ul0001-0003" num="0077">3. Brian J. Soller and Dennis G. Hall, “Energy transfer at optical frequencies to silicon-based waveguiding structures,” J. Opt. Soc. Am. A, vol. 18, no. 10, pp. 2577–2584 (2001).</li></ul>