Die-wafer package and method of fabricating same

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention relates generally to the packaging of semiconductor die and, more particularly, to a die-wafer packaging solution including multichip packages, stacked die arrangements and methods related to the fabrication thereof.

00032. State of the Art

0004Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. Increased integrated circuit density is limited, in large part, by the space or “real estate” available for mounting die on a substrate such as a printed circuit board.

0005Conventional lead frame designs have been used in the past in the fabrication of multichip packages, but such designs inherently limit package density for a given die size because the die-attach paddle of the lead frame is conventionally larger than the die to which it is bonded. Generally speaking, the larger the die, the less space that remains around the periphery of the die-bonding pad for wire bonding. Furthermore, the wire bonding pads on a conventional lead frame provide anchorage for the leads when the leads and the die are encapsulated in plastic. Therefore, as die size is increased in relation to a given package size, there is a corresponding reduction in the space along the sides of the package for the encapsulating plastic which joins the top and bottom of the plastic body at the mold part line and anchors the leads. Thus, as the leads and encapsulant are subjected to the normal stresses of subsequent forming and assembly operations, the encapsulating plastic may crack, compromising package integrity and substantially increasing the probability of premature device failure.

0006More recently, chip-on-wafer or chip-on-chip designs have been implemented, using both conventional wire bonding techniques as well as some flip-chip fabrication techniques, in order to increase package density and functionality. Such packages may include the interconnection of different chips used for specific functions within the package. For example, memory chips, such as dynamic random access memory (DRAM) and/or flash memory chips, may be combined with one or more types of logic circuit chips to provide an integrated system.

0007Such packages may be manufactured so as to provide a package with a relatively small footprint. Generally, such packages consume less surface area on a substrate than two separately packaged semiconductor dice coupled to the same substrate. Additionally, integration of more components into an electronic system generally reduces the cost of the system as well as the overall complexity thereof.

0008One attempt to provide such a multichip package includes U.S. Pat. No. 6,392,304, issued May 21, 2002, to Butler. The Butler patent discloses a multichip integrated circuit including a memory chip operatively coupled with a nonmemory chip. Butler teaches that there are reduced levels of capacitance and inductance due to the chip-on-chip interface and, therefore, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption. However, the final package taught by Butler appears to require wire bonds from at least one of the chips to an associated lead frame. As noted above, such an arrangement generally consumes valuable real estate on a carrier substrate or other device to which the package is ultimately mounted. Furthermore, the use of a lead frame and wire bonds may limit the speed of the device for some configurations.

0009Multichip packages not incorporating lead frames or wire bond connections are shown in U.S. Pat. No. 6,204,562, issued Mar. 20, 2001, to Ho et al., and U.S. Pat. No. 6,084,308, issued Jul. 4, 2000, to Kelkar et al.

0010The Ho patent discloses a package including a first die coupled with a second die in a face-to-face arrangement using flip-chip techniques. The input/output (I/O) connections of the first die are coupled with a redistribution layer formed between the two dice. Conductive bumps are formed on the face of the second die around the periphery of the first die and function as I/O connections for the resultant package. A molding material may be disposed about the first die and the conductive bumps to form the resulting package. While providing a multichip package using flip-chip techniques, the requirement of the package I/O connections being located about the periphery of the package outward of the first die's periphery may limit the flexibility in the placement and design of the resulting array of package I/O connections.

0011The Kelkar patent discloses a chip-on-chip integrated circuit package which includes a first die disposed within a cavity of a substrate. A second die is mounted over the top of the first die and is electrically coupled to I/O connections of the first die as well as to bond pads on the substrate by way of solder balls disposed therebetween. The bond pads of the substrate are electrically coupled to electrical contacts, such as conductive bumps or pins, formed on an opposing surface of the substrate. The first die is attached to the substrate using a die attach material which exhibits a reflow temperature which is substantially the same as the reflow temperature of the solder balls disposed between the second die and the substrate and first die. While allowing more flexibility in configuration and design of the package I/O connections than the package disclosed by Ho, the Kelkar package requires additional materials and procedures in the fabrication thereof. For example, the Kelkar package requires an additional substrate having electrical connections on opposing surfaces thereof as well as connecting circuitry formed between the electrical connections of both surfaces. Furthermore, the resulting package appears to be significantly larger than just the continuation of the two dice because of the requirements of the additional substrate.

0012Thus, there is a continued desire to provide wafer-level packages providing improved density and functionality while reducing the cost to manufacture and simplifying the associated fabrication processes.

BRIEF SUMMARY OF THE INVENTION

0013In accordance with one aspect of the present invention, a die-wafer package is provided. The die-wafer package includes a first semiconductor die having an active surface and a plurality of bond pads disposed on the active surface. The package further includes a second semiconductor die having a first side and a second opposing side. The second semiconductor die includes a first plurality of bond pads disposed on the first side and a second plurality of bond pads disposed on the second side. The first and second pluralities of bond pads each include an under-bump metallization layer. A first plurality of conductive bumps electrically interconnects at least a first set of the bond pads disposed on the active surface of the first semiconductor die and at least some of the second plurality of bond pads of the second semiconductor die.

0014In accordance with another aspect of the present invention, a semiconductor device package is provided. The semiconductor device package includes at least two semiconductor dice wherein at least one of the semiconductor die includes a first plurality of bond pads disposed on a first surface and a second plurality of bond pads disposed on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization layer. A first plurality of conductive bumps electrically interconnects at least some of the first plurality of bond pads of the at least one semiconductor die with a first set of bond pads disposed on a first surface of at least one other semiconductor die.

0015In accordance with yet another aspect of the present invention, a multichip module is provided. The multichip module includes a carrier substrate having at least two sets of bond pads disposed on a first surface thereof. At least two semiconductor device packages are provided wherein each semiconductor device package is electrically coupled with a corresponding set of bond pads of the at least two sets of bond pads. At least one of the at least two semiconductor device packages comprises at least one semiconductor die having a plurality of bond pads on a first surface and a plurality of bond pads on a second opposing surface thereof wherein each bond pad of the two pluralities of bond pads includes an under-bump metallization layer.

0016In accordance with a further aspect of the present invention, a method of fabricating a semiconductor device package is provided. The method includes providing a wafer having at least one semiconductor die site, the at least one semiconductor die site having a plurality of bond pads including at least a first set of bond pads and a second set of bond pads. At least one singulated semiconductor die is provided wherein the singulated die has a first plurality of bond pads disposed on a first surface thereof and a second plurality of bond pads disposed on a second opposing surface. Each of the first and second pluralities of bond pads includes an under-bump metallization layer. A first plurality of conductive bumps is disposed between and electrically couples the first set of bond pads with at least some of the first plurality of bond pads of the at least one singulated semiconductor die.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

0017The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

0018<figref idref="DRAWINGS">FIG. 1</figref> is a perspective view of a semiconductor wafer containing an array of electronic devices;

0019<figref idref="DRAWINGS">FIG. 2A</figref> is a partial sectional view of the wafer shown in <figref idref="DRAWINGS">FIG. 1</figref> having conductive bumps attached in a direct bump configuration;

0020<figref idref="DRAWINGS">FIG. 2B</figref> is a partial sectional view of a wafer having a redistribution layer and associated conductive bumps;

0021<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> show partial sectional views of a singulated semiconductor die which may be utilized in an embodiment of the present invention;

0022<figref idref="DRAWINGS">FIGS. 4A and 4B</figref> show elevational views of a plurality of singulated semiconductor dice coupled to a wafer in accordance with an aspect of the present invention;

0023<figref idref="DRAWINGS">FIGS. 5A–5C</figref> show partial sectional views of the assembly of <figref idref="DRAWINGS">FIGS. 4A and 4B</figref> at various stages of fabrication, including a resultant multichip package, in accordance with an aspect of the present invention;

0024<figref idref="DRAWINGS">FIG. 5D</figref> shows a partial sectional perspective view of the multichip package shown in <figref idref="DRAWINGS">FIG. 5C</figref>;

0025<figref idref="DRAWINGS">FIG. 6</figref> is an elevational view showing a multichip package attached to a carrier substrate in accordance with an aspect of the present invention;

0026<figref idref="DRAWINGS">FIG. 7</figref> is an elevational view of a multichip package during fabrication in accordance with another embodiment of the present invention;

0027<figref idref="DRAWINGS">FIG. 8</figref> is an elevational view of a multichip package utilizing multiple semiconductor dice of a wafer in accordance with another embodiment of the present invention;

0028<figref idref="DRAWINGS">FIG. 9</figref> is an elevational view of another multichip package during the fabrication thereof in accordance with yet another embodiment of the present invention;

0029<figref idref="DRAWINGS">FIG. 10</figref> is an elevational view of yet another multichip package during the fabrication thereof in accordance with a further embodiment of the present invention;

0030<figref idref="DRAWINGS">FIG. 11</figref> is an elevational view of a multichip package during the fabrication thereof in accordance with yet a further embodiment of the present invention;

0031<figref idref="DRAWINGS">FIG. 12</figref> is a schematic showing a multichip package employed in a computer environment according to an embodiment of the present invention; and

0032<figref idref="DRAWINGS">FIG. 13</figref> is a schematic showing a multichip package according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

0033Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a semiconductor wafer <b>100</b> is shown which may be used in the fabrication of a die-wafer package according to one embodiment of the present invention. The semiconductor wafer <b>100</b> includes an array of semiconductor dice <b>102</b> (also referred to herein as “semiconductor die sites”) formed thereon which may be conventionally fabricated as circuit layers (not shown) on and/or extending into the wafer <b>100</b>. Discrete semiconductor devices may be identified and at least initially segregated by streets or street lines <b>104</b> as will be appreciated by those of ordinary skill in the art. The circuit layers of the wafer <b>100</b> and semiconductor dice <b>102</b> may be formed on what is referred to as an active surface <b>106</b> of the wafer <b>100</b>. The opposite side or backside of the wafer <b>100</b> may remain free of circuitry and may be referred to as a passive surface <b>108</b>. It is noted that the wafer <b>100</b> described herein is exemplary and that various other configurations may be utilized in the present invention.

0034The fabrication of the wafer <b>100</b> enables many semiconductor dice <b>102</b> to be formed and processed substantially simultaneously for subsequent separation into individual or discrete semiconductor dice as will be appreciated by those of ordinary skill in the art. Bond pads <b>112</b> may be formed on the active surface <b>106</b> of each individual or discrete semiconductor die <b>102</b> for electrical interconnection between an individual semiconductor die <b>102</b> and another electronic device such as will be described in greater detail herein below.

0035A first passivation layer <b>114</b> may be disposed on the active surface <b>106</b> during wafer fabrication for protection of the circuitry of the semiconductor dice <b>102</b> from external environmental elements. The first passivation layer <b>114</b> may be formed of, for example, silicon-based materials such as silicon oxides or silicon nitrides, which may be deposited by conventional sputtering or chemical vapor deposition (CVD) processes. After the first passivation layer <b>114</b> is formed on the wafer <b>100</b>, the underlying bond pads <b>112</b> may be exposed through the first passivation layer <b>114</b>, such as by an etching process.

0036Referring to <figref idref="DRAWINGS">FIG. 2A</figref>, a partial sectional view of the wafer <b>100</b> and, more particularly, of a semiconductor die <b>102</b> is shown. Conductive bumps <b>116</b> may be formed on the active surface <b>106</b> of the wafer <b>100</b> in a direct bump configuration over bond pads <b>112</b> of the semiconductor die <b>102</b>. A second passivation layer <b>118</b> may be deposited over the first passivation layer <b>114</b>, and an under-bump metallization (UBM) layer <b>120</b> may be formed on the bond pads <b>112</b> and also to overlap a portion of the first and second passivation layers <b>114</b>, <b>118</b>. Conductive bumps <b>116</b> are then attached to the UBM layer <b>120</b> directly over the bond pads <b>112</b>, which may include one or more layers of solder wettable material or other barrier layers of material thereon. Conductive bumps <b>116</b> may be formed using known techniques such as screen printing or by ball bumping with wire bonding equipment. Exemplary materials for conductive bumps <b>116</b> may include gold, eutectic tin/lead solder, and conductive or conductor-filled epoxies. Furthermore, while described in terms of bumps, it should be understood that conductive bumps <b>116</b> may be configured as balls, columns, pillars, or other desired geometrical configurations.

0037Referring briefly to <figref idref="DRAWINGS">FIG. 2B</figref>, a partial sectional view of a semiconductor die <b>102</b>′ according to another embodiment of the present invention is shown. A redistribution layer (RDL) may be used to relocate connection points for the bond pads <b>112</b> of the individual semiconductor die <b>102</b>′. This may be required when the bond pads <b>112</b> of a semiconductor die <b>102</b>′ are not configured in a suitable pattern for attachment or are too closely spaced to allow effective formation of the conductive bumps <b>116</b>. Thus, subsequent to depositing the second passivation layer <b>118</b>, redistribution circuits <b>122</b> may be formed thereon. The redistribution circuits <b>122</b> may be deposited as a layer of metal, polysilicon or other conductive material on the second passivation layer <b>118</b> and etched to form a desired circuit pattern. Next, a third passivation layer <b>124</b> may be deposited over the redistribution circuits <b>122</b> using similar materials and deposition techniques as with the first and second passivation layers <b>114</b>, <b>118</b>. The third passivation layer <b>124</b> may then be etched to expose new bump connection locations <b>126</b> on the redistribution circuits <b>122</b>. A UBM layer <b>120</b>′ may be formed to cover the bump connection locations <b>126</b> and overlap a portion of the third passivation layer <b>124</b>. The conductive bumps <b>116</b> are attached to UBM layer <b>120</b>′ directly over bump connection locations <b>126</b>.

0038While <figref idref="DRAWINGS">FIGS. 2A and 2B</figref> illustrate an exemplary conductive bump <b>116</b> and associated connection structure, it is noted that multiple sets of conductive bumps may be formed on the semiconductor devices <b>102</b> of the wafer <b>100</b>. Each set of conductive bumps may exhibit characteristics which differ from other sets of conductive bumps formed on the same semiconductor die <b>102</b>. For example, a first set of conductive bumps may be formed of a first material while the second set of conductive bumps may be formed of a second material. Also, the conductive bumps of one set may be of a first geometric configuration, size and/or volume which is different from the conductive bumps of another set of the same semiconductor die <b>102</b>.

0039Referring now to <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, <figref idref="DRAWINGS">FIG. 3A</figref> shows a partial sectional view of a singulated semiconductor die <b>140</b> and <figref idref="DRAWINGS">FIG. 3B</figref> shows an enlarged view of a portion of the singulated die <b>140</b>. The singulated die <b>140</b> may include a plurality of bond pads <b>142</b> formed on a first surface <b>144</b> or upper side of the die. A UBM layer <b>146</b> may be formed over the bond pads <b>142</b> with a conductive bumps <b>148</b> being formed over the UBM layer <b>146</b>. As with the wafer <b>100</b> described above with respect to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>A and <b>2</b>B, the UBM layer <b>146</b> may be formed of a solder wettable material or other barrier material and the conductive bumps <b>148</b> may be formed of a material such as gold, eutectic tin/lead solder, conductive or conductor-filled epoxies or another appropriate conductive material.

0040The singulated die <b>140</b> may further include a plurality of bond pads <b>150</b> formed on a second surface <b>152</b> or underside of the die <b>140</b>. A UBM layer <b>154</b> may also be formed over the bond pads <b>150</b> on the second surface <b>152</b>. One or more of the bond pads <b>142</b> formed on the first surface <b>144</b> may be in electrical communication with one or more bond pads <b>150</b> formed on the second surface <b>152</b> through circuitry (not shown) formed within the die <b>140</b>. However, if so desired, each bond pad <b>142</b> and <b>150</b> may act as a discrete I/O connection depending, for example, on the desired function of the die <b>140</b>. The formation of bond pads <b>142</b> and <b>150</b> with associated UBM layers <b>146</b> and <b>154</b> on opposing surfaces <b>144</b> and <b>152</b> of the singulated die <b>140</b> provides considerable flexibility in forming a multichip package.

0041The singulated die <b>140</b> may be fabricated in a manner generally similar to the wafer <b>100</b> shown and described with respect to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>A and <b>2</b>B including the formation of various passivation layers <b>160</b>, <b>162</b>, <b>164</b> and <b>166</b>. Additionally, while not specifically shown in <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, redistribution layers may be formed in the singulated die <b>140</b> as will be appreciated by those of ordinary skill in the art.

0042It is noted that the singulated die <b>140</b> shown and described with respect to <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, and the semiconductor dice <b>102</b> on the wafer <b>100</b> shown and described with respect to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>A and <b>2</b>B, may be similar or dissimilar devices. In other words, the singulated die <b>140</b> and the semiconductor dice <b>102</b> may each be configured, for example, as a memory device or one device may be configured, for example, as a memory device while the other is configured as a logic device.

0043Referring now to <figref idref="DRAWINGS">FIGS. 4A and 4B</figref>, a plurality of singulated dice <b>140</b> is disposed on the wafer <b>100</b> over corresponding semiconductor dice <b>102</b>. The singulated die <b>140</b> may be electrically coupled to their respective semiconductor devices <b>102</b> by contacting a first set of conductive bumps <b>116</b>A formed on the surface of the semiconductor die <b>102</b> with the UBM-covered bond pads <b>150</b>, <b>154</b> (<figref idref="DRAWINGS">FIGS. 3A and 3B</figref>) on the second surface <b>152</b> of the singulated die <b>140</b> and forming an appropriate electrical connection therebetween using flip-chip fabrication techniques. A second set of conductive bumps <b>116</b>B, which are generally larger in volume, or at least taller in height, than the first set of conductive bumps <b>116</b>A, may be formed and located on UBM-covered bond pads <b>112</b>, <b>120</b> (<figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>A and <b>2</b>B) of the semiconductor dice <b>102</b> such that they are not directly electrically coupled with the singulated die <b>140</b>.

0044It is noted that, in some embodiments, the second set of conductive bumps <b>116</b>B and the bond pads <b>142</b> on the first surface <b>144</b> of the singulated semiconductor die <b>140</b> may terminate at their respective upper ends at substantially the same height or distance above the wafer's active surface <b>106</b>. However, as will be discussed in further detail below, such may depend on the geometric configuration of the conductive bumps <b>148</b> and <b>116</b>B.

0045Referring now to <figref idref="DRAWINGS">FIG. 5A</figref>, a passivation layer <b>170</b> may be formed over the wafer <b>100</b> and the plurality of singulated die <b>140</b> coupled therewith. The passivation layer <b>170</b> may be formed, for example, of an appropriate glass material, silicon nitride or silicon oxide or as a layer of epoxy or other polymer material to protect the resulting packages from external environmental elements. While shown to be contiguous with the passivation layer <b>170</b> for purposes of convenience in illustration, a layer of underfill material may be disposed between the active surface <b>106</b> of the wafer <b>100</b> and the singulated die <b>140</b> about the first set of conductive bumps <b>116</b>A.

0046Referring to <figref idref="DRAWINGS">FIG. 5B</figref>, the passivation layer <b>170</b> may be subjected to an appropriate planarization process or other material removal process to expose a portion of the upper surfaces of the second set of conductive bumps <b>116</b>B and the conductive bumps <b>148</b> formed on the first surface <b>144</b> of the singulated die <b>140</b>. Such a process may include, for example, a mechanical grinding process or other mechanical planarization process, a chemical-mechanical planarization process (CMP), a chemical planarization process or an etching process. It is noted that the second set of conductive bumps <b>116</b>B and the conductive bumps <b>148</b> formed on the first surface <b>144</b> of the singulated die <b>140</b> may each be sized, located and configured such that, when a portion of each is exposed by way of an appropriate planarization or other material removal process, the exposed portion of each set of conductive bumps <b>116</b>B, <b>148</b> exhibits a substantially similar surface area which is configured for subsequent electrical connection with, for example, a carrier substrate or other electronic device. This may be accomplished even if the conductive bumps <b>116</b>B and <b>148</b> are of different relative sizes or geometrical configurations.

0047For example, assuming that the conductive bumps <b>116</b>B and <b>148</b> are each configured as conductive balls, they may be sized, located and configured such that, when subjected to the above-referenced material removal process, the conductive bumps <b>148</b> formed on the first surface <b>144</b> of the singulated die <b>140</b> are exposed down to a level which is at or near their midsections. This would provide the maximum surface area for such conductive bumps <b>148</b> as indicated generally by the exposed diameter D₁. On the other hand, the second set of conductive bumps <b>116</b>B may only have the tips thereof exposed as a result of the material removal process, thereby providing a surface area for the second set of conductive bumps <b>116</b>B which is indicated generally by the exposed diameter D₂. In one embodiment, the conductive bumps <b>116</b>B and <b>148</b> may be sized, located and configured such that their respective exposed diameters D₂and D₁will be substantially equal, thereby rendering substantially equal exposed surface areas.

0048In other configurations, if it is desired to have the conductive bumps <b>116</b>B and <b>148</b> exhibit substantially equal exposed surface areas, the exposed conductive bumps <b>116</b>B and <b>148</b> may be configured as conductive columns, each exhibiting similar diameters. In other configuration, one set of conductive bumps <b>116</b>B and <b>148</b> may exhibit one geometric configurations (e.g., a conductive ball) while another set may exhibit another geometric configuration (e.g., a conductive column) while still providing substantially similar exposed surface areas.

0049Referring now to <figref idref="DRAWINGS">FIGS. 5C and 5D</figref>, a multichip package <b>180</b> is shown after singulation thereof. Singulation may be accomplished by, for example, scoring or cutting the wafer with a wafer saw along the street lines <b>104</b> (indicated by dashed lines in <figref idref="DRAWINGS">FIGS. 5A and 5B</figref>). The resulting multichip package <b>180</b> includes two discrete devices (semiconductor die <b>102</b> and previously singulated die <b>140</b>) coupled directly to one another by way of conductive bumps <b>116</b>A wherein each discrete device is also configured for direct coupling with, for example, a carrier substrate by way of conductive bumps <b>116</b>B and <b>148</b> respectively. The use of conductive bumps <b>116</b>A, <b>116</b>B and <b>148</b> and UBM layers <b>120</b>, <b>146</b> and <b>154</b> (see <figref idref="DRAWINGS">FIGS. 2A and 3B</figref>) throughout the multichip package <b>180</b> provides for faster and more reliable interconnections. Furthermore, such interconnections provide for a multichip package <b>180</b> which exhibits an overall reduced size.

0050Referring briefly to <figref idref="DRAWINGS">FIG. 6</figref>, the multichip package <b>180</b> may be mounted, for example, to a carrier substrate <b>182</b>, such as a printed circuit board, using flip-chip techniques such that the exposed portions of conductive bumps <b>116</b>B and <b>148</b> are electrically coupled with the bond pads <b>184</b> of the carrier substrate <b>182</b>. In one embodiment, a plurality of multichip packages <b>180</b> may be mounted to the same carrier substrate to form, for example, a memory module.

0051As previously noted, the multichip package <b>180</b> may be formed using similar device types (e.g., the semiconductor die <b>102</b> and singulated die <b>140</b> both being memory devices) or each being a distinct type of device (e.g., one being a memory device and the other being a logic device). Thus, a variety of arrangements may be employed providing considerable flexibility in the design of the multichip package with regard to its intended use.

0052Referring now to <figref idref="DRAWINGS">FIG. 7</figref>, a multichip package in the form of a stacked semiconductor arrangement <b>190</b> according to another embodiment of the present invention is shown wherein a first singulated die <b>140</b> is electrically coupled to a semiconductor die <b>102</b> by way of a first set of conductive bumps <b>116</b>A. A second set of conductive bumps <b>116</b>B is provided for direct electrical interconnection between the semiconductor die <b>102</b> and an external device such as a carrier substrate. A second singulated chip <b>192</b> is coupled to the first singulated die <b>140</b> by way of conductive bumps <b>194</b>. Another set of conductive bumps <b>196</b> is disposed on top of the second singulated chip <b>192</b> and configured for direct electrical interconnection with an external device.

0053Referring to <figref idref="DRAWINGS">FIG. 8</figref>, a multichip package in the form of a stacked semiconductor arrangement <b>200</b> according to yet another embodiment of the present invention is shown wherein a plurality of singulated dice <b>140</b>A and <b>140</b>B, each being electrically coupled to an associated semiconductor die <b>102</b>A and <b>102</b>B respectively, are bridged by, and electrically coupled to, a second common singulated chip <b>192</b>′. Thus, a resulting package would include both semiconductor dice <b>102</b>A and <b>102</b>B. Conductive bumps <b>116</b>B may again provide direct electrical interconnection between the semiconductor dice <b>102</b>A and <b>102</b>B and an external device. As with other embodiments described herein, the semiconductor dice <b>102</b>A and <b>102</b>B and the singulated dice <b>140</b>A, <b>140</b>B and <b>190</b>′ may include similar types of devices or may include a mixture of differing types of devices.

0054Referring to <figref idref="DRAWINGS">FIG. 9</figref>, a multichip package in the form of a stacked semiconductor arrangement <b>202</b> is shown in accordance with a further embodiment of the present invention wherein a first singulated die <b>140</b> is electrically interconnected with the semiconductor die <b>102</b> of a wafer <b>100</b> by way of a first set of conductive bumps <b>116</b>A. A second singulated chip <b>192</b>″ is electrically interconnected to the semiconductor die <b>102</b> by way of a second set of conductive bumps <b>116</b>B and also electrically interconnected with the first singulated die <b>140</b> by way of another set of conductive bumps <b>194</b>′. Conductive bumps <b>196</b>′ are also formed on the upper surface of the second singulated chip <b>192</b>″ and configured for electrical interconnection with an external device.

0055Referring to <figref idref="DRAWINGS">FIG. 10</figref>, a multichip package in the form of a stacked semiconductor arrangement <b>204</b> is shown in accordance with yet a further embodiment of the present invention wherein a first singulated die <b>140</b> is electrically interconnected with the semiconductor die <b>102</b> of a wafer <b>100</b> by way of a first set of conductive bumps <b>116</b>A. A second set of conductive bumps <b>116</b>B is configured to provide direct electrical interconnection between the semiconductor die <b>102</b> and an external device. A second singulated chip <b>192</b>′″ is electrically interconnected with the first singulated die <b>140</b> by way of conductive bumps <b>194</b>′ and is also electrically interconnected with the semiconductor die <b>102</b> by way of conductive bumps <b>206</b>. Conductive bumps <b>196</b>″ are formed on the upper surface of the second singulated chip <b>192</b>′″ and configured for electrical interconnection with an external device.

0056Referring now to <figref idref="DRAWINGS">FIG. 11</figref>, another multichip package in the form of stacked semiconductor arrangement <b>208</b> is shown wherein the arrangement <b>208</b> is similar to that which is shown and described with respect to <figref idref="DRAWINGS">FIG. 10</figref>, except that the first singulated die <b>140</b> and second singulated chip <b>192</b>′″ are reversed in their positions within the stacked arrangement <b>208</b> and conductive bumps <b>206</b>′ are configured to electrically interconnect the second singulated chip <b>192</b>′″ with an external device rather than with the semiconductor die <b>102</b>. The embodiment of <figref idref="DRAWINGS">FIG. 11</figref> enables each die or device (<b>102</b>, <b>140</b>, <b>192</b>′″) to be directly connected with an external device using flip-chip mounting techniques. More particularly, semiconductor die <b>102</b> may be electrically interconnected with an external device by way of conductive bumps <b>116</b>B, the first singulated die <b>140</b> may be electrically interconnected with an external device by way of conductive bumps <b>116</b>A, and the second singulated chip <b>192</b>′″ may be electrically interconnected with an external device by way of conductive bumps <b>206</b>′.

0057It is noted that the stacked arrangements shown in <figref idref="DRAWINGS">FIGS. 7–11</figref> are shown at an intermediate stage of fabrication and that, as described above herein with respect to other embodiments, a passivation layer or other encapsulant material may be disposed over the stacked arrangements and that each stacked arrangement may be subsequently singulated into a discrete semiconductor device package.

0058It is further noted that any of the above-described multichip packages may be utilized in a computer environment. For example, referring to <figref idref="DRAWINGS">FIG. 12</figref>, a multichip package <b>180</b>, <b>190</b>, <b>200</b>, <b>202</b>, <b>204</b> and/or <b>208</b> may be configured as memory devices and incorporated into a computing system <b>220</b>, which may further include, for example, a processor device <b>222</b>, such as a central processing unit or other logic device, operably coupled with the memory device(s). The processor device may also be coupled with one or more appropriate input devices <b>224</b> (e.g., mouse, keyboard, hard drive, microphone, etc.) and one or more output devices <b>226</b> (e.g., monitor, printer, speaker, etc.). It is particularly noted that the multichip packages may be utilized in environments requiring relatively large amounts of memory configured in a small volume or package such as, for example, cell phones, personal data assistants (PDAs), and other similar devices.

0059Referring briefly to <figref idref="DRAWINGS">FIG. 13</figref>, in another embodiment, a multichip package <b>180</b>, <b>190</b>, <b>200</b>, <b>202</b>, <b>204</b> and/or <b>208</b> may be configured to include a die configured as a logic device <b>230</b> and a die configured as a memory device <b>232</b>, such as described above, and independently coupled with one or more input devices <b>224</b> and one or more output devices <b>226</b> as part of a specified computer system <b>220</b>′.

0060The above-illustrated embodiments of the present invention, and variations thereof, provide die-wafer packaging or multichip packaging of semiconductor dice including stacked arrangements configured for flip-chip mounting or attachment to an external device. Although the present invention has been depicted and described with respect to the illustrated embodiments, various additions, deletions and modifications are contemplated within its scope. The scope of the invention is, therefore, indicated by the appended claims rather than the foregoing description. Further, all changes which may fall within the meaning and range of equivalency of the claims and elements and features thereof are to be embraced within their scope.