Chip scale surface mounted device and process of manufacture
Summary by NHIP
Clip-mounted MOSFET package
The package mounts a MOSFET die drain-side down within a conductive clip where the drain contact connects to an inner web surface via solder. A conductive leg extends from the web opposite the die edge, facing the same direction as the die's second major surface while extending between the drain and control contacts.
Claim Score by NHIP
Abstract
A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

Term
Term ended
Expired 3 August 2021, 5.1 years ago.
- Priority
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- Granted
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- Today
31 claims: 4 independent, 27 dependent
- 1A semiconductor device package comprising:an electrical connector formed of an electrically and thermally conductive material including a web portion and a conductive leg extending from an edge of said web portion said leg including a free surface, said web portion and said conductive leg forming a unitary body, said web portion and said conductive leg each including an inner surface and an outer surface opposite said inner surface;a semiconductor die having a first power contact on a first major surface thereof and a second power contact and a control contact on a second major surface thereof opposite to said first power contact, said first power contact being electrically connected to said inner surface of said web portion by a conductive adhesive and spaced from said inner surface of said conductive leg;and mold compound disposed over at least said outer surface of said web portion and said outer surface of said conductive leg;wherein said conductive leg is located opposite an edge of said die and extends at least between said first power contact and said second power contact and said free surface faces a same direction as said second major surface of said semiconductor die.
- 6Broadest claimClaim Score 61, broad(NHIP)A semiconductor device package comprising:an electrically and thermally conductive cup-shaped clip including an interior web surface;and a semiconductor die having a first power contact on a first major surface thereof and a second power contact on a second major surface thereof opposite to said first power contact, said first power contact being electrically connected to said interior web surface by a conductive adhesive;wherein said cup-shaped clip further includes at least one projection having a projection surface facing a same direction as said second power electrode.
- 11A semiconductor device package comprising a semiconductor device die having parallel top and bottom surfaces;said top surface having a first planar metallic electrode, said bottom surface having a second planar metallic electrode;a metal clip having a flat web portion and at least one peripheral rim portion extending from an edge of said flat web portion;said bottom surface of said web being electrically connected in surface to surface contact to said second planar metallic electrode on the bottom surface of said die by a conductive adhesive;said peripheral rim portion of said clip being extended over and spaced from an edge of said die and including a projection terminating in a projection surface which is in plane parallel to the plane of said first planar metallic electrode, wherein said rim portion and said web portion are integral and form a unitary body, said clip is a cup-shaped structure, said peripheral rim is a continuous rim surrounding and spaced from the exterior of said die, and said metallic clip serves as an electrical connector for electrical connection to said second planar metal electrode.
- 16A semiconductor device package comprising a semiconductor device die having parallel top and bottom surfaces;said top surface having a first planar metallic electrode, said bottom surface having a second planar metallic electrode;at least one solderable body on at least a first portion of said first planar metallic electrode, said at least one solderable body having an upper planar surface;a metal clip having a flat web portion and at least one peripheral rim portion extending from an edge of said flat web portion;said bottom surface of said web portion being electrically connected to said second planar metallic electrode on the bottom surface of said die by a conductive adhesive;said peripheral rim portion of said clip being extended over and spaced from an edge of said die and including at least one projection terminating in a projection surface which is in plane parallel to the plane of said upper planar surface of said at least one solderable body and being insulated therefrom, wherein said rim portion and said web portion are integral and form a unitary body, said clip is a cup-shaped structure, said peripheral rim is a continuous rim surrounding and spaced from the exterior of said die, and said metal clip serves as an electrical connector for electrical connection to said second planar metallic electrode.
Independent claims4
55 paragraphs in 5 sections, as filed
RELATED APPLICATIONS
0001This application is a divisional of U.S. application Ser. No. 09/819,774, filed Mar. 28, 2001 now U.S. Pat. No. 6,624,522 by Martin Standing and Hazel Deborah Schofield entitled CHIP SCALE SURFACE MOUNTED DEVICE AND PROCESS OF MANUFACTURE and is related to and claims priority to provisional application Ser. No. 60/194,522, filed Apr. 4, 2000 in the names of Martin Standing and Hazel Deborah Schofield.
BACKGROUND OF THE INVENTION
0002This invention relates to semiconductor devices and more specifically relates to a process for the low cost manufacture of a novel semiconductor device.
0003Semiconductor devices and housings are well known. In prior art devices, the housing area is frequently a large multiple of the area of the semiconductor device. Further, in many known semiconductor device packages, heat is taken out only from one side of the die, usually the bottom surface. Further, in present packages the manufacturing process is costly, using single device handling techniques.
0004More specifically, in present semiconductor devices, particularly power MOSgated devices, the top contact (the source) is generally an aluminum contact containing about 1.0% silicon (hereafter an aluminum contact). The aluminum contact is used because it is well adapted to the wafer manufacturing process. However, it is difficult to form electrical connections to such aluminum contacts so a wire bond process is usually used in which a wire is ultrasonically bonded to the underlying aluminum contact. These wire-bond connections have a limited area and are thus a source of electrical resistance (R<sub>DSON</sub>) and of heat generation during operation. However, the bottom drain contact is frequently a trimetal which is easily solderable or otherwise electrically connectable to a wide area contact surface without wire bonding as shown, for example, in U.S. Pat. No. 5,451,544. Heat is primarily removed from the silicon die at the back contact surface, even though most heat is generated at the junction in the top surface and at the wire bonds.
0005It is further known that solderable top contacts can be made to the top surface of a die, as shown in U.S. Pat. No. 5,047,833. However, the packages used for such solderable top contact structures have had very large “footprints” in comparison to the die area.
0006It would be desirable to produce a package design and process for its manufacture which would use a smaller package for the same die, while improving electrical characteristics such as R<sub>DSON </sub>of a MOSgated semiconductor type device. It would be further desirable to produce such devices in a process which permits batch handling with reduced equipment on the production line and lower costs.
BRIEF SUMMARY OF THE INVENTION
0007In accordance with one aspect of the invention, the source side of a MOSgated device wafer is covered with a passivation layer, preferably a photosensitive liquid epoxy, or a silicon nitride layer, or the like. The wafer is coated by a spinning, screening, or otherwise depositing the liquid epoxy onto the wafer surface. The material is then dried and the coated wafer is exposed using standard photolithographic techniques to image the wafer and openings are formed in the passivation layer to produce a plurality of spaced exposed surface areas of the underlying source metal and a similar opening to expose the underlying gate electrode of each die on the wafer. Thus, the novel passivation layer acts as a conventional passivation layer, but further acts as a plating resist (if required) and as a solder mask, designating and shaping the solder areas. The openings in the novel passivation layer can be made through to a conventional underlying solderable top metal such as a titanium/tungsten/nickel/silver metal. Alternatively, if the underlying metal is the more conventional aluminum metal the exposed aluminum can be plated with nickel and gold flash or other series of metals, resulting in a solderable surface, using the passivation as a plating resist. The tops of the plated metal segments are easily solderable, or otherwise contacted with low resistance, as compared to the high resistance connection of the usual wire bond to an aluminum electrode.
0008The source contact areas may have various geometries and can even constitute a single large area region.
0009The wafer is then sawn or otherwise singulated into individual die. The individual die are then placed source-side down and a U-shaped or cup shaped, partially plated drain clip is connected to the solderable drain side of the die, using a conductive epoxy or solder, or the like to bond the drain clip to the bottom drain electrode of the die. The bottoms of the legs of the drain clip are coplanar with the source-side surface (that is the tops of the contact projections) of the die. The outer surface of the die is then over molded in a mold tray. A large number of die with such drain clips can be simultaneously molded in the mold tray.
0010The bonding material may be protected with a fillet of passive material or by overmolding all, or a part of the assembly. The parts can be made in production by using a lead frame, a continuous strip, or by molding devices in a single block and singulating devices from that block.
0011After molding, the devices are tested and laser marked and are again sawn into individual devices.
BRIEF DESCRIPTION OF THE DRAWINGS
0012<figref idref="DRAWINGS">FIG. 1</figref> is a top view of a singulated power MOSFET die which can be housed in accordance with the invention.
0013<figref idref="DRAWINGS">FIG. 2</figref> is a cross-section of <figref idref="DRAWINGS">FIG. 1</figref> taken across section line <b>2</b>—<b>2</b> in <figref idref="DRAWINGS">FIG. 1</figref>.
0014<figref idref="DRAWINGS">FIG. 3</figref> is a top view of the die of <figref idref="DRAWINGS">FIG. 1</figref> after it has been processed in accordance with the invention to define a plurality of separate “solderable” source contact areas and a “solderable” gate area.
0015<figref idref="DRAWINGS">FIG. 4</figref> is a cross-section of <figref idref="DRAWINGS">FIG. 3</figref> taken across section line <b>4</b>—<b>4</b> in <figref idref="DRAWINGS">FIG. 3</figref>.
0016<figref idref="DRAWINGS">FIG. 5</figref> is a view like that of <figref idref="DRAWINGS">FIG. 3</figref> of a die with a modified source contact pattern.
0017<figref idref="DRAWINGS">FIG. 6</figref> is a view like that of <figref idref="DRAWINGS">FIGS. 3 and 5</figref> of a still further and large area “solderable” source contact pattern.
0018<figref idref="DRAWINGS">FIG. 7</figref> is a top view of a still further contact topology (with a corner gate) formed using the process of the invention.
0019<figref idref="DRAWINGS">FIG. 8</figref> is a cross-section of <figref idref="DRAWINGS">FIG. 7</figref> taken across section lines <b>8</b>—<b>8</b> in <figref idref="DRAWINGS">FIG. 7</figref>.
0020<figref idref="DRAWINGS">FIG. 9</figref> is a perspective view of a first form of a drain clip of the invention.
0021<figref idref="DRAWINGS">FIG. 10</figref> is a top view of the drain clip of <figref idref="DRAWINGS">FIG. 9</figref>, with mold lock openings formed in the clip.
0022<figref idref="DRAWINGS">FIG. 11</figref> is a bottom view of the subassembly of the die of <figref idref="DRAWINGS">FIGS. 3 and 4</figref> and the clip of <figref idref="DRAWINGS">FIG. 9</figref>.
0023<figref idref="DRAWINGS">FIG. 12</figref> is a cross-section of <figref idref="DRAWINGS">FIG. 11</figref> taken across section line <b>12</b>—<b>12</b> in <figref idref="DRAWINGS">FIG. 11</figref>.
0024<figref idref="DRAWINGS">FIG. 13</figref> shows the subassembly of <figref idref="DRAWINGS">FIGS. 11 and 12</figref> after overmolding in a molding tray.
0025<figref idref="DRAWINGS">FIG. 14</figref> is a cross-section of <figref idref="DRAWINGS">FIG. 13</figref>, taken across section lines <b>14</b>—<b>14</b> in <figref idref="DRAWINGS">FIG. 13</figref>.
0026<figref idref="DRAWINGS">FIG. 15</figref> is a cross-section of <figref idref="DRAWINGS">FIG. 13</figref> taken across section line <b>15</b>—<b>15</b> in <figref idref="DRAWINGS">FIG. 13</figref>.
0027<figref idref="DRAWINGS">FIG. 16</figref> is a perspective view of a further embodiment of a drain clip.
0028<figref idref="DRAWINGS">FIG. 17</figref> is a top view of the clip of <figref idref="DRAWINGS">FIG. 16</figref>.
0029<figref idref="DRAWINGS">FIG. 18</figref> is a bottom view of assembly of the clip of <figref idref="DRAWINGS">FIGS. 16 and 17</figref> with a die of the general kind of that of <figref idref="DRAWINGS">FIGS. 3 and 4</figref> after overmolding.
0030<figref idref="DRAWINGS">FIG. 19</figref> is a cross-section of <figref idref="DRAWINGS">FIG. 18</figref> taken across section line <b>19</b>—<b>19</b> in <figref idref="DRAWINGS">FIG. 18</figref>.
0031<figref idref="DRAWINGS">FIG. 20</figref> is a bottom view of a cup shaped drain clip with a die of the topology of <figref idref="DRAWINGS">FIGS. 7 and 8</figref>.
0032<figref idref="DRAWINGS">FIG. 21</figref> is a cross-section of <figref idref="DRAWINGS">FIG. 20</figref> taken across section lines <b>21</b>—<b>21</b> in <figref idref="DRAWINGS">FIG. 20</figref>.
0033<figref idref="DRAWINGS">FIG. 22</figref> shows a wafer of MOSFET die before singulation.
0034<figref idref="DRAWINGS">FIG. 23</figref> shows process steps for the formation and patterning of a passivation layer on the source surface of the wafer of <figref idref="DRAWINGS">FIG. 22</figref>.
0035<figref idref="DRAWINGS">FIG. 24</figref> shows the metalizing atop the passivation layer of <figref idref="DRAWINGS">FIG. 23</figref>.
DETAILED DESCRIPTION OF THE DRAWINGS
0036The present invention provides a novel package for semiconductor die of the kind having power or other electrodes on opposite surfaces of the die and makes it possible, with low cost manufacturing techniques, to make both electrodes available for surface mounting on a common support surface, for example the metallized pattern on a printed circuit board. While the invention is described with reference to a vertical conduction power MOSFET having the gate and source electrode on one surface and a drain electrode on the opposite surface, the invention is equally applicable to IGBTs, thyristors, diodes and the like of various topologies.
0037Thus, as will be seen, a novel die clip surrounds and contacts at least a portion of the back side electrode (a drain electrode in a MOSFET) and at least one leg of the clip extends over an edge of the die and terminates in a plane which is coplanar with, but insulated from the front surface contacts (gate and source in a MOSFET). The device may then be overmolded around the back and sides of the die and clip to present flat, coplanar solderble contact surfaces for all die electrodes to a mounting surface.
0038All top contact surfaces are formed, using a novel solder mask to form easily solderable contact surfaces on the die top surface, while the die are in the wafer stage. Drain clips are then attached to the die after die singulation and are overmolded in a batch molding process.
0039<figref idref="DRAWINGS">FIG. 1</figref> shows a typical power MOSFET <b>30</b> to which the invention can apply. The die <b>30</b> may be of the type shown in U.S. Pat. No. 5,795,793 but can be any kind of die having a junction containing silicon body <b>31</b>, a top aluminum (that is, aluminum with 1.0% silicon) source electrode <b>32</b>, an aluminum gate electrode <b>33</b> and a bottom drain electrode <b>34</b>, which may be a conventional easily solderable trimetal. The top aluminum layer may be any other suitable metallic material. Connections are normally made to aluminum electrodes <b>32</b> and <b>33</b> by wire bonding.
0040In accordance with the invention and as will be later described, a plurality of easily solderable contact posts <b>36</b> are secured to (formed on) the source electrode <b>32</b> and a contact post <b>37</b> is secured to the gate electrode <b>33</b> as shown in <figref idref="DRAWINGS">FIGS. 3 and 4</figref>. Contacts <b>36</b> and <b>37</b> are sub-flush by the thickness of the passivation in the case of a silver top metal die; and by about one-half the passivation thickness in the case of a plated aluminum top metal die. The flat contact tops are coplanar. Contact to these contact surfaces is made by a solder paste, which at minimum printable solder thickness is about 4 to 5 times as thick as layer <b>38</b>.
0041The pattern of contacts <b>36</b> can take different forms such as those shown in <figref idref="DRAWINGS">FIGS. 5</figref>, <b>11</b> and <b>18</b>. Further, it is also possible to use a large area solderable contact such as source contacts <b>40</b> or <b>41</b>, for the die of <figref idref="DRAWINGS">FIG. 6</figref> and <figref idref="DRAWINGS">FIGS. 7 and 8</figref>. A metallizing process for forming contacts <b>36</b>, <b>37</b> and <b>40</b> shall be later described.
0042In forming the novel package with die prepared as shown in <figref idref="DRAWINGS">FIGS. 3 to 8</figref>, a novel conductive plated (or partly plated) metal clip <b>45</b> of <figref idref="DRAWINGS">FIG. 9</figref> is employed. Clip <b>45</b> may be a copper alloy with at least partially plated silver surfaces where contact to other surfaces is to be made.
0043Clip <b>45</b> has a general “U-shape” with shallow legs <b>46</b> of a length slightly greater than the thickness of die <b>31</b> as measured from the surface <b>47</b> to the free surfaces of columns <b>36</b>, <b>37</b>, plus the thickness of an adhesive used to connect the drain to the plated interior surface <b>47</b> of the flat thin web <b>48</b> of the clip. For example, the clip may have a total thickness along the full length of legs <b>45</b> of 0.7 mm and a length from surface <b>47</b> to the free end of legs <b>46</b> of about 0.39 mm the distance between the legs <b>46</b> depends on the size of the die, and a distance of 5.6 mm has been used for a size 4.6 die of International Rectifier Corporation, with a total width of about 1.5 mm for each of legs <b>46</b>.
0044Mold lock openings <b>48</b> and <b>49</b> may also be formed in the clip <b>45</b> as shown in <figref idref="DRAWINGS">FIG. 10</figref>.
0045In accordance with a feature of the invention, the solderable bottom drain electrode <b>34</b> of the die <b>30</b> is electrically connected to and secured to the plated interior of drain clip <b>45</b> as by a conductive adhesive <b>60</b> as shown in <figref idref="DRAWINGS">FIG. 12</figref>. The adhesive can, for example, be a silver loaded epoxy material which is suitably cured. Gaps <b>61</b> and <b>62</b> are left between the side edges of die <b>30</b> and the opposite sides of legs <b>46</b> of clip <b>45</b>.
0046The structure is dimensioned so that the free surfaces of legs <b>46</b> (the drain connector) and posts <b>36</b> and <b>37</b> are coplanar.
0047Thereafter and as shown in <figref idref="DRAWINGS">FIGS. 13</figref>, <b>14</b> and <b>15</b>, the device of <figref idref="DRAWINGS">FIGS. 11 and 12</figref> is overmolded with mold compound <b>70</b> in a mold tray. Mold compound <b>70</b> lies over the full exposed outer surface of clip <b>45</b>, except for the outer free surfaces of legs <b>46</b>. Mold compound fills into the gaps <b>61</b> and <b>62</b> as shown in <figref idref="DRAWINGS">FIGS. 13 and 15</figref>. The device is now ready for surface mounting to conductive traces on a printed circuit board, which are aligned with contacts <b>36</b>, <b>37</b> and <b>46</b>.
0048<figref idref="DRAWINGS">FIGS. 16 to 19</figref> show a further embodiment of the invention, using a different clip geometry. Thus, the clip <b>80</b> of <figref idref="DRAWINGS">FIGS. 16 and 17</figref> has a web <b>81</b> and three segmented projecting legs <b>82</b>, <b>83</b> and <b>84</b>. A die <b>30</b>, which has projecting contacts <b>36</b> and <b>37</b> is first adhered, at its drain contact (not shown) to web <b>81</b> as shown in <figref idref="DRAWINGS">FIGS. 18 and 19</figref> so that contacts <b>36</b>, <b>37</b> and the free surfaces of drain clip projections <b>82</b>, <b>83</b> and <b>84</b> lie in a common plane. The device is then overmolded with molded compound <b>70</b> in a suitable mold tray.
0049<figref idref="DRAWINGS">FIGS. 20 and 21</figref> show a still further embodiment of the invention in which the die of <figref idref="DRAWINGS">FIGS. 7 and 8</figref> is mounted in a cup-shaped clip <b>100</b> which is a silver plated copper alloy. Clip <b>100</b> has an internal area greater in length and width than the die <b>30</b>, and, the bottom drain electrode of die <b>30</b> is connected to the interior web surface <b>101</b> (<figref idref="DRAWINGS">FIG. 21</figref>) by silver loaded (conductive) epoxy <b>102</b>. The epoxy is cured. Optimally, a ring of low stress high adhesion epoxy <b>103</b> may be applied around the die edge, sealing the package and adding structural strength to the package.
0050The top surface of solderable contact <b>40</b> is coplanar with drain clip projection surfaces <b>105</b>. Thus, all of contacts <b>105</b>, <b>40</b> and <b>37</b> will align with contact traces on a printed circuit board. The drain contacts may take any suitable form and could comprise a single contact er side, if desired.
0051<figref idref="DRAWINGS">FIGS. 22 to 24</figref> show a novel process for forming conductive posts on the aluminum electrodes of conventional die. Thus, a plurality of identical die, each having a gate electrode <b>37</b> and separate source electrodes (not numbered) are shown within wafer <b>110</b> prior to die singulation. While still in wafer form, the top surface of the wafer <b>110</b> is coated with a photoimagable solder mask <b>111</b>. Mask <b>111</b> is a photosensitive liquid epoxy which will act as a passivation layer, a plating resist (if required) and a solder mask designating and shaping the solder areas. However, other mask materials, for example, silicon nitride, can be used. Using a conventional reticule, multiple openings <b>111</b><i>a </i>to <b>111</b> dare formed through the mask to the underlying source and gate contacts on the die top metal. A laser etch process can also be used to form these openings.
0052As shown in <figref idref="DRAWINGS">FIG. 24</figref>, a series of metals <b>112</b> are then plated atop the surface of the wafer and the plating adheres to the metal of source <b>32</b> (and other electrodes) which are exposed through openings <b>111</b><i>a </i>to <b>111</b><i>b</i>, forming contacts <b>112</b><i>a </i>to <b>112</b><i>d </i>with the source and a similar contact to the gate. Metals <b>112</b><i>a </i>to <b>112</b><i>d </i>can consist of a first layer of nickel which makes good contact to the aluminum, followed by a gold flash. Alternatively, the nickel can be followed by layers of copper or tin, and the like, ending with an easily solderable metal top surface such a silver.
0053The wafer is then sawn to separate the die at lines <b>112</b> and <b>113</b> for example, and the die are singulated. The typical die <b>30</b> has the appearance shown in <figref idref="DRAWINGS">FIGS. 3 to 8</figref> and has a plurality of solderable source contacts and gate contacts which project above insulation surface <b>50</b>.
0054The singulated die are then placed drain source-side down, into conductive clips which are plated on their interior as with silver or some other conductive coating. The die is bonded to the clip, using conventional bond material such as a conductive epoxy as previously described. The clips/cans can be presented in the form of a lead frame and the devices can be later singulated from the lead frame.
0055Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
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49 members in 8 offices
Priority claims2
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| WO0175961A8 | World Intellectual Property Organization (WIPO) | A8 | |
| TW503487B | Taiwan Province of China | B | |
| EP1287553A1 | European Patent Office (EPO) | A1 | |
| TW200301553A | Taiwan Province of China | A | |
| CN1430791A | China | A | |
| US2003132531A1 | United States of America | A1 | |
| WO03060984A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO03060984A1 | World Intellectual Property Organization (WIPO) | A1 | |
| AU2002361873A1 | Australia | A1 | |
| US6624522B2 | United States of America | B2 | |
| JP2004500720A | Japan | A | |
| US2004026796A1 | United States of America | A1 | |
| US2004038509A1 | United States of America | A1 | |
| HK1057648A1 | Hong Kong, China | A1 | |
| US2004104489A1 | United States of America | A1 | |
| US6767820B2 | United States of America | B2 | |
| EP1466357A1 | European Patent Office (EPO) | A1 | |
| US2004224438A1 | United States of America | A1 | |
| CN1605121A | China | A | |
| US6890845B2 | United States of America | B2 | |
| JP2005515635A | Japan | A | |
| US6930397B2 | United States of America | B2 | |
| US2005186707A1 | United States of America | A1 | |
| US2005224960A1 | United States of America | A1 | |
| JP2005354105A | Japan | A | |
| JP3768158B2 | Japan | B2 | |
| US2006220123A1 | United States of America | A1 | |
| US7119447B2 | United States of America | B2 | |
| US7122887B2This record | United States of America | B2 | |
| US2007012947A1 | United States of America | A1 | |
| TWI278076B | Taiwan Province of China | B | |
| CN1316577C | China | C | |
| US7253090B2 | United States of America | B2 | |
| EP1466357A4 | European Patent Office (EPO) | A4 | |
| US7285866B2 | United States of America | B2 | |
| EP1287553A4 | European Patent Office (EPO) | A4 | |
| JP2007295014A | Japan | A | |
| US7397137B2 | United States of America | B2 | |
| US2008246127A1 | United States of America | A1 | |
| US7476979B2 | United States of America | B2 | |
| JP2009105437A | Japan | A | |
| US7579697B2 | United States of America | B2 | |
| JP4343158B2 | Japan | B2 | |
| CN100559557C | China | C | |
| JP4535730B2 | Japan | B2 | |
| EP1466357B1 | European Patent Office (EPO) | B1 |
49 transactions on the USPTO file
Allowed after 1 non-final rejection and 1 final rejection.
- Non-final rejections
- 1
- Final rejections
- 1
- RCEs
- 0
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Payment of Maintenance Fee, 12th Year, Large EntityM1553 | M1553 | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Mail Miscellaneous Communication to ApplicantMM327 | MM327 | |
| Miscellaneous Communication to Applicant - No Action CountM327 | M327 | |
| Mail Miscellaneous Communication to ApplicantMM327 | MM327 | |
| Miscellaneous Communication to Applicant - No Action CountM327 | M327 | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Pubs Case Remand to TCPUBTC | PUBTC | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Final ActionA.NE | A.NE | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Miscellaneous Incoming LetterLET. | LET. | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Application Is Now CompleteCOMP | COMP | |
| Application Return from OIPEWROIPE | WROIPE | |
| Application Is Now CompleteCOMP | COMP | |
| Application Return TO OIPEROIPE | ROIPE | |
| Application Is Now CompleteCOMP | COMP | |
| Application Is Now CompleteCOMP | COMP | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Initial Exam Team nnIEXX | IEXX |
5 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| AssignmentAS | AS | |
| Maintenance fee paymentMAFP | MAFP | |
| Fee paymentFPAY | FPAY | |
| Fee paymentFPAY | FPAY | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF |
Numbers
- Publication
- 7122887
- Application
- 10634447
Titles
- English
- Chip scale surface mounted device and process of manufacture
Patent term adjustment
- A delay
- +206 daysthe office missed an examination deadline
- Applicant delay
- −78 days
- Net adjustment
- 128 days
Classification
- CPC, 14
- H10W70/20
- H10W74/129
- H10W74/111
- H10W46/00
- H10W90/736
- H10W72/01255
- H10W72/325
- H10W72/354
- H10W72/352
- H10W72/07234
- H10W72/07236
- H10W72/074
- H10W46/607
- H10W72/856
- IPC, 7
- H01L23 48
- H01L21 52
- H01L21 60
- H10W40 60
- H10W46 00
- H10W70 20
- H10W70 60