Display device and driving method of the same

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a matrix type display device that uses electric current as transmitting signal, and a driving method thereof.

2. Description of the Related Art

The matrix type display device such as a liquid crystal display device and a plasma display panel (also referred to as PDP) is provided with a display controller that sequentially outputs image data, a source driver that generates a drive signal for driving a display panel based on the image data output from the display controller, and a display panel that displays an image by the drive signal.

In such a display device, the signal between the display controller and the source driver has conventionally been transmitted by a voltage signal that consists of two values of power source potential and earth potential. However, parasitic capacitance of transmission path causes delay if the voltage signal is made to be high-speed, and the level of high-speed voltage signal is limited.

The applicant then developed a technique of transmitting a signal by electric current, which is disclosed in Japanese Patent Application Laid-open No. 2001-053598. This technique restricts the affect of the parasitic capacitance of the transmission path, and the high-speed signal can be realized. Further, Japanese Patent Application Laid-open No. 2001-053598 also discloses a technique that a power source is not provided for a transmission section but for a receiving section. Thus, it is not necessary to change the specification of the transmission section even if the number of the receiving sections is changed, and the design of the transmission section becomes easy.

Specifically, a pair of wirings for transmitting signal is provided between the transmission section and the receiving section. Then, in the transmission section, one of the wirings is connected to an earth electrode and the other wiring is set to a floating state (high-impedance state) based on a signal intended to transmit. Accordingly, electric current flows from the power source provided for the receiving section to the earth electrode via the wiring connected to the earth electrode and the electric current does not flow to the other wiring. As a result, it is possible to transmit a complementary signal by a pair of the wirings. The applicant has named the transmission method as CMADS (Current Mode Advanced Differential Signaling).

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram showing a conventional liquid crystal display device for which the CMADS was applied. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the conventional liquid crystal display device is provided with a display controller <b>101</b>, a source driver <b>102</b>, and a liquid crystal panel <b>103</b>. Further, two pairs of wirings <b>104</b><i>a </i>and <b>104</b><i>b</i>, <b>105</b><i>a </i>and <b>105</b><i>b </i>are provided between the display controller <b>101</b> and the source driver <b>102</b>.

The display controller <b>101</b> is one to which image data as digital two-value voltage signal is input from outside and that outputs the image data by every line. The display controller <b>101</b> is provided with a display data memory <b>106</b>, a timing control circuit <b>107</b>, a V-I conversion circuit for image data <b>108</b>, and a V-I conversion circuit for clock signal <b>109</b>. The display data memory <b>106</b> is one to which the image data is input from outside and that holds the image data for one screen. The timing control circuit <b>107</b> reads out the image data equivalent to one line from the display data memory <b>106</b>, outputs a clock signal to the V-I conversion circuit for clock signal <b>109</b>, and sequentially outputs the image data equivalent to one line to the V-I conversion circuit for image data <b>108</b> synchronously with the clock signal. The V-I conversion circuit for image data <b>108</b> is connected to one end of a pair of the wirings <b>104</b><i>a </i>and <b>104</b><i>b</i>, in which either one of the wirings <b>104</b><i>a </i>and <b>104</b><i>b </i>is connected to the earth electrode and the other wiring is set to the floating state based on the image data. The V-I conversion circuit for clock signal <b>109</b> is connected to one end of a pair of the wirings <b>105</b><i>a </i>and <b>105</b><i>b</i>, in which either one of the wirings <b>105</b><i>a </i>and <b>105</b><i>b </i>is connected to the earth electrode and the other wiring is set to the floating state based on the clock signal.

Furthermore, the source driver <b>102</b> is provided with an I-V conversion circuit for image data <b>121</b>, an I-V conversion circuit for clock signal <b>122</b>, a shift register <b>123</b>, a data latch circuit <b>124</b>, a gradation selecting circuit <b>125</b>, and an output circuit <b>126</b>. The I-V conversion circuit for image data <b>121</b> is connected to the other end of a pair of the wirings <b>104</b><i>a </i>and <b>104</b><i>b</i>. Then, when the V-I conversion circuit for image data <b>108</b> connects either one of the wirings <b>104</b><i>a </i>and <b>104</b><i>b </i>to the earth electrode, The I-V conversion circuit for image data <b>121</b> allows electric current to flow in the wiring connected to the earth electrode to generate a complementary current signal in a pair of the wirings <b>104</b><i>a </i>and <b>104</b><i>b</i>. Consequently, the I-V conversion circuit for image data <b>121</b> receives the image data as the current signal from the V-I conversion circuit for image data <b>108</b>. Then, the I-V conversion circuit for image data <b>121</b> converts the image data again into the two-valued voltage signal based on the current signal, and outputs the signal to the data latch circuit <b>124</b>. The I-V conversion circuit for clock signal <b>122</b> is connected to the other end of a pair of the wirings <b>105</b><i>a </i>and <b>105</b><i>b</i>. Then, when the V-I conversion circuit for clock signal <b>109</b> connects either one of the wirings <b>105</b><i>a </i>and <b>105</b><i>b </i>to the earth electrode, the I-V conversion circuit for clock signal <b>122</b> allows electric current to flow in the wiring connected to the earth electrode to generate the complementary current signal in a pair of the wirings <b>105</b><i>a </i>and <b>105</b><i>b</i>. Consequently, the I-V conversion circuit for clock signal <b>122</b> receives the clock signal as the current signal from the V-I conversion circuit for clock signal <b>109</b>. Then, the I-V conversion circuit for clock signal <b>122</b> converts the clock signal again into the two-valued voltage signal based on the current signal, and outputs the signal to the shift register <b>123</b>.

The shift register <b>123</b> is one to which the clock signal is input and that sequentially outputs pulse signals from a plurality of output terminals to the data latch circuit <b>124</b>. The data latch circuit <b>124</b> downloads a plural image data synchronously with the pulse signals to output a plurality of the image data to the gradation selecting circuit <b>125</b> simultaneously. The gradation selecting circuit <b>125</b> is a D/A converter, which performs digital-analog conversion (D/A conversion) to the output signal from the data latch circuit <b>124</b> and outputs a gradation signal that is an analog voltage signal to an output circuit <b>126</b>. The voltage of the gradation signal is a voltage applied for each pixel of the liquid crystal panel <b>103</b>. The output circuit <b>126</b> performs current amplification to the gradation signal to generate a drive signal, and outputs the drive signal to each pixel of the liquid crystal panel <b>103</b>.

Moreover, the liquid crystal panel <b>103</b> is provided with two transparent substrates (not shown) arranged facing with each other, a liquid crystal layer (not shown) sandwiched between the transparent substrates, and a backlight (not shown) arranged behind the two transparent substrates. Further, pixels (not shown) are arranged in a matrix state on the liquid crystal panel <b>103</b>.

Next, description will be made for the operation of the conventional liquid crystal display device. Firstly, the image data as the two-valued voltage signal is input to the display data memory <b>106</b>, and the data equivalent to one screen is held. Then, the timing control circuit <b>107</b> reads out the image data equivalent to one line from the display data memory <b>106</b>. The timing control circuit <b>107</b> then outputs the clock signal that is the two-valued voltage signal to the V-I conversion circuit for clock signal <b>109</b>. Further, the timing control circuit <b>107</b> sequentially outputs the image data to the V-I conversion circuit for image data <b>108</b> synchronously with the clock signal.

Next, the V-I conversion circuit for image data <b>108</b> connects one end of a pair of the wirings <b>104</b><i>a </i>and <b>104</b><i>b </i>to the earth electrode and sets the other wiring to the floating state based on the image data. For example, the wiring <b>104</b><i>a </i>is connected to the earth electrode and the wiring <b>104</b><i>b </i>is set to the floating state when the image data is high, and the wiring <b>104</b><i>a </i>is set to the floating state and the wiring <b>104</b><i>b </i>is connected to the earth electrode when the image data is low. Further, the V-I conversion circuit for clock signal <b>109</b> connects one end of a pair of the wirings <b>105</b><i>a </i>and <b>105</b><i>b </i>to the earth electrode and sets the other wiring to the floating state based on the clock signal.

Accordingly, the I-V conversion circuit for image data <b>121</b> allows electric current to flow in either wiring of a pair of the wirings <b>104</b><i>a </i>and <b>104</b><i>b</i>, which is connected to the earth electrode. The electric current flows from the I-V conversion circuit for image data <b>121</b> to the earth electrode via the wiring <b>104</b><i>a </i>or <b>104</b><i>b</i>. On the other hand, the electric current does not flow in the wiring on the floating state. As a result, the image data that is the voltage signal is converted into a pair of complementary current signals, and is transmitted from the V-I conversion circuit for image data <b>108</b> to the I-V conversion circuit for image data <b>121</b> via a pair of the wirings <b>104</b><i>a </i>and <b>104</b><i>b</i>. Then, the I-V conversion circuit for image data <b>121</b> converts the current signal into the two-valued voltage signal again to regenerate the image data, and outputs the data to the data latch circuit <b>124</b>.

Similarly, the I-V conversion circuit for clock signal <b>122</b> allows the electric current to flow in either wiring of a pair of the wirings <b>105</b><i>a </i>and <b>105</b><i>b</i>, which is connected to the earth electrode. On the other hand, the electric current does not flow in the wiring on the floating state. As a result, the clock signal that is the voltage signal is converted into a pair of complementary current signals, and is transmitted from the V-I conversion circuit for clock signal <b>109</b> to the I-V conversion circuit for clock signal <b>122</b> via a pair of the wirings <b>105</b><i>a </i>and <b>105</b><i>b</i>. Then the I-V conversion circuit for clock signal <b>122</b> converts the current signal into the two-valued voltage signal again to regenerate the clock signal, and outputs the signal to the shift register <b>123</b>.

The shift register <b>123</b> downloads the clock signal from the I-V conversion circuit for clock signal <b>122</b>, and sequentially outputs the pulse signal from a plurality of output terminals to the data latch circuit <b>124</b>. The data latch circuit <b>124</b> downloads a plurality of image data from the I-V conversion circuit for image data <b>121</b> synchronously with the pulse signal, and simultaneously outputs a plurality of the image data to the gradation selecting circuit <b>125</b>. Next, the gradation selecting circuit <b>125</b> performs D/A conversion to the output signal to generate the gradation signal that is the analog voltage signal, and outputs the signal to the output circuit <b>126</b>. Then, the output circuit <b>126</b> performs current amplification to the gradation signal to generate the drive signal, and applies it to each pixel of the liquid crystal panel <b>103</b>.

On the other hand, in the liquid crystal panel <b>103</b>, the backlight irradiates light to each pixel. Then, the liquid crystal layer of each pixel changes transmission factor of light according to the voltage of the drive signal applied, forms an image as the entire liquid crystal panel <b>103</b>.

However, the above-described prior art has the following problems. Recently, a small display device such as a cellular phone in particular is normally equipped with a function such as a subtractive color mode to economize image data amount. The function subtracts colors of the image data from 260,000 colors to 8 colors, for example, and thus reducing the image data amount from 18 bits to 3 bits. In addition, a technique to encode and compress the image data has generally been used.

In the case of reducing the image data amount, dummy transfer is performed in signal transfer between the display controller and the source driver other than the data necessary for displaying the image. At this point, when the image data is transmitted by the voltage signal as conventionally performed, power consumption can be reduced by reducing the image data amount. However, when the image data is transmitted by the current signal, the electric current continuously flows in the wiring between the display controller and the source driver during the dummy transfer, and there exists a problem that the effects to reduce the power consumption is not obtained.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a display device in which high-speed signal transmission and reduction of power consumption can be realized, and a driving method thereof.

A display device according to the present invention comprises a pair of or plural pairs of wirings for image data, a display controller that is connected to one end of the wirings for image data and outputs the image data by connecting either one of each pair of wirings for image data to a reference potential terminal and setting the other one to a floating state based on the image data, a source driver that is connected to the other end of the wirings for image data, generates a pair of or plural pairs of complementary current signals based on the image data by allowing electric current to flow in the wiring connected to the reference potential terminal out of a pair of or plural pairs of the wirings for image data and generates a drive signal based on the current signal when the display controller outputs the image data, and does not allow the electric current to flow in both of the wirings for image data when the display controller stops outputting the image data, and a display panel which displays an image based on the drive signal.

In the present invention, by generating the complementary current signal based on the image data, the current signal transmits through the wirings for image data. Thus, it is possible to transmit the image data in a high-speed. Further, when the display controller connects neither one of each pair of the wirings for image data to the reference potential terminal and does not set the other one to the floating state based on the image data, that is, when the output of the image data is stopped, the power consumption can be reduced by not allowing the electric current to flow in both of the wirings for image data.

Further, it is preferable that the display device have a pair of wirings for clock signal, the display controller be connected to one end of the wirings for clock signal, output the clock signal by connecting either one of a pair of the wirings for clock signal to the reference potential terminal and setting the other one to the floating state based on a clock signal, the source driver be connected to the other end of the wirings for clock signal, generate a pair of complementary current signals based on the clock signal by allowing electric current to flow in the wiring connected to the reference potential terminal out of a pair of the wirings for clock signal when the display controller outputs the clock signal, and do not allow the electric current to flow in both of the wirings for clock signal when the display controller does not output the clock signal.

Thus, by generating the complementary current signal based on the clock signal, the current signal transmits through the wirings for clock signal. Thus, it is possible to transmit the clock signal in a high-speed. In addition, when the output of the clock signal is stopped, it is possible to reduce power consumption by not allowing the electric current to flow in both of the wirings for clock signal.

Moreover, the display controller may have a timing control circuit that outputs a receiver control signal showing whether the display controller is outputting the image data or stops outputting the image data and an image data switching circuit that connects either one of each pair of the wirings for image data to the reference potential terminal and sets the other one to the floating state based on the image data output from the timing control circuit. And the source driver, when the receiver control signal shows that the display controller is outputting the image data, may generate a pair of or plural pairs of complementary current signals based on the image data by allowing the electric current to flow in the wiring connected to the reference potential terminal out of a pair of or plural pairs of the wirings for image data and regenerate the image data based on the current signal, and may stop allowing the electric current to flow in the wirings for image data connected to the reference potential terminal when the receiver control signal shows that the display controller stops outputting the image data.

Alternatively, the source driver may have a clock signal conversion circuit that generates a pair of complementary current signals based on the clock signal by allowing the electric current to flow in the wiring connected to the reference potential terminal out of a pair of the wirings for clock signal and regenerates the clock signal based on the current signal, and a detecting circuit for clock signal stop that detects whether the clock signal conversion circuit generates the current signal based on the clock signal or not, and may determine according to a detection result whether the display controller is outputting the clock signal or stops outputting the clock signal.

Alternatively, the display controller may have a timing control circuit that reads the image data of a predetermined amount to sequentially output the image data, a data comparing circuit that compares a predetermined amount of image data that the timing control circuit has read before one drive timing with a predetermined amount of image data currently read and outputs a result to the timing control circuit, and an image data switching circuit that connects either one of each pair of the wirings for image data to the reference potential terminal and sets the other one to the floating state based on the image data output from the timing control circuit. And, the timing control circuit may output the receiver control signal showing whether the display controller is outputting the image data or has stopped outputting the image data based on the comparison result of the data comparing circuit, and the source driver, when the receiver control signal shows that the display controller is outputting the image data, may generate a pair of or plural pairs of complementary current signals based on the image data by allowing the electric current to flow in the wiring connected to the reference potential terminal out of a pair of or plural pairs of the wirings for image data and regenerates the image data based on the current signal, and may stop allowing the electric current to flow in the wirings for image data connected to the reference potential terminal when the receiver control signal shows that the display controller stops outputting the image data.

Another display device according to the present invention has the wirings for image data, the display controller connected to one end of the wirings for image data, the source driver that is connected to the other end of the wirings for image data and generates the drive signal based on the image data sent out to the wirings for image data, and the display panel that displays an image based on the drive signal, and the display controller adjusts the frequency of the image data according to the display mode of the image.

In the present invention, by adjusting the frequency of the current signal according to the display mode, it is possible to lower the frequency of the current signal when the image data amount is small. Thus, the power consumption can be reduced.

Further, the display controller may have a mode register that outputs the control signal according to the display mode of image, and the timing control circuit that sequentially outputs the image data by a frequency adjusted based on the control signal and outputs the receiver control signal showing the display mode of the image. And the source driver may generate the drive signal based on the display mode of the image that the receiver control signal shows. Furthermore, a pair of or plural pairs of the wirings for image data may be provided, the display controller may have an image data switching control circuit that connects either one of each pair of the wirings for image data to the reference potential terminal and sets the other one to the floating state based on the image data, and the source driver may generate a pair of or plural pairs of complementary current signals based on the image data by allowing the electric current to flow in the wiring connected to the reference potential terminal out of the wirings for image data, may generate the drive signal based on the current signals, and may control the magnitude of the electric current allowed to flow in the wirings for image data according to the display mode of the image that the receiver control signal shows. Consequently, since a current value necessary for transmitting the current signal reduces in the display mode such as the subtractive color mode having smaller image data, the current value can be lowered. As a result, it is possible to restrict power consumption.

Further, the display panel may be a liquid crystal display panel, a plasma display panel, or an organic EL (Electro Luminescence) display panel.

The driving method of the display device according to the present invention has steps of: connecting either one of each pair of a pair of or plural pairs of the wirings for image data to the reference potential terminal to allow the electric current to flow and setting the other one to the floating state based on the image data to generate a pair of or plural pairs of complementary current signals based on the image data or not allowing the electric current to flow in both of the wirings for image data; generating the drive signal based on the current signal; and displaying an image based on the drive signal.

Another driving method of the display device according to the present invention comprises the steps of: generating a pair of complementary current signals based on the clock signal by connecting either one of a pair of wirings for clock signal to the reference potential terminal to allow the electric current to flow and setting the other one to the floating state based on the clock signal, generating a pair of a pair of or plural pairs of complementary current signals based on the image data by connecting either one of each pair of or plural pairs of wirings for image data to the reference potential terminal to allow the electric current to flow and setting the other one to-the floating state based on the image data, or not allowing the electric current to flow in both of the wirings for clock signal and the wirings for image data; generating the drive signal based on the current signal; and displaying an image based on the drive signal.

According to the present invention, as described above, when the image data is transmitted between the display controller and the source driver in the display device, the high-speed signal transmission and the reduction of power consumption can be realized by transmitting the image data by the current signal and stopping the electric current when the image data is not transmitted.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram showing a conventional liquid crystal display device to which CMADS is applied.

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 3</figref> is a circuit diagram showing a V-I conversion circuit for image data of the liquid crystal display device shown in <figref idref="DRAWINGS">FIG. 2</figref>.

<figref idref="DRAWINGS">FIG. 4</figref> is a circuit diagram showing an I-V conversion circuit for image data of the liquid crystal display device shown in <figref idref="DRAWINGS">FIG. 2</figref>.

<figref idref="DRAWINGS">FIG. 5</figref> is a timing chart showing the driving method of the liquid crystal display device according to the first embodiment.

<figref idref="DRAWINGS">FIG. 6</figref> is a timing chart showing the operation of the V-I conversion circuit for image data and the I-V conversion circuit for image data according to the first embodiment.

<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram showing the liquid crystal display device according to a second embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 8</figref> is a timing chart showing the driving method of the liquid crystal display device according to the second embodiment.

<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram showing the liquid crystal display device according to a third embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 10</figref> is a timing chart showing the driving method of the liquid crystal display device according to the third embodiment.

<figref idref="DRAWINGS">FIG. 11</figref> is a block diagram showing the liquid crystal display device according to a fourth embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 12</figref> is a timing chart showing the driving method of the liquid crystal display device according to the fourth embodiment.

<figref idref="DRAWINGS">FIG. 13</figref> is a graph showing the relationship between the maximum frequency of current signal and necessary current by setting the maximum frequency fmax of electric current to be transmitted to the axis of abscissas and a constant current value necessary for transmitting the current signal of the maximum frequency to the axis of ordinate.

<figref idref="DRAWINGS">FIG. 14</figref> is a block diagram showing the liquid crystal display device according to a fifth embodiment of the present invention.

<figref idref="DRAWINGS">FIG. 15</figref> is a block diagram showing a plasma display panel (PDP) according to a sixth embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings. The first embodiment of the present invention will be described first. <figref idref="DRAWINGS">FIG. 2</figref> is the block diagram showing the liquid crystal display device according to the embodiment, <figref idref="DRAWINGS">FIG. 3</figref> is the circuit diagram showing the V-I conversion circuit for image data of the liquid crystal display device shown in <figref idref="DRAWINGS">FIG. 2</figref>, and <figref idref="DRAWINGS">FIG. 4</figref> is the circuit diagram showing the I-V conversion circuit for image data of the liquid crystal display device shown in <figref idref="DRAWINGS">FIG. 2</figref>. The liquid crystal display device according to the embodiment is the liquid crystal display device to which the CMADS is applied.

As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the liquid crystal display device according to the embodiment is provided with a display controller <b>1</b>, a source driver <b>2</b>, and a liquid crystal panel <b>3</b>. Further, two pairs of wirings <b>4</b><i>a </i>and <b>4</b><i>b</i>, <b>5</b><i>a </i>and <b>5</b><i>b </i>are provided between the display controller <b>1</b> and the source driver <b>2</b>, and a wiring <b>11</b> is further provided. Note that the number of the source driver <b>2</b> depends on the size of the liquid crystal panel <b>3</b> and the performance of the source driver <b>2</b>. For example, <b>1</b> source driver is provided for the display device including a small liquid crystal panel such as a cellular phone, and approximately 10 to 12 source drivers are provided for a large display, for example.

The display controller <b>1</b> is one to which the image data as digital two-value voltage signal is input from outside and that outputs the image data by every line of an image. The display controller <b>1</b> is provided with a display data memory <b>6</b>, a timing control circuit <b>7</b>, a V-I conversion circuit for image data <b>8</b>, a V-I conversion circuit for clock signal <b>9</b>, and a mode register <b>10</b>. The display data memory <b>6</b> is one to which the image data is input from outside and that holds the image data of a certain amount that is the image data for one screen, for example. The mode register <b>10</b> is one to which data regarding the display mode of an image such as the subtractive color mode is input, for example, and that outputs the control signal to the display data memory <b>6</b> and the timing control circuit <b>7</b> in response to the display mode. Input terminals are provided for the display data memory <b>6</b> and the mode register <b>10</b>.

The timing control circuit <b>7</b> reads out the image data for a certain amount, that is, the image data equivalent to one line from the display data memory <b>6</b> based on the control signal output from the mode register <b>10</b>, outputs the clock signal to the V-I conversion circuit for clock signal <b>9</b>, sequentially outputs the image data equivalent to one line to the V-I conversion circuit for image data <b>8</b> based on the control signal synchronously with the clock signal, and further outputs the receiver control signal, which shows whether the clock signal and the image data are being output or not, to the source driver <b>2</b> via the wiring <b>11</b>. Further, the timing control circuit <b>7</b> outputs a signal STH that activates the source driver <b>2</b>. The signal STH is transmitted to the source driver <b>2</b> via a wiring (not shown).

As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the V-I conversion circuit for image data <b>8</b> is provided with an input terminal T<b>1</b>, two inverters INV<b>1</b>, INV<b>2</b>, two N-channel type MOS transistors Qn<b>9</b>, Qn<b>10</b>, and earth electrodes GND<b>1</b>, GND<b>2</b>. The input terminal of the inverter INV<b>1</b> is connected to the input terminal T<b>1</b>, and the output terminal is connected to the input terminal of the inverter INV<b>2</b> and the gate of the transistor Qn<b>9</b>. The output terminal of the inverter INV<b>2</b> is connected to the gate of the transistor Qn<b>10</b>. Further, the drain and the source of the transistor Qn<b>9</b> are connected to the wiring <b>4</b><i>a </i>and the earth electrode GND<b>1</b> respectively, and the drain and the source of the transistor Qn<b>10</b> are connected to the wiring <b>4</b><i>b </i>and the earth electrode GND<b>2</b> respectively. The V-I conversion circuit for image data <b>8</b> is an image data switching circuit.

The configuration of the V-I conversion circuit for clock signal <b>9</b> is the same as the configuration of the V-I conversion circuit for image data <b>8</b>, which is connected to one end of a pair of the wirings <b>5</b><i>a</i>, <b>5</b><i>b</i>, and either one of a pair of the wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>is connected to an earth electrode (not shown) and the other one is set to the floating state based on the clock signal.

The source driver <b>2</b> is provided with an I-V conversion circuit for image data <b>21</b>, an I-V conversion circuit for clock signal <b>22</b>, a shift register <b>23</b>, a data latch circuit <b>24</b>, a gradation selecting circuit <b>25</b>, and an output circuit <b>26</b>.

As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the I-V conversion circuit for image data <b>21</b> is provided with a bias terminal T<b>2</b>, an input terminal T<b>3</b> connected to the wiring <b>4</b><i>a</i>, an input terminal T<b>4</b> connected to the wiring <b>4</b><i>b</i>, an input terminal T<b>5</b> connected to the wiring <b>11</b>, and an output terminal T<b>6</b>. Further, the I-V conversion circuit for image data <b>21</b> is provided with P-channel type MOS transistors Qp<b>1</b> to Qp<b>6</b>, N-channel type MOS transistors Qn<b>1</b> to Qn<b>8</b>, NAND gates with two outputs NAND<b>1</b>, NAND<b>2</b>, and an inverter INV<b>3</b>. The transistor Qp<b>5</b> constitutes a current detecting section <b>27</b>, the transistors Qp<b>6</b>, Qp<b>7</b>, Qp<b>8</b> constitute a potential control section <b>28</b>, the transistors Qp<b>1</b>, Qn<b>1</b>, Qp<b>3</b>, Qn<b>3</b> constitute a first current supply section, and the transistors Qp<b>2</b>, Qn<b>2</b>, Qp<b>4</b>, Qn<b>4</b> constitute a second current supply section. Each of the transistors Qp<b>1</b> to Qp<b>4</b> constitutes a constant current source, and each of the transistors Qn<b>1</b> to Qn<b>4</b> constitutes a switching transistor. In other words, a pair of the constant current source and switching transistor is provided for each current supply source. Further, NAND gates NAND<b>1</b>, NAND<b>2</b> and the inverter INV<b>3</b> constitute an RS latch circuit <b>29</b>.

The source of the transistor Qp<b>5</b> and the gates of the transistors Qn<b>7</b>, Qn<b>8</b> are connected to a power source electrode VDD<b>1</b>. The gates of the transistors Qp<b>5</b>, Qn<b>5</b>, Qn<b>6</b> are connected to the bias terminal T<b>2</b>. The drain of the transistor Qp<b>5</b> and the sources of the transistors Qp<b>1</b> to Qp<b>4</b>, Qp<b>6</b> are connected to a node Nc.

The sources of the transistors Qn<b>5</b>, Qn<b>6</b>, Q<b>8</b> and the gate of the transistor Qp<b>6</b> are connected to a switch Si, and the switch S<b>1</b> is designed to be connected to an earth electrode GND<b>3</b> or a power source electrode VDD<b>2</b>. Specifically, the switch S<b>1</b> is designed to select whether the source of the transistor Qn<b>8</b> is made to connect to the earth electrode GND<b>3</b> or to the power source electrode VDD<b>2</b> by the receiver control signal entered via the wiring <b>11</b> and the input terminal T<b>5</b>. By connecting the source of the transistor Qn<b>8</b> to the earth electrode GND<b>3</b>, the first current supply section and the second current supply section operate, and the electric current is allowed to flow either to the first current supply section or the second current supply section. By connecting the source of the transistor Qn<b>8</b> to the power source electrode VDD<b>2</b>, the operation of the first current supply section and the second current supply section stops, and the electric current is not allowed to flow both to the first and second current supply sections. Note that there exists another method to stop the operation of the first and second current supply sections. For example, a node Nd may be connected to the earth electrode, or the bias terminal T<b>2</b> may be connected to the power source electrode.

The drains of the transistors Qp<b>1</b>, Qn<b>1</b> are connected to the gates of the transistors Qp<b>1</b>, Qp<b>2</b>. The gates of the transistors Qn<b>1</b> to Qn<b>4</b> and the drains of the transistors Qp<b>6</b>, Qp<b>7</b> are connected to the node Nd. The sources of the transistors Qn<b>1</b>, Qn<b>3</b> and the drains of the transistor Qn<b>5</b> are connected to the input terminal T<b>3</b>. The sources of the transistors Qn<b>2</b>, Qn<b>4</b> and the drains of the transistor Qn<b>6</b> are connected to the input terminal T<b>4</b>. The drains of the transistors Qp<b>2</b>, Qn<b>2</b> and one input terminal of the NAND gate NAND<b>1</b> that is a reset input of the RS latch circuit <b>29</b> are connected to a node Na.

The drains of the transistors Qp<b>3</b>, Qn<b>3</b> and one input terminal of the NAND gate NAND<b>2</b> that is a set input of the RS latch circuit <b>29</b> are connected to a node Nb. The drains of the transistors Qp<b>4</b>, Qn<b>4</b> are connected to the gates of the transistors Qp<b>3</b>, Qp<b>4</b>. The source of the transistor Qn<b>7</b> is connected to the drain of the transistor Qp<b>8</b>. The output terminal of the NAND gate NAND<b>1</b> is connected to the other input terminal of the NAND gate NAND<b>2</b> and the input terminal of the inverter INV<b>3</b>, and the output terminal of the NAND gate NAND<b>2</b> is connected to the other input terminal of the NAND gate NAND<b>1</b>. The output terminal of the inverter INV<b>3</b> that is the output terminal of the RS latch circuit <b>29</b> is an output terminal T<b>6</b> of the I-V conversion circuit for image data <b>21</b>. Note that the potential of nodes Na, Nb, Nc, Nd are potential Va, Vb, Vc and Vd, respectively.

The configuration of the I-V conversion circuit for clock signal <b>22</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> is the same as the configuration of the I-V conversion circuit for image data <b>21</b>, which is connected to a pair of the wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>and the wiring <b>11</b>.

The shift register <b>23</b> is one to which the clock signal is input from the I-V conversion circuit for clock signal <b>22</b> and that sequentially outputs the pulse signal from a plurality of output terminals (not shown) to the data latch circuit <b>24</b>. The signal STH to start downloading the clock signal is also input to the shift register <b>23</b>. The data latch circuit <b>24</b> downloads a plural image data from the I-V conversion circuit for image data <b>21</b> synchronously with the pulse signal to output simultaneously a plurality of the image data to the gradation selecting circuit <b>25</b>. The gradation selecting circuit <b>25</b> is the D/A converter, which performs D/A conversion to the output signal from the data latch circuit <b>24</b> to generate the gradation signal that is an analog voltage signal and outputs the signal to the output circuit <b>26</b>. The voltage of the gradation signal is the voltage applied for each pixel of the liquid crystal panel <b>3</b>. The output circuit <b>26</b> performs current amplification to the gradation signal to generate the drive signal, and outputs the signal to each pixel of the liquid crystal panel <b>3</b>.

Moreover, the liquid crystal panel <b>3</b> is provided with the two transparent substrates (not shown) arranged facing with each other, the liquid crystal layer (not shown) sandwiched between the transparent substrates, and the backlight (not shown) arranged behind the two transparent substrates. Further, the pixels (not shown) are arranged in a matrix state on the liquid crystal panel <b>3</b>. Note that one pixel is formed by three cells of RBG (red, blue, green).

Next, description will be made for the driving method of the liquid crystal display device according to the embodiment. <figref idref="DRAWINGS">FIG. 5</figref> is the timing chart showing the driving method of the liquid crystal display device according to the embodiment, and <figref idref="DRAWINGS">FIG. 6</figref> is the timing chart showing the operation of the V-I conversion circuit for image data <b>8</b> and the I-V conversion circuit for image data <b>21</b> of the liquid crystal display device according to the embodiment.

As shown in <figref idref="DRAWINGS">FIGS. 2 and 5</figref>, the image data as the two-valued voltage signal is input to the display data memory <b>6</b> of the display controller <b>1</b>, and the display data memory <b>6</b> holds the image data equivalent to one screen, for example. Further, the signal showing the display mode of an image is input to the mode register <b>10</b>, and the mode register <b>10</b> outputs the control signal to the display data memory <b>6</b> and the timing control circuit <b>7</b> in response to the display mode. Note that the display mode has a regular mode that shows an image in 260,000 colors and a subtractive color mode that shows an image in 8 colors, for example.

Next, the timing control circuit <b>7</b> reads out the image data equivalent to one line from the display data memory <b>6</b> based on the control signal output from the mode register <b>10</b>, and outputs the clock signal that is the two-valued voltage signal to the V-I conversion circuit for clock signal <b>9</b>. Further, the timing control circuit <b>7</b> sequentially outputs the image data to the V-I conversion circuit for image data <b>8</b> synchronously with the clock signal. The timing: control circuit <b>7</b> sequentially outputs the image data equivalent to 260,000 colors when the display mode is in the regular mode, outputs the image data equivalent to 8 colors in a lump, and stops outputting the clock signal and the image data during the remainder of the time when the display mode is the subtractive color mode of 8 colors, as shown in <figref idref="DRAWINGS">FIG. 5</figref>. Then, the timing control circuit <b>7</b> outputs the receiver control signal showing whether the clock signal and the image data are being output or not to the source driver <b>2</b> via the wiring <b>11</b>. The receiver control signal is the two-valued voltage signal that is low (L) when the clock signal and the image data are output and is high (H) when they are not output, for example.

Next, as shown in <figref idref="DRAWINGS">FIGS. 3 and 6</figref>, the V-I conversion circuit for image data <b>8</b> connects one of a pair of the wirings <b>4</b><i>a</i>, <b>4</b><i>b </i>to the earth electrode and sets the other one to the floating state based on the image data entered from the timing control circuit <b>7</b>. For example, when the image data input to the input terminal T<b>1</b> is high, the output terminal of the inverter INV<b>1</b> becomes low, the gate of the transistor Qn<b>9</b> becomes low, and source-drain of the transistor Qn<b>9</b> is turned off. Thus, the wiring <b>4</b><i>a </i>is set to the floating state. Further, the output terminal of the inverter INV<b>2</b> becomes high, the gate of the transistor Qn<b>10</b> becomes high, and the source-drain of the transistor Qn<b>10</b> is turned on. Thus, the wiring <b>4</b><i>b </i>is connected to the earth electrode GND<b>2</b>. Similarly, when the image data is low, the wiring <b>4</b><i>a </i>is connected to the earth electrode GND<b>1</b> and the wiring <b>4</b><i>b </i>is set to the floating state.

Furthermore, the V-I conversion circuit for clock signal <b>9</b> connects one of a pair of the wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>to the earth electrode and sets the other one to the floating state based on the clock signal. The operation of the V-I conversion circuit for clock signal <b>9</b> is the same as the operation of the V-I conversion circuit for image data <b>8</b>.

As shown in <figref idref="DRAWINGS">FIGS. 4 and 6</figref>, the switch S<b>1</b> is connected to the earth electrode GND<b>3</b> when the timing control circuit <b>7</b> outputs the clock signal and the image data, in the I-V conversion circuit for image data <b>21</b>. Then, in the case where the image data is low, the wiring <b>4</b><i>a </i>is connected to the earth electrode GND<b>1</b> to be the earth potential, and the wiring <b>4</b><i>b </i>is set to the floating state to be a floating potential, a gate-source voltage of the transistors Qn<b>1</b>, Qn<b>3</b> becomes Vd to turn on, and thus exerting a current driving capability based on the voltage Vd. Consequently, the transistors Qp<b>1</b>, Qp<b>3</b> allow the electric current to flow to the earth electrode GND<b>1</b> of the V-I conversion circuit for image data <b>8</b> via the input terminal T<b>3</b> and the wiring <b>4</b><i>a </i>by a constant current operation based on the voltage Vc. At this point, the voltage Vb becomes low. On the other hand, the electric current is not allowed to flow in the wiring <b>4</b><i>b</i>. Specifically, the first current supply section supplies the electric current to the wiring <b>4</b><i>a </i>and the second current supply section stops supplying the electric current to the wiring <b>4</b><i>b</i>. At this point, the potential of the wiring <b>4</b><i>a </i>becomes the earth potential, and the potential of the wiring <b>4</b><i>b </i>becomes a potential that is the floating potential and higher than the earth potential by approximately 100 to 200 mV.

Furthermore, the gate-source voltage of the transistors Qn<b>2</b>, Qn<b>4</b> becomes zero to turn off. The potential Va of the transistors Qp<b>2</b>, Qp<b>4</b> becomes high by the constant current operation. Thus, the set input and the reset input of the RS latch circuit <b>29</b> become high and low, respectively.

A bias voltage Vs having a predetermined value is applied to the bias terminal T<b>2</b>. Accordingly, the gate-source voltage of the transistors Qp<b>5</b>, Qn<b>5</b>, Qn<b>6</b> becomes Vs to turn on, and thus exerting the current driving capability based on the voltage Vs.

On the other hand, in the case where the image data is high, the wiring <b>4</b><i>a </i>is in the floating state to be the floating potential, and the wiring <b>4</b><i>b </i>is connected to the earth electrode GND<b>2</b> to be the earth potential, the gate-source voltage of the transistors Qn<b>1</b>, Qn<b>3</b> becomes zero to turn off. Further, the potential Vb of the transistors Qp<b>1</b>, Qp<b>3</b> becomes high by the constant current operation. In addition, the gate-source voltage of the transistors Qp<b>2</b>, Qn<b>4</b> becomes Vd to turn on, and thus exerting the current driving capability based on the voltage Vd. Consequently, the transistors Qp<b>2</b>, Qp<b>4</b> allow the electric current to flow to the earth electrode GND<b>2</b> of the V-I conversion circuit for image data <b>8</b> via the input terminal T<b>4</b> and the wiring <b>4</b><i>b </i>by the constant current operation based on the voltage Vc. On the other hand, the electric current is not allowed to flow in the wiring <b>4</b><i>a</i>. Specifically, the first current supply section stops supplying the electric current to the wiring <b>4</b><i>a </i>and the second current supply section supplies the electric current to the wiring <b>4</b><i>b</i>. At this point, the potential of the wiring <b>4</b><i>b </i>becomes the earth potential, and the potential of the wiring <b>4</b><i>a </i>becomes the potential that is the floating potential and higher than the earth potential by approximately 100 to 200 mV. Further, the voltage Va becomes low. Thus, set input and the reset input of the RS latch circuit <b>29</b> become low and high, respectively.

As described above, by allowing the electric current to flow in the wiring <b>4</b><i>a </i>or <b>4</b><i>b </i>based on the image data, the complementary current signal based on the image data is generated in a pair of the wirings <b>4</b><i>a</i>, <b>4</b><i>b</i>. Consequently, the image data that is the two-valued voltage signal, which has been input to the V-I conversion circuit for image data <b>8</b>, is converted into the complementary current signal, and the current signal is transmitted from the V-I conversion circuit for image data <b>8</b> to the I-V conversion circuit for image data <b>21</b> via a pair of the wirings <b>4</b><i>a</i>, <b>4</b><i>b</i>. For example, when the image data is high, the electric current is not allowed to flow in the wiring <b>4</b><i>a </i>but allowed to flow in the wiring <b>4</b><i>b</i>. Further, when the image data is low, the electric current is allowed to flow in the wiring <b>4</b><i>a </i>but not allowed to flow in the wiring <b>4</b><i>b. </i>

Furthermore, the RS latch circuit <b>29</b> determines a value to be held when the set input or the reset input changes from a high level to a low level. The value of the output terminal T<b>6</b> becomes high when the set input changes from low to high, and the value of the output terminal T<b>6</b> becomes low when the reset input changes from low to high. As a result, the I-V conversion circuit for image data <b>21</b> converts the current signal flowing in a pair of the wirings <b>4</b><i>a</i>, <b>4</b><i>b </i>into the two-valued voltage signal, and thus regenerating the image data. Then, the circuit <b>21</b> outputs the regenerated image data to the data latch circuit <b>24</b>.

When the timing control circuit <b>7</b> does not output the clock signal and the image data, the switch S<b>1</b> is connected to the power source electrode VDD<b>2</b>. This makes the first and second current supply sections stop their functions, and does not allow the electric current to flow in the both wirings <b>4</b><i>a</i>, <b>4</b><i>b. </i>

Note that a necessary current amount is determined when the frequency of the image data to be transmitted is determined. The current detecting section <b>27</b> controls the current amount based on the bias signal entered via the bias terminal T<b>2</b>.

By an operation similar to that of the I-V conversion circuit for image data <b>21</b>, the I-V conversion circuit for clock signal <b>22</b> allows the electric current to flow in the wiring out of a pair of the wirings <b>5</b><i>a</i>, <b>5</b><i>b</i>, which is connected to the earth electrode. On the other hand, the electric current is not allowed to flow in the wiring in the floating state. As a result, the clock signal that is the voltage signal is converted into a pair of complementary current signals, and the V-I conversion circuit for clock signal <b>9</b> transmits the current signal to the I-V conversion circuit for clock signal <b>22</b>. Then, the I-V conversion circuit for clock signal <b>22</b> converts the current signal into the two-valued voltage signal again to regenerate the clock signal, and outputs the clock signal to the shift register <b>23</b>. Note that the I-V conversion circuit for clock signal <b>22</b> does not allow the electric current to flow in the both wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>when the timing control circuit <b>7</b> does not output the clock signal and the image data.

The shift register <b>23</b> downloads the clock signal from the I-V conversion circuit for clock signal <b>22</b>, and sequentially outputs the pulse signal from a plurality of output terminals to the data latch circuit <b>24</b>. Then, the data latch circuit <b>24</b> downloads a plurality of image data from the I-V conversion circuit for image data <b>21</b> synchronously with the pulse signal, and simultaneously outputs a plurality of the image data to the gradation selecting circuit <b>25</b>. Next, the gradation selecting circuit <b>25</b> performs D/A conversion to the output signal to generate the gradation signal that is the analog voltage signal, and outputs the signal to the output circuit <b>26</b>. Next, the output circuit <b>26</b> performs current amplification to the gradation signal to generate the drive signal, and applies it to each pixel of the liquid crystal panel <b>3</b>.

On the other hand, in the liquid crystal panel <b>3</b>, the backlight irradiates light to each pixel. Thus, the liquid crystal layer of each pixel changes transmission factor of light according to the voltage of the drive signal, forms an image as the entire liquid crystal panel <b>3</b>.

In the embodiment, transmission of the image data and the clock signal between the display controller <b>1</b> and the source driver <b>2</b> is performed by the current signal. This restricts the affect of the parasitic capacitance of the wiring, and the high-speed transmission of the signal can be realized. As a result, although a conventional voltage transmission method has required <b>18</b> wirings in order to transmit the image data of 18 bits, for example, and <b>19</b> wirings have been required in total including one wiring for transmitting the clock signal, the transmission of the image data and the clock signal can be performed in high-speed according to the embodiment. Accordingly, it is possible to transmit the image data and the clock signal only by 4 wirings in total including a pair of wirings for transmitting image data and a pair of wirings for transmitting clock signal. As a result, the number of wirings can be reduced and a circuit section of the liquid crystal display device can be manufactured in a smaller size.

Further, as described above, since the amplitude of voltage is as small as approximately 100 to 200 mV in the wiring pairs <b>4</b><i>a </i>and <b>4</b><i>b</i>, <b>5</b><i>a </i>and <b>5</b><i>b</i>, noise in transmitting signal is small. Moreover, since the current power source is not provided for a transmitter, that is, the display controller <b>1</b>, but for a receiver, that is, the source driver <b>2</b>, it is not necessary to change the specification of the display controller even if the number of the source driver <b>2</b> changes, and the design of the display controller is easy.

Still further, in the embodiment, the display controller <b>1</b> is provided with the mode register <b>10</b> and the timing control circuit <b>7</b> outputs the receiver control signal showing whether the image data and the clock signal are being output or not, so that the I-V conversion circuit for image data <b>21</b> and the I-V conversion circuit for clock signal <b>22</b> stop allowing the electric current to flow in the wirings <b>4</b><i>a </i>and <b>4</b><i>b </i>and the wirings <b>5</b><i>a </i>and <b>5</b><i>b </i>when the image data and the clock signal are not output. Thus, in adopting the display mode with small image data such as the subtractive color mode, it is possible to stop allowing the electric current to flow in the wirings during a period when the image data is not transmitted. As a result, reduction of the power consumption can be achieved.

Next, the second embodiment of the present invention will be described. <figref idref="DRAWINGS">FIG. 7</figref> is the block diagram showing the liquid crystal display device according to the embodiment. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, in the liquid crystal display device according to the embodiment, a display controller <b>1</b><i>a </i>is provided with a timing control circuit <b>7</b><i>a </i>instead of the timing control circuit <b>7</b>, and a source driver <b>2</b><i>a </i>is provided with a CLK stop detecting circuit <b>30</b>, comparing with the above-described liquid crystal display device according to the first embodiment (refer to <figref idref="DRAWINGS">FIG. 2</figref>). Further, the wiring <b>11</b> is not provided. The configuration of the liquid crystal display device of the embodiment other than the one described above is the same as the configuration of the liquid crystal display device of the first embodiment described above.

What the timing control circuit <b>7</b><i>a </i>is different from the timing control circuit <b>7</b> of the first embodiment is that the circuit <b>7</b><i>a </i>does not output the receiver control signal. The configuration and the operation other than this is the same-as the timing control circuit <b>7</b>. Further, the CLK stop detecting circuit <b>30</b> is connected to the I-V conversion circuit for clock signal <b>22</b>, detects whether the current signal based on the clock signal has been input to the I-V conversion circuit for clock signal <b>22</b> or not, and outputs the result as the receiver control signal to the I-V conversion circuit for image data <b>21</b> and the I-V conversion circuit for clock signal <b>22</b>. Then, when the current signal based on the clock signal has not been input to the I-V conversion circuit for clock signal <b>22</b>, the I-V conversion circuit for image data <b>21</b> stops allowing the electric current to flow in the wirings <b>4</b><i>a</i>, <b>4</b><i>b. </i>

Next, description will be made for the driving method of the liquid crystal display device according to the embodiment. <figref idref="DRAWINGS">FIG. 8</figref> is the timing chart showing the driving method of the liquid crystal display device of the embodiment. Note that detailed description will be omitted for the area of the driving method of the embodiment, which is the same as the driving method of the above-described first embodiment.

Firstly, as shown in <figref idref="DRAWINGS">FIGS. 7 and 8</figref>, the display data memory <b>6</b> holds the image data that is the two-valued voltage signal in the same manner as the above-described first embodiment. Further, the mode register <b>10</b> outputs the control signal to the display data memory <b>6</b> and the timing control circuit <b>7</b><i>a </i>according to the display mode.

Next, the timing control circuit <b>7</b><i>a </i>reads out the image data equivalent to one line from the display data memory <b>6</b> based on the control signal, and outputs the clock signal that is the two-valued voltage signal to the V-I conversion circuit for clock signal <b>9</b>. In addition, the timing control circuit <b>7</b><i>a </i>sequentially outputs the image data to the V-I conversion circuit for image data <b>8</b> synchronously with the clock signal. At this point,-when the display mode is the subtractive color mode of 8 colors, for example, the circuit <b>7</b><i>a </i>outputs the image data equivalent to 8 colors in a lump, and stops outputting the clock signal and the image data during the remainder of the time, as shown in <figref idref="DRAWINGS">FIG. 8</figref>. Note that the timing control circuit <b>7</b><i>a </i>does not output the receiver control signal unlike the timing control circuit <b>7</b> of the first embodiment.

Next, the V-I conversion circuit for image data <b>8</b> connects one of a pair of the wirings <b>4</b><i>a</i>, <b>4</b><i>b </i>to the earth electrode and sets the other one to the floating state based on the image data entered from the timing control circuit <b>7</b><i>a</i>. Similarly, the V-I conversion circuit for clock signal <b>9</b> connects one of a pair of the wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>to the earth electrode and sets the other one to the floating state based on the clock signal.

In the I-V conversion circuit for image data <b>21</b>, the switch S<b>1</b> is connected to the earth electrode GND<b>3</b> when the timing control circuit <b>7</b><i>a </i>outputs the clock signal and the image data. Then, with the same operation as the above-described first embodiment, the circuit <b>21</b> allows the electric current to flow in the wiring out of the wirings <b>4</b><i>a</i>, <b>4</b><i>b</i>, which is connected to the earth electrode. Thus, the circuit <b>21</b> converts the image data that is the voltage signal into a pair of complementary current signals to receive them, and converts the current signal into the voltage signal again to regenerate the image data. Similarly, the I-V conversion circuit for clock signal <b>22</b> receives and regenerates the clock signal.

At this point, the CLK stop detecting circuit <b>30</b> detects whether the current signal based on the clock signal has been input to the I-V conversion circuit for clock signal <b>22</b>, and outputs the result as the receiver control signal to the switch S<b>1</b> (refer to <figref idref="DRAWINGS">FIG. 4</figref>) of the I-V conversion circuit for image data <b>21</b>. Then, the switch S<b>1</b> (refer to <figref idref="DRAWINGS">FIG. 4</figref>) of the I-V conversion circuit for image data <b>21</b> is switched to connect the source of the transistor Qn<b>8</b> to the power source electrode VDD<b>2</b> when the current signal has not been input to the I-V conversion circuit for clock signal <b>22</b>. Accordingly, the I-V conversion circuit for image data <b>21</b> stops allowing the electric current to flow in the wirings <b>4</b><i>a</i>, <b>4</b><i>b</i>. Note that the I-V conversion circuit for clock signal <b>22</b> continues to allow the electric current to flow constantly in one of the wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>in order to detect whether the current signal based on the clock signal has been input to the I-V conversion circuit for clock signal <b>22</b> or not.

The subsequent process is the same as the above-described embodiment. Specifically, the shift register <b>23</b> downloads the clock signal, the data latch circuit <b>24</b> downloads the image data, and outputs the image data to the gradation selecting circuit <b>25</b>. Next, the gradation selecting circuit <b>25</b> performs D/A conversion to the output signal to generate the gradation signal that is the analog voltage signal, and outputs it to the output circuit <b>26</b>. The output circuit <b>26</b> performs current amplification to the gradation signal to generate the drive signal and applies it to each pixel of the liquid crystal panel <b>3</b>. Then, the liquid crystal panel <b>3</b> displays an image.

In the embodiment, a receiver, that is, the source driver <b>2</b><i>a </i>is provided with the CLK stop detecting circuit <b>30</b>, and the CLK stop detecting circuit <b>30</b> determines whether the clock signal stops or not. Accordingly, it is unnecessary to transmit the receiver control signal between the display controller <b>1</b><i>a </i>and the source driver <b>2</b><i>a</i>. As a result, the embodiment has effects that wiring (equivalent to the wiring <b>11</b> shown in <figref idref="DRAWINGS">FIG. 2</figref>) for transmitting the receiver control signal is not required in addition to the effects of the above-described first embodiment.

Next, description will be made for the third embodiment. <figref idref="DRAWINGS">FIG. 9</figref> is the block diagram showing the liquid crystal display device according to the embodiment. As shown in <figref idref="DRAWINGS">FIG. 9</figref>, in the liquid crystal display device according to the embodiment, a display controller <b>1</b><i>b </i>is provided with a timing control circuit <b>7</b><i>b </i>instead of the timing control circuit <b>7</b>, and a data comparing circuit <b>12</b> is provided, comparing with the above-described liquid crystal display device according to the first embodiment (refer to <figref idref="DRAWINGS">FIG. 2</figref>). Further, the mode register is not provided. The configuration of the liquid crystal display device of the embodiment other than the one described above is the same as the configuration of the liquid crystal display device of the first embodiment described above.

The data comparing circuit <b>12</b> is connected to the display data memory <b>6</b> and the timing control circuit <b>7</b><i>b</i>, the timing control circuit <b>7</b><i>b </i>holds the image data read from the display-data memory <b>6</b>, the data comparing circuit <b>12</b> compares the image data with image data that the timing control circuit <b>7</b><i>b </i>reads next from the display data memory <b>6</b>, and outputs the result to the timing control circuit <b>7</b><i>b</i>. Further, what the timing control circuit <b>7</b><i>b </i>is different from the timing control circuit <b>7</b> of the first embodiment is that the output signal of the data comparing circuit <b>12</b> is input thereto and stops outputting the image data and the clock signal based on the input. The configuration and operation other than this are the same as those of the timing control circuit <b>7</b>.

Next, the driving method of the liquid crystal display device according to the embodiment will be described. <figref idref="DRAWINGS">FIG. 10</figref> is the timing chart showing the driving method of the liquid crystal display device according to the embodiment. Note that detailed description will be omitted for the area of the driving method of the embodiment, which is the same as the driving method of the above-described first embodiment.

Firstly, as shown in <figref idref="DRAWINGS">FIGS. 9 and 10</figref>, the display data memory <b>6</b> holds the image data that is the two-valued voltage signal. Next, the timing control circuit <b>7</b><i>b </i>reads out a certain amount of the image data from the display data memory <b>6</b>. At this point, the image data is also output to the data comparing circuit <b>12</b>, and the data comparing circuit <b>12</b> stores the image data. Then, when the timing control circuit <b>7</b><i>b </i>reads out a certain amount of the image data from the display data memory <b>6</b> next, the data comparing circuit <b>12</b> compares the image data with the latest image data stored in the circuit <b>12</b>, and outputs the result to the timing control circuit <b>7</b><i>b</i>. At this point, the data comparing circuit <b>12</b> compares the image data equivalent to one pixel, for example, with the image data of an adjacent pixel, and determines whether the data are equal to each other.

Subsequently, when the data comparing circuit <b>12</b> determines that the image data of the adjacent pixels are not equal to each other, the timing control circuit <b>7</b><i>b </i>outputs the clock signal to the V-I conversion circuit for clock signal <b>9</b>, and sequentially outputs the image data to the V-I conversion circuit for image data <b>8</b> synchronously with the clock signal. Further, when the data comparing circuit <b>12</b> determines that the image data of the adjacent pixels are equal to each other, the timing control circuit <b>7</b><i>b </i>stops outputting the clock signal and the image data. Furthermore, the timing control circuit <b>7</b><i>b </i>outputs the receiver control signal showing whether the clock signal and the image data are being output or not to the source driver <b>2</b> via the wiring <b>11</b>.

The subsequent process is the same as the above-described first embodiment. Specifically, the V-I conversion circuit for image data <b>8</b> connects one of a pair of the wirings <b>4</b><i>a</i>, <b>4</b><i>b </i>to the earth electrode and sets the other one to the floating state based on the image data. Similarly, the V-I conversion circuit for clock signal <b>9</b> connects one of a pair of the wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>to the earth electrode and sets the other one to the floating state based on the clock signal.

Then, the source driver <b>2</b> generates a pair of current signals based on the image data and a pair of current signals based on the clock signal. At this point, when the timing control circuit <b>7</b><i>b </i>does not output the image data and the clock signal based on the receiver control signal, the driver <b>2</b> stops generating the current signal. Then, the driver <b>2</b> generates the drive signal for the liquid crystal panel <b>3</b> based on the current signals and outputs them. Alternatively, when the generation of the current signal is stopped, the driver <b>2</b> outputs a drive signal same as the previous drive signal. Then, the liquid crystal panel <b>3</b> displays an image based on the drive signal. For example, assuming that one pixel consists of three display elements of RGB, data driving each display element are 6 bits and data equivalent to one pixel are 18 bits, the data latch circuit <b>24</b> latches the 18-bit data, the gradation selecting circuit <b>25</b> generates three analog signals from the 6-bit data for each of RGB, and the output circuit <b>26</b> drives the three display elements of RGB.

As described, in the embodiment, it is possible to compress pixel data and stop transmitting the image data when the image data are equal between adjacent pixels. Alternatively, generation of the current signal is stopped when the image data is not transmitted. Thus, in the case of displaying a uniform image such as an all-white display, the image data amount to be transmitted is reduced and the electric current is stopped when the image data is not transmitted, so that power consumption with the transmission of the image data can be restricted.

Note that the embodiment has shown an example where the image data between a pixel and another pixel, which are adjacent to each other, is compared, but the present invention is not limited to this. For example, image data of a pixel group that consists of a plurality of pixels may be compared with image data that consists of pixels of the same number as the pixel group and adjacent to the pixel group, or image data equivalent to one line may be compared with image data equivalent to the next one line adjacent to the line. Further, the embodiment has shown an example where the timing control circuit <b>7</b><i>b </i>stopped outputting the image data and the clock signal when the image data between the adjacent pixels are the same, but the present invention is not limited to this. For example, when image data of a pixel is equal to inverted image data of image data of an adjacent pixel, the timing control circuit <b>7</b><i>b </i>may stop outputting the image data and the clock signal. Thus, the image data amount can be reduced in the case of a black-and-white mode. Alternatively, the image data is encoded to compress the image data by another method, and the output of the image data and the clock signal may be stopped during the remainder of the time.

Next, the fourth embodiment of the present invention will be described. <figref idref="DRAWINGS">FIG. 11</figref> is the block diagram showing the liquid crystal display device according to the embodiment. As shown in <figref idref="DRAWINGS">FIG. 11</figref>, in the liquid crystal display device according to the embodiment, a display controller <b>1</b><i>c </i>is provided with a timing control circuit <b>7</b><i>c </i>instead of the timing control circuit <b>7</b>, comparing with the above-described liquid crystal display device according to the first embodiment (refer to <figref idref="DRAWINGS">FIG. 2</figref>). Further, the receiver control signal output from the timing control circuit <b>7</b><i>c </i>is designed to be input to the bias terminal T<b>2</b> (refer to <figref idref="DRAWINGS">FIG. 4</figref>) of the I-V conversion circuit for image data <b>21</b> and the bias terminal of the I-V conversion circuit for clock signal <b>22</b>. The configuration of the liquid crystal display device of the embodiment other than the one described above is the same as the configuration of the liquid crystal display device of the first embodiment.

The timing control circuit <b>7</b><i>c </i>reads out a certain amount of the image data from the display data memory <b>6</b> based on the control signal output from the mode register <b>10</b>, outputs the clock signal to the V-I conversion circuit for clock signal <b>9</b>, and sequentially outputs a predetermined amount of image data to the V-I conversion circuit for image data <b>8</b> based on the control signal synchronously with the clock signal. At this point, the timing control circuit <b>7</b><i>c </i>adjusts the frequencies of the image data and the clock signal based on the control signal output from the mode register <b>10</b>. Specifically, when the display mode is the subtractive color mode and has a smaller image data amount comparing with the regular mode, the circuit <b>7</b><i>c </i>reduces frequencies of the image data and the clock signal. Further, the timing control circuit <b>7</b><i>c </i>outputs the receiver control signal showing the frequencies of the image data and the clock signal to the source driver <b>2</b> via the wiring <b>11</b>. Furthermore, the I-V conversion circuit for image data <b>21</b> and the I-V conversion circuit for clock signal <b>22</b> adjust the volume of the electric current allowed to flow in the wirings <b>4</b><i>a</i>, <b>4</b><i>b</i>, <b>5</b><i>a</i>, <b>5</b><i>b </i>based on the receiver control signal.

Next, description will be made for the driving method of the liquid crystal display device according to the embodiment. <figref idref="DRAWINGS">FIG. 12</figref> is the timing chart showing the driving method of the liquid crystal display device according to the embodiment, and <figref idref="DRAWINGS">FIG. 13</figref> is the graph showing the relationship between the maximum frequency of the current signal and the necessary current by setting the maximum frequency fmax of electric current to be transmitted to the axis of abscissas and the constant current value necessary for transmitting the current signal of the maximum frequency to the axis of ordinate. Note that detailed description will be omitted for the area of the driving method of the embodiment, which is the same as the driving method of the above-described first embodiment.

Firstly, as shown in <figref idref="DRAWINGS">FIGS. 11 and 12</figref>, the display data memory <b>6</b> holds the image data that is the two-valued voltage signal in the same manner as the first embodiment described above. Further, the mode register <b>10</b> outputs the control signal to the display data memory <b>6</b> and the timing control circuit <b>7</b><i>c </i>according to the display mode.

Next, the timing control circuit <b>7</b><i>c </i>reads out a predetermined amount of the image data from the display data memory <b>6</b> based on the control signal, and outputs the clock signal to the V-I conversion circuit for clock signal <b>9</b>. Further, the timing control circuit <b>7</b><i>c </i>sequentially outputs the image data to the V-I conversion circuit for image data <b>8</b> synchronously with the clock signal. At this point, the circuit <b>7</b><i>c </i>adjusts the frequencies of the image data and the clock signal according to the image data amount. Specifically, when the display mode is the subtractive color mode of 8 colors, for example, the circuit <b>7</b><i>c </i>reduces the frequencies so as to send the image data equivalent to 8 colors while making the best use of a transfer period, that is, to make residual time be the minimum.

Next, the V-I conversion circuit for image data <b>8</b> connects either one of a pair of the wirings <b>4</b><i>a</i>, <b>4</b><i>b </i>to the earth electrode and sets the other one to the floating state based on the image data entered from the timing control circuit <b>7</b><i>c</i>. Similarly, the V-I conversion circuit for clock signal <b>9</b> connects either one of a pair of the wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>to the earth electrode and sets the other one to the floating state based on the clock signal.

In the I-V conversion circuit for image data <b>21</b>, the switch S<b>1</b> is fixed such that the source of the transistor Qn<b>8</b> is constantly connected to the earth electrode GND<b>3</b>. Then, with the same operation as the above-described first embodiment, the circuit <b>21</b> allows the electric current to flow in the wiring out of the wirings <b>4</b><i>a</i>, <b>4</b><i>b</i>, which is connected to the earth electrode. Thus, the circuit <b>21</b> converts the image data that is the voltage signal into a pair of complementary current signals to receive them, and converts the current signal into the voltage signal again to regenerate the image data. Similarly, the I-V conversion circuit for clock signal <b>22</b> receives and regenerates the clock signal.

At this point, the frequencies of the image data and the clock signal fluctuate due to the amount of the image data transmitted, as shown in <figref idref="DRAWINGS">FIG. 12</figref>, and the frequencies reduce during the subtractive color mode, for example. As shown in <figref idref="DRAWINGS">FIG. 13</figref>, when the frequency of the current signal transmitted is low, the constant current value necessary for transmitting the current signal becomes low. In the embodiment, when the display mode is the mode having a small image data amount such as the subtractive color mode, the constant current values of the I-V conversion circuit for image data <b>21</b> and the I-V conversion circuit for clock signal <b>22</b> are reduced by the receiver control signal. For example, in the I-V conversion circuit for image data <b>21</b>, the receiver control signal is input to the current detecting section <b>27</b> via the bias terminal T<b>2</b>. Thus, it is possible to adjust the constant current value of the I-V conversion circuit for image data <b>21</b>. The subsequent process is the same as the above-described first embodiment.

In the embodiment, the timing control circuit <b>7</b><i>c </i>adjusts the frequencies of the image data and the clock signal according to the image data amount, and the I-V conversion circuit for image data <b>21</b> and the I-V conversion circuit for clock signal <b>22</b> adjust their constant current values based on the frequencies, so that the constant current values can be lowered in the case of a small image data amount. Consequently, the power consumption can be reduced.

Note that, in the embodiment, the image data amount may be reduced by encoding the image data as shown in the above described third embodiment.

Next, the fifth embodiment of the present invention will be described. <figref idref="DRAWINGS">FIG. 14</figref> is the block diagram showing the liquid crystal display device according to the embodiment. As shown in <figref idref="DRAWINGS">FIG. 14</figref>, the embodiment shows an example where a plurality of source drivers <b>2</b><i>d </i>are provided in one liquid crystal display device. The applicant developed a technique to sequentially transmit the drive signal between receivers as a technique to efficiently drive a plurality of receivers and disclosed it in Japanese Patent Laid-open No.2002-026231. The embodiment is the example in which the technique and the present invention are combined. The liquid crystal display device according to the embodiment is provided with one display controller <b>1</b>, a plurality of source drivers <b>2</b><i>d</i>, and one liquid crystal panel <b>3</b>. Although the wirings <b>4</b><i>a</i>, <b>4</b><i>b</i>, <b>5</b><i>a</i>, <b>5</b><i>b</i>, <b>11</b> are provided between the display controller <b>1</b> and the source drivers <b>2</b><i>d</i>, <figref idref="DRAWINGS">FIG. 14</figref> shows only the wirings <b>4</b><i>a</i>, <b>11</b> and the wirings <b>4</b><i>b</i>, <b>5</b><i>a</i>, <b>5</b><i>b </i>are omitted. Disposing positions of the wirings <b>4</b><i>b</i>, <b>5</b><i>a </i>and <b>5</b><i>b </i>are the same as that-of the wiring <b>4</b><i>a</i>. Each source driver <b>2</b><i>d </i>drives the pixel of columns of a part of the liquid crystal panel <b>3</b> to display an image. Then the display controller <b>1</b> outputs the image data, the clock signal and the receiver control signal parallelly to a plurality of the source drivers <b>2</b><i>d</i>. The display controller <b>1</b> also outputs the signal STH, which begins the operation of the shift register <b>23</b> (refer to <figref idref="DRAWINGS">FIG. 2</figref>), only to a source driver <b>2</b><i>d </i>arranged in the closest position to the display controller <b>1</b>. Then, the source driver <b>2</b><i>d </i>to which the signal STH has been input is designed to output the signal STH to a source driver <b>2</b><i>d </i>arranged next to the source driver <b>2</b><i>d</i>. In this manner, the signal STH is to be sequentially input to all source drivers <b>2</b><i>d</i>. The configuration of the liquid crystal display device of the embodiment other than the one described above is the same as the configuration of the liquid crystal display device of the first embodiment described above.

Next, description will be made for the driving method of the liquid crystal display device according to the embodiment. With the similar method as the above-described first embodiment, the display controller <b>1</b> sets either one of the wirings <b>4</b><i>a</i>, <b>4</b><i>b </i>to the floating state and connects the other wiring to the earth electrode based on the image data. Further, the controller <b>1</b> sets either one of the wirings <b>5</b><i>a</i>, <b>5</b><i>b </i>to the floating state and connects the other wiring to the earth electrode based on the clock signal. Thus, the display controller <b>1</b> simultaneously outputs the image data and the clock signal to all the source drivers <b>2</b><i>d. </i>

The display controller <b>1</b> also outputs the signal STH to the source drivers <b>2</b><i>d</i>. Then, the source driver <b>2</b><i>d </i>to which the signal STH has been input starts an operation to display an image on a predetermined column of the liquid crystal panel <b>3</b> based on the image data input. At this point, the other source drivers <b>2</b><i>d </i>are in a stop state and do not drive the liquid crystal panel <b>3</b> even if the image data are entered.

When all necessary image data are input to this source driver <b>2</b><i>d</i>, the source driver <b>2</b><i>d </i>outputs the signal STH to another source driver <b>2</b><i>d </i>arranged next to the source driver <b>2</b><i>d</i>, and stops the operation. Consequently, the source driver <b>2</b><i>d </i>to which the signal STH has newly been input start an operation to drive the liquid crystal panel <b>3</b> based on the image data. Furthermore, the source driver <b>2</b><i>d </i>outputs the signal STH to the next source driver <b>2</b><i>d</i>, and stops the operation. In this manner, all source drivers <b>2</b><i>d </i>sequentially operate to drive the liquid crystal panel <b>3</b>. As a result, an image is displayed as the entire liquid crystal panel <b>3</b>. The operation of the embodiment other than the above-described ones is the same as the first embodiment described above.

In the embodiment, even if a plurality of source drivers are provided, the same image data is not downloaded into a plurality of source drivers and a right image can be displayed. The effects of the embodiment other than the above described ones are the same as the first embodiment described above.

Next, description will be made for the sixth embodiment. <figref idref="DRAWINGS">FIG. 15</figref> is the block diagram showing a plasma display panel (PDP) according to the embodiment. The embodiment is an example where the present invention has been applied to the PDP.

As shown in <figref idref="DRAWINGS">FIG. 15</figref>, the PDP according to the embodiment is provided with a video signal processing circuit <b>51</b>, a data driver <b>52</b> and a panel <b>53</b>. Further, a pair of wirings <b>54</b><i>a</i>, <b>54</b><i>b </i>is provided between the video signal processing circuit <b>51</b> and the data driver <b>52</b>. The video signal processing circuit <b>51</b> is provided with an inverse gamma processing block <b>32</b>, an error diffusion or dither block <b>33</b>, an average picture level computing block <b>34</b>, an SF coding block <b>35</b>, a frame memory <b>36</b>, a drive control block <b>37</b>, and a V-I conversion circuit <b>43</b>. Further, the data driver <b>52</b> is provided with an I-V conversion circuit <b>44</b> and an internal circuit <b>45</b>. The V-I conversion circuit <b>43</b> is connected to one end of the wirings <b>54</b><i>a</i>, <b>54</b><i>b</i>, and the I-V conversion circuit <b>44</b> is connected to the other end of the wirings <b>54</b><i>a</i>, <b>54</b><i>b</i>. The configuration of the V-I conversion circuit <b>43</b> is the same as that of the V-I conversion circuit for image data <b>8</b> (refer to <figref idref="DRAWINGS">FIG. 3</figref>) in the above-described first embodiment, and the configuration of the I-V conversion circuit <b>44</b> is the same as that of the I-V conversion circuit for image data <b>21</b> (refer to <figref idref="DRAWINGS">FIG. 4</figref>) in the above described first embodiment. Moreover, the output signal of the drive control block <b>37</b> is designed- to be input to a panel <b>53</b>.

Next, the driving method of the PDP according to the embodiment will be described. Firstly, as shown in <figref idref="DRAWINGS">FIG. 15</figref>, image data <b>31</b> that is a video signal for a TV video, a PC screen or the like is input to the inverse gamma processing block <b>32</b>. The inverse gamma processing block <b>32</b> enhances the gradation resolution of the video signal. For example, the video signal is input as a signal, where each of Red, Green and Blue has an 8-bit gradation, to the inverse gamma processing block <b>32</b>, and the inverse gamma processing block <b>32</b> performs nonlinear conversion to the video signal into the form of y=x^2.2. At this point, in the case where input gradation accuracy and output gradation accuracy are the same, all input video having a small gradation value such as the gradation values <b>0</b>, <b>2</b> and <b>5</b> becomes <b>0</b>, which cannot express a gradation difference and causes the gradation to deteriorate. To prevent the gradation deterioration, the output of the inverse gamma processing block <b>32</b> is generally set to 10 bits. The inverse gamma processing block <b>32</b> outputs its output signal (10 bits) to the error diffusion or dither block <b>33</b>. The error diffusion or dither block <b>33</b> spatially diffuses least significant 2 bits out of the gradation resolution 10 bits of the video signal input, for example, and outputs it as an 8-bit signal. The video signal to which the inverse gamma processing and the error diffusion or dither processing have been performed is input to the average picture level computing block <b>34</b>, the average picture level computing block <b>34</b> computes an average picture level (APL) value <b>38</b>, and outputs the value to the drive control block <b>37</b> and the SF coding block <b>35</b>.

The drive control block <b>37</b> converts the APL value <b>38</b> into a sustain pulse number that determines the brightness of video, and outputs it as a sustain pulse output <b>41</b> to the panel <b>53</b>. Further, to perform gradation expression on the panel <b>53</b>, the sub-field (SF) coding block <b>35</b> converts the video signal into SF coding data and outputs the data to the frame memory <b>36</b>. Generally, the 8-bit video signal is converted into 12 pieces of the SF data. The frame memory <b>36</b> converts the 12 pieces of the SF data into video signal output <b>42</b>, and outputs it to the V-I conversion circuit <b>43</b>. The V-I conversion circuit <b>43</b> connects either one of a pair of the wirings <b>54</b><i>a</i>, <b>54</b><i>b </i>to the earth electrode (not shown) and sets the other one to the floating state based on the video signal output <b>42</b> that is the two-valued voltage signal.

The I-V conversion circuit <b>44</b> of the data driver <b>52</b> allows the electric current to flow in the wiring out of a pair of the wirings <b>54</b><i>a</i>, <b>54</b><i>b</i>, which is connected to the earth electrode. Accordingly, the I-V conversion circuit <b>44</b> converts the video signal output <b>42</b> into a pair of complementary current signals to receive them, and converts the current signal into the voltage signal to regenerate the video signal output <b>42</b>. The circuit <b>44</b> stops current signal when the video signal output <b>42</b> is not transmitted. Then, the I-V conversion circuit <b>44</b> outputs the regenerated video signal output <b>42</b> to the internal circuit <b>45</b>.

Subsequently, the internal circuit <b>45</b> adjusts transfer timing and transfer speed of the video signal output <b>42</b>, and transfers it to the data driver (not shown) of the panel <b>53</b>. Thus, the panel <b>53</b> generates writing discharge in each display cell (not shown) of the panel <b>53</b> to write wall charge, and thus determines luminescence/non-luminescence of each display cell. On the other hand, the sustain pulse output <b>41</b> is transferred to a sustain driver (not shown) of the panel <b>53</b>, and the pulse number of sustain discharge after the writing discharge in each display cell is determined. Generally, since a pulse interval is constant, the pulse number of each SF (sub-field) corresponds to luminescence time of each SF. Accordingly, the brightness of each display cell is controlled. As described above, the video signal output <b>42</b> and the sustain pulse output <b>41</b> drive the panel <b>53</b> to display a picture.

In the embodiment, the V-I conversion circuit and the I-V conversion circuit, which characterize the present invention, are used in an area where the video signal output is transferred from the video signal processing circuit <b>51</b> to the data driver <b>52</b>. This can realizes high-speed data transfer and reduce the power consumption. Unlike the liquid crystal display device, data write time in the PDP does not contribute to luminescence, so that the data write time can be performed in high-speed insofar as write defect is not caused. Specifically, data write speed can be increased to a point where the write defect to the panel occurs, and the data write speed is determined by the performance of the panel. However, since a few write defects are not conspicuous in the least significant SF, high-speed writing can be performed while permitting the write defects to some extent.

In the PDP, data are transferred by every SF unlike the liquid crystal display device. Therefore, with the method shown in the above-described third embodiment, data equivalent to one SF are compared with each other and encoded, and the data amount can be thus reduced. Particularly, since the data in a most significant SF does not change much even in a natural image, the data amount can be effectively reduced.

Further, write time (transfer time) and luminescence time are set separately in the PDP, so that data are not transferred in time other than the transfer time, that is, a sustain period, a pre-discharge period, or the like. Accordingly, it is possible to stop the receiver (I-V conversion circuit) during the time, and thus exerting large reduction effect of power consumption.

Note that the number of pixels that one data driver drives in the PDP is normally 256 or 192 pixels, for example. Assuming that the number of pixels in one line of the panel is 640 times 3 colors (640×3), 10 data drivers are required to drive 192 pixels. Therefore, it is preferable to transfer data parallelly to the 10 data drivers with the method shown in the above-described fifth embodiment.

Although the above-described first to sixth embodiment have shown the examples where the present invention is applied for the liquid crystal display device or the PDP, the present invention is not limited to them, and can be applied for other matrix type display devices such as the organic EL display panel.