Phase lock loop with coarse control loop having frequency lock detector and device including same

FIELD OF THE INVENTION

0001The invention pertains to phase lock loop (PLL) circuits and to transceivers, transmitters, receivers, and other devices that include PLL circuits. In some embodiments, the invention pertains to a circuit (e.g., a data sampling circuit) including a PLL circuit (having both coarse control and fine control loops) for controlling the phase of a clock (e.g., a sampling clock), and to a device (e.g., an 10 Gb Ethernet transceiver) including such a PLL circuit.

BACKGROUND OF THE INVENTION

0002The term “transceiver” is used herein to denote any device that performs the functions of a transmitter and a receiver. The term “transmitter” is used herein in a broad sense to denote any device capable of transmitting data over a link (e.g., a serial link), and optionally also capable of performing additional functions which can include encoding and/or encrypting the data to be transmitted. The term “receiver” is used herein in a broad sense to denote any device capable of receiving data that has been transmitted over a link (e.g., a serial link), and optionally also capable of performing additional functions which can include decoding and/or decryption of the received data, and other operations related to decoding, reception, or decryption of the received data.

0003A transceiver typically includes a data sampling circuit that includes a feedback loop for controlling the phase of a sampling clock. Such a feedback loop typically includes a phase detector (“PD”) that determines the phase error (O) present between a sampling clock and data being sampled by the sampling clock. Typically, the phase detector determines the phase error between the sampling clock and a reference clock derived from the data being sampled by the sampling clock.

0004The expressions “high frequency operation” and “high speed operation” are used herein synonymously to denote operation of a circuit in response to an input signal (e.g., an input clock) having frequency of 1 GHz or more (e.g., an input clock having frequency 5 GHz or 5.15625 GHz).

0005Transceivers (sometimes referred to as “10 Gb Ethernet transceivers”) that comply with the recently established standard known as the “10 Gb Ethernet” standard (IEEE 802.3-ae, promulgated in 2002, entitled CSMA/CD Access Method and Physical Layer Specifications-MAC Parameters, Physical Layer and Management Parameters for 10 Gb/s Operation”) have been implemented.

0006Scaled-down technology and low supply voltage allow a 10 Gb Ethernet transceiver to be implemented in a single CMOS integrated circuit which includes a 10.3125-Gb/s serial interface and a four-channel 3.125-Gb/s interface (XAUI). See, for example, the transceiver described in Sidiropoulos, et al., “An 800 mW 10 Gb Ethernet Transceiver in 0.13 μm CMOS,” <i>IEEE ISSCC Dig. Tech. Papers</i>, pp. 168–169, February 2004.

0007For physical coding sub-layer (PCS) and management functions, it is conventional for a 10 Gb Ethernet transceiver to employ an elastic buffer or gearbox that uses 312.5 MHz and 322.27 MHz read/write clocks to generate 10.3125-Gb/s serial data in response to quad 3.125-Gb/s data, to generate quad 3.125-Gb/s data in response to 10.3125-Gb/s serial data, and to handle 64/66b coding. A 10 Gb Ethernet transceiver typically also includes a clock-multiplying unit (“CMU”) or clock-and-data recovery unit (“CDR”) that generates a 5.15625 GHz clock. A 10 Gb transceiver typically also includes a divide-by-16 frequency divider circuit (“÷16” circuit) and a divide-by-16.5 frequency divider circuit (“÷16.5” circuit) that generate, respectively, a 322.27 MHz clock and a 312.5 MHz clock in response to the 5.15625 GHz clock output from the transceiver's CMU or CDR. The 322.27 MHz and 312.5 MHz clocks can be supplied to divide-by-2 frequency divider circuits (to generate 161.135 MHz and 156.25 MHz clocks), and the 161.135 MHz and 156.25 MHz clocks can be used in feedback loops of data sampling circuits for sampling the 10.3125-Gb/s and 3.125-Gb/s data. Alternatively, the 322.27 MHz and 312.5 MHz clocks themselves can be used in feedback loops of data sampling circuits for sampling the 10.3125-Gb/s and 3.125-Gb/s data.

0008A 10 Gb Ethernet transceiver can be implemented as an integrated circuit, for example, using a 0.13-μm CMOS technology. Such an advanced CMOS technology offers fast transistor speed to achieve 10 Gb/s operation, but also poses design challenges. For example, in a PLL for generating a clock (e.g., a sampling clock) for such an integrated circuit implementation of a 10 Gb Ethernet transceiver, the reduced supply voltage narrows the input voltage range of the VCO of the PLL. If the PLL has conventional design, the reduction in supply voltage implies that VCO gain must be increased in order for the PLL to be operable over the desired frequency range under all possible PVT conditions (i.e., all possible variations in process, voltage, and temperature parameters during manufacture and operation). For example, a VCO implemented as an integrated circuit using a 0.13-μm CMOS technology and operating with a 1.2 Volt supply voltage may require a voltage-to-frequency gain of as high as 10 GHz/V to cover the desired frequency range under all possible PVT conditions.

0009Voltage-to-frequency gain of a VCO (sometimes denoted herein as “Kvco”) is the slope of the curve indicating the VCO's output clock frequency as a function of control voltage. The functional relation of output clock frequency versus control voltage for a VCO, will sometimes be referred to herein as the “frequency-voltage characteristic” of the VCO.

0010Operation of a VCO having high Kvco in a PLL undesirably causes the PLL to have high noise sensitivity, since noise on the power supply and control node is modulated onto the VCO output. To make a PLL (including a VCO) operable under a wide range of PVT conditions without the need for high Kvco, it has been proposed to design the VCO to be operable with any selected one of multiple frequency-voltage characteristics each having low Kvco, with sufficient frequency overlap between the characteristics, rather than to be operable in accordance with only one frequency-voltage characteristic having large Kvco in a desired operating range. In operation of a PLL including such a VCO (sometimes referred to as a “multi-range VCO”), coarse control is achieved by causing the VCO to operate with a selected “best” one of the available frequency-voltage characteristics, and fine control is achieved by causing the VCO to operate at a “best” operating point along the selected frequency-voltage characteristic. Generally, to avoid malfunction or false operation of a PLL that includes a multi-range VCO, the PLL should satisfy the following conditions: each operating frequency must be included within a segment of at least one of the frequency-voltage characteristics; there must be sufficient frequency overlap between the frequency-voltage characteristics so that the PLL can operate at any target frequency in the full range of operating frequencies (the range of frequencies at which the PLL is intended to be operable) and the PLL can be switched between different ones of the frequency-voltage characteristics to operate at any frequency in the full range; the PLL can be switched to the appropriate frequency-voltage characteristic sufficiently rapidly regardless of initial conditions (i.e., the conditions at power on or reset); and the PLL must operate with adequate immunity to noise.

0011<figref idref="DRAWINGS">FIG. 1A</figref> is a graph of a frequency-voltage characteristic of a VCO which operates in a PLL only in accordance with this characteristic. To allow the PLL to operate at any frequency in the full range from f<b>1</b> to f<b>2</b> in response to control voltages V in the range VL&lt;V&lt;VH, where VL is a minimum control voltage and VH is a maximum control voltage, the characteristic has relatively large slope (Kvco) throughout that operating range. <figref idref="DRAWINGS">FIG. 1B</figref> is a graph of a set of frequency-voltage characteristics of a VCO. A modified version of the PLL of <figref idref="DRAWINGS">FIG. 1A</figref> includes the VCO of <figref idref="DRAWINGS">FIG. 1B</figref>. This modified PLL includes a coarse control loop which implements a coarse control algorithm to ensure that the VCO of <figref idref="DRAWINGS">FIG. 1B</figref> always operates in accordance with a current best (selected) one of the frequency-voltage characteristics. Each characteristic graphed in <figref idref="DRAWINGS">FIG. 1B</figref> has a relatively small slope (VCO gain). By operating in accordance with a sequence of different ones of these characteristics, the VCO of <figref idref="DRAWINGS">FIG. 1B</figref> can operate at any frequency in the same range (from f<b>1</b> to f<b>2</b>) as does the VCO of <figref idref="DRAWINGS">FIG. 1A</figref> in response to control voltages in the same range (from VL to VH) as does the VCO of <figref idref="DRAWINGS">FIG. 1A</figref>. There is sufficient frequency overlap between the frequency-voltage characteristics of <figref idref="DRAWINGS">FIG. 1B</figref> to allow the coarse control loop to switch between them. Fine control of the PLL of <figref idref="DRAWINGS">FIG. 1B</figref> is achieved by choosing the best operating point along the currently selected one of the frequency-voltage characteristics.

0012In PLLs that use VCOs having inductor and capacitor-based design (“LC” VCOs), it is conventional to implement coarse control (of the type mentioned in the two previous paragraphs) with a coarse control loop and to implement fine control (of the type also mentioned in the two previous paragraphs) with a fine control loop (see, for example, T. H. Lin et al., “A 900 MHz 2.5 mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” J. <i>Solid</i>-<i>State Circuits</i>, vol. 36, pp. 424–431, March 2001).

0013Two schemes have been employed to implement such a coarse control loop: monitoring the VCO's control voltage (for example, as described in the above-referenced paper by Lin, et al.); and directly counting edges of the VCO's output clock signal to determine its frequency directly. <figref idref="DRAWINGS">FIG. 2</figref> shows circuitry for use in a conventional coarse control loop to monitor a VCO's control voltage. Since a typical LC VCO includes a MOS varactor having predictable tuning range, the <figref idref="DRAWINGS">FIG. 2</figref> circuitry can be used to monitor the control voltage and achieve coarse control of an LC VCO (e.g., select a best one of multiple available frequency-voltage characteristics for the LC VCO). The <figref idref="DRAWINGS">FIG. 2</figref> circuitry allows coarse control to be achieved by inferring the frequency of the VCO's output clock from the control voltage measurements using assumptions about the currently employed frequency-voltage characteristic. In operation of a coarse control loop that includes the <figref idref="DRAWINGS">FIG. 2</figref> circuitry, the voltage comparators shown in <figref idref="DRAWINGS">FIG. 2</figref> compare predetermined voltages VH and VL with a low-pass-filtered version (identified as “Vcap” in <figref idref="DRAWINGS">FIG. 2</figref>) of the fine control voltage currently being applied to the VCO. The output of the comparators is sampled, and the samples are asserted to an Up/Down counter. The Up/Down counter generates control signals for controlling the switch positions of a switched-capacitor (SC) network (not shown in <figref idref="DRAWINGS">FIG. 2</figref>) in response to the sampled outputs of the comparators, to allow the coarse control loop to select an assumed “best” one of multiple available frequency-voltage characteristics for the VCO. As long as predetermined voltage conditions are met (i.e., when the voltage Vcap satisfies VL&lt;Vcap and Vcap&lt;VH), the coarse control loop does not change the frequency-voltage characteristic of the VCO, but a fine control loop operates continuously to control the operating point along the current frequency-voltage characteristic. Coarse control implemented using the <figref idref="DRAWINGS">FIG. 2</figref> circuitry is adequate where the VCO's voltage-frequency relationship is predictable and does not change unless it is changed by the coarse control loop. However, if the VCO's frequency-voltage characteristic changes (e.g., as a result of a temperature change or other environmental change) without being affirmatively changed by the coarse control loop, or if the coarse control loop otherwise makes a wrong assumption about the current frequency-voltage characteristic for the VCO, the coarse control loop will infer an incorrect current VCO output frequency from the control voltage measurements and its (incorrect) assumptions about the currently employed frequency-voltage characteristic, and thus will not generate appropriate control signals for controlling the switch positions of the switched-capacitor (SC) network to select a “best” one of the multiple available frequency-voltage characteristics for the VCO.

0014For example, when the voltage Vcap satisfies VL&lt;Vcap and Vcap&lt;VH but is much closer to VH than to VL, the <figref idref="DRAWINGS">FIG. 2</figref> circuitry would not change the VCO's frequency-voltage characteristic, even where there is a high probability that a small change in supply voltage or temperature will cause the control voltage to rise above VH without any significant change in VCO output frequency (and although neither the coarse control circuitry nor fine control circuitry causes any change in operation of the VCO). If, for example, a small temperature change shifts the frequency-voltage characteristic downward, thereby increasing the control voltage to a value above VH (without significantly changing the VCO output frequency), the <figref idref="DRAWINGS">FIG. 2</figref> circuitry could undesirably cause a compensating change in the frequency-voltage characteristic that raises the control voltage, which then causes the fine control circuitry to decrease the control voltage to a level just slightly above VL. In this state, another slight change in supply voltage or temperature (lowering the control voltage to below VL without changing the VCO frequency) could cause the <figref idref="DRAWINGS">FIG. 2</figref> circuitry to execute another compensating change in the frequency-voltage characteristic, resulting in another move of the control voltage to another unstable value (a value slightly below VH), and so on. To prevent such unstable operation, in which the coarse control circuitry changes frequency-voltage characteristics too frequently, hysteresis must be provided. However, provision of hysteresis (e.g., by employing additional voltage comparators with reference voltages higher than VH and lower than VL) would have disadvantages (e.g., it could reduce the operating range of a selected frequency-voltage characteristic).

0015Another conventional scheme for implementing coarse control of a VCO (other than by VCO control voltage monitoring as described with reference to <figref idref="DRAWINGS">FIG. 2</figref>) is a frequency counting scheme in which edges of the VCO's output clock signal (and edges of a reference clock whose frequency is the target frequency) are counted directly. By counting such clock edges, a coarse control loop can compare the VCO output clock and reference clock frequencies and determine whether the output clock frequency is greater or less than the target frequency. Since this scheme does not assume any particular voltage-frequency relationship for the VCO, it can be used with a VCO whose operating range is less predictable than that of a typical LC VCO. However, the frequency counting method cannot itself resolve the ambiguity as to which one of multiple available frequency-voltage characteristics (all containing the target frequency) should be selected. One technique for resolving such ambiguity is to implement the PLL's coarse control loop to use predetermined rules to choose one of the candidate frequency-voltage characteristics. For example, the rules can select the lowest (or highest) candidate frequency-voltage characteristic (e.g., the candidate characteristic having lowest or highest average frequency in a given control voltage range). However, since the frequency counting method does not measure the actual control voltage, a coarse control loop relying only on the frequency counting method cannot reliably select (as an optimal frequency-voltage characteristic) one of multiple available frequency-voltage characteristics which has the target frequency nearest to the middle of its control voltage range. To reliably select (as an optimal frequency-voltage characteristic) the one of multiple candidate frequency-voltage characteristics which has the target frequency nearest to the middle of a control voltage range, a coarse control loop relying on the frequency counting method must also implement some other control technique (e.g., a complicated technique including a sweep through each of the candidate characteristics and selection of one of the candidate characteristics in which the target frequency lies nearest to the middle of the control voltage range).

0016It had not been known until the present invention how to implement both coarse and fine control loops in a PLL for reliable (but simply implemented) control of a ring oscillator (“ring OSC”) or other VCO whose voltage-frequency characteristic is unpredictable or changes even when not affirmatively changed by the coarse control loop. The frequency-voltage characteristic of a PLL using a ring OSC as a multi-range VCO is less predictable than that of a PLL using an LC VCO in place of the ring OSC, and tends to change during operation of the PLL even when not affirmatively changed by the coarse control loop. Preferred embodiments of the present invention implement coarse control of a PLL (whose multi-range VCO is implemented as a ring OSC), e.g., a PLL in a clock and data recovery (CDR) circuit, in accordance with a robust algorithm to avoid the need for frequent resetting of the PLL's coarse control loop.

SUMMARY OF THE INVENTION

0017In a class of embodiments, the invention is a PLL circuit (sometimes referred to herein as a “PLL” for convenience) for controlling a clock (e.g., a sampling clock). In other embodiments, the invention is a data sampling circuit including such PLL circuit. The PLL includes a multi-range voltage-controlled oscillator (“multi-range VCO”), at least one fine control loop for controlling the VCO (typically without changing its frequency-voltage characteristic), and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic as appropriate (e.g., to compensate for changes in the VCO's frequency-voltage characteristic due to environmental changes). The coarse control loop includes a frequency lock detector (typically implemented as frequency lock monitoring logic) and voltage range monitoring logic. When the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, the frequency lock detector locks operation of the coarse control loop. When not locked, typical embodiments of the coarse control loop operate in response to the output of the voltage range monitoring logic to change the VCO's frequency-voltage characteristic when the fine control voltage asserted to the VCO leaves a predetermined range (e.g., to compensate for changes in the VCO's frequency-voltage characteristic due to environmental changes). By locking operation of the coarse control loop using a frequency lock detector, the invention avoids problems and limitations (some of which have been noted above) of conventional PLLs which use only voltage range monitoring logic to implement coarse control. In preferred embodiments in this class, the coarse control loop of the inventive PLL implements a robust digital coarse control algorithm that employs both frequency lock monitor logic and voltage range monitoring logic to avoid unnecessary changes to the VCO's frequency-voltage characteristic while appropriately changing the frequency-voltage characteristic to compensate for changes (e.g., temperature, voltage, or other environmental changes) not affirmatively caused by the coarse control loop. In preferred embodiments, the invention employs two schemes (control voltage monitoring and frequency counting) in a coarse control loop to avoid the need to resolve ambiguities as to which one of multiple available frequency-voltage characteristics the coarse control loop should select (e.g., ambiguities that would otherwise arise when using only the frequency counting scheme) and avoid unnecessary changes to the VCO's frequency-voltage characteristic that would otherwise result from using only a control voltage monitoring scheme when the VCO's voltage-frequency relationship is unpredictable or changes during operation (e.g., as a result of a temperature change or other environmental change). The invention is especially useful to control a VCO of the ring oscillator type, or any other VCO for whose voltage-frequency characteristic is unpredictable or changes during operation.

0018Another aspect of the invention is a data sampling circuit including a PLL (of any of the types described in the previous paragraph). Another aspect of the invention is a 10 Gb Ethernet transceiver (typically implemented as or in a single CMOS IC) including a 10.3125-Gb/s serial interface, a four-channel 3.125-Gb/s interface (sometimes referred to as a “XAUI”), and at least one PLL implemented in the 10.3125-Gb/s serial interface in accordance with the invention. Other aspects of the invention are other devices that include any embodiment of the inventive PLL.

0019Some embodiments of the coarse control circuitry of the inventive PLL include digital circuitry for generating coarse control bits, and a DAC for generating a coarse control voltage (for assertion to a VCO) in response to the coarse control bits. When the VCO of the PLL is a ring oscillator including CMOS delay cells connected in a ring structure, use of the DAC allows each of the VCO's delay cells to be implemented much more simply than would be required if the coarse control bits were asserted directly to the VCO's delay cells.

0020Another aspect of the invention is a transceiver (e.g., a 10 Gb Ethernet transceiver, typically implemented as or in a single CMOS IC) including a first receiver interface configured to receive data having a first data rate (e.g., a four-channel 3.125-Gb/s interface comprising four layers, or another multi-layered receiver interface), a second receiver interface configured to receive data at a second data rate greater than the first data rate (e.g., a 10.3125-Gb/s receiver interface), at least one transmitter interface configured to transmit data having a third data rate (identical to or different than the second data rate) greater than the first data rate (e.g., a 10.3125-Gb/s transmitter interface), and additional circuitry (e.g., circuitry for performing physical coding sub-layer (PCS) and management functions). The device implements a clocking scheme in which no more than three phase locked loops are used for clock generation. For example, the transceiver can include only three clock-generating PLLs: a first PLL in circuitry which generates all clocks generated (and needed) by the first receiver interface and at least one clock needed by the additional circuitry; a second PLL in circuitry which generates all clocks needed by the second receiver interface and at least one clock generated (and needed) by the additional circuitry; and a third PLL in circuitry which generates all clocks generated (and needed) by the transmitter interface and at least one clock needed by the additional circuitry.

0021Another aspect of the invention is a transceiver (e.g., a 10 Gb Ethernet transceiver, typically implemented as or in a single CMOS IC) including a multi-layered receiver interface for receiving and sampling signals, each of the signals being indicative of data having a first data rate (e.g., a four-channel 3.125-Gb/s interface). The receiver interface includes digital circuitry and a single clock-generating PLL: an analog PLL circuit for generating a multiphase clock (to be shared by all layers of the receiver interface). The analog PLL circuit generates all clocks (including the multiphase clock) generated by the receiver interface, or each clock (other than the multiphase clock) generated by the receiver circuitry is generated by circuitry that does not include (and is not) a clock-generating PLL. Each layer of the receiver interface performs blind oversampling on one of the received signals using the multiphase clock. The digital circuitry of the receiver interface includes multilayered digital phase lock loop (DPLL) circuitry which receives the oversampled data. Each layer of the DPLL circuitry effectively selects one phase of the multiphase clock at which one received signal is sampled (by selecting a subset of the oversampled data samples having a “best” phase). The DPLL circuitry typically includes a phase detector (“PD”) that determines a phase error (φ_Δ) present between each of multiple sampling clocks (determined by the multiphase clock) and data (determined by a received signal) being sampled by each such sampling clock. Because all layers of the receiver interface implement blind oversampling, the digital circuitry (including each layer of the DPLL circuitry) of the receiver interface (and any analog circuitry, other than the analog PLL circuit, of the receiver interface) can share the multiphase clock and/or use clocks derived therefrom. Thus, synchronization is readily achieved between all clocks employed by the receiver interface. When the receiver interface is integrated with additional digital circuitry, and the only analog circuitry in the receiver interface is the shared analog PLL circuit, the digital circuitry of the receiver interface (including the DPLL circuitry) can be synthesized along with the additional digital circuitry, e.g., to achieve good portability.

0022Other aspects of the invention are a transceiver (preferably implemented as an integrated circuit) including any embodiment of the inventive PLL, a transmitter (preferably implemented as an integrated circuit) including any embodiment of the inventive PLL, and a receiver (preferably implemented as an integrated circuit) including any embodiment of the inventive PLL.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="DRAWINGS">FIG. 1A</figref> is a graph of a frequency versus control voltage characteristic of a VCO in a PLL. The characteristic has a relatively large slope (VCO gain) when the PLL operates in response to a control voltage in a range from VL (a minimum control voltage) to VH (a maximum control voltage).

<figref idref="DRAWINGS">FIG. 1B</figref> is a graph of a set of frequency versus control voltage characteristics of a VCO in a modified version of the PLL whose characteristic is graphed in <figref idref="DRAWINGS">FIG. 1A</figref>. The PLL is configured so that each characteristic can be selected in accordance with a coarse control algorithm. Each characteristic has a relatively small slope (VCO gain) when the PLL operates in response to a control voltage in the range from VL to VH.

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of conventional circuitry for use in a coarse control loop of a PLL including a multi-range VCO.

<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram of an integrated circuit implementation of a 10 Gb Ethernet transceiver which is an embodiment of the invention.

<figref idref="DRAWINGS">FIG. 3A</figref> is block diagram of an implementation of circuitry <b>12</b> (which is a 10.3125 Gb/s receiver) of <figref idref="DRAWINGS">FIG. 3</figref>.

<figref idref="DRAWINGS">FIG. 3B</figref> is a block diagram of one layer of circuitry <b>20</b> of <figref idref="DRAWINGS">FIG. 3</figref>.

<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram of elements of the coarse control circuitry of <figref idref="DRAWINGS">FIG. 3A</figref>.

<figref idref="DRAWINGS">FIG. 5A</figref> is a flow chart of steps performed during typical operation of the coarse control circuitry of <figref idref="DRAWINGS">FIG. 3A</figref>.

<figref idref="DRAWINGS">FIG. 5B</figref> is a graph of frequency versus control voltage characteristics of VCO <b>30</b> of <figref idref="DRAWINGS">FIG. 3A</figref>, with reference to which typical operation of the fine and coarse control circuitry of <figref idref="DRAWINGS">FIG. 3A</figref> is described.

<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of an embodiment of voltage range conditioning circuitry <b>37</b> of <figref idref="DRAWINGS">FIG. 3A</figref>, filter <b>29</b> of <figref idref="DRAWINGS">FIG. 3A</figref>, and an embodiment of VCO <b>30</b> of <figref idref="DRAWINGS">FIG. 3A</figref>.

<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram of an embodiment of a delay cell of the <figref idref="DRAWINGS">FIG. 6</figref> embodiment of VCO <b>30</b>.

<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram of elements of an implementation of circuitry <b>14</b> (which is a 10.3125 Gb/s transmitter) of <figref idref="DRAWINGS">FIG. 3</figref>.

<figref idref="DRAWINGS">FIG. 9</figref> is a schematic diagram of driver <b>63</b> of <figref idref="DRAWINGS">FIG. 8</figref>.

<figref idref="DRAWINGS">FIG. 10</figref> is a schematic diagram of VCO <b>42</b> of <figref idref="DRAWINGS">FIG. 8</figref>.

<figref idref="DRAWINGS">FIG. 11</figref> is a block diagram of elements of the <figref idref="DRAWINGS">FIG. 3</figref> transceiver, shown partitioned into three clock domains.

<figref idref="DRAWINGS">FIG. 12</figref> is a block diagram of a “divide by 8.25” frequency divider that can be used in a transceiver that embodies the invention.

<figref idref="DRAWINGS">FIG. 13</figref> is a schematic diagram of an implementation of a “divide by 1.5” frequency divider used in the <figref idref="DRAWINGS">FIG. 12</figref> frequency divider.

<figref idref="DRAWINGS">FIG. 14</figref> is a timing diagram showing signals received or generated by the <figref idref="DRAWINGS">FIG. 13</figref> circuit.

<figref idref="DRAWINGS">FIG. 15</figref> is a schematic diagram of an implementation of a “divide by 5.5” frequency divider used in the <figref idref="DRAWINGS">FIG. 12</figref> frequency divider.

<figref idref="DRAWINGS">FIG. 16</figref> is a timing diagram showing signals received or generated by the <figref idref="DRAWINGS">FIG. 15</figref> circuit.

<figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) is a simplified block diagram of a ÷16.5 frequency divider that can be employed in the <figref idref="DRAWINGS">FIG. 3</figref> transceiver (e.g., to implement frequency divider <b>32</b> of <figref idref="DRAWINGS">FIG. 3A</figref> and <figref idref="DRAWINGS">FIG. 4)</figref>. The frequency divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) includes ÷3 frequency divider <b>120</b>, and ÷5.5 frequency divider <b>121</b> coupled to receive the differential output of ÷3 divider <b>120</b>.

<figref idref="DRAWINGS">FIG. 17(</figref><i>b</i>) is a timing diagram of signals received or generated by the <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) circuit. In <figref idref="DRAWINGS">FIG. 17(</figref><i>b</i>), circuit delay is ignored for simplicity.

<figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) is a simplified schematic diagram of a portion of an embodiment of the ÷3 frequency divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>), including a conventional ÷3 frequency divider (block <b>130</b>) implemented using single-edge-triggered flip-flops (“STFFs”) <b>131</b> and <b>132</b>, and additional elements (<b>133</b> and <b>134</b>) connected as shown.

<figref idref="DRAWINGS">FIG. 18(</figref><i>b</i>) is a timing diagram of signals received or generated by the <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) circuit.

<figref idref="DRAWINGS">FIG. 19(</figref><i>a</i>) is a timing diagram of signals received or generated by a conventional ÷3 frequency divider (i.e., block <b>130</b> of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>)).

<figref idref="DRAWINGS">FIG. 19(</figref><i>b</i>) is a block diagram of a conventional ÷1.5 frequency divider having the same structure as block <b>130</b> of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) but implemented using double-edge-triggered flip-flops (“DTFFs”) instead of STFFs <b>131</b> and <b>132</b> of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>). <figref idref="DRAWINGS">FIG. 19(</figref><i>b</i>) also includes a timing diagram of signals received or generated by the ÷1.5 frequency divider of <figref idref="DRAWINGS">FIG. 19(</figref><i>b</i>).

<figref idref="DRAWINGS">FIG. 20</figref> is a schematic diagram of a DTFF that can be used in an implementation of the ÷5.5 frequency divider of the ÷16.5 frequency divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>).

<figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) is a simplified schematic diagram of an embodiment of the ÷5.5 frequency divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>).

<figref idref="DRAWINGS">FIG. 21(</figref><i>b</i>) is a state diagram for the circuit of <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>).

<figref idref="DRAWINGS">FIG. 22</figref> is a simplified schematic diagram of an implementation of each of circuits <b>140</b>, <b>141</b>, <b>142</b>, and <b>143</b> of <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>).

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

0053<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram of an integrated circuit implementation of a 10 Gb Ethernet transceiver which is an embodiment of the invention. Transceiver chip <b>10</b> of <figref idref="DRAWINGS">FIG. 3</figref> includes a 10.3125 Gb/s Serializer/Deserializer (SerDes) including 10.3125 Gb/s receiver <b>12</b> and 10.3125 Gb/s transmitter <b>14</b>, a four-layer 3.125 Gb/s SerDes including four-layer 3.125 Gb/s transmitter <b>17</b>, four-layer 3.125 Gb/s receiver <b>19</b>, and four-layer digital phase lock loop (DPLL) circuitry <b>20</b>, and physical coding sublayer (PCS) circuitry <b>16</b> between the 10.3125 Gb/s SerDes and the 3.125 Gb/s SerDes. Transmitter <b>14</b> is configured to transmit over a serial link a differential signal indicative of a bit stream having data rate 10.3125 Gigabits/second. Receiver <b>12</b> is configured to receive (from a serial link) and sample a differential signal indicative of a bit stream having data rate 10.3125 Gigabits/second. Transmitter <b>17</b> is configured to transmit four differential signals, each over a different serial link, each such signal being indicative of a bit stream having data rate 3.125 Gigabits/second.

0054Receiver <b>19</b> includes four circuits (denoted herein as “layers”), each coupled to receive a different one of four differential input signals. Each of the input signals is indicative of a different bit stream having data rate 3.125 Gigabits/second. Although the incoming data rates of the signals received by receiver <b>19</b> are the same, the phases of the data streams recovered therefrom can be different from each other.

0055Receiver <b>19</b> and DPLL <b>20</b> could be replaced by four receiver layers, each implementing a tracking type CDR, but the tracking type CDR circuitry would require at least four different clock domains and the four data streams recovered by the CDR circuitry would thus need to be retimed to one central clock. Instead, this troublesome clock synchronization problem is eliminated by employing receiver <b>19</b> and DPLL <b>20</b> to perform blind oversampling of the incoming signals and selection of a subset of the resulting samples as the recovered data, with all layers of receiver <b>19</b> and DPLL <b>20</b> sharing a single clock domain. Instead of implementing each layer of receiver <b>19</b> to track incoming data with its own PLL, the <figref idref="DRAWINGS">FIG. 3</figref> embodiment uses shared analog PLL <b>18</b> to generate a fixed frequency multiphase clock signal which is shared by receiver <b>19</b>, DPLL <b>20</b>, and transmitter <b>17</b>. A data selector within DPLL <b>20</b> selects recovered data (from among the blind oversampled data samples asserted to DPLL <b>20</b>), preferably using a digital edge tracking algorithm.

0056The expression “multiphase clock” is used herein to denote a set of L clocks, each having frequency f_dckand each having a different phase φ_mthat satisfies φ_m=φ_offset÷2π(m/L)+Δφ_mwhere the index “m” is a non-negative integer in the range {0, . . . , L-1}, and Δφ_mis an error term. Typically Δφ_mis much smaller than the phase increment 27π/L, and a multi-phase clock set is generated to approximate (as closely as is practical) an ideal multi-phase clock set consisting of L clocks, each having frequency f_dckand each having a different phase φ_m=φ_offset+2π(m/L). In typical applications, a multiphase clock is generated in response to a principal clock having frequency f_dckand phase φ_offset(in other typical applications, the principal clock has frequency other than f_dck).

0057Receiver <b>19</b> and DPLL <b>20</b> employ a blind oversampling CDR technique as described in, for example, K. Lee et al., “A CMOS Serial Link for Fully Duplexed Data Communication,” <i>IEEE J. Solid</i>-<i>State Circuits</i>, vol. 30, pp. 353–364, April 1995. Since a blind oversampling CDR simply selects recovered data from among equally-spaced samples (generated using an oversampling clock) generated during each bit period instead of continuously adjusting the sample timing, the four layers of receiver <b>19</b>, the four layers of transmitter <b>17</b>, and the layers of DPLL <b>20</b>, can and do share a common multiphase clock domain. Thus, synchronization is readily achieved between all clocks employed by receiver <b>19</b> and DPLL <b>20</b>. When analog PLL <b>18</b>, receiver <b>19</b>, DPLL <b>20</b>, and PCS circuitry <b>16</b> are integrated within a single chip, and there is only digital circuitry (not analog circuitry) within DPLL <b>20</b> and PCS circuitry <b>16</b>, the digital circuitry of DPLL <b>20</b> and PCS circuitry <b>16</b> can be synthesized, e.g., to achieve good portability.

0058Still with reference to <figref idref="DRAWINGS">FIG. 3</figref>, analog PLL <b>18</b> includes a VCO (implemented as a ring oscillator including CMOS delay cells connected in a ring structure) which is controlled to generate a multiphase clock (having 20 different phases). Each individual clock of this multiphase clock has frequency 781.25 MHz. Since each layer of receiver <b>19</b> receives incoming data at the rate 3.125 Gb/s, each layer is configured to process groups of four sequentially received bits in parallel, in the following sense. During each cycle of the multiphase clock (i.e., once during each period of duration (781.25 MHz)⁻¹), each layer of receiver <b>19</b> performs blind <b>5</b>×-oversampling on the incoming signal using the multiphase clock to generate twenty samples of the incoming signal. Each set of twenty samples is 5×-oversampled data indicative of four sequentially received bits of the received signal. Each layer of receiver <b>19</b> is implemented with a parallel architecture (to process groups of four sequentially received bits in parallel) so that receiver <b>19</b> can operate in response to a clock having lower frequency (781.25 MHz) than the incoming data rate (4*781.25 Mb/s=3.125 Gb/s), and so that this relatively low frequency (781.25 MHz) clock can also be used by other circuitry in the transceiver (e.g., DPLL <b>20</b>) which could not practically operate in response to a higher frequency clock. Thus, a preferred implementation of receiver <b>19</b> asserts a sequence of 80-bit data sample words to DPLL <b>20</b> (twenty sample bits from each layer of receiver <b>19</b> to a corresponding layer of DPLL <b>20</b> per cycle of the 781.25 MHz) clock). Once per cycle of the 781.25 MHz clock, DPLL <b>20</b> selects a best one of each set of five candidate samples from receiver <b>19</b>, and each layer of DPLL <b>20</b> outputs a best four-sample subset of a set of twenty candidate samples. Thus, DPLL <b>20</b> asserts to PCS circuitry <b>16</b> a total of sixteen recovered data bits (indicative of four bits of each of the four incoming signals) during each cycle of the 781.25 MHz clock.

0059<figref idref="DRAWINGS">FIG. 3B</figref> shows the structure of a preferred implementation of one of the four identical layers of DPLL <b>20</b>, which includes a data shifter, edge detection circuitry, majority voter circuitry, shift registers, unanimous voter circuitry, and phase counter logic, connected as shown. During each cycle of the 781.25 MHz clock, twenty samples (candidate samples) of blind oversampled data (from one layer of receiver <b>19</b>) are loaded into the data shifter of <figref idref="DRAWINGS">FIG. 3B</figref>. A phase selection word (“φ[0:4]”) asserted by the phase counter logic selects a four-sample subset from each set of twenty candidate samples for output (as “recovered data”) from this layer of DPLL <b>20</b> to PCS circuitry <b>16</b>. Specifically, {φ[0]=0, φ[1]=0, φ[2]=1, φ[3]=0, and φ[4]=0} selects the third one of each set of five consecutive candidate samples as a bit of recovered data, {φ[0]=0, φ[1]=1, φ[2]=0, φ[3]=0, and φ[4]=0} selects the second one of each set of five consecutive candidate samples as a bit of recovered data, and so on. The edge detector and the majority voter circuitry examine the twenty candidate samples in the data shifter to determine therefrom the phase of the transitions between successive ones of the four bits of data represented by the twenty candidate samples (i.e., to determine a data transition phase), and to generate filtered binary control bits (“up,” “down,” and “stay”) indicative of relation between the data transition phase and the phase determined by the current phase selection word φ[0:4] (where the “phase” determined by the current phase selection word φ[0:4] can be denoted as “n” when φ[n]=1 and all other bits of φ[0:4] are indicative of logical zeros). The filtered binary control bits are used for clock phase adjustment, in the sense that they are used to update the current phase selection word φ[0:4]. The majority voter circuitry filters raw binary control bits (“up,” “down,” and “stay”) generated by the edge detector to filter out false indications of phase mismatch, and thereby prevent the bits of the phase selection word φ[0:4] from being changed too frequently. Once per cycle of the 781.25 MHz clock, the shift registers and unanimous voter circuitry generate updated control bits “Pup” and “Pdn” in response to the filtered binary control bits from the majority voter circuitry. The control bits “Pup” and “Pdn” determine whether the phase determined by the current phase selection word φ[0:4] should be advanced or retarded. The unanimous voter circuitry generates control bits “Pup” and “Pdn” that cause advancement of the phase determined by the current phase selection word φ[0:4] only in response to three consecutive decisions by the majority voter circuitry (in the three most recent cycles of the 781.25 MHz clock) to advance such phase. Similarly, the unanimous voter circuitry generates control bits “Pup” and “Pdn” that cause retardation of the phase determined by the current phase selection word φ[0:4] only in response to three consecutive decisions by the majority voter circuitry (in the three most recent cycles of the 781.25 MHz clock) to retard such phase. The phase counter updates the phase selection word φ[0:4] in response to the control bits “Pup” and “Pdn.” Thus, the unanimous voter circuitry functions as a low pass filter.

0060With reference again to <figref idref="DRAWINGS">FIG. 3</figref>, PCS circuitry <b>16</b> is configured to perform several digital functions such as 8 bit/10 bit coding, 64 bit/66 bit coding, clock rate compensation, deskew, word alignment, gearbox, and flow control functions. Since the recovered data from the four layers of DPLL <b>20</b> are already in a single clock domain, PCS circuitry <b>16</b> can be implemented much more simply to perform word alignment and deskew functions than would otherwise be required, and the size of FIFOs within PCS circuitry <b>16</b> can be smaller than would otherwise be required if receiver <b>19</b> and DPLL <b>20</b> were replaced by four receiver layers, each implementing a tracking type CDR. Instead of adjusting PLL frequency to incoming data rate, receiver <b>19</b> oversamples the incoming signals using a fixed frequency multiphase clock generated by analog PLL <b>18</b>. Thus, DPLL <b>20</b>, which includes frequency compensation logic that compensates for the frequency offset between the incoming data and the system clock can be integrated in the same block of digital circuitry in which PCS circuitry <b>16</b> is implemented. Since all of receiver <b>19</b>, transmitter <b>17</b>, receiver <b>12</b>, and transmitter <b>14</b> use the same reference clock (in a preferred implementation of transceiver <b>10</b> of <figref idref="DRAWINGS">FIG. 3</figref>), there is no need for such preferred implementation of transceiver <b>10</b> to include frequency compensation logic between receiver <b>19</b> and transmitter <b>14</b>. The gearbox circuitry (within PCS circuitry <b>16</b>) between receiver <b>19</b> and transmitter <b>14</b> is preferably of the type specified by the above-referenced “10 Gb Ethernet” standard, which converts the data width from 33 bits to 32 bits without changing the data throughput. In order not to change total throughput, the gearbox circuitry between receiver <b>19</b> and transmitter <b>14</b> uses a 322.27 MHz clock (as indicated in <figref idref="DRAWINGS">FIG. 11</figref>) along with a 312.5 MHz clock (33/32×312.5 MHz=322.27 MHz). The gearbox circuitry (within PCS circuitry <b>16</b>) between receiver <b>12</b> and transmitter <b>17</b> is preferably also of the type specified by the above-referenced “10 Gb Ethernet” standard, and this gearbox circuitry also uses a 322.27 MHz clock along with a 312.5 MHz clock (as indicated in <figref idref="DRAWINGS">FIG. 11</figref>).

0061Preferably, each block of <figref idref="DRAWINGS">FIG. 3</figref> is optimized to maximize performance and to reduce the overall complexity of transceiver <b>10</b>. For example, transmitter <b>14</b> includes an LC-VCO (VCO <b>42</b>) for better jitter performance (although this type of VCO requires more area on the chip), but receiver <b>12</b> includes a ring OSC (VCO <b>30</b>) which includes CMOS delay cells connected in a ring structure, since such a ring OSC can be implemented using less area on the chip than would be required to implement an LC-vCO.

0062<figref idref="DRAWINGS">FIG. 11</figref> is a block diagram of elements of transceiver <b>10</b> of <figref idref="DRAWINGS">FIG. 3</figref>, showing how they are partitioned into three clock domains. One domain includes analog PLL circuitry <b>18</b> which generates a 781.25 MHz multiphase clock for transmitter <b>17</b>, receiver <b>19</b>, and DPLL <b>20</b>, and a 312.5 MHz clock for DPLL <b>20</b> and 8 bit/10 bit encoding portion <b>16</b>A, elastic buffer portion <b>16</b>B, and word alignment, decoding, deskewing, frequency compensation, and 64 bit/66 bit encoding portion <b>16</b>E of circuitry <b>16</b>. The second domain includes receiver <b>12</b> which uses a 2.578 GHz clock to sample a received data signal and includes a “divide by 8.25” frequency divider for generating a 312.5 MHz clock (from the 2.578 GHz clock) for use within receiver <b>12</b> and by elastic buffer portion <b>16</b>B, 64 bit/66 bit decoding portion <b>16</b>C, and gearbox portion <b>16</b>D of circuitry <b>16</b>, and also generates a 322.27 MHz clock for use by gearbox portion <b>16</b>D of circuitry <b>16</b>. The third domain includes clock-multiplying unit portion <b>14</b>A of transmitter <b>14</b> which generates a 10.3125 GHz clock for use within portion <b>50</b> of transmitter <b>14</b>, and includes a “divide by 32” frequency divider for generating a 322.27 MHz clock (from the 10.3125 GHz clock) for use by gearbox portion 16F of circuitry <b>16</b>. Each clock domain receives and operates in response to a 156.25 MHz reference clock.

0063The “divide by 8.25” frequency divider within receiver <b>12</b> can be implemented by cascaded “divide by 1.5” and “divide by 5.5” frequency divider circuits as shown in <figref idref="DRAWINGS">FIG. 12</figref>. The divide by 1.5 circuit can be realized using a double edge triggered flip-flop (“double edge triggered D-FF” or “DEFF”) in place of a single edge triggered flip flop (“single edge triggered D-FF” or “SEFF) in a conventional “divide by 3” circuit. <figref idref="DRAWINGS">FIG. 13</figref> is a schematic diagram of an implementation of the “divide by 1.5” frequency divider, <figref idref="DRAWINGS">FIG. 14</figref> is a timing diagram showing signals received or generated by the <figref idref="DRAWINGS">FIG. 13</figref> circuit, <figref idref="DRAWINGS">FIG. 15</figref> is a schematic diagram of an implementation of the “divide by 5.5” frequency divider, and <figref idref="DRAWINGS">FIG. 16</figref> is a timing diagram showing signals received or generated by the <figref idref="DRAWINGS">FIG. 15</figref> circuit.

0064The frequency divider of <figref idref="DRAWINGS">FIG. 13</figref> receives input clock CK, the inverse (“CKB”) of clock CK, a 90′-phase-delayed version (“CKQ”) of clock CK (CKQ has 90° phase delay relative to clock CK), and the inverse (“CKQB”) of clock CKQ. The frequency divider of <figref idref="DRAWINGS">FIG. 13</figref> includes logic for generating signals Q<b>2</b>, Q<b>3</b>, Q<b>4</b>, and Q<b>5</b> whose waveforms are shown in <figref idref="DRAWINGS">FIG. 14</figref>, and duty cycle corrector <b>101</b> which generates the differential clock output (CK<b>1</b><i>p</i><b>5</b> and CK<b>1</b><i>p</i><b>5</b>B) of <figref idref="DRAWINGS">FIG. 13</figref> in response to signals Q<b>3</b> and Q<b>5</b>. Duty cycle corrector <b>101</b> generates each component CK<b>1</b><i>p</i><b>5</b> and CK<b>1</b><i>p</i><b>5</b>B of the differential clock output with a duty cycle of 50% to maximize the timing margin of the “divide by 5.5” frequency divider of <figref idref="DRAWINGS">FIG. 15</figref>. In contrast, <figref idref="DRAWINGS">FIG. 14</figref> shows that the duty cycle of signal Q<b>2</b> (generated by a double edge triggered flip-flop of the <figref idref="DRAWINGS">FIG. 13</figref> circuitry) is 33%. To allow generation of each component (CK<b>1</b><i>p</i><b>5</b> and CK<b>1</b><i>p</i><b>5</b>B) of the differential clock output with a 50% duty cycle, the Q<b>2</b> signal is sequentially latched as indicated to generate the signals Q<b>3</b>, Q<b>4</b> and Q<b>5</b>. Using the rising edge of Q<b>3</b> and Q<b>5</b>, the duty cycle corrector generates components CK<b>1</b><i>p</i><b>5</b> and CK<b>1</b><i>p</i><b>5</b>B of the differential clock output.

0065The frequency divider of <figref idref="DRAWINGS">FIG. 15</figref> has the design of a conventional “divide by 11” frequency divider with two conventional double edge triggered flip-flops replaced by a pair of single edge triggered flip-flops that generate output clock CK<b>5</b><i>p</i><b>5</b> as indicated. The frequency divider of <figref idref="DRAWINGS">FIG. 15</figref> generates output clock CK<b>5</b><i>p</i><b>5</b> in response to the differential clock (CK<b>1</b><i>p</i><b>5</b> and CK<b>1</b><i>p</i><b>5</b>B) generated by the <figref idref="DRAWINGS">FIG. 13</figref> circuit, but the components of differential clock CK<b>1</b><i>p</i><b>5</b> and CK<b>1</b><i>p</i><b>5</b>B are respectively labeled CK and CKB in <figref idref="DRAWINGS">FIG. 15</figref> for convenience. The duty cycle of FIG. <b>15</b>'s output signal CK<b>5</b><i>p</i><b>5</b> is 5/11. Since the duty cycle of output signal CK<b>5</b><i>p</i><b>5</b> is nearly 50% and this signal has relatively low frequency, there is no need for the <figref idref="DRAWINGS">FIG. 15</figref> circuit to include a duty cycle corrector (similar to that included in <figref idref="DRAWINGS">FIG. 13</figref>).

0066Receiver <b>12</b> preferably includes a “divide by 16.5” frequency divider (i.e., “divide by 16.5” frequency divider <b>32</b> of <figref idref="DRAWINGS">FIG. 3A</figref>), to be described below. This “divide by 16.5” frequency divider can be implemented in any way, but is preferably implemented as a cascade of the above-described “divide by 8.25” and a conventional “divide by 2” frequency divider. If the “divide by 16.5” frequency divider is implemented by cascaded “divide by 8.25” and “divide by 2” dividers, the “divide by 8.25” divider can be used to generate the above-discussed 312.5 MHz clock used by circuitry <b>16</b>B, <b>16</b>C, and <b>16</b>D of <figref idref="DRAWINGS">FIG. 11</figref>, as well as to provide input to the “divide by 2” divider (or to receive the output of the “divide by 2” divider).

0067Receiver <b>12</b> of <figref idref="DRAWINGS">FIG. 3</figref> recovers a stream of binary data and a 5.15625 GHz clock from the signal it receives over the indicated 10.3125 Gb/s serial link, preferably using binary phase detection with a dead-zone (for example, as described in B. J. Lee et al., “A 2.5–10 Gb/s CMOS Transceiver with Alternating Edge Sampling Phase Detection for Loop Characteristic Stabilization,” <i>ISSCC Dig. Tech. Papers</i>, pp. 76–77, February 2003). The CDR circuitry of receiver <b>12</b> (to be described below) uses multiphase clocks for clock and data recovery, and the VCO within receiver <b>12</b> is a ring oscillator (“ring OSC”) that occupies only a small area of the transceiver chip.

0068We next describe typical implementations of 10 Gb/s receiver <b>12</b> of <figref idref="DRAWINGS">FIG. 3</figref>. As shown in <figref idref="DRAWINGS">FIG. 3</figref>, sampling circuitry (sampler) <b>22</b> of receiver <b>12</b> generates samples of a signal received by transceiver <b>10</b> over a 10.3125 Gb/s serial link, using a 2.578 GHz clock generated by VCO <b>30</b>. VCO <b>30</b> is a ring OSC, including CMOS delay cells connected in a ring structure and having inputs for fine control voltages and coarse control voltages. Serial to parallel conversion circuitry <b>24</b> parallelizes the samples generated by sampler <b>22</b> and asserts them to PCS circuitry <b>16</b> for decoding and other processing. Receiver <b>12</b> includes PLL circuitry (including a coarse control loop and two fine control loops) for controlling VCO <b>30</b>. <figref idref="DRAWINGS">FIG. 3</figref> shows some elements of the fine control loops and coarse control circuitry <b>34</b> of the coarse control loop. The PLL circuitry controls VCO <b>30</b> to cause it to generate the 2.578 GHz clock (for use by sampling circuitry <b>22</b>), including by locking the frequency of VCO <b>30</b>'s output to a 156.25 MHz reference clock.

0069<figref idref="DRAWINGS">FIG. 3A</figref> shows additional details of an implementation of receiver <b>12</b> of <figref idref="DRAWINGS">FIG. 3</figref>. The <figref idref="DRAWINGS">FIG. 3A</figref> implementation has a dual-loop CDR architecture including a data recovery loop and a frequency acquisition loop for control of VCO <b>30</b> (both of these loops to be referred to as fine control loops) and an additional coarse control loop. The coarse control loop allows the PLL to achieve the target frequency despite PVT variations, while keeping the voltage-to-frequency gain of VCO <b>30</b> small. Only after both coarse control fix (in which the coarse control loop determines a coarse control voltage to cause VCO <b>30</b> to operate with an appropriate one of multiple available frequency-voltage characteristics) and frequency lock (accomplished by the frequency acquisition loop), control circuitry (with coarse control block <b>34</b>) activates the data recovery loop (i.e., causes switch <b>35</b> to assert the output of charge pump circuitry <b>28</b> to low pass filter <b>29</b>). This control circuitry does not reactivate the frequency acquisition loop (i.e., by causing switch <b>35</b> to assert the output of charge pump <b>33</b>A to low pass filter <b>29</b>) unless frequency lock is broken.

0070While active, the frequency acquisition loop operates (with the coarse control loop) to achieve frequency lock between the output of VCO <b>30</b> and the 156.25 MHz reference clock. More specifically, “divide by 16.5” frequency divider <b>32</b> of the frequency acquisition loop generates a frequency-divided clock in response to a clock (having frequency at least substantially equal to 2.578 GHz) output from VCO <b>30</b>. When frequency lock is achieved, the output of VCO <b>30</b> has frequency 2.578 GHz, and the frequency-divided clock output from divider <b>32</b> has frequency 156.25 MHz. Before frequency lock is achieved, phase-frequency detector (PFD) <b>33</b> of the frequency acquisition loop generates control signals (identified as “up” and “dn” in <figref idref="DRAWINGS">FIG. 3A</figref>) indicating whether the frequency of VCO <b>30</b>'s output should be increased or decreased. In response to the control signals from PFD <b>33</b>, charge pump <b>33</b>A generates a current having magnitude for controlling the state of VCO <b>30</b>. While the frequency acquisition loop is active, switch <b>35</b> passes this control current from charge pump <b>33</b>A to low pass filter (LPF) <b>29</b>, and LPF <b>29</b> generates a fine control voltage for VCO <b>30</b> in response to the control current. When frequency lock is achieved (and after coarse control fix), control circuitry (within coarse control circuitry <b>34</b>) coupled to switch <b>35</b> places switch <b>35</b> in a state in which it decouples charge pump <b>33</b>A from LPF and instead couples LPF <b>29</b> to the output of charge pump circuitry <b>28</b>.

0071With reference again to <figref idref="DRAWINGS">FIG. 3A</figref>, VCO <b>30</b> is controlled to generate a multiphase clock having eight different phases. Each individual clock of this multiphase clock has frequency at least substantially equal to 2.578 GHz. Sampler <b>22</b> includes twelve identical sampling layers, and circuitry for generating from the multiphase clock (output from VCO <b>30</b>) a second 2.578 GHz multiphase clock having twelve different phases. Each layer of sampler <b>22</b> operates as follows in response to a different one of the twelve individual 2.578 GHz clocks of the second multiphase clock. Sampler <b>22</b> receives a signal indicative of data having the rate 10.3125 Gb/s, and the incoming signal is asserted to each layer of sampler <b>22</b>. During each cycle of the second multiphase clock (i.e., once during each period of duration (2.578 GHz)⁻¹), each layer of sampler <b>22</b> uses a different one of the individual clocks of the second multiphase clock to generate one sample of the incoming signal. During each cycle of the second multiphase clock, data selection circuitry within sampler <b>22</b> receives a new set of twelve samples from the twelve layers, and (once per cycle of the 2.578 GHz multiphase clock) selects a best four-sample subset (having a best one of a first phase, a second phase, and a third phase) of this set of samples (i.e., the data selection circuitry selects the first, fourth, seventh, and tenth samples of the set, or the second, fifth, eighth, and eleventh samples of the set, or the third, sixth, ninth, and twelfth samples of the set). The samples in each selected four-sample subset thus comprise a “best” sample of each of four successive bits of the incoming serial data received by sampler <b>22</b>, and sampler <b>22</b> asserts to serial to parallel conversion circuitry <b>24</b> (shown in <figref idref="DRAWINGS">FIG. 3</figref>) a total of four recovered data bits (indicative of four successive bits of the incoming serial data) during each cycle of the 2.578 GHz clock.

0072Sampler <b>22</b> is implemented with a parallel architecture with a sufficient number of layers (i.e., twelve layers of sampling circuitry in a preferred implementation) so that it can operate in response to a sufficiently low frequency multiphase clock (or in other words, so that it can operate at sufficiently lower speed than if it were implemented with fewer layers). For example, a preferred twelve-layer implementation of sampler <b>22</b> asserts to circuitry <b>24</b> (of <figref idref="DRAWINGS">FIG. 3</figref>) a sequence of four-bit data sample words DS[0:3], each bit from a different layer of sampler <b>22</b>, in response to a multiphase sampling clock having frequency F (e.g., F=2.578 GHz), thereby recovering data from the incoming signal at the same sample rate that could be attained by omitting all but three layers of sampler <b>22</b> and operating the remaining layers in response to a multiphase sampling clock having frequency 4F (e.g., 4F=10.3125 GHz) and three different phases.

0073As described, preferred implementations of sampler <b>22</b> implement <b>3</b>×oversampling, so that sampler <b>22</b> generates twelve “candidate” samples during each cycle of the 2.578 GHz clock. While the data recovery loop of <figref idref="DRAWINGS">FIG. 3A</figref> is active, circuitry within sampler <b>22</b> (including binary phase detector circuitry <b>26</b> and charge pump circuitry <b>28</b>) continuously operates to control the phase of the multiphase clock generated by VCO <b>30</b>. Since sampler <b>22</b> generates three candidate samples for each bit period of the incoming serial data, and the phase of all three of these candidate samples depends on the phase of the multiphase clock generated by VCO <b>30</b>, the middle one of each set of three candidate samples is typically selected as the “best” sample for the bit period. The four samples selected (during each cycle of the 2.578 GHz clock) from the current set of four (three-bit) candidate sample sets determine a best sample of each of the four bits determined current set of twelve candidate samples. As a result, sampler <b>22</b> outputs a “best” four-sample subset of each set of twelve candidate samples during each cycle of the 2.578 GHz multiphase clock.

0074Binary phase detector circuitry <b>26</b> and charge pump circuitry <b>28</b> of sampler <b>22</b> are elements of the data recovery loop of <figref idref="DRAWINGS">FIG. 3A</figref>. The data recovery loop is active when frequency lock has been achieved and coarse control fix has been accomplished. Binary phase detector circuitry <b>26</b> receives each set of twelve samples output from sampler <b>22</b> per cycle of the 2.578 GHz multiphase clock, and generates in response control bits “up[0:3]” and “dn[0:3]” which are indicative of whether the frequency of the multiphase clock should be increased or decreased to maintain proper alignment between the edges of the multiphase sampling clock and the transitions between bits of the incoming data (a sequence of multiphase clock frequency adjustments can maintain the average phase of each individual clock of the multiphase clock at an optimal value determined by the control bits “up[0:3]” and “dn[0:3]”). Charge pump circuitry <b>28</b> (included within charge pump and low pass filter circuitry <b>27</b>) includes four identical charge pump circuits (each receiving pair, up[i] and dn[i], of the control bits, where “i”=1, 2, 3, or 4). Charge pump and low pass filter circuitry <b>27</b> also includes switch <b>35</b>, and low pass filter (“LPF”) <b>29</b>, connected as shown. When switch <b>35</b> couples circuitry <b>28</b> to LPF <b>29</b> (i.e., when the data recovery loop is active), each of the four charge pump circuits of circuitry <b>28</b> sources or sinks a current I_pi(where “i”=1, 2, 3, or 4) to or from the capacitors of LPF <b>29</b>, to cause LPF <b>29</b> to assert to VCO <b>30</b> a low-pass-filtered “fine control” voltage (determined by the sum of the four currents I_Pifrom the four charge pump circuits) to control VCO <b>30</b>'s generation of the multiphase sampling clock. The fine control voltage for VCO <b>30</b> is thus generated in response to the output of phase detector circuitry <b>26</b> so as to set the frequency of VCO <b>30</b>'s output clock at the appropriate value and maintain the average phase of VCO <b>30</b>'s output clock at an optimal value.

0075As explained, when the data recovery loop is active, the sum of the control currents generated by charge pump circuitry <b>28</b> is passed through switch <b>35</b> to LPF <b>29</b>, and in response thereto, LPF <b>29</b> generates a fine control voltage for VCO <b>30</b>. The data recovery loop is active only when frequency lock has been achieved. When frequency lock is lost, the data recovery loop becomes inactive, the frequency acquisition loop and coarse control loop of <figref idref="DRAWINGS">FIG. 3A</figref> become active, coarse control circuitry <b>34</b> causes switch <b>35</b> to couple charge pump <b>33</b>A to LPF <b>29</b> and to decouple charge pump circuitry <b>28</b> from LPF, and the coarse control loop asserts an adjusted coarse control voltage (from circuit block <b>37</b> of circuitry <b>34</b>) to VCO <b>30</b> in a manner to be explained below in more detail.

0076An implementation of the coarse control loop of <figref idref="DRAWINGS">FIG. 3A</figref> will be described with reference to <figref idref="DRAWINGS">FIGS. 4</figref>, <b>5</b>A, <b>5</b>B, and <b>6</b>. Coarse control circuitry <b>34</b> of <figref idref="DRAWINGS">FIG. 3A</figref> includes frequency lock detector <b>36</b> and voltage range conditioning circuitry <b>37</b>, connected as shown. Circuitry <b>37</b> includes a voltage range detector and a finite-state machine or “FSM” (within coarse control circuitry block <b>38</b> of <figref idref="DRAWINGS">FIG. 6</figref>). As shown in <figref idref="DRAWINGS">FIG. 6</figref>, circuitry <b>37</b> preferably also includes DAC <b>39</b>, connected as shown between coarse control circuitry block <b>38</b> and VCO <b>30</b>.

0077In preferred embodiments, the coarse control loop is locked when the data recovery loop is active and active when the frequency acquisition loop is active (as indicated in <figref idref="DRAWINGS">FIG. 5A</figref>). In alternative embodiments, the coarse control loop is active both when the data recovery loop is active and when the frequency acquisition loop is active, except when locked in response to the output of the frequency lock detector. Only when the coarse control loop is unlocked can it change the coarse control signal that it asserts to VCO <b>30</b>. When frequency lock detector <b>36</b> has locked the coarse control loop (as it does under some frequency lock conditions to be described), the coarse control signal asserted to VCO <b>30</b> does not change. In preferred embodiments, coarse control circuitry <b>37</b> of the coarse control loop continuously monitors the fine control voltage being asserted (by the data recovery loop or the frequency acquisition loop) to VCO <b>30</b>, and frequency lock detector <b>36</b> continuously monitors the frequency of VCO <b>30</b>'s output clock (or a frequency divided version thereof) during operation of both the data recovery loop and the frequency acquisition loop.

0078With reference to <figref idref="DRAWINGS">FIG. 5A</figref>, when the coarse control loop is unlocked and voltage range monitoring logic (within circuit block <b>37</b> of the coarse control loop) determines that the fine control voltage being asserted to VCO <b>30</b> is within a predetermined range, coarse control circuitry <b>34</b> does not change the coarse control signal it asserts to VCO <b>30</b> and maintains the frequency acquisition loop in an active state (by causing switch <b>35</b> to couple charge pump <b>33</b>A to LPF <b>29</b>). When the coarse control loop is unlocked and voltage range monitoring logic (within circuit block <b>37</b> of the coarse control loop) determines that the fine control voltage being asserted to VCO <b>30</b> is not within the predetermined range, coarse control circuitry <b>34</b> asserts a different coarse control signal to VCO <b>30</b> and maintains the frequency acquisition loop in an active state. Coarse control circuitry <b>34</b> activates the data recovery loop and deactivates the frequency acquisition loop (by causing switch <b>35</b> to couple charge pump circuitry <b>28</b> to LPF <b>29</b>) when the coarse control loop enters its “locked” state.

0079Voltage range monitoring logic within block <b>37</b> of coarse control circuitry <b>34</b> monitors a signal (i.e., voltage Vcap shown in <figref idref="DRAWINGS">FIG. 4</figref>) indicative of the fine control voltage being asserted by LPF <b>29</b> to VCO <b>30</b>, and coarse control circuitry <b>34</b> uses this signal as feedback to change the coarse control signal it asserts to VCO <b>30</b>. Both frequency lock detector <b>36</b> within circuitry <b>34</b> and the frequency acquisition loop monitor the output of VCO <b>30</b> (i.e., a frequency-divided version of an output clock produced by VCO <b>30</b>), and the frequency acquisition loop (when active) uses this signal as feedback to change the fine control signal it asserts to VCO <b>30</b>. When active, the frequency acquisition loop controls the operating point of VCO <b>30</b> along the current frequency-voltage characteristic (e.g., to move VCO <b>30</b>'s operating point from point P<b>1</b> to point P<b>2</b> along the bottom characteristic shown in <figref idref="DRAWINGS">FIG. 5B</figref>). To implement coarse control of the operating point of VCO <b>30</b>, coarse control circuitry <b>34</b> changes the coarse control signal it asserts to VCO <b>30</b> to change VCO <b>30</b>'s frequency-voltage characteristic (e.g., to move VCO <b>30</b>'s operating point from point P<b>2</b> to point P<b>3</b> of <figref idref="DRAWINGS">FIG. 5B</figref>) without changing the fine control voltage asserted by the frequency acquisition loop to VCO <b>30</b>.

0080As shown in <figref idref="DRAWINGS">FIGS. 3A</figref>, <b>4</b>, and <b>6</b>, coarse control circuitry <b>34</b> preferably receives a voltage indicative of the low-pass-filtered fine control voltage being applied to VCO <b>30</b>. More specifically, voltage range monitoring logic within circuitry <b>37</b> of the implementation of circuitry <b>34</b> shown in <figref idref="DRAWINGS">FIGS. 3A and 4</figref> receives a voltage (“Vcap”) from LPF <b>29</b> of circuitry <b>27</b> that is proportional to the low-pass-filtered fine control voltage being applied to VCO <b>30</b>. Except when circuitry <b>37</b> is locked by frequency lock detector <b>36</b>, the coarse control voltage generated by DAC <b>39</b> (shown in <figref idref="DRAWINGS">FIG. 6</figref>) of circuitry <b>37</b> is determined by the current value of the feedback signal Vcap. The lock signal asserted by frequency lock detector <b>36</b> to circuitry <b>37</b> is generated by frequency lock detector <b>36</b> in response to the 156.25 MHz reference clock and a frequency-divided version of the output of VCO <b>30</b>.

0081Coarse control circuitry <b>38</b> of <figref idref="DRAWINGS">FIG. 4</figref> is an element of circuitry <b>37</b>, as shown in <figref idref="DRAWINGS">FIG. 6</figref>. The <figref idref="DRAWINGS">FIG. 4</figref> embodiment of coarse control circuitry <b>38</b> includes voltage comparators <b>200</b> and <b>201</b>, sampling circuitry <b>202</b>, 5-bit Up/Down counter <b>203</b>, encoder <b>204</b>, and frequency divider <b>205</b>, connected as shown. In operation of circuitry <b>38</b> (when the frequency acquisition loop and coarse control loop of <figref idref="DRAWINGS">FIG. 3A</figref> are active), voltage comparators <b>200</b> and <b>201</b> compare predetermined voltages VH and VL with a low-pass-filtered version (identified as “Vcap” in <figref idref="DRAWINGS">FIGS. 4 and 5A</figref>) of the fine control voltage being applied to VCO <b>30</b> by the frequency acquisition loop. The output of each of comparators <b>200</b> and <b>201</b> is sampled in sampling circuitry <b>202</b>, and circuitry <b>202</b> asserts the samples to counter <b>203</b>. Counter <b>203</b> includes logic for generating a five-bit control signal in response to the samples (unless counter <b>203</b> is in a locked state in response to the “lock” control bit it receives from frequency lock detector <b>36</b>). The five-bit control signal generated by counter <b>203</b> determines (selects) one of the available frequency-voltage characteristics of VCO <b>30</b>, and the coarse control loop controls VCO <b>30</b> to cause it to operate in accordance with the selected characteristic. Specifically, encoder <b>204</b> encodes each five-bit control signal generated by counter <b>203</b> as a 31-bit control word and asserts each 31-bit control word to DAC <b>39</b> (shown in <figref idref="DRAWINGS">FIG. 6</figref>). DAC <b>39</b> generates (and asserts to VCO <b>30</b>) an analog coarse control voltage in response to each 31-bit control word from encoder <b>204</b>. Each five-bit control signal asserted to encoder <b>204</b> by counter <b>203</b> determines a “best” one of multiple available frequency-voltage characteristics for VCO <b>30</b>.

0082With reference to <figref idref="DRAWINGS">FIG. 5A</figref> and <figref idref="DRAWINGS">FIG. 4</figref>, circuitry <b>38</b> operates as follows when the frequency acquisition loop and coarse control loop of <figref idref="DRAWINGS">FIG. 3A</figref> are active (and counter <b>203</b> is not locked in response to the lock bit from frequency lock detector <b>36</b>):

0083when voltage Vcap is less than voltage VL, counter <b>203</b> asserts a five-bit control signal that selects a lower frequency-voltage characteristic for VCO <b>30</b> (this step is repeated during each cycle of counter <b>203</b> until the output frequency of VCO <b>30</b> falls sufficiently for the frequency acquisition loop to be operable to raise the output frequency of VCO <b>30</b> to the desired value without triggering a further change in the frequency-voltage characteristic);

0084when voltage Vcap is greater than voltage VH, counter <b>203</b> asserts a five-bit control signal that selects a higher frequency-voltage characteristic for VCO <b>30</b> (e.g., a value that moves VCO <b>30</b>'s operating point from point P<b>2</b> to point P<b>3</b> of <figref idref="DRAWINGS">FIG. 5B</figref>). This step is repeated during each cycle of counter <b>203</b> until the output frequency of VCO <b>30</b> rises sufficiently for the frequency acquisition loop to be operable to lower the output frequency of VCO <b>30</b> to the desired value without triggering a further change in the frequency-voltage characteristic (e.g., until counter <b>203</b> sets VCO <b>30</b>'s operating point at point P<b>4</b> of <figref idref="DRAWINGS">FIG. 5B</figref>, and the frequency acquisition loop moves VCO <b>30</b>'s operating point from point P<b>4</b> to point P<b>5</b> of <figref idref="DRAWINGS">FIG. 5B</figref>); and

0085when VL&lt;Vcap&lt;VH, the five-bit control signal output from counter <b>203</b> does not change the current frequency-voltage characteristic for VCO <b>30</b>.

0086Frequency divider <b>205</b> (of <figref idref="DRAWINGS">FIG. 4</figref>) generates a clock (for clocking sampling circuitry <b>202</b>, counter <b>203</b>, and frequency lock detector <b>36</b>) in response to a reference clock. In typical implementations, the output of frequency divider <b>205</b> has frequency equal to F/N, where N=2¹³and F is the frequency of the reference clock. Typically, the reference clock has frequency 156.25 MHz.

0087Frequency divider <b>32</b> (of <figref idref="DRAWINGS">FIGS. 3A and 4</figref>) generates a clock (for comparison with the reference clock in frequency lock detector <b>36</b>) in response to VCO <b>30</b>'s output clock. In a typical implementation, the output of frequency divider <b>32</b> is in phase with VCO <b>30</b>'s output clock but has frequency equal to F_o/M, where M=16.5 and F_ois the frequency of VCO <b>30</b>'s output clock. Typically, F_ois equal to about (10.3125)/4 GHz=2.578 GHz.

0088When implemented as a “÷16.5” frequency divider, frequency divider <b>32</b> can be implemented as a “÷8.25” frequency divider (of any of the types described with reference to <figref idref="DRAWINGS">FIGS. 12–16</figref>) cascaded with a “÷2” frequency divider. Such an embodiment of divider <b>32</b> can be implemented using CMOS logic so as to consume very low power. Alternatively, a “÷16.5” frequency divider implementation of frequency divider <b>32</b> can be implemented as shown in (and described with reference to) <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>), and its elements can be implemented as described with reference to <figref idref="DRAWINGS">FIGS. 18(</figref><i>a</i>), <b>20</b>, <b>21</b>, and/or <b>22</b>. If implemented as in <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) using CML logic, divider <b>32</b> requires only a two-phase input clock (the differential input signal of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>)) rather than a four-phase input clock (the four input signals shown in <figref idref="DRAWINGS">FIG. 12)</figref>. However, such a CML implementation would typically consume more power than a CMOS implementation of an “÷8.25” frequency divider (of any of the types described with reference to <figref idref="DRAWINGS">FIGS. 12–16</figref>) cascaded with a “÷2” frequency divider.

0089Frequency lock detector <b>36</b> counts edges of two clocks (the reference clock whose frequency is typically equal to 156.25 MHz, and the clock output from frequency divider <b>32</b>) and generates a control bit (identified as “lock” in <figref idref="DRAWINGS">FIG. 3A</figref>) in response to the resulting counts. If frequency lock detector <b>36</b> determines that the frequency difference between the two clocks is within a predetermined threshold (typically equal to 200 ppm), frequency lock detector <b>36</b> asserts the “lock” bit with a first value (e.g., a value indicative of a logical “1”). Otherwise, frequency lock detector <b>36</b> asserts the “lock” bit with a second value (e.g., a value indicative of a logical “0”). Detector <b>36</b> can use a first frequency difference threshold (e.g., 200 ppm, as indicated in the state diagram at the bottom of <figref idref="DRAWINGS">FIG. 4</figref>) for transition from the “unlock” state (in which the “lock” bit has the second value) to the “lock” state (in which the “lock” bit has the first value), and a greater frequency difference threshold (e.g., 1000 ppm, as indicated in the state diagram at the bottom of <figref idref="DRAWINGS">FIG. 4</figref>) for transition from the “lock” state to the “unlock” state for stable operation. In the “unlock” state, counter <b>203</b>'s output is free to change in response to changes in the samples asserted by sampler <b>202</b>, and the <figref idref="DRAWINGS">FIG. 3A</figref> circuitry performs both coarse control and fine control of VCO <b>30</b>'s output clock frequency. In the “lock” state, logic within counter <b>203</b> fixes counter <b>203</b>'s output in response to the “lock” bit (thereby locking the coarse control loop of <figref idref="DRAWINGS">FIG. 3A</figref>), so that the <figref idref="DRAWINGS">FIG. 3A</figref> circuitry performs only fine control of VCO <b>30</b>'s output clock frequency. The lock bit asserted by detector <b>36</b> to coarse control circuitry <b>37</b> cannot falsely lock circuitry <b>37</b> when the PLL is in transient operation (i.e., when the frequency-divided version of VCO <b>30</b>'s output clock frequency differs by more than the relevant predetermined frequency difference threshold from the reference clock frequency). The lock bit locks coarse control (and the <figref idref="DRAWINGS">FIG. 3A</figref> circuitry performs only fine control of VCO <b>30</b>'s output clock frequency) when VCO <b>30</b>'s output clock frequency is locked to the target value, so that environmental changes (such as VT variation) that occur in the “lock” state cannot result in selection of a new frequency-voltage characteristic from among the multiple available characteristics. With coarse control locked, the fine control loop can utilize the full range of the selected frequency-voltage characteristic. Frequency lock detector <b>36</b> remains active at all times to monitor lock status and cause circuitry <b>37</b> to activate coarse control when frequency lock is broken. By using a frequency lock detector (e.g., detector <b>36</b>) to examine VCO output frequency directly, the inventive scheme employs coarse control only when appropriate (e.g., to compensate for some temperature or supply voltage variations) and disables coarse control when appropriate so that fine control only is employed when appropriate.

0090With reference to <figref idref="DRAWINGS">FIG. 5A</figref>, when the frequency acquisition loop is active, and frequency lock detector <b>36</b> asserts its “lock” bit to counter <b>203</b> with the value “lock”=0, the frequency acquisition loop performs fine control of VCO <b>30</b> and counter <b>203</b> operates to cause the coarse control loop to a select new frequency-voltage characteristic each time Vcap leaves the range VL&lt;Vcap&lt;VH. When the frequency acquisition loop is active, if frequency lock detector <b>36</b> asserts its “lock” bit to counter <b>203</b> with the value “lock”=1, the output of counter <b>203</b> becomes locked (so that the coarse control loop becomes locked), and counter <b>203</b> asserts the data loop enable signal (indicated in <figref idref="DRAWINGS">FIG. 4</figref>) to switch <b>35</b> (shown in <figref idref="DRAWINGS">FIG. 3A</figref>) with a value that deactivates the frequency acquisition loop and activates the data recovery loop. While the data recovery loop is active, the data recovery loop performs fine control of VCO <b>30</b> and the coarse control loop remains locked. When the data recovery loop is active and the coarse control loop is locked, a 1-to-0 transition of the lock bit asserted to counter <b>203</b> by frequency lock detector <b>36</b> unlocks operation of counter <b>203</b> and causes counter <b>203</b> to assert the data loop enable signal (indicated in <figref idref="DRAWINGS">FIG. 4</figref>) to switch <b>35</b> (shown in <figref idref="DRAWINGS">FIG. 3A</figref>) with a value that activates the frequency acquisition loop and deactivates the data recovery loop.

0091In cases in which the power supply voltage asserted to the <figref idref="DRAWINGS">FIG. 4</figref> circuitry is low, care must be taken to choose appropriate values for the voltages VH and VL asserted to comparators <b>200</b> and <b>201</b> of <figref idref="DRAWINGS">FIG. 4</figref>. A narrower span between VH and VL results in longer search time. Also, since adjacent ones of the available frequency-voltage characteristics must overlap in this span, a narrower span between VH and VL increases the number of frequency-voltage characteristics curves that must be available to cover the whole operating range. Wider span between VH and VL provides shorter search time but results in narrower operating range along each frequency-voltage characteristic. Also, wider span between VH and VL narrows the range outside of this span that is used (by the fine control loop) to compensate for voltage and temperature variation while the VCO output is locked to the target frequency.

0092<figref idref="DRAWINGS">FIGS. 6 and 7</figref> show a preferred implementation of VCO <b>30</b> of <figref idref="DRAWINGS">FIGS. 3 and 3A</figref>, and elements of a preferred implementation of the coarse control loop for such VCO. To cover an adequate range of PVT variation while maintaining sufficiently small Kvco and providing sufficient overlap between the selectable frequency-voltage characteristics of VCO <b>30</b>, the coarse control loop and VCO of <figref idref="DRAWINGS">FIGS. 6 and 7</figref> are implemented so that VCO <b>30</b> can operate in accordance with any selected one of thirty-two discrete frequency-voltage characteristics (with each 31-bit control word asserted to DAC <b>39</b> of <figref idref="DRAWINGS">FIG. 6</figref> from coarse control block <b>38</b> determining one of these characteristics). To prevent unwanted dead frequency zones (not covered by any of the frequency-voltage characteristics), a thermometer code scheme is used instead of a binary weighted current switch, because current switches of different size can be more prone to suffer from random device mismatch.

0093<figref idref="DRAWINGS">FIG. 7</figref> shows the circuit details of each delay cell <b>40</b> used in a preferred ring OSC implementation (shown in <figref idref="DRAWINGS">FIG. 6</figref>) of VCO <b>30</b> of <figref idref="DRAWINGS">FIGS. 3 and 3A</figref>. Instead of implementing each delay cell <b>40</b> of the ring OSC to include segmented MOS switches to allow the ring OSC's frequency-voltage characteristic to be controlled (as described, for example, in S. J Song et al., “A 4-Gb/s CMOS Clock and Data Recovery Circuit Using ⅛-Rate Clock Technique,” <i>IEEE J. Solid</i>-<i>State Circuits</i>, vol. 38, pp. 1213–1219, July 2003), the <figref idref="DRAWINGS">FIG. 6</figref> circuit uses shared DAC <b>39</b> to generate an analog coarse tuning voltage from the digital control bits output from coarse control block <b>38</b>. DAC <b>39</b> includes thirty-one transistors, each functioning as a switch to control the analog output of DAC <b>39</b>, with the gate of each transistor being controlled by a different bit of each 31-bit control word output from block <b>38</b>. Use of DAC <b>39</b> simplifies the individual delay cell circuitry within the ring OSC and reduces routing complexity, since a segmented switch array is built only once (within DAC <b>39</b>; not within each delay cell of the ring OSC) and each delay cell needs only one or two additional transistors for the analog coarse control input (e.g., delay cell <b>40</b> of <figref idref="DRAWINGS">FIG. 6</figref> can be implemented as shown in <figref idref="DRAWINGS">FIG. 7</figref>, with the analog coarse control voltage “coarse” produced by DAC <b>39</b> asserted to the gate of each of two NMOS transistors).

0094With a segmented switch in each delay cell of a ring OSC, the area of the ring OSC can be too big and it can be too hard to maintain the symmetry needed within the ring OSC that is needed to maintain multi-phase evenness. The size of each switch in DAC <b>39</b> should be carefully designed to make the frequency-voltage characteristics (each determined by and resulting from a particular value of the 31-bit control word output from block <b>38</b>) have enough overlap and be distributed evenly. Since the analog coarse control voltage generated by DAC <b>39</b> still has large Kvco, special care will typically need to be taken to ensure adequate shielding and decoupling capacitance for this analog coarse control signal.

0095<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram of elements of an implementation of 10.3125 Gb/s transmitter circuitry <b>14</b> of <figref idref="DRAWINGS">FIG. 3</figref>. <figref idref="DRAWINGS">FIG. 9</figref> is a schematic diagram of driver <b>63</b> of <figref idref="DRAWINGS">FIG. 8</figref>. <figref idref="DRAWINGS">FIG. 10</figref> is a schematic diagram of VCO <b>42</b> of <figref idref="DRAWINGS">FIG. 8</figref>. The serialized data generated by multiplexer <b>50</b> of <figref idref="DRAWINGS">FIG. 8</figref> are retimed at a 10.3125 GHz full-rate clock and the PLL employs LC-VCO <b>42</b> (rather than a ring OSC) for low jitter. Since positioning the output frequency of LC-VCO <b>42</b> precisely at 10.3125 GHz is difficult given the uncertainty in process parameters, the <figref idref="DRAWINGS">FIG. 8</figref> circuitry applies a coarse control scheme as well as a fine control scheme. The coarse control of the LC-VCO frequency can be accomplished by controlling a segmented array of capacitors. Such an array of capacitors is described, for example, in J. Cao et al., “OC-192 Transmitter and Receiver in Standard 0.18-μm CMOS,” <i>IEEE J. Solid</i>-<i>State Circuits</i>, vol. 37, pp. 1768–1780, December 2002. The algorithm to find the proper coarse control settings is similar to that of the 10 Gb/s CDR. The output drivers of the 10 Gb/s transmitter have a pre-emphasis function to mitigate inter-symbol interference (ISI).

009610 Gb Ethernet transceiver chip <b>10</b> of <figref idref="DRAWINGS">FIG. 3</figref> can be fabricated using a 0.13 μm CMOS process in such a manner that it dissipates 898 mW from a single 1.2V supply during operation.

0097LC VCO <b>42</b> of <figref idref="DRAWINGS">FIG. 8</figref> is controlled to output a full rate (10.3125 GHz) clock, to avoid deterministic jitter caused by duty cycle distortion that would otherwise result if LC VCO <b>42</b> were controlled to output a half-rate clock. In <figref idref="DRAWINGS">FIG. 8</figref>, parallel to serial data conversion circuit <b>50</b> (which is a 16:1 MUX) receives sixteen-bit words of encoded data from PCS circuitry <b>16</b> of <figref idref="DRAWINGS">FIG. 3</figref>. The stream of serial data and its complement that are output from conversion circuit <b>50</b> are retimed by the full rate clock from VCO <b>42</b> to further reduce jitter from the MUX states. Transmitter circuitry <b>51</b> puts the serialized data output from circuit <b>50</b> into form for transmission as a differential signal over a serial link. Circuitry <b>51</b> includes flip-flops <b>60</b> and <b>61</b>, main driver <b>63</b>, and pre-emphasis driver <b>62</b>, connected as shown.

0098The PLL of <figref idref="DRAWINGS">FIG. 8</figref> controls LC VCO <b>42</b> to cause it to generate the 10.3125 GHz clock in response to a 156.25 MHz reference clock. Since a tail current source in a LC VCO would be a major source of flicker noise that could degrade performance, a preferred implementation of LC VCO <b>42</b> (e.g., that shown in <figref idref="DRAWINGS">FIG. 10</figref>) does not have a tail current transistor. Without a tail current source, the swing of VCO <b>42</b> can be maximized. It is desirable for it to have large swing because phase noise is quadratically inversely proportional to the magnitude of the swing.

0099For fine control of LC VCO <b>42</b>, the output of LC VCO <b>42</b> is frequency divided in “divide by 66” frequency divider <b>41</b>, and the output of divider <b>41</b> (with the reference clock) are asserted to the inputs of phase-frequency detector (PFD) <b>55</b>. The up and down control bits generated by PFD <b>55</b> are asserted to charge pump <b>56</b>. The output of charge pump <b>56</b> is low pass filtered in filter <b>43</b>, and the output of filter <b>43</b> is employed as the fine control voltage (labeled “V_CTRL” in <figref idref="DRAWINGS">FIG. 10</figref>) of LC VCO <b>42</b>.

0100To implement coarse control of LC VCO <b>42</b>, LC VCO <b>42</b> includes a metal-insulator-metal (MIM) capacitor array (identified as “MIM” in <figref idref="DRAWINGS">FIG. 10</figref>) and the coarse control algorithm implemented in preferred embodiments of receiver <b>12</b> can be used to generate the coarse control voltages that control the MIM capacitor array. Specifically, the output of LC VCO <b>42</b> is frequency divided in “divide by 66” frequency divider <b>41</b>, and the output of divider <b>41</b> is employed as one of the inputs to a frequency lock detector (which can be identical to lock detector <b>36</b> of <figref idref="DRAWINGS">FIG. 3A</figref>) within coarse control block <b>53</b>. The 156.25 MHz reference clock is the other input to the frequency lock detector within block <b>53</b>. Voltage range conditioning circuitry within block <b>53</b> (which can be identical to circuitry <b>37</b> of <figref idref="DRAWINGS">FIG. 3A</figref>) receives the output of low pass filter <b>43</b>, the “lock” control bit generated by the frequency lock detector (within block <b>53</b>), and reference voltages VH and VL (not shown in <figref idref="DRAWINGS">FIG. 8</figref>), and generates the coarse control voltages (labeled “Coarse CTL₁,” “Coarse CTL₂,” . . . , “Coarse CTL_M,” and “Coarse CTL_N” in <figref idref="DRAWINGS">FIG. 10</figref>) in response thereto. Though the operating range of the MOS varactor within LC VCO <b>42</b> is predictable, a frequency lock detector (which can be identical to that within coarse control circuitry <b>34</b> of <figref idref="DRAWINGS">FIG. 3</figref>) is preferably included within coarse control block <b>53</b> to ensure proper locking.

0101For power optimization without sacrificing performance, parallel to serial data conversion circuit <b>50</b> of <figref idref="DRAWINGS">FIG. 8</figref> can be implemented as a 16:8 MUX (implemented with CMOS logic) and a 8:1 MUX (implemented with CML) coupled to receive the output of the 16:8 MUX, and driver stages <b>62</b> and <b>63</b> are implemented with CML. When enabled, driver <b>63</b> of <figref idref="DRAWINGS">FIG. 8</figref> can provide pre-emphasis (up to 20%) to mitigate inter-symbol-interference. Inductive peaking is preferably used to extend the bandwidth of pre-emphasis driver <b>63</b>.

0102<figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) is a simplified block diagram of an embodiment of a ÷16.5 frequency divider that can be employed in the <figref idref="DRAWINGS">FIG. 3</figref> transceiver (e.g., to implement frequency divider <b>32</b> of <figref idref="DRAWINGS">FIG. 3A</figref> and <figref idref="DRAWINGS">FIG. 4)</figref>. The frequency divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) includes ÷3 frequency divider <b>120</b>, and ÷5.5 frequency divider <b>121</b> coupled to receive the differential output (CK<b>3</b><i>p </i>and CK<b>3</b><i>n</i>) of circuit <b>120</b>. Preferably, circuit <b>121</b> outputs a single ended clock signal CK<b>312</b><i>x </i>having frequency 312.5 MHz in response to a 5.15625 GHz differential clock signal (CKp and CKn) at the inputs of circuit <b>120</b>. Alternatively, circuit <b>121</b> produces a differential output clock signal having frequency f/(16.5) in response to a differential clock signal having frequency “f” at the inputs of circuit <b>20</b>.

0103<figref idref="DRAWINGS">FIG. 17(</figref><i>b</i>) is a timing diagram of signals received or generated by the <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) circuit.

0104The <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) circuit has a cascaded structure in which ÷3 frequency divider circuit <b>120</b> produces a differential output clock signal whose frequency is f/(3) in response to a differential clock signal having frequency “f” at the inputs of circuit <b>120</b>, and ÷5.5 frequency divider circuit <b>121</b> produces an output clock signal having frequency f/(16.5) in response to a differential clock signal having frequency “f/3” received from circuit <b>120</b>. In response to an input having frequency 5.15625 GHz, ÷3 divider <b>120</b> generates 1.71875 GHz differential clocks, CK<b>3</b><i>p </i>and CK<b>3</b><i>n</i>. As will be described with reference to the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) embodiment of circuit <b>121</b>, DTFFs are preferably utilized to implement circuit <b>121</b>, so that circuit <b>121</b> can have simple design and be capable of high-speed operation. In preferred embodiments in which frequency divider <b>121</b> utilizes both positive and negative edges of CK<b>3</b><i>p </i>and CK<b>3</b><i>n</i>, frequency divider <b>120</b> is preferably designed carefully so that CK<b>3</b><i>p </i>and CK<b>3</b><i>n </i>have a 50% duty cycle as shown in <figref idref="DRAWINGS">FIG. 17(</figref><i>b</i>) or a duty cycle at least substantially equal to 50%.

0105<figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) is a simplified schematic diagram of a preferred embodiment of a portion of ÷3 divider <b>120</b> of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>). The <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) circuit includes conventional ÷3 frequency divider <b>130</b> implemented using AND gate <b>135</b> and single-edge-triggered flip-flops (“STFFs”) <b>131</b> and <b>132</b>, connected as shown. The <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) circuit also includes negative level-sensitive latch (“LT₀”) <b>133</b> and multiplexer <b>134</b>, connected as shown. <figref idref="DRAWINGS">FIG. 18(</figref><i>b</i>) is a timing diagram of signals received or generated by the <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) circuit.

0106A preferred embodiment of the <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) circuit generates a differential output in response to a differential input (i.e., signal CK<b>3</b> of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) represents both CK<b>3</b><i>p </i>and CK<b>3</b><i>n </i>of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) and input CK of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) represents both CKp and CKn of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>)). In such preferred embodiment, each of a CML implementation of flip-flop <b>131</b> and a CML implementation of flip-flop <b>132</b> is clocked by differential clock signals CKp and CKn but only one of the clocks CKp and CKn is shown in <figref idref="DRAWINGS">FIG. 3(</figref><i>a</i>) identified as “CK,” the CML implementation of flip-flop <b>132</b> asserts differential output signals Q₁and ˜Q₁to multiplexer <b>134</b> but these differential output signals are shown (for simplicity) in <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) as a single signal Q₁asserted to an input of multiplexer <b>134</b>, and a CML implementation of flip-flop <b>133</b> asserts differential output signals Q₂and ˜Q₂to multiplexer <b>134</b> but these differential output signals are shown (for simplicity) in <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) as a single signal Q₂asserted to an input of multiplexer <b>134</b>. In alternative embodiments, ÷3 divider <b>120</b> of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) could include two copies of a single-ended implementation of the <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) circuit connected in parallel: one for generating output CK<b>3</b><i>p </i>in response to input CKp; the other for generating output CK<b>3</b><i>n </i>in response to input CKn.

0107The <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) circuit is a high-speed, divide-by-3 circuit. Flip-flops <b>131</b> and <b>132</b> together with AND gate <b>135</b> to create three states of signal pair Q₀and Q₁. However, since the duty cycle of each of signals Q₀and Q₁is far from 50% as shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>b</i>), elements <b>131</b>, <b>132</b>, and <b>135</b> alone are not suitable for generating the clock (CK<b>3</b><i>p </i>and CK<b>3</b><i>n</i>) input to ÷5.5 divider <b>121</b> of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>). To solve this problem, negative level-sensitive latch (“LT₀”) <b>133</b> is coupled to the output of flip-flop <b>131</b> as shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>), to generate differential signal Q₂in response to differential signal Q₀, and multiplexer <b>134</b> is coupled to receive signal Q₂at one of its inputs and differential signal Q₁at its other input. MUX <b>134</b> (and each of elements <b>131</b>, <b>132</b>, and <b>133</b>) is clocked by the input clock CK (CKp and CKn of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>)) to assert at its output the signal CK<b>3</b> (CK<b>3</b><i>p </i>and CK<b>3</b><i>n</i>) in response to its inputs. The waveform of one of CK<b>3</b><i>p </i>and CK<b>3</b><i>n </i>is labeled as “CK<b>3</b>” at the bottom of <figref idref="DRAWINGS">FIG. 18(</figref><i>b</i>), and the waveform of the other one of CK<b>3</b><i>p </i>and CK<b>3</b><i>n </i>is the inverse thereof.

0108Latch <b>133</b> passes signal Q₀to its output when clock CK (i.e., clock CKp and CKn) is low. When CK is high, the output of latch <b>133</b> (signal Q₂) is held. MUX gate <b>134</b> selects signals Q₁and Q₂alternately according to CK. Those selections are indicated as the solid lines on the waveforms of Q₁and Q₂in <figref idref="DRAWINGS">FIG. 18(</figref><i>b</i>). Although the signal integrity of input clock CK is typically carefully dealt with, its duty cycle can be distorted and such duty cycle distortion can distort the duty cycle of output clock CK<b>3</b> (i.e., clock CK<b>3</b><i>p </i>and CK<b>3</b><i>n</i>). However, such duty cycle distortion of output CK<b>3</b> is threefold reduced. For example, if input clock CK has a 10% distortion, CK<b>3</b> will have a 3.3% distortion, resulting in a 46.7% duty cycle.

0109The ÷3 divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) (e.g., the <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) embodiment of divider <b>120</b> of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>)) is preferably implemented using CML gates in a 0.13 μm CMOS technology. In such a preferred implementation of the <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) circuit, all gates have differential signaling although only the positive (or negative) signal is drawn in FIG. <b>18</b>(<i>a</i>) for simplicity (for example, a CML implementation of flip-flop <b>131</b> is clocked by differential clock signals CKp and CKn, but only one of these clocks is shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) identified as “CK”, and a CML implementation of flip-flop <b>131</b> asserts differential output signals Q_0pand Q_0n, but only one of these is shown in <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) identified as “Q₀”). Simulations of such a CML gate implementation of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>), assuming a differential input clock having frequency 5.15625 GHz, show that the gate delays and the clock-to-output delays are less than 40 ps in the worst process, voltage, and temperature (PVT) condition and their nominal delays are about 25 ps. Based on the simulation results, the circuit can be implemented so that it does not have any critical path for 5.15625 GHz operation.

0110In preferred embodiments in which the ÷3 divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) has a differential output having a duty cycle at least substantially equal to 50%, the ÷5.5 divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) fully utilizes double-edge-triggered flip-flops (DTFFs) implemented as CML circuitry. For example, the ÷5.5 divider can have a simple design (including DTFFs) that is similar to the design of a ÷11 divider implemented with a single-edge-triggered flip-flop in place of each DTFF.

0111To understand the reason for this, one should recognize that if a DTFF is used instead of a single-edge-triggered flip-flop (STFF) in a frequency divider, a multiply-by-2 effect can occur, resulting in divide-ratio reduction by 2. For example, a divide-by-3 circuit (e.g., circuit <b>130</b> of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>)) can function as a divide-by-1.5 circuit (e.g., one whose waveforms are as shown in <figref idref="DRAWINGS">FIG. 19(</figref><i>b</i>)) if STFFs of the divide-by-3 circuit are replaced by DTFFs. Thus, for example, the divide-by-1.5 circuit of <figref idref="DRAWINGS">FIG. 19(</figref><i>b</i>) differs from divide-by-3 circuit <b>130</b> of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>) only in that DTFFs <b>151</b> and <b>152</b> of <figref idref="DRAWINGS">FIG. 19(</figref><i>b</i>) replace STFFs <b>131</b> and <b>132</b> of circuit <b>130</b> of <figref idref="DRAWINGS">FIG. 18(</figref><i>a</i>). However, the clock duty-cycle of each DTFF should be close to 50% to guarantee that the related combinational-logic has enough time to operate during both the clock high and the clock low cycles.

0112<figref idref="DRAWINGS">FIG. 20</figref> is a schematic diagram of a DTFF that can be used in a preferred implementation of the ÷5.5 divider of the ÷16.5 divider of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>). The DTFF of <figref idref="DRAWINGS">FIG. 20</figref> includes two level-sensitive latches (LT₀and LT₁) and a MUX gate (coupled to receive the outputs of latches LT₀and LT₁), all implemented as CML circuitry. The MUX gate is switched by a differential input clock (which is output from the ÷3 divider when the <figref idref="DRAWINGS">FIG. 20</figref> circuit is included in the ÷5.5 divider of the ÷16.5 divider of FIG. <b>17</b>(<i>a</i>)) so as always to select the latch that is holding sampled data. In terms of integrated circuit area, only one MUX gate must be added to implement the DTFF of <figref idref="DRAWINGS">FIG. 20</figref> (in comparison with the integrated circuit area of a STFF circuit, assuming as is typical that the STFF circuit comprises two latches).

0113HSPICE simulations have been performed on a toggle flip-flop having the <figref idref="DRAWINGS">FIG. 20</figref> design, with the negative output directly connected to the positive input. The results show that this CML-type DTFF can operate properly in response to an input clock having frequency greater than 8 GHz even assuming the worst PVT condition.

0114If implemented using DTFFs, a frequency divider with eleven states can act as a ÷5.5 divider. For eleven states, at least four flip-flops are required together with combinational-logic gates. For example, the ÷5.5 frequency divider of <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) has eleven states and includes four pipelined DTFFs (<b>140</b>, <b>141</b>, <b>142</b>, and <b>143</b>), and is an embodiment of ÷5.5 frequency divider <b>121</b> of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>). <figref idref="DRAWINGS">FIG. 21(</figref><i>b</i>) is a state diagram for the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) circuit. <figref idref="DRAWINGS">FIG. 22</figref> is a simplified schematic diagram of an implementation of each of DTFF circuits <b>140</b>, <b>141</b>, <b>142</b>, and <b>143</b> of <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>).

0115In order to reduce the delay of each pipeline stage of the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) circuit, the gates are configured with three additional flip-flops (DTFFs <b>144</b>, <b>145</b>, and <b>146</b>) connected with four AND gates and two OR gates as shown in <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>). Each of DTTFFs <b>140</b>, <b>141</b>, <b>142</b>, and <b>143</b> of <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) is preferably implemented as shown in <figref idref="DRAWINGS">FIG. 22</figref>, with MUX gate <b>170</b> controlled by the signal asserted to enable node “E” (enable node “E” of each of DTFFs <b>140</b>, <b>141</b>, <b>142</b>, and <b>142</b> is indicated in <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>)) and data node “D” of flip-flop <b>171</b> coupled to receive the output of MUX <b>170</b>. Flip-flop <b>171</b> of <figref idref="DRAWINGS">FIG. 22</figref> is preferably implemented as a DTFF having the design shown in <figref idref="DRAWINGS">FIG. 20</figref>. With each of DTFFs <b>140</b>, <b>141</b>, <b>142</b>, and <b>143</b> of <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) implemented as shown in <figref idref="DRAWINGS">FIG. 22</figref> (with flip-flop <b>171</b> implemented as shown in <figref idref="DRAWINGS">FIG. 20)</figref>, and each of DTFFs <b>144</b>, <b>145</b>, and <b>146</b> of <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) implemented as shown in <figref idref="DRAWINGS">FIG. 20</figref>, the maximum number of gates in each pipeline stage of the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) circuit is limited to two in order to guarantee high-speed operation during both clock high and clock low cycles.

0116The desired eleven states of the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) circuit are indicated in <figref idref="DRAWINGS">FIG. 21(</figref><i>b</i>) and are chosen among the sixteen states generated by flip-flops <b>140</b>, <b>141</b>, <b>142</b>, and <b>143</b>. In operation, the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) circuit cycles through the eleven states shown in <figref idref="DRAWINGS">FIG. 21(</figref><i>b</i>), and the other five states (from 1011 to 1000) are skipped. As a result, signal Q<b>3</b> has six continuous 0's and five continuous 1's alternately, and thus has a duty cycle of about 50% (more precisely, its duty cycle is 45.5%= 5/11).

0117In preferred implementations of <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>), all gates have differential signaling although only the positive signals, and one negative signal (the input ˜Q₃to converter <b>147</b>), are drawn in <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) for simplicity. For example, the CML implementation of flip-flop <b>143</b> is clocked by differential clock signals CK<b>3</b><i>p </i>and CK<b>3</b><i>n</i>, (received from the ÷3 frequency divider) but only one of these clocks is shown in <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) identified as “CK<b>3</b>”, and the CML implementation of flip-flop <b>143</b> asserts differential output signals Q₃and ˜Q₃, but only one of the outputs of flip-flop <b>143</b> (the output signal Q₃, which is asserted to one input of converter <b>147</b>) is shown in <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>). The other output of the CML implementation of flip-flop <b>143</b> would assert the signal ˜Q₃to converter <b>147</b>'s other input.

0118Differential-to-single-ended-signal converter <b>147</b> generates a single-ended output clock (“CK<b>312</b><i>x</i>”) in response to the differential signals Q₃and ˜Q₃asserted thereto by flip-flop <b>143</b>. In embodiments in which the differential clock signals CK<b>3</b><i>p </i>and CK<b>3</b><i>n</i>, received by the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) circuit (from the ÷3 frequency divider) have the frequency 1.71875 GHz, the output clock CK<b>312</b><i>x </i>has the frequency 312.5 MHz. The device sizes of converter <b>147</b> should be tuned so that the duty cycle of its output, CK<b>312</b><i>x</i>, is about 50% (e.g., about 47%)

0119Since the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) embodiment of ÷5.5 divider circuit <b>121</b> (of <figref idref="DRAWINGS">FIG. 17(</figref><i>a</i>) has seven flip-flop outputs, Q₀, Q₁, Q₂, Q₃, X, SKIP, and EN, the initial state of this circuit can be any of 2⁷(=128) states at power-up. Verifications using a model checker have shown that each of the 128 states will converge to one of the eleven states of <figref idref="DRAWINGS">FIG. 21(</figref><i>b</i>), and once the <figref idref="DRAWINGS">FIG. 21(</figref><i>a</i>) circuit enters one of the eleven states of <figref idref="DRAWINGS">FIG. 21(</figref><i>b</i>) it will never diverge from the eleven states of <figref idref="DRAWINGS">FIG. 21(</figref><i>b</i>).

0120It should be understood that while some embodiments of the present invention are illustrated and described herein, the invention is not to be limited to the specific embodiments described and shown.