US7098086B2

Semiconductor device and method of manufacturing thereof

Summary by NHIP

Layered semiconductor device manufacturing

The method forms a gate electrode on a second insulating film above a semiconductor film that sits on a first wiring. The gate connects to the first wiring through a contact hole, while a third wiring connects to the semiconductor film via another contact hole through a third insulating film.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

US7098086B2, drawing sheet 1 — Sheet 1 of 21

Term

Term ended

Expired 31 August 2020, 6.1 years ago.

38 claims: 5 independent, 33 dependent

1
Broadest claimClaim Score 58, broad(NHIP)A method of manufacturing a semiconductor device comprising:forming a first wiring on a substrate having an insulating surface;forming a first insulating film on the first wiring;forming a semiconductor film on the first wiring;forming a second insulating film on the semiconductor film;forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;forming a gate electrode on the second insulating film, wherein the gate electrode is electrically connected to the first wiring through the first contact hole;forming a third insulating film on the gate electrode;forming a second contact hole reaching the semiconductor film by selectively etching the second insulating film and the third insulating film;and forming a third wiring on the third insulating film, wherein the third wiring is electrically connected to the semiconductor film through the second contact hole.
8
A method of manufacturing a semiconductor device comprising:forming a first wiring on a substrate having an insulating surface;forming a first insulating film on the first wiring;forming a semiconductor film on the first wiring;forming a second insulating film on the semiconductor film;forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;forming a gate electrode and a second wiring on the second insulating film, wherein the gate electrode is electrically connected to the first wiring through the first contact hole;forming a third insulating film on the gate electrode;forming a second contact hole reaching the semiconductor film by selectively etching the second insulating film and the third insulating film;and forming a third wiring on the third insulating film, wherein the third wiring is electrically connected to the semiconductor film through the second contact hole.
16
A method of manufacturing a semiconductor device comprising:forming a first wiring on a substrate having an insulating surface;forming a first insulating film on the first wiring;forming a semiconductor film on the first wiring;forming a second insulating film on the semiconductor film;forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;forming a gate electrode and a second wiring on the second insulating film, wherein the gate electrode is electrically connected to the first wiring through the first contact hole;forming a third insulating film on the gate electrode;forming a second contact hole reaching the semiconductor film by selectively etching the second insulating film and the third insulating film;and forming a third wiring on the third insulating film, wherein the third wiring is electrically connected to the semiconductor film through the second contact hole, and wherein the third wiring is formed in parallel with the second wiring.
24
A method of manufacturing a semiconductor device comprising:forming a first wiring on a substrate having an insulating surface;forming a first insulating film on the first wiring;forming a semiconductor film on the first wiring;forming a second insulating film on the semiconductor film;forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;forming a gate electrode on the second insulating film, wherein the gate electrode is electrically connected to the first wiring in each pixel through the first contact hole;forming a third insulating film on the gate electrode;forming a second contact hole reaching the semiconductor film by selectively etching the second insulating film and the third insulating film;and forming a third wiring on the third insulating film, wherein the third wiring is electrically connected to the semiconductor film through the second contact hole.
31
A method of manufacturing a semiconductor device comprising:forming a first wiring on a substrate having an insulating surface;forming a first insulating film on the first wiring;forming a semiconductor film on the first wiring;forming a second insulating film on the semiconductor film;forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;forming a gate electrode and a second wiring on the second insulating film, wherein the gate electrode is electrically connected to the first wiring in each pixel through the first contact hole;forming a third insulating film on the gate electrode;forming a second contact hole reaching the semiconductor film by selectively etching the second insulating film and the third insulating film;and forming a third wiring on the third insulating film, wherein the third wiring is electrically connected to the semiconductor film through the second contact hole.

Independent claims5

195 paragraphs in 4 sections, as filed

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention relates to a semiconductor device having a circuit constructed of a thin film transistor (hereinafter referred to as TFTs) and a method of manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel, and electronic equipment having such an electro-optical device mounted thereon as a part.

0003It is to be noted that a semiconductor device as used herein throughout the present specification denotes a general device which functions by utilizing semiconductor characteristics, and that electro-optical devices, semiconductor circuits, and electronic equipments are all semiconductor devices.

00042. Description of the Related Art

0005Techniques for structuring a thin film transistor (TFT) using a semiconductor thin film (having a thickness on the order of about several to several hundred nm) formed on a substrate having an insulating surface have been in the spotlight in recent years. Thin film transistors are widely applied to electronic devices such as an IC or an electro-optical device, and in particular, development of the TFT as a switching element of a liquid crystal display device is proceeding rapidly.

0006In order to obtain high quality images in the liquid crystal display device, an active matrix type liquid crystal display device that utilizes TFTs as switching elements to be connected to respective pixel electrodes which are arranged in matrix is attracting much attention.

0007It is necessary that the electric potential of an image signal is held in each pixel electrode connected to the TFTs until the next write-in time in order to perform good quality display in the active matrix type liquid crystal display device. Generally, the provision of a storage capacitor (Cs) in each pixel holds the electric potential of the image signal.

0008Various proposals have been made for the structure and the formation methods of the above stated storage capacitor (Cs). However, from the viewpoint of reliability or simplicity of the manufacturing process, it is preferable that, of the insulating films for structuring a pixel, a gate insulating film of a TFT, which has the highest quality is utilized as a dielectric of the storage capacitor (Cs). Conventionally, as shown in <figref idref="DRAWINGS">FIG. 18</figref>, a capacitor wiring that becomes an upper electrode is first provided by utilizing a scanning line, and then the formation of the storage capacitor (Cs) is carried out by using the upper electrode (capacitor wiring), a dielectric layer (gate insulating film), and a lower electrode (semiconductor film).

0009Also, from the viewpoint of display performances, there is a demand for giving pixels larger storage capacitors as well as making the aperture ratio higher. Efficient utilization of a back light is improved if each pixel has a high aperture ratio. Consequently, the amount of back light for obtaining a predetermined display luminance can be restrained, and therefore attainment of a power-saving and small scale display device can be achieved. Furthermore, each pixel is provided with a large storage capacitor, thereby improving the characteristic of each pixel in holding display data, to improve the display quality. In addition, in case of point sequential driving of the display device, a signal storage capacitor (sample hold capacitor) is required in the driver circuit side of each signal line. However, with the provision of a large storage capacitor in each pixel, a surface area occupied by the sample hold capacitor can be made smaller, and therefore the display device can be made smaller.

0010Such demands become problems in proceeding with the progress of making the pitch of each display pixel microscopic which accompanies the progress of making a liquid crystal display device smaller and high definition (increasing the number of pixels).

0011There is an additional problem in that it is difficult to make a high aperture ratio and a large storage capacitor compatible with each other in the above stated conventional pixel structure.

0012An example in which a conventional pixel structure having the size of a pixel formed to 19.2 μm in accordance with the design rule of Table 1 is shown in FIG. 18.

0013<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="168pt" align="left" /><thead><row><entry namest="1" nameend="2" rowsep="1">TABLE 1</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>Si layer:</entry><entry>minimum size = 0.8 μm, minimum spacing = 1.5 μm</entry></row><row><entry>Gate electrode:</entry><entry>minimum size = 1.0 μm, minimum spacing = 1.5 μm</entry></row><row><entry>Scanning line:</entry><entry>minimum size = 1.5 μm, minimum spacing = 1.5 μm</entry></row><row><entry>Contact hole of</entry><entry>minimum size = 1.0 μm□</entry></row><row><entry>signal line</entry><entry>margin of the contact hole and the Si layer = 1.0 μm</entry></row><row><entry>and Si layer:</entry><entry>minimum spacing of the contact hole and the scanning</entry></row><row><entry /><entry>(gate electrode) line = 1.3 μm</entry></row><row><entry>Signal line:</entry><entry>minimum size = 1.5 μm, minimum spacing = 1.5 μm</entry></row><row><entry /><entry>margin of the contact hole and the signal line = 1.3 μm</entry></row><row><entry>Pixel size:</entry><entry>19.2 μm□</entry></row><row><entry>Pixel TFT:</entry><entry>L = 1.5 μm, W = 0.8 μm, single gate</entry></row><row><entry>Scanning line:</entry><entry>minimum size of the wiring width = 1.0 μm</entry></row><row><entry>Scanning line:</entry><entry>minimum size of the wiring width at a portion of</entry></row><row><entry /><entry>overleaping Si layer = 1.5 μm</entry></row><row><entry>Capacitor</entry><entry>minimum size = 2.0 μm</entry></row><row><entry>wiring:</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0014A characteristic of the conventional pixel structure is that two wirings (a scanning line and a capacitor wiring) are arranged parallel to each other in relation to the continuous formation of the two respective wirings, the scanning line and the capacitor wiring. In <figref idref="DRAWINGS">FIG. 18</figref>, reference numeral 10 denotes a semiconductor film, 11 denotes a scanning line, 12 denotes a signal line, 13 denotes an electrode, and 14 denotes a capacitor wiring. Note that <figref idref="DRAWINGS">FIG. 18</figref> is a simplified top view of the pixel, and therefore a pixel electrode that is connected to the electrode 13 and a contact hole that reaches the electrode 13 are both not shown in the figure.

0015Thus, in the case of structuring the storage capacitor with a upper electrode (capacitor wiring), a dielectric layer (gate insulating film), and a lower electrode (semiconductor film), all the circuit elements (a pixel TFT, a storage capacitor, a contact hole, ect.) necessary for structuring a circuit of the pixel become elements relevant to a gate insulating film. Accordingly, these elements constituting the circuit elements are arranged almost planarly within each pixel.

0016Therefore, it is crucial to efficiently layout the circuit elements that are necessary for constructing the circuit of the pixel in order to attain both a high aperture ratio and a large storage capacitor of each pixel within the regulated pixel size. In other words, from the fact that all the circuit elements are in connection with the gate insulating film, it can be said that it is essential to improve the efficiency of utilizing the gate insulating film.

0017Thus, from the above perspective, an efficient planar layout of the example of the circuit structure of a pixel of <figref idref="DRAWINGS">FIG. 18</figref> is shown in FIG. 19. In <figref idref="DRAWINGS">FIG. 19</figref>, reference numeral 21 denotes a single pixel region, 22 denotes a pixel opening region, 23 denotes a storage capacitor region, 24 denotes an A region, and 25 denotes a portion of the TFT and a contact region.

0018With respect to the area of the pixel opening region 22 which is 216.7 μm2 (aperture ratio of 5.8.8%) as shown in <figref idref="DRAWINGS">FIG. 19</figref>, it is composed of the areas of the storage capacitor region 23 which is 64.2 μm2, the portion of the TFT and the contact region 25 which is 42.2 μm2, and the A region 24 which is 34.1 μm2.

0019The A region 24 is a segregation region of the scanning line and the capacitor wiring which originated from the fact that a wiring portion for mutually connecting a region that functions as a gate electrode of a TFT, the scanning line and the capacitor wiring are arranged parallel to each other. The gate insulating film of the A region is not rendered its original function, becoming a cause of reducing the efficiency of layout.

0020Further, in the case of the above structure, there is a problem in that the demand for a capacitor wiring resistance has become strict.

0021In a normal liquid crystal display device drive, the writing-in of the electric potential of the image signal to the plurality of pixels connected to each scanning line is performed consecutively in the scanning line direction (in the case of the point sequential drive) or all at the same time (in the case of the linear sequential drive).

0022In terms of arranging the capacitor wiring and the scanning line parallel to each other in the pixel structure as stated above, the plurality of pixels connected to the respective scanning lines are connected to a common capacitor wiring. Therefore, opposing electric currents for a plurality of pixels corresponding to the pixel writing-in electric current continuously or simultaneously flow in the common capacitor wiring. In order to avoid a reduction in display quality caused by the electric potential variation of the capacitor wiring, it is necessary to sufficiently lower the capacitor wiring resistance.

0023However, widening the width of the wiring for lowering the resistance of the capacitor wiring means that the surface area of the storage capacitor is enlarged while the aperture ratio of the pixel is reduced.

SUMMARY OF THE INVENTION

0024The present invention has been made in view of the above problems as a solution for the designing side, and therefore has an object to provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of the capacitor wiring in a timely manner to effectively reduce the load.

0025The structure of the invention disclosed in the present specification is a semiconductor device, characterized by comprising:

0026a first wiring on an insulating surface;

0027a first insulating film on said first wiring;

0028a semiconductor film on said first insulating film;

0029a second insulating film on said semiconductor film;

0030a second wiring and a gate electrode to be connected to said first wiring on said second insulating film;

0031a third insulating film on said second wiring and said gate electrode; and

0032a third wiring to be connected to said semiconductor film on said third insulating film.

0033In the above-mentioned structure, the semiconductor device is characterized in that the semiconductor film and the second wiring overlap via the second insulating film.

0034Further, in the above-mentioned respective structures, the semiconductor device is characterized in that a storage capacitor is formed with the second insulating film as a dielectric in a region where the second wiring and the semiconductor film overlap via the second insulating film.

0035Further, in the above-mentioned respective structures, the semiconductor device is characterized in that an impurity element that imparts a conductivity type is doped into the region of the semiconductor film where the second wiring overlaps via the second insulating film.

0036Further, in the above-mentioned respective structures, the semiconductor device is characterized by further comprising an electrode to be connected to the semiconductor film and a pixel to be connected to the electrode on the third insulating film.

0037Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the first wiring and the second wiring are arranged in a direction orthogonal with each other.

0038Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the first wiring is arranged in a direction orthogonal to the third wiring.

0039Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is formed on a different layer from the first wiring.

0040Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is patterned into an island shape.

0041Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the first wiring comprises a scanning line.

0042Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the second wiring comprises a capacitor wiring.

0043Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the third wiring comprises a signal line.

0044Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the second insulating film comprises a gate insulating film.

0045Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is made of a film having as its principal constituent an element selected from the group consisting of poly-Si, W, WSix, Al, Ta, Cr, or Mo which have been doped with an impurity element that imparts a type of conductivity, or a lamination film of a combination of these elements.

0046Further, the structure of another invention is a semiconductor device, characterized by comprising:

0047a plurality of signal lines arranged parallel to each other at a predetermined interval and connected to a signal line driver circuit;

0048a plurality of scanning lines arranged parallel to each other at a predetermined interval and connected to a scanning line driver circuit; and

0049a capacitor wiring arranged parallel to the signal line.

0050Further, in the above-mentioned structures, the semiconductor device is characterized in that the scanning lines are orthogonal to the signal lines.

0051Further, in the above-mentioned respective structures, the semiconductor device is characterized by further comprising a thin film transistor having a gate electrode connected to the scanning line which is orthogonal to the signal line and a pixel electrode connected to the thin film transistor.

0052Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is formed on a different layer from the scanning line.

0053Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is patterned into an island shape.

0054Further, the structure of the invention to attain the above structure is a method of manufacturing a semiconductor device, characterized by comprising:

0055a first step of forming a first wiring on a substrate having an insulating surface;

0056a second step of forming a first insulating film on the first wiring;

0057a third step of forming a semiconductor film on the first wiring;

0058a fourth step of forming a second insulating film on the semiconductor film;

0059a fifth step of forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;

0060a sixth step of forming a gate electrode on the second insulating film overlapping a portion of the semiconductor film and connected to the first wiring through the first contact hole;

0061a seventh step of forming a third insulating film on the gate electrode;

0062an eighth step of forming a second contact hole reaching the semiconductor film by selectively etching the second insulating film and the third insulating film; and

0063a ninth step of forming a third wiring on the third insulating film connected to the semiconductor film through the second contact hole.

0064Further, in the above-mentioned structure, the manufacturing method is characterized in that a second wiring is formed on the second insulating film to overlap a portion of the semiconductor film in the same step as forming the gate electrode.

0065Further, in the above-mentioned structure, the manufacturing method is characterized by further comprising a step of partially thinning the second insulating film that overlaps the second wiring after the step of forming the second insulating film on the semiconductor film.

0066Further, in the above-mentioned structure, the manufacturing method is characterized in that the second insulating film is a gate insulating film, the first wiring is a scanning line, the second wiring is a capacitor wiring, and the third wiring is a signal line.

BRIEF DESCRIPTION OF THE DRAWINGS

0067In the accompanying drawings:

0068<figref idref="DRAWINGS">FIG. 1</figref> is a top view of a pixel;

0069<figref idref="DRAWINGS">FIG. 2</figref> is a diagram showing a circuit structure of a TFT substrate;

0070<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are diagrams showing cross-sectional views of the TFT substrate;

0071<figref idref="DRAWINGS">FIG. 4</figref> is a diagram illustrating the cross-sectional structure of an active matrix type liquid crystal display device;

0072<figref idref="DRAWINGS">FIG. 5</figref> is a view showing the outer appearance of an AM-LCD;

0073<figref idref="DRAWINGS">FIGS. 6A</figref> to 6F are diagrams showing examples of electronic equipment;

0074<figref idref="DRAWINGS">FIGS. 7A</figref> to 7D are diagrams showing examples of electronic equipment;

0075<figref idref="DRAWINGS">FIGS. 8A</figref> to 8C(1) and FIG. 8C(2) are cross-sectional views and a top view, respectively, showing a process of manufacturing a pixel portion;

0076<figref idref="DRAWINGS">FIGS. 9A</figref> to 9C(1) and FIG. 9C(2) are cross-sectional views and a top view, respectively, showing a process of manufacturing a pixel portion;

0077<figref idref="DRAWINGS">FIGS. 10A</figref> to 10C(1) and FIG. 10C(2) are cross-sectional views and a top view, respectively, showing a process of manufacturing a pixel portion;

0078FIGS. 11A and 11B(1) and FIG. 11B(2) are cross-sectional views and a top view, respectively, showing a process of manufacturing a pixel portion;

0079<figref idref="DRAWINGS">FIGS. 12A and 12B</figref> are a cross-sectional view and a top view, respecitvely, showing a process of manufacturing a pixel portion;

0080<figref idref="DRAWINGS">FIG. 13</figref> is a graph illustrating a TFT characteristic;

0081<figref idref="DRAWINGS">FIG. 14</figref> is a diagram showing a top view of a pixel;

0082<figref idref="DRAWINGS">FIGS. 15A and 15B</figref> are diagrams showing cross-sectional views of a pixel structure;

0083<figref idref="DRAWINGS">FIG. 16</figref> is a diagram showing cross-sectional view of a pixel structure;

0084<figref idref="DRAWINGS">FIGS. 17A and 17B</figref> are is a diagram showing a top view of a pixel;

0085<figref idref="DRAWINGS">FIG. 18</figref> is a top view of a conventional pixel; and

0086<figref idref="DRAWINGS">FIG. 19</figref> is a view showing a conventional pixel opening region.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0087Hereinafter, preferred embodiments of the present invention will be described.

0088The present invention is characterized in that a scanning line is formed on a different layer from a gate electrode in order to increase an aperture ratio as well as to increase a storage capacitor. An example of a pixel structure of the present invention is shown in FIG. 1.

0089In <figref idref="DRAWINGS">FIG. 1</figref>, a gate electrode 106 formed into an island shape by patterning is connected to a scanning line 102 through a contact hole 100c formed at an insulating film. Further, a semiconductor film 104 is connected to a signal line 109 through a contact hole 100a. In addition, the semiconductor film 104 is connected to an electrode 110 through a contact hole 100b. A region of the semiconductor film that is connected to the signal line 109 or the electrode 110 is referred to as a source region or a drain region. Further, a channel forming region is formed between the source region and the drain region, and the gate electrode 106 is present on the channel forming region through a gate insulating film. Note that the source region, the drain region, and the channel forming region are not shown in the figure for simplification.

0090According to the present invention, in the case of forming the scanning lines 102 on the lower layer of the gate electrode 106 as shown in <figref idref="DRAWINGS">FIG. 1</figref>, the scanning lines 102 will be provided on the lower layer of the semiconductor film 104, thus making it possible to function as a light shielding film. In addition, the storage capacitor is formed with the lower electrode as the semiconductor film, the insulating film covering the semiconductor film as a dielectric, and the upper electrode as a capacitor wiring 107. It is to be noted that the storage capacitor may be enlarged by partially thinning the insulating film which covers the semiconductor film.

0091Further, according to an aspect of the present invention, TFTs of each pixel can be a dual gate structure in which a gate electrode is provided on the upper and lower part of the channel forming region through an insulating film, and the storage capacitor formed of the scanning line and another wiring can be restrained while improving the characteristics of the TFTs by setting the film thickness of a first insulating film appropriately.

0092The present invention, unlike the prior art (the capacitor wiring is arranged parallel with the scanning line), is characterized in that the capacitor wiring is arranged so that it is parallel with the signal line. Accordingly, good display image can be obtained since variations in the electric potential of the capacitor wiring due to a writing-in current of a neighboring pixel are avoided because each pixel is connected to storage capacitors formed of respective independent capacitor wirings even if consecutive writing-in of the image signals is performed to the pixels corresponding to each scanning line under the driving method.

0093Conventionally, a sample hold capacitor is provided in each signal line in order to prevent the signal line electric potential (a writing electric potential) from being reduced during a writing period to each scanning line. In the present invention, the capacitor wiring is arranged parallel with and overlapping the signal line. Therefore, it is not necessary to provide the sample hold capacitor in a portion of the peripheral circuit from the fact that the parasitic capacitance of the signal line increases, thereby improving the holding characteristics of the signal line electric potential. In comparison with the prior art, the peripheral circuits can be made smaller.

0094In addition, the demand performance for the capacitor wiring resistance has been alleviated because of the same reasons as the above, and therefore there is more degree of freedom in designing the arrangement, size, and film thickness of the capacitance wiring. Furthermore, because the selection range of the materials for the capacitor wiring has widened, the degree of complication in designing and manufacturing has lessened, leading to the attainment of a higher production yield.

0095Regarding the present invention composed of the above aspect, a detailed description will be made of the embodiments shown in the following.

0000[Embodiment 1]

0096Hereinafter, embodiments of the present invention will be described taking a point sequential drive of a projector type liquid crystal display device as an example.

0097An active matrix type liquid crystal display device utilizing a TFT as its switching element is constructed of a substrate (TFT substrate) with pixel electrodes arranged in matrix and an opposing substrate with opposing electrodes formed thereon arranged facing the TFT substrate via a liquid crystal layer. The space between the two substrates are controlled at a predetermined interval via spacers, etc. and a sealing material is used around the outer periphery portion of the display region to enclose the liquid crystal layer.

0098<figref idref="DRAWINGS">FIG. 4</figref> is a view schematically showing a cross-sectional structure of the liquid crystal display device of the present embodiment. In <figref idref="DRAWINGS">FIG. 4</figref>, reference numeral 101 denotes a substrate (TFT substrate), 102 denotes the scanning lines, 103 denotes a first insulating film, 104 denotes the semiconductor film, 105 denotes a gate insulating film (a second insulating film), 106 denotes the gate electrode, 107 denotes a capacitor wiring, 108 denotes a third insulating film, and 109 and 111 denote signal lines or electrodes diverged from the signal lines. Reference numeral 110 denotes an electrode which is connected to the semiconductor film through a contact hole (not shown in the figure) which is formed with the third insulating film. Further, the gate electrode 110 is an electrode for connecting the TFTs to the pixel electrodes.

0099It is to be noted that throughout the present specification, the term “electrode” implies a part of the “wiring” and indicates a place at which the wiring is electrically connected with another wiring, or a place at which the wiring intersects a semiconductor layer. Thus, for the sake of explanation conveniences, the terms “wiring” and “electrode” are used distinguishably. However, the term “electrode” shall always include the meaning of “wiring”.

0100Note that portions denoted by the reference numerals 101 to 110 are defined as TFTs throughout the present specification. In addition, reference numerals 109 and 110 may be an electrode diverged from a wiring or a wiring.

0101Furthermore, reference numeral 112 denotes a fourth insulating film which covers the TFTs, 113 denotes a light shielding film for preventing the TFTs from light deterioration, 114 denotes a fifth insulating film, 115 denotes a pixel electrode connected to the electrode 110 through a contact hole 100d, and 116 denotes an alignment film for orientating a liquid crystal layer 117.

0102Also in <figref idref="DRAWINGS">FIG. 4</figref>, an opposing electrode 119 and an alignment film 118 are provided on an opposing substrate 120, and besides, a light shielding film and a color filter may be provided when necessary.

0103The substrate (TFT substrate) 101 comprises a pixel portion 201, and a scanning line driver circuit 202 and a signal line driver circuit 203 formed in the periphery thereof as shown in FIG. 2.

0104The scanning line driver circuit 202 is mainly composed of shift registers for sequentially transmitting scanning signals. The signal line driver circuit 203 is mainly composed of sample hold circuits for holding an image signal and driving a signal line after sampling a shift register and the image signal that is inputted on the basis of an output of the shift register.

0105In the pixel portion 201, a plurality of scanning lines (gate wirings) 207 connected to the scanning line driver circuit 202 and arranged parallel to each other at a predetermined interval and a plurality of signal lines 208 connected to the signal line driver circuit 203 with a terminal for inputting an image signal 205 and arranged parallel to each other at a predetermined interval. The scanning lines 207 are orthogonal to the signal lines 208. Together with arranging TFTs (not shown in the figure) at each point of intersection, pixel electrodes (not shown in the figure) are arranged in the respective regions marked off by the scanning lines and signal lines. Thus, each pixel electrode is arranged in matrix from this structure. In addition, a plurality of capacitor wirings 209 connected to a GND (ground) or a fixed electric potential 206 are provided parallel to the signal lines 208. Reference numeral 204 denotes a driver circuit disposed on an opposing substrate. It is to be noted that for simplification, only a few lines of the signal lines, the scanning lines, and the capacitor wirings are shown in FIG. 2.

0106Hereinafter, a simplified process of manufacturing a semiconductor device shown in <figref idref="DRAWINGS">FIG. 4</figref> is described with references to <figref idref="DRAWINGS">FIGS. 1</figref>, 3A, and 3B.

0107First, besides a glass substrate as the substrate 101, a quartz substrate and a plastic substrate can also be used. In the case of using a glass substrate, heat treatment may be performed in advance at a temperature that is approximately 10 to 20° C. lower than the distortion point of glass. Furthermore, a base film is formed on the surface of the substrate 101 on which the TFTs will be formed in order to prevent the diffusion of impurities from the substrate 101. The base film is made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

0108Next, a conductive film is formed on the substrate and then patterning is performed to thereby form the scanning lines 102. Conductive materials such as poly-Si, WSix (X=2.0 to 2.8), Al, Ta, W, and Cr which have been doped with an impurity element that imparts a type of conductivity and a laminated structure thereof can be used for the scanning lines 102. In this embodiment, the scanning lines 102, arranged at a predetermined interval, are formed of a laminated structure composed of a WSix film (film thickness: 100 nm) and a poly-Si film (film thickness: 50 nm), which are conductive materials having high light blocking characteristics.

0109Covering the scanning lines 102 and having a film thickness of about 500 nm, the first insulating film 103 is formed next. An insulating film containing silicon formed by known methods such as plasma CVD or sputtering is used for the first insulating film 103. In addition, the first insulating film 103 may be formed of a film made of an organic insulating material, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film, or a lamination film of a combination of these films.

0110The semiconductor film is formed next to a thickness of between 25 and 80 nm (preferably between 30 and 60 nm) by known methods such as plasma CVD or sputtering, and then patterned into a desired shape. In this embodiment, an amorphous silicon film is formed to about 50 nm thick by plasma CVD. With a known crystallization method, a crystallization process is performed to form a crystalline silicon film (poly-Si) from the amorphous silicon film. Then patterning is conducted on the crystalline silicon film to pattern it into an island shape. Although the present embodiment uses a crystalline silicon film (poly-Si), no particular limitations are placed as long as it is a semiconductor film.

0111Note that throughout the present specification, the term “semiconductor film” denotes a single crystal semiconductor film, a crystalline semiconductor film (such as poly-Si), an amorphous semiconductor film (such as a-Si), or a microcrystalline semiconductor film. Further, a compound semiconductor film such as a silicon germanium film is also included as the “semiconductor film”.

0112An insulating film containing silicon formed by methods such as plasma CVD or sputtering, or an oxide film formed of a semiconductor film (such as an Si film) which has been thermally oxidized is used to form the second insulating film (gate insulating film) 105. The second insulating film 105 may be a laminate structure made up of a plurality of layers such as two layers or three layers when necessary.

0113Thereafter, in order to construct a TFT that functions as an image signal writing-in switch, with utilization of the respective island shape semiconductor films, a known technique is employed to selectively dope an impurity element (such as phosphorus or boron) that imparts a p-type or an n-type conductivity into the island shape semiconductor film, thereby forming a low resistance source region and drain region, and further forming a low resistance region. This low resistance region is similar to the drain region in that it is doped with an impurity element (typically phosphorus or boron) and is a part of the semiconductor films that have been made low resistance. Note that the order of the process of selectively doping the impurity element is not particularly limited. For example, the impurity element may be doped before the formation of the first insulating film and the gate electrode, or after the formation of the gate electrode. In addition, an LDD region and an offset region may be formed in response to the circuit structure. It is to be noted that the respective regions are not shown in the figure for simplification.

0114Thus, a channel forming region is formed between the source region and the drain region in the semiconductor film 104.

0115Next, selective etching is performed on the the first insulating film 103 and the second insulating film 105 to thereby form the first contact hole 100c shown in <figref idref="DRAWINGS">FIG. 3B</figref> reaching the scanning lines 102.

0116A conductive film is formed next on the second insulating film 105. Then patterning is performed to form the gate electrode 106 and the capacitor wiring 107. The gate electrode 106 and the capacitor wiring 107 are formed at the thickness of about 300 nm with conductive materials such as poly-Si, WSix (X=2.0 to 2.8), Al, Ta, W, Cr, and Mo which have been doped with an impurity element that imparts a type of conductivity, and a laminated structure thereof. Further, a single layer may be formed for the gate electrode 106 and the capacitor wiring 107, but a laminate structure made up of a plurality of layers such as two layers or three layers may also be formed when necessary. In this case, each gate electrode formed into an island shape is electrically connected to the scanning lines 102 via the first contact hole 100c which is formed with the first insulating film 103 and the second insulating film 105.

0117The island shape gate electrode 106 is arranged on the channel forming region of each pixel through the second insulating film 105. Further, the capacitor wirings 107 are arranged on the low resistance region through the second insulating film 105. Note that the storage capacitor may be enlarged by adding a process in which the film of a region where the capacitor wirings 107 overlap the second insulating film 105 is partially thinned. The capacitor wirings 107 are also arranged continuously to each pixel in the signal line direction and electrically connected outside the display region to the ground or to the fixed electric potential.

0118The third insulating film 108 is formed next covering the gate electrode 106 and the capacitor wirings 107. An insulating film containing silicon formed by methods such as plasma CVD or sputtering is used for the third insulating film 108. In addition, the third insulating film 108 may be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a lamination film of a combination of these films.

0119Next, selective etching is performed on the the second insulating film 105 and the third insulating film 108 to thereby form the second contact holes 100a and 100b shown in <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, respectively, to reach the semiconductor film (the source region or the drain region).

0120A film having Al, W, Ti, and TiN as its main component or a conductive film (film thickness: 500 μm) having a laminated structure of these elements is next formed on the third insulating film 108. Then patterning is performed, thereby forming the signal lines 109 and 111 and the island shape electrode 110 for connection with a pixel electrode which will be formed later. The signal lines 109 and 111 are connected to either the source region or the drain region through the second contact holes 100a and 100b that reach the semiconductor film. Similarly, the island shape electrode 110 is connected to either the source region or the drain region through the second contact hole 100a that reaches the semiconductor film. Furthermore, the signal lines 109 and 111 are arranged in a direction parallel to the capacitor wirings 107.

0121The island shape electrode 110 is arranged so as to be isolated from the signal line 109. However, both the signal line 109 and the island shape electrode 110 will not be connected to the source region together. Similarly, both the signal line 109 and the island shape electrode 110 will not be connected to the drain region together.

0122A top view of the pixel at this stage corresponds to <figref idref="DRAWINGS">FIG. 1</figref>, and the schematic views of the cross-sectional structure in which the cross sections are taken along the broken line A-A′ and the broken line B-B′ in <figref idref="DRAWINGS">FIG. 1</figref> correspond to <figref idref="DRAWINGS">FIGS. 3A and 3B</figref> respectively.

0123The fourth insulating film 112 is formed next covering the signal line 109 and the island shape electrode 110. The fourth insulating film 112 may be formed of a film such as an organic insulating material film, a silicon oxide film, a silicon oxynitride film or a silicon nitride film, or a lamination film of a combination of these films.

0124Subsequently, a film having high light shielding characteristics formed of materials such as Ti, Al, W, Cr, or black-colored resin is formed on the fourth insulating film 112 and then patterned into a desired shape, thereby forming the light shielding film 113. The light shielding film 113 is arranged mesh like so that other areas, except the opening portion of the pixel, are shielded from light.

0125In Embodiment 1, although the light shielding film 113 becomes electrically floating, if a low resistance film is selected as the material for the light shielding film, then it is possible to control the light shielding film to an optional electric potential outside the display portion.

0126A fifth insulating film 114 is formed next on the light shielding film 113. It is appropriate to form the fifth insulating film 114 with a film made of an organic insulating material. By forming the fifth insulating film 114 with an organic insulating material, the surface can be sufficiently flattened. In addition, parasitic capacitance can be reduced since organic resin materials are generally low in dielectric constant. However, because organic resin materials are absorbent, they are not suitable as protection films. Thus, the fifth insulating film 114 may be a laminate structure with combinations of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

0127Next, selective etching is performed on the the fourth insulating film 112 and the fifth insulating film 114 to thereby form the third contact hole 100d to reach island shape electrode. The third contact hole 100d is indicated by the broken line in <figref idref="DRAWINGS">FIG. 4</figref> for the sake of convenience.

0128A transparent conductive film such as an ITO film is formed next and then patterned to thereby form the pixel electrode 115. The pixel electrode 115 is connected to the island shape electrode 110 through the third contact hole 100d. The respective pixel electrodes are each independently arranged so as to cover the opening portion of each pixel.

0129The alignment film 116 for orientating the liquid crystal layer 117 is formed on the TFT substrate thus formed. Then the TFT substrate and the opposing substrate 120, which is provided with the opposing electrode 119 and the alignment film 118, are joined together by using a known cell construction technique. Thereafter, a liquid crystal material is injected between both substrates and enclosed therein. The liquid crystal cell in which the liquid crystal layer is held between the two substrates, is thus completed.

0130By employing the above described manufacturing steps, and furthermore arranging the wirings, the semiconductor film, etc. in accordance with the design rules of Table 2, a surface area of 236.9 μm2 of the pixel opening region (aperture ratio: 64.3%) and a surface area of 62.8 μm2 of the storage capacitor region can be obtained.

0131<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217pt" align="left" /><thead><row><entry namest="1" nameend="1" rowsep="1">TABLE 2</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>Si layer: minimum size = 0.8 μm, minimum spacing = 1.5 μm</entry></row><row><entry>Gate electrode: minimum size = 1.0 μm, minimum spacing = 1.5 μm</entry></row><row><entry>A contact hole of the scanning line and the gate electrode: minimum</entry></row><row><entry>size = 1.0 μm</entry></row><row><entry>margin of the contact hole and the gate electrode = 1.0 μm</entry></row><row><entry>Scanning line: minimum size = 1.5 μm, minimum spacing = 1.5 μm</entry></row><row><entry>Contact hole of signal line and Si layer: minimum size = 1.0 μm□</entry></row><row><entry>margin of the contact hole and the Si layer = 1.0 μm</entry></row><row><entry>minimum spacing of the contact hole and the scanning (gate</entry></row><row><entry>electrode) line = 1.3 μm</entry></row><row><entry>Signal line: minimum size = 1.5 μm, minimum spacing = 1.5 μm</entry></row><row><entry>margin of the contact hole and the signal line = 1.3 μm</entry></row><row><entry>Pixel size: 19.2 μm□</entry></row><row><entry>Pixel TFT: L = 1.5 μm, W = 0.8 μm, single gate</entry></row><row><entry>Scanning line: minimum size of the wiring width = 1.0 μm</entry></row><row><entry>Scanning line: minimum size of the wiring width at a portion of</entry></row><row><entry>overleaping Si layer = 1.5 μm</entry></row><row><entry>Capacitor wiring: minimum size = 2.0 μm</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0132In Embodiment 1, the provision of a region for the contact hole 100c for connecting the gate electrode 106 and the scanning line 102 is required in the restructured pixel region. Further, in Embodiment 1, an upper light shielding film is only the film for shielding the peripheral portion of the channel forming region of the island shape Si film from light. Accordingly, it is desired that the structure be provided with an upper light shielding film.

0133According to the present structure, because the scanning lines 102 function as a lower light shielding film to the channel forming region and the peripheral portion thereof, light incident from the liquid crystal layer 117 is reflected at the lower interface of the TFT substrate and then become incident on the channel forming region and the peripheral portion thereof. Accordingly, the occurrence of light leaking from the TFT can be prevented, making it possible to obtain better display quality.

0000[Embodiment 2]

0134A structure of the active matrix type liquid crystal display device shown in Embodiment 1 will be described here in Embodiment 2 with reference to the perspective view of FIG. 5. It is to be noted that the same reference numerals designate components corresponding to those in Embodiment 1.

0135In <figref idref="DRAWINGS">FIG. 5</figref>, a matrix substrate is composed of a pixel portion, a scanning line driver circuit 802, a signal line driver circuit 803, and other signal processing circuits formed on a substrate 101. A pixel TFT 800 and a storage capacitor 200 are provided in the pixel portion, and the driver circuits provided in the periphery thereof are structured based on a CMOS circuit.

0136Further, the capacitor wiring 107 is provided in a direction parallel with the signal line 109 and functions as the upper electrode of the storage capacitor 200. The capacitor wiring 107 is also connected to the ground or to a fixed electric potential.

0137The scanning line 102 and the signal line 109, from the scanning line driver circuit 802 and the signal line driver circuit 803, respectively, extend to the pixel portion and are connected to the pixel TFT 800. Further, an FPC (Flexible Printed Circuit) 804 is connected to an external input terminal 805 to be utilized for inputting signals such as image signals. The FPC 804 is firmly fixed with a reinforced resin. Then connecting wirings 806 and 807 are connected to the respective driver circuits. Though not shown in the figure, a light shielding film and a transparent electrode are provided on an opposing substrate 808.

0000[Embodiment 3]

0138The pixel matrix circuit formed by implementing the present invention can be used in various electro-optical devices (active matrix type liquid crystal display device, active matrix EL display, and active matrix EC display). That is, the present invention can be implemented in all electronic equipment that incorporate these electro-optical devices as a display portion.

0139The following can be given as such electronic equipment: a video camera, a digital camera, a projector (a rear type or a front type), a head mount display (goggle type display), a car navigation system, a personal computer, a portable information terminal (such as a mobile computer, a cellular phone, and an electronic book) etc. Some examples of these are shown in <figref idref="DRAWINGS">FIGS. 6A</figref> to 6F and <figref idref="DRAWINGS">FIGS. 7A</figref> to 7D.

0140<figref idref="DRAWINGS">FIG. 6A</figref> shows a personal computer that is comprised of a main body 2001, an image input portion 2002, a display portion 2003, and a keyboard 2004. The present invention can be applied to the display portion 2003.

0141<figref idref="DRAWINGS">FIG. 6B</figref> shows a video camera that is comprised of a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display portion 2102.

0142<figref idref="DRAWINGS">FIG. 6C</figref> shows a mobile computer that is composed of a main body 2201, a camera portion 2202, an image receiving portion 2203, operation switches 2204, and a display portion 2205. The present invention can be applied to the display portion 2205.

0143<figref idref="DRAWINGS">FIG. 6D</figref> shows a goggle type display that is comprised of a main body 2301, display portions 2302, and arm portions 2303. The present invention can be applied to the display portion 2302.

0144<figref idref="DRAWINGS">FIG. 6E</figref> shows a player which uses a recording medium in which a program is stored (hereinafter referred to as a recording medium) and which is comprised of a main body 2401, a display portion 2402, speaker portions 2403, a recording medium 2404, and operation switches 2405. A DVD (Digital Versatile Disc), a compact disc (CD) or the like is used as the recording medium to enable the player to appreciate music and the movies, and play a video game or the Internet. The present invention can be applied to the display portion 2402.

0145<figref idref="DRAWINGS">FIG. 6F</figref> shows a digital camera that is comprised of a main body 2501, a display portion 2502, an eye-piece portion 2503, operation switches 2504, and an image receiving portion (not shown in the figure). The present invention can be applied to the display portion 2502.

0146<figref idref="DRAWINGS">FIG. 7A</figref> shows a front type projector that is comprised of a projection unit 2601, a screen 2602, and the like. The present invention can be applied to a liquid crystal display device 2808 which is a part structuring the projection unit 2601.

0147<figref idref="DRAWINGS">FIG. 7B</figref> shows a rear type projector that is comprised of a main body 2701, a projection unit 2702, a mirror 2703, a screen 2704, and the like. The present invention can be applied to the liquid crystal display device 2808 which is a part structuring the projection unit 2702.

0148Illustrated in <figref idref="DRAWINGS">FIG. 7C</figref> is an example of the structure of the projection units 2601 and 2702 that are shown in <figref idref="DRAWINGS">FIGS. 7A and 7B</figref>, respectively. Each of the projection units 2601 and 2702 is comprised of a light source optical system 2801, mirrors 2802 and 2804 to 2806, dichroic mirrors 2803, a prism 2807, liquid crystal display devices 2808, phase difference plates 2809, and a projection optical system 2810. The projection optical system 2810 is constructed of an optical system including projection lenses. An example of a three plate system is shown in Embodiment 3, but there are no special limitations. For instance, an optical system of single plate system is acceptable. Further, the operator may suitably set optical systems such as optical lenses, polarizing film, film to regulate the phase difference, IR film, within the optical path shown by the arrows in FIG. 7C.

0149In addition, <figref idref="DRAWINGS">FIG. 7D</figref> shows an example of the structure of the light source optical system 2801 of FIG. 7C. In this embodiment, the light source optical system 2801 is composed of a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarizing conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in <figref idref="DRAWINGS">FIG. 7D</figref> is an example, and it is not limited to the illustrated structure. For example, the operator may suitably set optical systems such as optical lenses, polarizing film, film to regulate the phase difference, and IR film.

0150Thus, the application range for the present invention is extremely wide, and it may be applied to electronic equipment in all fields. Further, the electronic equipment of this Embodiment can be realized with a composition that uses any combination of Embodiments 1 and 2.

0000[Embodiment 4]

0151An example of a single gate TFT was shown in Embodiment 1, but an example of a double gate TFT will be shown here in Embodiment 4. Nonetheless, their structures are basically the same.

0152First, a conductive film is formed on a substrate 401 having an insulating surface, and then patterning is carried out to thereby form a scanning line 402. (see <figref idref="DRAWINGS">FIG. 8A</figref>) The scanning line 402 also functions as a light shielding layer to protect an active layer, which will be formed later, from light. A quartz substrate is used as the substrate 401, and a laminate structure of a poly-silicon film (having a film thickness of 50 nm) and a tungsten silicide (W-Si) film (having a film thickness of 100 nm) is used for the scanning line 402. In addition, the poly-silicon film protects the substrate from contamination from the tungsten silicide film.

0153Next, insulating films 403a and 403b are formed to a film thickness of between 100 and 1000 nm (typically between 300 and 500 nm) covering the scanning line 402. (see <figref idref="DRAWINGS">FIG. 8B</figref>) Here, a 100 nm thick silicon oxide film formed by employing the CVD method and a 280 nm thick silicon oxide film formed by employing the LPCVD method are laminated.

0154An amorphous semiconductor film is then formed with a thickness of 10 to 100 nm. A 69 nm thick amorphous silicon film is formed here by using the LPCVD method. Next, as a technique to crystallize the amorphous semiconductor film, the crystallization technique disclosed in Japanese Patent Application Laid-open No. Hei 8-78329 is employed to perform crystallization of the amorphous semiconductor film. The technique disclosed in the above publication is a crystallization technique in which a metal element for promoting crystallization is selectively doped into the amorphous silicon film, and then heat treatment is carried out. By carrying out the heat treatment, a crystalline silicon film in which its formation starts from the doped region is formed. Nickel is used here as the metal element for promoting crystallization. Heat treatment for crystallization (600° C., 12 hours) was performed after the performing of a heat treatment for releasing hydrogen (450° C., 1 hour).

0155Thereafter, Ni is gettered from a region as the active layer of the TFT. The region as the active layer of the TFT is covered with a mask (silicon oxide film), and then phosphorus (P) is doped into a portion of the crystalline silicon film. Next, heat treatment is performed under a nitrogen atmosphere at 600° C. for 12 hours.

0156After removing the mask, patterning is performed to remove the unnecessary portions of the crystalline silicon film, thereby forming a semiconductor layer 404. (see FIG. 8C(1)) Note that a top view of the pixel after the formation of the semiconductor layer 404 is shown in FIG. 8C(2). The sectional view cut along the broken line A-A′ in FIG. 8C(2) corresponds to FIG. 8C(1).

0157A mask 405 is formed next, and then phosphorus is doped into a portion of the semiconductor layer (a region as the storage capacitor) 406 to form the storage capacitor. (see <figref idref="DRAWINGS">FIG. 9A</figref>)

0158Then the mask 405 is removed, and after forming an insulating film for covering the semiconductor layer, a mask 407 is formed. The insulating film on the region 406 as the storage capacitor is then removed. (See <figref idref="DRAWINGS">FIG. 9B</figref>)

0159Thereafter, the mask 407 is removed and thermal oxidation is conducted to form an insulating film 408a (gate insulating film). Through thermal oxidation, the final film thickness of the gate insulating film became 80 nm. Note that an insulating film 408b is formed thinner than those of other regions on the region as the storage capacitor. (see FIG. 9C(1)) A top view of the pixel at this stage is shown in FIG. 9C(2). In FIG. 9C(2), the sectional view cut along the broken line B-B′ corresponds to FIG. 9C(1). Further, the region shown inside the dashed line in FIGS. 9C(1) and(2) are portions in which the thin insulating film 408b is formed.

0160A channel dope process for doping an impurity element that imparts a p-type or an n-type conductivity at a low concentration into a region that is to become a channel forming region of the TFT is performed on the entire surface or selectively. The channel dope process is a process for controlling the threshold voltage of the TFT. Note that diborane (B2H6) is not mass separated but boron is doped by a plasma excited ion dope method. Of course, the ion implantation method may be employed to perform mass separation.

0161Next, a mask 409 is formed on the insulating film 408a and the insulating films 403a and 403b to thereby form a contact hole to reach the scanning line 402. (see <figref idref="DRAWINGS">FIG. 10A</figref>) Then the mask is removed after the formation of the contact hole.

0162A conductive film is formed next, and then patterning is performed to form a gate electrode 410 and a capacitor wiring 411. (see <figref idref="DRAWINGS">FIG. 10B</figref>) A laminated structure of a silicon film (having a film thickness of 150 nm) and a tungsten silicide film (having a film thickness of 150 nm), which have been doped with phosphorus, is used here. It is to be noted that the storage capacitor, with the insulating film 408b as a dielectric, is composed of the capacitor wiring 411 and the portion 406 of the semiconductor layer.

0163Then phosphorus is doped at low concentration in a self-aligning manner using the gate electrode 410 and the capacitor wiring 411 as a mask. (see FIG. 10C(1)) A top view of the pixel at this stage is shown in FIG. 10C(2). In FIG. 10C(2), the sectional view cut along the broken line C-C′ corresponds to FIG. 10C(1). The phophorus concentration of this region doped at low concentration is adjusted so that it becomes 1×1016 to 5×1018 atoms/cm3, typically 3×1017 to 3×1018 atoms/cm3.

0164A mask 412 is formed next, and phophorus is doped at a high concentration, thereby forming a high concentration impurity region 413 that is to become a source region or a drain region. (see <figref idref="DRAWINGS">FIG. 11A</figref>) The phophorus concentration of this high concentration impurity region is adjusted so that it becomes 1×1020 to 1×1021 atoms/cm3, (typically 2×1020 to 5×1020 atoms/cm3). Note that a region of the semiconductor layer 404 which overlaps with the gate electrode 410 becomes a channel forming region 414 and a region of the semiconductor layer 404 which is covered by the mask 412 becomes a low concentration impurity region 415 functioning as an LDD region. Then the mask 412 is removed after doping an impurity element.

0165Although not shown in the figure, in order to form a p-channel TFT utilized in a driver circuit that is formed on the same substrate as the pixel, a region that is to become an n-channel TFT is covered with a mask and then doped with boron to form a source region or a drain region.

0166A passivation film 416 is formed next to cover the gate electrode 410 and the capacitor wiring 411 after removing the mask 412. A silicon oxide film formed to a thickness of 70 nm is used for the passivation film here. Next, heat treatment is performed to activate the impurity element that imparts a p-type conductivity or an n-type conductivity doped at respective concentrations into the semiconductor layer. Heat treatment is performed at 850° C. for 30 minutes.

0167Next, an interlayer insulating film 417 made of an organic resin material is formed. An acrylic resin film formed to a thickness of 400 nm is used here. Then an electrode 418 and a source wiring 419 are formed after forming a contact hole to reach the semiconductor layer. In Embodiment 4, the electrode 418 and the source wiring 419 are used for a laminated film of a three-layered structure composed of a 100 nm Ti film, a 300 nm aluminum film containing Ti, and a 150 nm Ti film which are formed in succession by sputtering (FIG. 11B(1)). In FIG. 11B(2), the sectional view cut along the broken line D-D′ corresponds to FIG. 11B(1).

0168Then after performing the hydrogenation process, an interlayer insulating film 420 made of acrylic is formed (FIG. 12A(1)). A 100 nm conductive film having light shielding characteristics is formed on the interlayer insulating film 420, to thereby form a light shielding layer 421. Following this, an interlayer insulating film 422 is formed, and then a contact hole is formed to reach the gate electrode 418. A 100 nm transparent conductive film (here it is an indium tin oxide (ITO) film) is formed and patterned to form pixel electrodes 423 and 424. In FIG. 12A(2), the sectional view cut along the broken line E-E′ corresponds to FIG. 12A(1).

0169Accordingly, in the pixel portion, a surface area of the display region (pixel size 26 μm×26 μm) (aperture ration of 76.5%) can be secured, while the pixel TFT, which is formed from the n-channel TFT, is formed, and a sufficient storage capacitor (51.5 fF) can be obtained.

0170Note that Embodiment 4 is an example, and therefore, needless to say, the present invention is not limited to the process of this Embodiment. For example, a film formed from an element selected from the group consisting of tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chrome (Cr) and silicon (Si), or from an alloy film of a combination of these elements (typically Mo—W alloy and Mo—Ta alloy) can be used as the respective conductive films. Furthermore, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a film made of an organic resin material (such as polyimide, acrylic, polyamide, polyimide amide, and BCB (benzocyclobutene)) can be used as the respective insulating films.

0171The characteristic of the TFT thus obtained showed a satisfactory value. The TFT characteristic (V-I characteristic) is shown in FIG. 13. An S-value shows an excellent value of 105.8 (mV/dec) since, particularly, the structure of the present invention is a dual gate structure. In addition, by fabricating the structure of the present invention, a threshold value (Vth) that indicates a voltage value at the starting point in the V-I characteristic graph is 0.946 V in the case of Vd=0.1 V and 0.886 V in the case of Vd=5 V. Thus, there is a difference of 0.06 which is extremely small. It can be said that the smaller the difference is, the more short-channel effect is suppressed. Further, a mobility (μFF) shows an excellent value of 220 (cm2/Vs).

0000[Embodiment 5]

0172Embodiment 5 is characterized in that a scanning line 502a is formed on a different layer from a gate electrode, and furthermore, a capacitor electrode 502b is formed on the same layer as the scanning line 502a in order to increase the aperture ratio as well as enlarge the storage capacitor. An example of the pixel structure of the present invention is shown in FIG. 14 and <figref idref="DRAWINGS">FIGS. 15A and 15B</figref>.

0173Note that the schematic cross-sectional structural views cut along the broken lines A-A′ and B-B′ in <figref idref="DRAWINGS">FIG. 14</figref> correspond to <figref idref="DRAWINGS">FIGS. 15A and 15B</figref>, respectively.

0174In <figref idref="DRAWINGS">FIG. 14</figref>, a gate electrode 506 patterned into an island shape is connected to a scanning line 502a through a contact hole 500c formed at an insulating film. Further, a semiconductor film 504 is connected to a signal line 509 through a contact hole 500a. In addition, the semiconductor film 504 is connected to an electrode 510 through a contact hole 500b. A region of the semiconductor film that is connected to the signal line 509 or to the electrode 510 is referred to as a source region or a drain region. Further, a channel forming region is formed between the source region and the drain region, and the gate electrode 506 is present on the channel forming region through a gate insulating film. Note that the source region, the drain region, and the channel forming region are not shown in the figure for simplification.

0175In Embodiment 5, in the case of forming the scanning lines 502a on the lower layer of the gate electrode 506 as shown in <figref idref="DRAWINGS">FIG. 14</figref>, the scanning line 502a will be provided on the lower layer of the semiconductor film 504, thus it is made possible to function as a light shielding film. In addition, the storage capacitor is formed with a lower electrode as the semiconductor film, an insulating film covering the semiconductor film as a dielectric, and a upper electrode as a capacitor wiring 507. It is to be noted that the storage capacitor may be enlarged by partially thinning the insulating film which covers the semiconductor film.

0176Further, the storage capacitor of Embodiment 5 can also be formed with the capacitor electrode 502b connected to the capacitor wiring 507, with the insulating film 503 as a dielectric, as shown in <figref idref="DRAWINGS">FIGS. 15A and 15B</figref>. Accordingly, the storage capacitor can be efficiently secured and contrast of a liquid crystal display device utilizing this pixel structure can be improved. It is noted that reference numeral 501 denotes a substrate, 502 denotes a gate insulating film (second insulating film), 508 denotes a third insulating film, and 511 denotes a signal line.

0177According to the structure of Embodiment 5, the TFTs of each pixel can be a dual gate structure in which a gate electrode is provided on the upper and lower parts of the channel forming region through an insulating film, and the parasitic capacitance formed by the scanning line and another wiring can be restrained while improving the characteristics of the TFTs by setting the film thickness of the first insulating appropriately.

0178A method of manufacturing the pixel structure shown in Embodiment 5 is nearly the same as that of Embodiment 1 or 4, and therefore descriptions thereof are omitted here.

0179It is to be noted that Embodiment 5 can be freely combined with any one of structures described in Embodiments 1 to 4.

0000[Embodiment 6]

0180Embodiment 6 discloses to increase the aperture ratio as well as enlarge the storage capacitor in case of decreasing a pixel size. In particular, the present embodiment is characterized in that the storage capacitor is formed of the light shielding film and the pixel electrode.

0181<figref idref="DRAWINGS">FIG. 16</figref> is a cross sectional view showing the liquid crystal display device of the present embodiment. Reference numeral 601 denotes a substrate (TFT substrate), 602 denotes a scanning line, 603 denotes a first insulating film, 604 denotes a semiconductor film, 605 denotes a gate insulating film (second insulating film), 606b denotes a gate electrode, 606c denotes a gate wiring, 606a denotes a capacitor wiring, 607 denotes a third insulating film, 608 denotes an electrode for connecting the pixel electrode 612 and the TFT through a contact hole formed in the third insulating film.

0182Reference numeral 609 denotes a fourth insulating film covering the TFT, 610 denotes a light shielding film preventing the TFT from distortion by light, 611 denotes a fifth insulating film, 612 denotes a pixel electrode connected to the electrode 608 through a contact hole, and 613 denotes an alignment film for orienting liquid crystal layer 614.

0183In <figref idref="DRAWINGS">FIG. 16</figref>, an opposing electrode 616 and an alignment film 615 are provided on the opposing substrate 617. A light shielding film or a color filter may be further provided on the opposing substrate 617.

0184As shown in <figref idref="DRAWINGS">FIG. 16</figref>, the storage capacitor of the present embodiment is constructed by first storage capacitor formed of the capacitor wiring 606a, semiconductor film 604, and the insulating film 605 as a dielectric, and second storage capacitor formed of the light shielding film 610, pixel electrode 612, and the insulating film 611 as a dielectric. It is noted that the insulating film 611 may be an organic resin film, or a inorganic insulating film such as silicon oxynitride and silicon oxide, etc. And the thickness of the insulating film may be appropriately decided by the operator.

0185For example, even if the pixel size is set to 14 μm×14 μm, enough storage capacitor (about 100 fF), and an aperture ratio of 48.8% can be secured by constructing the pixel electrode as shown in FIG. 17B.

0186<figref idref="DRAWINGS">FIG. 17A</figref> denotes a top view at the step of forming an electrode 608, and <figref idref="DRAWINGS">FIG. 17B</figref> is a top view at the step of forming the light shielding film 610 and the pixel electrode 612. The same reference numerals are used at the part corresponding to FIG. 16.

0187It is to be noted that Embodiment 6 can be freely combined with any one of structures described in Embodiments 1 to 5.

0188According to the present invention, a region (the region that corresponds to the A region in <figref idref="DRAWINGS">FIG. 19</figref>) that was conventionally used as a wiring region within the scanning line and the scanning line/capacitor wiring segregation region can be used as the storage capacitor. Further, by structuring the plurality of pixels connected to the respective scanning lines thereby being connected to the individually independent capacitor wiring, signal writing-in can be performed continuously to each pixel and the neighboring pixel, and even in the case of performing the above signal writing-in, each pixel does not receive the influence of the writing-in electric current of the neighboring pixel. In addition, the electric load of the respective capacitor wirings is dispersed in a timely manner, thereby reducing the effective load. Thus, the demand for the capacitor wiring resistance is alleviated.

0189Consequently, according to the liquid crystal display device employing the present invention, a liquid crystal display element having both a high aperture ratio and respective pixels having therein storage capacitors which hold sufficient display signal electric potential is obtained. Accordingly, satisfactory image display can be obtained while attaining small scale and power-saving devices.

Contents4

Every citation, both ways

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Priority claims
Document	Office	Kind	Date
24679899	Japan	A	1999-08-31
65353500	United States of America	A	2000-08-31

Members58

Family members, oldest first
Document	Office	Kind
CN1286493A	China	A	2001-03-07
EP1081676A1	European Patent Office (EPO)	A1	2001-03-07
KR20010039857A	Republic of Korea	A	2001-05-15
JP2001144301A	Japan	A	2001-05-25
TW478014B	Taiwan Province of China	B	2002-03-01
US6583472B1	United States of America	B1	2003-06-24
US2004126945A1	United States of America	A1	2004-07-01
US2005167674A1	United States of America	A1	2005-08-04
EP1564713A2	European Patent Office (EPO)	A2	2005-08-17
KR20050082168A	Republic of Korea	A	2005-08-22
EP1564713A3	European Patent Office (EPO)	A3	2005-09-21
CN1697179A	China	A	2005-11-16
JP2006013524A	Japan	A	2006-01-12
US7098086B2This record	United States of America	B2	2006-08-29
JP2006313369A	Japan	A	2006-11-16
KR100666150B1	Republic of Korea	B1	2007-01-09
CN1979877A	China	A	2007-06-13
JP3950906B2	Japan	B2	2007-08-01
CN100355013C	China	C	2007-12-12
KR100788870B1	Republic of Korea	B1	2007-12-27
CN101150135A	China	A	2008-03-26
US7501685B2	United States of America	B2	2009-03-10
CN100492640C	China	C	2009-05-27
US2009189173A1	United States of America	A1	2009-07-30
CN101150135B	China	B	2010-04-07
JP2010282216A	Japan	A	2010-12-16
EP2299435A2	European Patent Office (EPO)	A2	2011-03-23
US2011114964A1	United States of America	A1	2011-05-19
US7982267B2	United States of America	B2	2011-07-19
CN1979877B	China	B	2011-07-27
EP2299435A3	European Patent Office (EPO)	A3	2011-08-31
US8253140B2	United States of America	B2	2012-08-28
JP2012212936A	Japan	A	2012-11-01
JP5084114B2	Japan	B2	2012-11-28
US2012305924A1	United States of America	A1	2012-12-06
JP5277212B2	Japan	B2	2013-08-28
JP2013178525A	Japan	A	2013-09-09
US8552431B2	United States of America	B2	2013-10-08
US2014021476A1	United States of America	A1	2014-01-23
JP2014032415A	Japan	A	2014-02-20
JP5478678B2	Japan	B2	2014-04-23
JP5531136B2	Japan	B2	2014-06-25
JP2014170952A	Japan	A	2014-09-18
US8933455B2	United States of America	B2	2015-01-13
JP2015008336A	Japan	A	2015-01-15
US2015049278A1	United States of America	A1	2015-02-19
JP2015129968A	Japan	A	2015-07-16
US9250490B2	United States of America	B2	2016-02-02
JP5913514B2	Japan	B2	2016-04-27
US2016133656A1	United States of America	A1	2016-05-12
JP2016153917A	Japan	A	2016-08-25
US9466622B2	United States of America	B2	2016-10-11
EP2299435B1	European Patent Office (EPO)	B1	2017-03-08
JP6158848B2	Japan	B2	2017-07-05
JP2018087980A	Japan	A	2018-06-07
JP2018197859A	Japan	A	2018-12-13
JP2019083341A	Japan	A	2019-05-30
JP6546258B2	Japan	B2	2019-07-17

79 transactions on the USPTO file

Allowed after 1 RCE.

Non-final rejections: 0
Final rejections: 0
RCEs: 1
Appeals: 0

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Transactions

Prosecution transactions, newest first
	Event	Code
2018-10-01	Expire PatentEXP.	EXP.
2018-04-09	Maintenance Fee Reminder MailedREM.	REM.
2006-08-29	Recordation of Patent Grant MailedPGM/	PGM/
2006-08-29	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2006-08-09	Issue Notification MailedAllowedWPIR	WPIR
2006-07-24	Receipt into PubsR1021	R1021
2006-07-17	Dispatch to FDCD1935	D1935
2006-07-17	Application Is Considered Ready for IssuePILS	PILS
2006-03-29	Mail Miscellaneous Communication to ApplicantMM327	MM327
2006-03-27	Miscellaneous Communication to Applicant - No Action CountM327	M327
2006-02-11	Receipt into PubsR1021	R1021
2006-02-11	Printer Rush- No mailingTCPB	TCPB
2006-01-23	Information Disclosure Statement consideredIDSC	IDSC
2006-01-23	Reference capture on IDSRCAP	RCAP
2006-01-23	Information Disclosure Statement (IDS) FiledM844	M844
2006-01-23	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2006-01-19	Issue Fee Payment VerifiedN084	N084
2006-01-19	Information Disclosure Statement consideredIDSC	IDSC
2006-01-19	Reference capture on IDSRCAP	RCAP
2006-01-19	Information Disclosure Statement (IDS) FiledM844	M844
2006-01-19	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2006-01-19	Issue Fee Payment ReceivedIFEE	IFEE
2006-01-18	Receipt into PubsR1021	R1021
2006-01-10	Information Disclosure Statement consideredIDSC	IDSC
2006-01-10	Reference capture on IDSRCAP	RCAP
2006-01-10	Information Disclosure Statement (IDS) FiledM844	M844
2006-01-10	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2005-11-17	Receipt into PubsR1021	R1021
2005-11-09	Miscellaneous Incoming LetterLET.	LET.
2005-11-09	Miscellaneous Incoming LetterLET.	LET.
2005-10-24	Pubs Case Remand to TCPUBTC	PUBTC
2005-10-19	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2005-10-18	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2005-10-06	Date Forwarded to ExaminerFWDX	FWDX
2005-10-06	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2005-10-06	Case Docketed to Examiner in GAUDOCK	DOCK
2005-09-14	Mail-Record Petition Decision of Granted to Withdraw from IssueMP006	MP006
2005-09-13	Information Disclosure Statement consideredIDSC	IDSC
2005-09-13	Miscellaneous Incoming LetterLET.	LET.
2005-09-13	Request for Continued Examination (RCE)RCEX	RCEX
2005-09-13	Reference capture on IDSRCAP	RCAP
2005-09-13	Information Disclosure Statement (IDS) FiledM844	M844
2005-09-13	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2005-09-13	Workflow - Request for RCE - BeginBRCE	BRCE
2005-09-13	Petition EnteredPET.	PET.
2005-08-16	Mail Miscellaneous Communication to ApplicantMM327	MM327
2005-08-16	Miscellaneous Communication to Applicant - No Action CountM327	M327
2005-08-12	Receipt into PubsR1021	R1021
2005-03-04	Reverse Issue FeeVFEE	VFEE
2005-03-04	Issue Fee Payment ReceivedIFEE	IFEE
2005-02-22	Receipt into PubsR1021	R1021
2005-01-11	Reference capture on IDSRCAP	RCAP
2005-01-11	Information Disclosure Statement (IDS) FiledM844	M844
2005-01-11	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2005-01-11	Miscellaneous Incoming LetterLET.	LET.
2004-12-15	Receipt into PubsR1021	R1021
2004-12-14	Workflow - File Sent to ContractorSENT	SENT
2004-11-29	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2004-11-23	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2004-07-01	Case Docketed to Examiner in GAUDOCK	DOCK
2004-06-03	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2004-06-03	Case Docketed to Examiner in GAUDOCK	DOCK
2004-03-22	Application Is Now CompleteCOMP	COMP
2004-03-20	Application Return from OIPEWROIPE	WROIPE
2004-03-20	Additional Application Filing FeesADDFLFEE	ADDFLFEE
2004-03-20	Ommited Drawings. Applicant has Petitioned that the Filing Date not be changed and the Petition hasODRWNFD	ODRWNFD
2004-03-10	New or Additional Drawing FiledC614	C614
2004-03-10	Preliminary AmendmentA.PE	A.PE
2004-02-18	Mail-Petition Decision - DismissedMPTDI	MPTDI
2003-09-30	New or Additional Drawing FiledC614	C614
2003-09-30	Petition EnteredPET.	PET.
2003-08-04	Notice of Omitted ItemsOMIT	OMIT
2003-07-31	Pre-Exam Office Action WithdrawnW/OA	W/OA
2003-07-31	Application Return TO OIPEROIPE	ROIPE
2003-07-31	Application Dispatched from OIPEOIPE	OIPE
2003-07-31	Application Is Now CompleteCOMP	COMP
2003-06-25	Cleared by OIPE CSRL194	L194
2003-06-18	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2003-06-09	Initial Exam Team nnIEXX	IEXX

7 legal events, as the office reported them to INPADOC

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Events

Legal events, newest first
	Event	Code
2018-10-23	Lapsed due to failure to pay maintenance feeLapsedFP	FP
2018-10-01	Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYLAPS	LAPS
2018-10-01	Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH	STCH
2018-04-09	Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)FEPP	FEPP
2014-01-29	Fee paymentFPAY	FPAY
2010-01-29	Fee paymentFPAY	FPAY
2005-11-01	Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP