Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket

CROSS-REFERENCE TO RELATED APPLICATIONS

0001The present application claims the benefit under 35 USC § 119 of U.S. patent application Ser. No. 60/061,809, filed Oct. 14, 1997, and U.S. patent application Ser. No. 60/098,296, filed Aug. 27, 1998, and claims the benefit under 35 USC § 120 of U.S. patent application Ser. No. 09/067,544, filed Apr. 27, 1998, U.S. patent application Ser. No. 09/141,713, filed Aug. 28, 1998, U.S. patent application Ser. No. 09/384,792, filed Aug. 27, 1999, U.S. patent application Ser. No. 09/416,925, filed Oct. 13, 1999, U.S. patent application Ser. No. 09/439,603, filed Nov. 12, 1999, U.S. patent application Ser. No. 09/464,283, filed Dec. 15, 1999, U.S. patent application Ser. No. 09/514,425, filed Feb. 28, 2000, U.S. patent application Ser. No. 09/675,484, filed Sep. 29, 2000, U.S. patent application Ser. No. 09/675,700, filed Sep. 29, 2000, U.S. patent application Ser. No. 09/692,561, filed Oct. 18, 2000, U.S. patent application Ser. No. 09/748,936, filed Dec. 26, 2000, the U.S. patent application filed Feb. 20, 2001, inventors Laurence B. Boucher et al., entitled “Obtaining a Destination Address so that a Network Interface Device can Write Network Data Without Headers Directly into Host Memory,” the U.S. patent application filed Mar. 7, 2001, inventors Peter K. Craft et al., entitled “Port Aggregation for Network Connections that are Offloaded to Network Interface Devices,” the U.S. patent application filed Mar. 9, 2001, inventors Laurence B. Boucher et al., entitled “Intelligent Network Interface System and Method for Protocol Processing,” and the U.S. patent application filed Mar 9, 2001, inventors Stephen E. J. Blightman et al., entitled “Reducing Delays Associated with Inserting a Checksum into a Network Message,” all of which are incorporated by reference herein.

BACKGROUND

0002Over the past decade, advantages of and advances in network computing have encouraged tremendous growth of computer networks, which has in turn spurred more advances, growth and advantages. With this growth, however, dislocations and bottlenecks have occurred in utilizing conventional network devices. For example, a CPU of a computer connected to a network may spend an increasing proportion of its time processing network communications, leaving less time available for other work. In particular, demands for moving file data between the network and a storage unit of the computer, such as a disk drive, have accelerated. Conventionally such data is divided into packets for transportation over the network, with each packet encapsulated in layers of control information that are processed one layer at a time by the CPU of the receiving computer. Although the speed of CPUs has constantly increased, this protocol processing of network messages such as file transfers can consume most of the available processing power of the fastest commercially available CPU.

0003This situation may be even more challenging for a network file server whose primary function is to store and retrieve files, on its attached disk or tape drives, by transferring file data over the network. As networks and databases have grown, the volume of information stored at such servers has exploded, exposing limitations of such server-attached storage. In addition to the above-mentioned problems of protocol processing by the host CPU, limitations of parallel data channels such as conventional small computer system interface (SCSI) interfaces have become apparent as storage needs have increased. For example, parallel SCSI interfaces restrict the number of storage devices that can be attached to a server and the distance between the storage devices and the server.

0004As noted in the book by Tom Clark entitled “Designing Storage Area Networks,” (copyright 1999) incorporated by reference herein, one solution to the limits of server-attached parallel SCSI storage devices involves attaching other file servers to an existing local area network (LAN) in front of the network server. This network-attached storage (NAS) allows access to the NAS file servers from other servers and clients on the network, but may not increase the storage capacity dedicated to the original network server. Conversely, NAS may increase the protocol processing required by the original network server, since that server may need to communicate with the various NAS file servers. In addition, each of the NAS file servers may in turn be subject to the strain of protocol processing and the limitations of storage interfaces.

0005Storage area networking (SAN) provides another solution to the growing need for file transfer and storage over networks, by replacing daisy-chained SCSI storage devices with a network of storage devices connected behind a server. Instead of conventional network standards such as Ethernet or Fast Ethernet, SANs deploy an emerging networking standard called Fibre Channel (FC). Due to its relatively recent introduction, however, many commercially available FC devices are incompatible with each other. Also, a FC network may dedicate bandwidth for communication between two points on the network, such as a server and a storage unit, the bandwidth being wasted when the points are not communicating.

0006NAS and SAN as known today can be differentiated according to the form of the data that is transferred and stored. NAS devices generally transfer data files to and from other file servers or clients, whereas device level blocks of data may be transferred over a SAN. For this reason, NAS devices conventionally include a file system for converting between files and blocks for storage, whereas a SAN may include storage devices that do not have such a file system.

0007Alternatively, NAS file servers can be attached to an Ethernet-based network dedicated to a server, as part of an Ethernet SAN. Marc Farley further states, in the book “Building Storage Networks,” (copyright 2000) incorporated by reference herein, that it is possible to run storage protocols over Ethernet, which may avoid Fibre Channel incompatibility issues. Increasing the number of storage devices connected to a server by employing a network topology such as SAN, however, increases the amount of protocol processing that must be performed by that server. As mentioned above, such protocol processing already strains the most advanced servers.

0008An example of conventional processing of a network message such as a file transfer illustrates some of the processing steps that slow network data storage. A network interface card (NIC) typically provides a physical connection between a host and a network or networks, as well as providing media access control (MAC) functions that allow the host to access the network or networks. When a network message packet sent to the host arrives at the NIC, MAC layer headers for that packet are processed and the packet undergoes cyclical redundancy checking (CRC) in the NIC. The packet is then sent across an input/output (I/O) bus such as a peripheral component interconnect (PCI) bus to the host, and stored in host memory. The CPU then processes each of the header layers of the packet sequentially by running instructions from the protocol stack. This requires a trip across the host memory bus initially for storing the packet and then subsequent trips across the host memory bus for sequentially processing each header layer. After all the header layers for that packet have been processed, the payload data from the packet is grouped in a file cache with other similarly-processed payload packets of the message. The data is reassembled by the CPU according to the file system as file blocks for storage on a disk or disks. After all the packets have been processed and the message has been reassembled as file blocks in the file cache, the file is sent, in blocks of data that may be each built from a few payload packets, back over the host memory bus and the I/O bus to host storage for long term storage on a disk, typically via a SCSI bus that is bridged to the I/O bus.

0009Alternatively, for storing the file on a SAN, the reassembled file in the file cache is sent in blocks back over the host memory bus and the I/O bus to an I/O controller configured for the SAN. For the situation in which the SAN is a FC network, a specialized FC controller is provided which can send the file blocks to a storage device on the SAN according to Fibre Channel Protocol (FCP). For the situation in which the file is to be stored on a NAS device, the file may be directed or redirected to the NAS device, which processes the packets much as described above but employs the CPU, protocol stack and file system of the NAS device, and stores blocks of the file on a storage unit of the NAS device.

0010Thus, a file that has been sent to a host from a network for storage on a SAN or NAS connected to the host typically requires two trips across an I/O bus for each message packet of the file. In addition, control information in header layers of each packet may cross the host memory bus repeatedly as it is temporarily stored, processed one layer at a time, and then sent back to the I/O bus. Retrieving such a file from storage on a SAN in response to a request from a client also conventionally requires significant processing by the host CPU and file system.

SUMMARY

0011An interface device such as an intelligent network interface card (INIC) for a local host is disclosed that provides hardware and processing mechanisms for accelerating data transfers between a network and a storage unit, while control of the data transfers remains with the host. The interface device includes hardware circuitry for processing network packet headers, and can use a dedicated fast-path for data transfer between the network and the storage unit, the fast-path set up by the host. The host CPU and protocol stack avoid protocol processing for data transfer over the fast-path, releasing host bus bandwidth from many demands of the network and storage subsystem. The storage unit, which may include a redundant array of independent disks (RAID) or other configurations of multiple drives, may be connected to the interface device by a parallel channel such as SCSI or by a serial channel such as Ethernet or Fibre Channel, and the interface device may be connected to the local host by an I/O bus such as a PCI bus. An additional storage unit may be attached to the local host by a parallel interface such as SCSI.

0012A file cache is provided on the interface device for storing data that may bypass the host, with organization of data in the interface device file cache controlled by a file system on the host. With this arrangement, data transfers between a remote host and the storage units can be processed over the interface device fast-path without the data passing between the interface device and the local host over the I/O bus. Also in contrast to conventional communication protocol processing, control information for fast-path data does not travel repeatedly over the host memory bus to be temporarily stored and then processed one layer at a time by the host CPU. The host may thus be liberated from involvement with a vast majority of data traffic for file reads or writes on host controlled storage units.

0013Additional interface devices may be connected to the host via the I/O bus, with each additional interface device having a file cache controlled by the host file system, and providing additional network connections and/or being connected to additional storage units. With plural interface devices attached to a single host, the host can control plural storage networks, with a vast majority of the data flow to and from the host-controlled networks bypassing host protocol processing, travel across the I/O bus, travel across the host bus, and storage in the host memory. In one example, storage units may be connected to such an interface device by a Gigabit Ethernet network, offering the speed and bandwidth of Fibre Channel without the drawbacks, and benefiting from the large installed base and compatibility of Ethernet-based networks.

BRIEF DESCRIPTION OF THE DRAWINGS

0014<figref idref="DRAWINGS">FIG. 1</figref> is a plan view diagram of a network storage system including a host computer connected to plural networks by an intelligent network interface card (INIC) having an I/O controller and file cache for a storage unit attached to the INIC.

0015<figref idref="DRAWINGS">FIG. 2</figref> is a plan view diagram of the functioning of an INIC and host computer in transferring data between plural networks according to the present invention.

0016<figref idref="DRAWINGS">FIG. 3</figref> is a flowchart depicting a sequence of steps involved in receiving a message packet from a network by the system of <figref idref="DRAWINGS">FIG. 1</figref>.

0017<figref idref="DRAWINGS">FIG. 4</figref> is a flowchart depicting a sequence of steps involved in transmitting a message packet to a network in response to a request from the network by the system of <figref idref="DRAWINGS">FIG. 1</figref>.

0018<figref idref="DRAWINGS">FIG. 5</figref> is a plan view diagram of a network storage system including a host computer connected to plural networks and plural storage units by plural INICs managed by the host computer.

0019<figref idref="DRAWINGS">FIG. 6</figref> is a plan view diagram of a network storage system including a host computer connected to plural LANs and plural SANs by an intelligent network interface card (INIC) without an I/O controller.

0020<figref idref="DRAWINGS">FIG. 7</figref> is a plan view diagram of a one of the SANs of <figref idref="DRAWINGS">FIG. 6</figref>, including Ethernet-SCSI adapters coupled between a network line and a storage unit.

0021<figref idref="DRAWINGS">FIG. 8</figref> is a plan view diagram of one of the Ethernet-SCSI adapters of <figref idref="DRAWINGS">FIG. 6</figref>.

0022<figref idref="DRAWINGS">FIG. 9</figref> is a plan view diagram of a network storage system including a host computer connected to plural LANs and plural SANs by plural INICs managed by the host computer.

0023<figref idref="DRAWINGS">FIG. 10</figref> is a diagram of hardware logic for the INIC embodiment shown in <figref idref="DRAWINGS">FIG. 1</figref>, including a packet control sequencer and a fly-by sequencer.

0024<figref idref="DRAWINGS">FIG. 11</figref> is a diagram of the fly-by sequencer of <figref idref="DRAWINGS">FIG. 10</figref> for analyzing header bytes as they are received by the INIC.

0025<figref idref="DRAWINGS">FIG. 12</figref> is a diagram of the specialized host protocol stack of <figref idref="DRAWINGS">FIG. 1</figref> for creating and controlling a communication control block for the fast-path as well as for processing packets in the slow path.

0026<figref idref="DRAWINGS">FIG. 13</figref> is a diagram of a Microsoft® TCP/IP stack and Alacritech command driver configured for NetBios communications.

0027<figref idref="DRAWINGS">FIG. 14</figref> is a diagram of a NetBios communication exchange between a client and server having a network storage unit.

0028<figref idref="DRAWINGS">FIG. 15</figref> is a diagram of a User Datagram Protocol (UDP) exchange that may transfer audio or video data between the client and server of <figref idref="DRAWINGS">FIG. 14</figref>.

0029<figref idref="DRAWINGS">FIG. 16</figref> is a diagram of hardware functions included in the INIC of <figref idref="DRAWINGS">FIG. 1</figref>.

0030<figref idref="DRAWINGS">FIG. 17</figref> is a diagram of a trio of pipelined microprocessors included in the INIC of <figref idref="DRAWINGS">FIG. 16</figref>, including three phases with a processor in each phase.

0031<figref idref="DRAWINGS">FIG. 18A</figref> is a diagram of a first phase of the pipelined microprocessor of <figref idref="DRAWINGS">FIG. 17</figref>.

0032<figref idref="DRAWINGS">FIG. 18B</figref> is a diagram of a second phase of the pipelined microprocessor of <figref idref="DRAWINGS">FIG. 17</figref>.

0033<figref idref="DRAWINGS">FIG. 18C</figref> is a diagram of a third phase of the pipelined microprocessor of <figref idref="DRAWINGS">FIG. 17</figref>.

0034<figref idref="DRAWINGS">FIG. 19</figref> is a diagram of a plurality of queue storage units that interact with the microprocessor of <figref idref="DRAWINGS">FIG. 17</figref> and include SRAM and DRAM.

0035<figref idref="DRAWINGS">FIG. 20</figref> is a diagram of a set of status registers for the queue storage units of <figref idref="DRAWINGS">FIG. 19</figref>.

0036<figref idref="DRAWINGS">FIG. 21</figref> is a diagram of a queue manager that interacts with the queue storage unit s and status registers of <figref idref="DRAWINGS">FIG. 19</figref> and <figref idref="DRAWINGS">FIG. 20</figref>.

0037<figref idref="DRAWINGS">FIGS. 22A–D</figref> are diagrams of various stages of a least-recently-used register that is employed for allocating cache memory.

0038<figref idref="DRAWINGS">FIG. 23</figref> is a diagram of the devices used to operate the least-recently-used register of <figref idref="DRAWINGS">FIGS. 22A–D</figref>.

0039<figref idref="DRAWINGS">FIG. 24</figref> is another diagram of the INIC of <figref idref="DRAWINGS">FIG. 16</figref>.

0040<figref idref="DRAWINGS">FIG. 25</figref> is a more detailed diagram of the receive sequencer <b>2105</b> of <figref idref="DRAWINGS">FIG. 24</figref>.

0041<figref idref="DRAWINGS">FIG. 26</figref> is a diagram of a mechanism for obtaining a destination in a file cache for data received from a network.

DETAILED DESCRIPTION

0042An overview of a network data communication system in accordance with the present invention is shown in <figref idref="DRAWINGS">FIG. 1</figref>. A host computer <b>20</b> is connected to an interface device such as intelligent network interface card (INI) <b>22</b> that may have one or more ports for connection to networks such as a local or wide area network <b>25</b>, or the Internet <b>28</b>. The host <b>20</b> contains a processor such as central processing unit (CPU) <b>30</b> connected to a host memory <b>33</b> by a host bus <b>35</b>, with an operating system, not shown, residing in memory <b>33</b>, for overseeing various tasks and devices, including a file system <b>23</b>. Also stored in host memory <b>33</b> is a protocol stack <b>38</b> of instructions for processing of network communications and a INIC driver <b>39</b> that communicates between the INIC <b>22</b> and the protocol stack <b>38</b>. A cache manager <b>26</b> runs under the control of the file system <b>23</b> and an optional memory manager <b>27</b>, such as the virtual memory manager of Windows® NT or 2000, to store and retrieve file portions, termed file streams, on a host file cache <b>24</b>.

0043The host <b>20</b> is connected to the INIC <b>22</b> by an I/O bus <b>40</b>, such as a PCI bus, which is coupled to the host bus <b>35</b> by a host I/O bridge <b>42</b>. The INIC includes an interface processor <b>44</b> and memory <b>46</b> that are interconnected by an INIC bus <b>48</b>. INIC bus <b>48</b> is coupled to the I/O bus <b>40</b> with an INIC I/O bridge <b>50</b>. Also connected to INIC bus <b>48</b> is a set of hardware sequencers <b>52</b> that provide upper layer processing of network messages. Physical connection to the LAN/WAN <b>25</b> and the Internet <b>28</b> is provided by conventional physical layer hardware PHY <b>58</b>. Each of the PHY <b>58</b> units is connected to a corresponding unit of media access control (MAC) <b>60</b>, the MAC units each providing a conventional data link layer connection between the INIC and one of the networks.

0044A host storage unit <b>66</b>, such as a disk drive or collection of disk drives and corresponding controller, may be coupled to the I/O bus <b>40</b> by a conventional I/O controller <b>64</b>, such as a SCSI adapter. A parallel data channel <b>62</b> connects controller <b>64</b> to host storage unit <b>66</b>. Alternatively, host storage unit <b>66</b> may be a redundant array of independent disks (RAID), and I/O controller <b>64</b> may be a RAID controller. An I/O driver <b>67</b>, e.g., a SCSI driver module, operating under command of the file system <b>23</b> interacts with controller <b>64</b> to read or write data on host storage unit <b>66</b>. Host storage unit <b>66</b> preferably contains the operating system code for the host <b>20</b>, including the file system <b>23</b>, which may be cached in host memory <b>33</b>.

0045An INIC storage unit <b>70</b>, such as a disk drive or collection of disk drives and corresponding controller, is coupled to the INIC bus <b>48</b> via a matching interface controller, INIC I/O controller <b>72</b>, which in turn is connected by a parallel data channel <b>75</b> to the INIC storage unit. INIC I/O controller <b>72</b> may be a SCSI controller, which is connected to INIC storage unit <b>70</b> by a parallel data channel <b>75</b>. Alternatively, INIC storage unit <b>70</b> may be a RAID system, and I/O controller <b>72</b> may be a RAID controller, with multiple or branching data channels <b>75</b>. Similarly, I/O controller <b>72</b> may be a SCSI controller that is connected to a RAID controller for the INIC storage unit <b>70</b>. In another implementation, INIC storage unit <b>70</b> is attached to a Fibre Channel (FC) network <b>75</b>, and I/O controller <b>72</b> is a FC controller. Although INIC I/O controller <b>72</b> is shown connected to INIC bus <b>48</b>, controller <b>72</b> may instead be connected to I/O bus <b>40</b>. INIC storage unit <b>70</b> may optionally contain the boot disk for the host <b>20</b>, from which the operating system kernel is loaded. INIC memory <b>46</b> includes frame buffers <b>77</b> for temporary storage of packets received from or transmitted to a network such as LAN/WAN <b>25</b>. INIC memory <b>46</b> also includes an interface file cache, INIC file cache <b>80</b>, for temporary storage of data stored on or retrieved from INIC storage unit <b>70</b>. Although INIC memory <b>46</b> is depicted in <figref idref="DRAWINGS">FIG. 1</figref> as a single block for clarity, memory <b>46</b> may be formed of separate units disposed in various locations in the INIC <b>22</b>, and may be composed of dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM) and other forms of memory.

0046The file system <b>23</b> is a high level software entity that contains general knowledge of the organization of information on storage units <b>66</b> and <b>70</b> and file caches <b>24</b> and <b>80</b>, and provides algorithms that implement the properties and performance of the storage architecture. The file system <b>23</b> logically organizes information stored on the storage units <b>66</b> and <b>70</b>, and respective file caches <b>24</b> and <b>80</b>, as a hierarchical structure of files, although such a logical file may be physically located in disparate blocks on different disks of a storage unit <b>66</b> or <b>70</b>. The file system <b>23</b> also manages the storage and retrieval of file data on storage units <b>66</b> and <b>70</b> and file caches <b>24</b> and <b>80</b>. I/O driver <b>67</b> software operating on the host <b>20</b> under the file system interacts with controllers <b>64</b> and <b>72</b> for respective storage units <b>66</b> and <b>70</b> to manipulate blocks of data, i.e., read the blocks from or write the blocks to those storage units. Host file cache <b>24</b> and INIC file cache <b>80</b> provide storage space for data that is being read from or written to the storage units <b>66</b> and <b>70</b>, with the data mapped by the file system <b>23</b> between the physical block format of the storage units <b>66</b> and <b>70</b> and the logical file format used for applications. Linear streams of bytes associated with a file and stored in host file cache <b>24</b> and INIC file cache <b>80</b> are termed file streams. Host file cache <b>24</b> and INIC file cache <b>80</b> each contain an index that lists the file streams held in that respective cache.

0047The file system <b>23</b> includes metadata that may be used to determine addresses of file blocks on the storage units <b>66</b> and <b>70</b>, with pointers to addresses of file blocks that have been recently accessed cached in a metadata cache. When access to a file block is requested, for example by a remote host on LAN/WAN <b>25</b>, the host file cache <b>24</b> and INIC file cache <b>80</b> indexes are initially referenced to see whether a file stream corresponding to the block is stored in their respective caches. If the file stream is not found in the file caches <b>24</b> or <b>80</b>, then a request for that block is sent to the appropriate storage unit address denoted by the metadata. One or more conventional caching algorithms are employed by cache manager <b>26</b> for the file caches <b>24</b> and <b>80</b> to choose which data is to be discarded when the caches are full and new data is to be cached. Caching file streams on the INIC file cache <b>80</b> greatly reduces the traffic over both I/O bus <b>40</b> and data channel <b>75</b> for file blocks stored on INIC storage unit <b>70</b>.

0048When a network packet that is directed to the host <b>20</b> arrives at the INIC <b>22</b>, the headers for that packet are processed by the sequencers <b>52</b> to validate the packet and create a summary or descriptor of the packet, with the summary prepended to the packet and stored in frame buffers <b>77</b> and a pointer to the packet stored in a queue. The summary is a status word (or words) that describes the protocol types of the packet headers and the results of checksumming. Included in this word is an indication whether or not the frame is a candidate for fast-path data flow. Unlike prior art approaches, upper layer headers containing protocol information, including transport and session layer information, are processed by the hardware logic of the sequencers <b>52</b> to create the summary. The dedicated logic circuits of the sequencers allow packet headers to be processed virtually as fast as the packets arrive from the network.

0049The INIC then chooses whether to send the packet to the host memory <b>33</b> for “slow-path” processing of the headers by the CPU <b>30</b> running protocol stack <b>38</b>, or to send the packet data directly to either INIC file cache <b>80</b> or host file cache <b>24</b>, according to a “fast-path.” The fast-path may be selected for the vast majority of data traffic having plural packets per message that are sequential and error-free, and avoids the time consuming protocol processing of each packet by the CPU, such as repeated copying of the data and repeated trips across the host memory bus <b>35</b>. For the fast-path situation in which the packet is moved directly into the INIC file cache <b>80</b>, additional trips across the host bus <b>35</b> and the I/O bus <b>40</b> are also avoided. Slow-path processing allows any packets that are not conveniently transferred by the fast-path of the INIC <b>22</b> to be processed conventionally by the host <b>20</b>.

0050In order to provide fast-path capability at the host <b>20</b>, a connection is first set up with the remote host, which may include handshake, authentication and other connection initialization procedures. A communication control block (CCB) is created by the protocol stack <b>38</b> during connection initialization procedures for connection-based messages, such as typified by TCP/IP or SPX/IPX protocols. The CCB includes connection information, such as source and destination addresses and ports. For TCP connections a CCB comprises source and destination media access control (MAC) addresses, source and destination IP addresses, source and destination TCP ports and TCP variables such as timers and receive and transmit windows for sliding window protocols. After a connection has been set up, the CCB is passed by INIC driver <b>39</b> from the host to the INIC memory <b>46</b> by writing to a command register in that memory <b>46</b>, where it may be stored along with other CCBs in CCB cache <b>74</b>. The INIC also creates a hash table corresponding to the cached CCBs for accelerated matching of the CCBs with packet summaries.

0051When a message, such as a file write, that corresponds to the CCB is received by the INIC, a header portion of an initial packet of the message is sent to the host <b>20</b> to be processed by the CPU <b>30</b> and protocol stack <b>38</b>. This header portion sent to the host contains a session layer header for the message, which is known to begin at a certain offset of the packet, and optionally contains some data from the packet. The processing of the session layer header by a session layer of protocol stack <b>38</b> identifies the data as belonging to the file and indicates the size of the message, which are used by the file system to determine whether to cache the message data in the host file cache <b>24</b> or INIC file cache <b>80</b>, and to reserve a destination for the data in the selected file cache. If any data was included in the header portion that was sent to the host, it is then stored in the destination. A list of buffer addresses for the destination in the selected file cache is sent to the INIC <b>22</b> and stored in or along with the CCB. The CCB also maintains state information regarding the message, such as the length of the message and the number and order of packets that have been processed, providing protocol and status information regarding each of the protocol layers, including which user is involved and storage space for per-transfer information.

0052Once the CCB indicates the destination, fast-path processing of packets corresponding to the CCB is available. After the above-mentioned processing of a subsequently received packet by the sequencers <b>52</b> to generate the packet summary, a hash of the packet summary is compared with the hash table, and if necessary with the CCBs stored in CCB cache <b>74</b>, to determine whether the packet belongs to a message for which a fast-path connection has been set up. Upon matching the packet summary with the CCB, assuming no exception conditions exist, the data of the packet, without network or transport layer headers, is sent by direct memory access (DMA) unit <b>68</b> to the destination in file cache <b>80</b> or file cache <b>24</b> denoted by the CCB.

0053At some point after all the data from the message has been cached as a file stream in INIC file cache <b>80</b> or host file cache <b>24</b>, the file stream of data is then sent, by DMA unit <b>68</b> under control of the file system <b>23</b>, from that file cache to the INIC storage unit <b>70</b> or host storage unit <b>66</b>, under control of the file system. Commonly, file streams cached in host file cache <b>24</b> are stored on INIC storage unit <b>66</b>, while file streams cached in INIC file cache <b>80</b> are stored on INIC storage unit <b>70</b>, but this arrangement is not necessary. Subsequent requests for file transfers may be handled by the same CCB, assuming the requests involve identical source and destination IP addresses and ports, with an initial packet of a write request being processed by the host CPU to determine a location in the host file cache <b>24</b> or INIC file cache <b>80</b> for storing the message. It is also possible for the file system to be configured to earmark a location on INIC storage unit <b>70</b> or host storage unit <b>66</b> as the destination for storing data from a message received from a remote host, bypassing the file caches.

0054An approximation for promoting a basic understanding of the present invention is depicted in <figref idref="DRAWINGS">FIG. 2</figref>, which segregates the main paths for information flow for the network data storage system of <figref idref="DRAWINGS">FIG. 1</figref> by showing the primary type of information for each path. <figref idref="DRAWINGS">FIG. 2</figref> shows information flow paths consisting primarily of control information with thin arrows, information flow paths consisting primarily of data with thick white arrows, and information flow paths consisting of both control information and data with thick black arrows. Note that host <b>20</b> is primarily involved with control information flows, while the INIC storage unit <b>70</b> is primarily involved with data transfer.

0055Information flow between a network such as LAN/WAN <b>25</b> and the INIC <b>22</b> may include control information and data, and so is shown with thick black arrow <b>85</b>. Examples of information flow <b>81</b> between network such as LAN/WAN <b>25</b> and the INIC <b>22</b> include control information, such as connection initialization dialogs and acknowledgements, as well as file reads or writes, which are sent as packets containing file data encapsulated in control information. The sequencers <b>52</b> process control information from file writes and pass data and control information to and from INIC frame buffers <b>77</b>, and so those transfers are represented with thick black arrow <b>88</b>. Control information regarding the data stored in frame buffers <b>77</b> is operated on by the processor <b>44</b>, as shown by thin arrow <b>90</b>, and control information such as network connection initialization packets and session layer headers are sent to the protocol stack <b>38</b>, as shown by thin arrow <b>92</b>. When a connection has been set up by the host, control information regarding that connection, such as a CCB, may be passed between host protocol stack <b>38</b> and INIC memory <b>46</b>, as shown by thin arrow <b>94</b>. Temporary storage of data being read from or written to INIC storage unit <b>70</b> is provided by INIC file cache <b>80</b> and frame buffers <b>77</b>, as illustrated by thick white arrows <b>96</b> and <b>98</b>. Control and knowledge of all file streams that are stored on INIC file cache <b>80</b> is provided by file system <b>23</b>, as shown by thin arrow <b>91</b>. In an embodiment for which host storage unit <b>66</b> does not store network accessible data, file system information is passed between host file cache <b>24</b> and host storage unit <b>66</b>, as shown by arrow <b>81</b>. Other embodiments, not shown in this figure, may not include a host storage unit, or alternatively may use a host storage unit and host file cache primarily for network file transfers.

0056It is apparent from <figref idref="DRAWINGS">FIG. 2</figref> that the data of network file reads or writes primarily pass through the INIC <b>22</b> and avoid the host <b>20</b>, whereas control information is primarily passed between the host and INIC. This segregation of control information from data for file transfers between a network and storage allows the host to manage the file transfers that flow through the INIC between the network and storage, while the INIC provides a fast-path for those file transfers that accelerates data throughput. Increased throughput afforded by the INIC data fast-path allows host and INIC to function, for example, as a database server for high bandwidth applications such as video, in addition to functioning as a file server.

0057<figref idref="DRAWINGS">FIG. 3</figref> illustrates some steps performed by the system of <figref idref="DRAWINGS">FIG. 1</figref> for storing messages received from a network. A packet sent from a network such as LAN/WAN <b>25</b> is first received <b>100</b> at the INIC <b>22</b> by the PHY unit <b>58</b>, and the MAC unit <b>60</b> performs link layer processing such as verifying that the packet is addressed to host <b>20</b>. The network, transport and, optionally, session layer headers of that packet are then processed <b>102</b> by the sequencers <b>52</b>, which validate the packet and create a summary of those headers. The summary is then added to the packet and stored <b>104</b> in one of the frame buffers <b>77</b>. The processor <b>44</b> then determines <b>106</b> whether the packet is a candidate for fast-path processing, by checking the packet summary. Whether a packet is a fast path candidate may be determined simply by the protocol of the packet, as denoted in the summary. For the case in which the packet is not a fast-path candidate, the packet is sent <b>108</b> across the I/O bus <b>40</b> to host memory <b>33</b> for processing the headers of the packet by the CPU <b>30</b> running instructions from the protocol stack <b>38</b>.

0058For the case in which the packet is a fast-path candidate, the packet summary is then compared <b>110</b> with a set of fast-path connections being handled by the card, each connection represented as a CCB, by matching the summary with CCB hashes and the CCB cache. If the summary does not match a CCB held in the INIC memory, the packet is sent <b>112</b> to host memory for processing the headers of the packet by the CPU running instructions from the protocol stack. For the case in which the packet is part of a connection initialization dialog, the packet may be used to create <b>115</b> a CCB for the message. If the packet summary instead matches a CCB held in the INIC memory, the processor checks <b>114</b> for exception conditions which may include, e.g., fragmented or out of order packets and, if such an exception condition is found, flushes <b>116</b> the CCB and the packet to the host protocol stack <b>38</b> for protocol processing. For the case in which a packet summary matches a CCB but a destination for the packet is not indicated with the CCB, the session layer header of the packet is sent to the host protocol stack <b>38</b> to determine <b>122</b> a destination in the host file cache or INIC file cache, according to the file system, with a list of cache addresses for that destination stored with the CCB in the INIC. The INIC also checks <b>114</b> the packet summary for exception conditions that would cause the CCB to be flushed to the host <b>116</b> and the packet to be sent to the host for processing by the stack.

0059For the case in which a packet summary matches a CCB and a destination for the packet is stored with the CCB, and no exception conditions exist, the data from the packet is sent <b>125</b> by DMA to the destination in the host file cache or the INIC file cache designated by the CCB. The message packet in this case bypasses processing of the headers by the host protocol processing stack, providing fast-path data transfer. For the situation in which the data of the packets is sent via the fast-path to the INIC file cache and INIC storage, the packets not only avoid protocol processing by the host but do not cross the I/O bus or the host memory bus, providing tremendous savings of time, CPU processing and bus traffic compared to traditional network storage.

0060<figref idref="DRAWINGS">FIG. 4</figref> shows some steps performed by the system of <figref idref="DRAWINGS">FIG. 1</figref> for retrieving a file or part of a file from host storage unit <b>66</b> or INIC storage unit <b>70</b> in response to a request <b>200</b> from a network, such as LAN/WAN <b>25</b>. First, the request packet is processed by the protocol stack, which directs the request to the file system. The file system locates <b>202</b> the file indicated in the request, including determining whether the file streams corresponding to the file are cached in INIC file cache or host file cache, and if the file streams are not located in one of the caches, determining whether the block or blocks corresponding to the file are stored on the host storage unit or the INIC storage unit. Assuming the file streams are not located in one of the caches, the file blocks are then read to the host file cache <b>204</b> or read to the INIC file cache <b>206</b>. For most situations, file blocks stored on the host storage unit will be read into the host file cache and file blocks stored on the INIC storage unit will be read into the INIC file cache, but this mapping is not necessary. It may be desirable, for example, to read file blocks stored on the host storage unit into the INIC file cache, thereby reducing traffic on the host memory bus.

0061For the case in which the file blocks are cached in the host file cache, the host determines <b>210</b> whether to send the file by fast-path processing, by noting whether a CCB corresponding to the request is being held by the INIC. If the host chooses not to use the fast-path but to send the file from the host by the slow-path, the CPU runs the protocol stack to create headers for the data held in the host file cache, and then adds the headers and checksums to the data, creating network frames <b>212</b> for transmission over the network by the INIC, as is conventional. The INIC then uses DMA to acquire the frames from the host <b>214</b>, and the INIC then sends the frames <b>208</b> onto the network. If instead the file is to be sent by the fast-path, the INIC processor uses the CCB to create headers and checksums and to DMA frame-sized segments of data from the host file cache, and then prepends the headers and checksums to the data segments to create network frames <b>218</b>, freeing the host from protocol processing.

0062Similarly, if the file blocks are cached in the INIC file cache, the host determines <b>220</b> whether to send the file by fast-path processing, by noting whether a CCB is being held by the INIC. If the host chooses not to use the fast-path <b>222</b>, the host CPU prepares headers and checksums for the file block data, storing the headers in host memory. The host then instructs the INIC to assemble network frames by prepending headers from host memory to data in INIC memory, creating message frames that are then sent over the network by the INIC. Even for this non-fast-path case, the data is not moved over the I/O bus to the host and back to the INIC, reducing I/O traffic compared to a conventional transmit of file blocks located on a storage unit connected to a host by an I/O bus or network. If instead the fast-path is selected <b>225</b>, the INIC processor creates headers and checksums corresponding to the CCB, and prepends the headers and checksums to data segments from the INIC file cache to create network frames, which are then sent <b>208</b> by the INIC over the network. In this fast-path case the host is relieved of protocol processing and host memory bus traffic as well as being relieved of I/O bus traffic.

0063<figref idref="DRAWINGS">FIG. 5</figref> shows a network storage system in which the host <b>20</b> is connected via the I/O bus <b>40</b> to several I/O INICs in addition to the first INIC <b>22</b>. Each of the INICs in this example is connected to at least one network and has at least one storage unit attached. Thus a second INIC <b>303</b> is connected to I/O bus <b>40</b> and provides an interface for the host to a second network <b>305</b>. First INIC <b>22</b> may, as mentioned above, actually have several network ports for connection to several networks, and second INIC <b>303</b> may also be connected to more than one network <b>305</b>, but for clarity only a single network connection is shown in this figure for each INIC. Second INIC <b>303</b> contains an I/O controller, such as a SCSI adapter, that is coupled to second INIC storage unit <b>308</b>. Alternatively, second INIC storage unit <b>308</b> may be a RAID system, and second INIC <b>303</b> may contain or be connected to a RAID controller. In another embodiment, second INIC <b>303</b> contains a FC controller that is coupled to second INIC storage unit <b>308</b> by a FC network loop or FC adapter and network line. A number N of INICs may be connected to the host <b>20</b> via the I/O bus, as depicted by N^thINIC <b>310</b>. Nh^thINIC <b>310</b> contains circuitry and control instructions providing a network interface and a storage interface that are coupled to N^thnetwork <b>313</b> and N^thstorage unit <b>315</b>, respectively. N^thINIC <b>310</b> may have several network ports for connection to several networks, and second N^thINIC <b>310</b> may also be connected to more than one network. Storage interface circuitry and control instructions of N^thINIC <b>310</b> may for example include a SCSI controller, that is coupled to N^thINIC storage unit <b>315</b> by a SCSI cable. Alternatively, N^thINIC storage unit <b>315</b> may be a RAID system, and N^thINIC <b>310</b> may contain or be connected to a RAID controller. In yet another embodiment, N^thINIC <b>310</b> contains a FC controller that is coupled to N^thINIC storage unit <b>315</b> by a FC adapter and FC network line.

0064The file system may be arranged so that network accessible files are stored on one of the network storage units <b>66</b>, <b>305</b> or <b>315</b>, and not on the host storage unit <b>66</b>, which instead includes the file system code and protocol stack, copies of which are cached in the host. With this configuration, the host <b>20</b> controls network file transfers but a vast majority of the data in those files may be transferred by fast-path through INIC <b>22</b>, <b>303</b> or <b>310</b> without ever entering the host. For a situation in which file blocks are transferred between a network and a storage unit that are connected to the same INIC, the file data may never cross the I/O bus or host memory bus. For a situation in which a file is transferred between a network and a storage unit that are connected to the different INICs, the file blocks may be sent by DMA over the I/O bus to or from a file cache on the INIC that is connected to the storage unit, still avoiding the host memory bus. In this worst case situation that is usually avoided, data may be transferred from one INIC to another, which involves a single transfer over the I/O bus and still avoids the host memory bus, rather than two I/O bus transfers and repeated host memory bus accesses that are conventional.

0065<figref idref="DRAWINGS">FIG. 6</figref> shows a network storage system including an INIC <b>400</b> that provides network communication connections and network storage connections, without the need for the INIC I/O controller <b>72</b> described above. For conciseness, the host <b>20</b> and related elements are illustrated as being unchanged from <figref idref="DRAWINGS">FIG. 1</figref>, although this is not necessarily the case. The INIC in this example has network connections or ports that are connected to first LAN <b>414</b>, second LAN <b>416</b>, first SAN <b>418</b> and second SAN <b>420</b>. Any or all of the networks <b>414</b>, <b>416</b>, <b>418</b> and <b>420</b> may operate in accordance with Ethernet, Fast Ethernet or Gigabit Ethernet standards. Gigabit Ethernet, examples of which are described by 802.3z and 802.3ab standards, may provide data transfer rates of 1 gigabit/second or 10 gigabits/second, or possibly greater rates in the future. SANs <b>418</b> and <b>420</b> may run a storage protocol such as SCSI over TCP/IP or SCSI Encapsulation Protocol. One such storage protocol is described by J. Satran et al. in the Internet-Draft of the Internet Engineering Task Force (IETF) entitled “iSCSI (Internet SCSI),” June 2000, which in an earlier Internet-Draft was entitled “SCSI/TCP (SCSI over TCP),” February 2000, both documents being incorporated by reference herein. Another such protocol, termed EtherStorage and promoted by Adaptec, employs SCSI Encapsulation Protocol (SEP) at the session layer, and either TCP or SAN transport protocol (STP) at the transport layer, depending primarily upon whether data is being transferred over a WAN or the Internet, for which TCP is used, or data is being transferred over a LAN or SAN, for which STP is used.

0066The host <b>20</b> is connected to the INIC <b>400</b> by the I/O bus <b>40</b>, such as a PCI bus, which is coupled to an INIC bus <b>404</b> by an INIC I/O bridge <b>406</b>, such as a PCI bus interface. The INIC <b>400</b> includes a specialized processor <b>408</b> connected by the I/O bus <b>40</b> to an INIC memory <b>410</b>. INIC memory <b>410</b> includes frame buffers <b>430</b> and an INIC file cache <b>433</b>. Also connected to INIC bus <b>404</b> is a set of hardware sequencers <b>412</b> that provide processing of network messages, including network, transport and session layer processing. Physical connection to the LANs <b>414</b> and <b>416</b> and SANs <b>418</b> and <b>420</b> is provided by conventional physical layer hardware PHY <b>422</b>. Each of the PHY <b>422</b> units is connected to a corresponding unit of media access control (MAC) <b>424</b>, the MAC units each providing a data link layer connection between the INIC <b>400</b> and one of the networks.

0067<figref idref="DRAWINGS">FIG. 7</figref> shows that SAN <b>418</b> includes a Gigabit Ethernet line <b>450</b>, which is connected between INIC <b>400</b> and a first Ethernet-SCSI adapter <b>452</b>, a second Ethernet-SCSI adapter <b>454</b>, and a third Ethernet-SCSI adapter <b>456</b>. The Ethernet-SCSI adapters <b>452</b>, <b>454</b> and <b>456</b> can create and shutdown TCP connections, send SCSI commands to or receive SCSI commands from INIC <b>400</b>, and send data to or receive data from INIC <b>400</b> via line <b>450</b>. A first storage unit <b>462</b> is connected to first Ethernet-SCSI adapter <b>452</b> by a first SCSI cable <b>458</b>. Similarly, a second storage unit <b>464</b> is connected to second Ethernet-SCSI adapter <b>454</b> by a second SCSI cable <b>459</b>, and a third storage unit <b>466</b> is connected to second Ethernet-SCSI adapter <b>456</b> by a third SCSI cable <b>460</b>. The storage units <b>462</b>, <b>464</b>, and <b>466</b> are operated by respective adapters <b>452</b>, <b>454</b> and <b>456</b> according to SCSI standards. Each storage unit may contain multiple disk drives daisy chained to their respective adapter.

0068<figref idref="DRAWINGS">FIG. 8</figref> shows details of the first Ethernet-SCSI adapter <b>452</b>, which in this embodiment is an INIC similar to that shown in <figref idref="DRAWINGS">FIG. 1</figref>. Adapter <b>452</b> has a single network port with physical layer connections to network line <b>450</b> provided by conventional PHY <b>470</b>, and media access provided by conventional MAC <b>472</b>. Processing of network message packet headers, including upper layer processing, is provided by sequencers <b>475</b>, which are connected via adapter bus <b>477</b> to processor <b>480</b> and adapter memory <b>482</b>. Adapter memory <b>482</b> includes frame buffers <b>484</b> and a file cache <b>486</b>. Also connected to adapter bus <b>477</b> is a SCSI controller, which is coupled to first storage unit <b>462</b> by SCSI channel <b>458</b>.

0069One difference between adapter <b>452</b> and INIC <b>20</b> is that adapter <b>452</b> is not necessarily connected to a host having a CPU and protocol stack for processing slow-path messages. Connection setup may in this case be handled by adapter <b>452</b>, for example, by INIC <b>400</b> sending an initial packet to adapter <b>452</b> during a connection initialization dialog, with the packet processed by sequencers <b>475</b> and then sent to processor <b>480</b> to create a CCB. Certain conditions that require slow-path processing by a CPU running a software protocol stack are likely to be even less frequent in this environment of communication between adapter <b>452</b> and INIC <b>400</b>. The messages that are sent between adapter <b>452</b> and INIC <b>400</b> may be structured in accordance with a single or restricted set of protocol layers, such as SCSI/TCP and simple network management protocol (SNMP), and are sent to or from a single source to a single or limited number of destinations. Reduction of many of the variables that cause complications in conventional communications networks affords increased use of fast-path processing, reducing the need at adapter <b>452</b> for error processing. Adapter <b>452</b> may have the capability to process several types of storage protocols over IP and TCP, for the case in which the adapter <b>452</b> may be connected to a host that uses one of those protocols for network storage, instead of being connected to INIC <b>400</b>. For the situation in which network <b>450</b> is not a SAN dedicated to storage transfers but also handles communication traffic, an INIC connected to a host having a CPU running a protocol stack for slow-path packets may be employed instead of adapter <b>452</b>.

0070As shown in <figref idref="DRAWINGS">FIG. 9</figref>, additional INICs similar to INIC <b>400</b> may be connected to the host <b>20</b> via the I/O bus <b>40</b>, with each additional INIC providing additional LAN connections and/or being connected to additional SANs. The plural INICs are represented by Nth INIC <b>490</b>, which is connected to Nth SAN <b>492</b> and Nth LAN <b>494</b>. With plural INICs attached to host <b>20</b>, the host can control plural storage networks, with a vast majority of the data flow to and from the host controlled networks bypassing host protocol processing, travel across the I/O bus, travel across the host bus, and storage in the host memory.

0071The processing of message packets received by INIC <b>22</b> of <figref idref="DRAWINGS">FIG. 1</figref> from a network such as network <b>25</b> is shown in more detail in <figref idref="DRAWINGS">FIG. 10</figref>. A received message packet first enters the media access controller <b>60</b>, which controls INIC access to the network and receipt of packets and can provide statistical information for network protocol management. From there, data flows one byte at a time into an assembly register <b>500</b>, which in this example is 128 bits wide. The data is categorized by a fly-by sequencer <b>502</b>, as will be explained in more detail with regard to <figref idref="DRAWINGS">FIG. 11</figref>, which examines the bytes of a packet as they fly by, and generates status from those bytes that will be used to summarize the packet. The status thus created is merged with the data by a multiplexer <b>505</b> and the resulting data stored in SRAM <b>508</b>. A packet control sequencer <b>510</b> oversees the fly-by sequencer <b>502</b>, examines information from the media access controller <b>60</b>, counts the bytes of data, generates addresses, moves status and manages the movement of data from the assembly register <b>500</b> to SRAM <b>508</b> and eventually DRAM <b>512</b>. The packet control sequencer <b>510</b> manages a buffer in SRAM <b>508</b> via SRAM controller <b>515</b>, and also indicates to a DRAM controller <b>518</b> when data needs to be moved from SRAM <b>508</b> to a buffer in DRAM <b>512</b>. Once data movement for the packet has been completed and all the data has been moved to the buffer in DRAM <b>512</b>, the packet control sequencer <b>510</b> will move the status that has been generated in the fly-by sequencer <b>502</b> out to the SRAM <b>508</b> and to the beginning of the DRAM <b>512</b> buffer to be prepended to the packet data. The packet control sequencer <b>510</b> then requests a queue manager <b>520</b> to enter a receive buffer descriptor into a receive queue, which in turn notifies the processor <b>44</b> that the packet has been processed by hardware logic and its status summarized.

0072<figref idref="DRAWINGS">FIG. 11</figref> shows that the fly-by sequencer <b>502</b> has several tiers, with each tier generally focusing on a particular portion of the packet header and thus on a particular protocol layer, for generating status pertaining to that layer. The fly-by sequencer <b>502</b> in this embodiment includes a media access control sequencer <b>540</b>, a network sequencer <b>542</b>, a transport sequencer <b>546</b> and a session sequencer <b>548</b>. Sequencers pertaining to higher protocol layers can additionally be provided. The fly-by sequencer <b>502</b> is reset by the packet control sequencer <b>510</b> and given pointers by the packet control sequencer that tell the fly-by sequencer whether a given byte is available from the assembly register <b>500</b>. The media access control sequencer <b>540</b> determines, by looking at bytes <b>0</b>–<b>5</b>, that a packet is addressed to host <b>20</b> rather than or in addition to another host. Offsets <b>12</b> and <b>13</b> of the packet are also processed by the media access control sequencer <b>540</b> to determine the type field, for example whether the packet is Ethernet or 802.3. If the type field is Ethernet those bytes also tell the media access control sequencer <b>540</b> the packet's network protocol type. For the 802.3 case, those bytes instead indicate the length of the entire frame, and the media access control sequencer <b>540</b> will check eight bytes further into the packet to determine the network layer type.

0073For most packets the network sequencer <b>542</b> validates that the header length received has the correct length, and checksums the network layer header. For fast-path candidates the network layer header is known to be IP or IPX from analysis done by the media access control sequencer <b>540</b>. Assuming for example that the type field is 802.3 and the network protocol is IP, the network sequencer <b>542</b> analyzes the first bytes of the network layer header, which will begin at byte <b>22</b>, in order to determine IP type. The first bytes of the IP header will be processed by the network sequencer <b>542</b> to determine what IP type the packet involves. Determining that the packet involves, for example, IP version <b>4</b>, directs further processing by the network sequencer <b>542</b>, which also looks at the protocol type located ten bytes into the IP header for an indication of the transport header protocol of the packet. For example, for IP over Ethernet, the IP header begins at offset <b>14</b>, and the protocol type byte is offset <b>23</b>, which will be processed by network logic to determine whether the transport layer protocol is TCP, for example. From the length of the network layer header, which is typically 20–40 bytes, network sequencer <b>542</b> determines the beginning of the packet's transport layer header for validating the transport layer header. Transport sequencer <b>546</b> may generate checksums for the transport layer header and data, which may include information from the IP header in the case of TCP at least.

0074Continuing with the example of a TCP packet, transport sequencer <b>546</b> also analyzes the first few bytes in the transport layer portion of the header to determine, in part, the TCP source and destination ports for the message, such as whether the packet is NetBios or other protocols. Byte <b>12</b> of the TCP header is processed by the transport sequencer <b>546</b> to determine and validate the TCP header length. Byte <b>13</b> of the TCP header contains flags that may, aside from ack flags and push flags, indicate unexpected options, such as reset and fin, that may cause the processor to categorize this packet as an exception. TCP offset bytes <b>16</b> and <b>17</b> are the checksum, which is pulled out and stored by the hardware logic while the rest of the frame is validated against the checksum.

0075Session sequencer <b>548</b> determines the length of the session layer header, which in the case of NetBios is only four bytes, two of which tell the length of the NetBios payload data, but which can be much larger for other protocols. The session sequencer <b>548</b> can also be used, for example, to categorize the type of message as a read or write, for which the fast-path may be particularly beneficial. Further upper layer logic processing, depending upon the message type, can be performed by the hardware logic of packet control sequencer <b>510</b> and fly-by sequencer <b>502</b>. Thus the sequencers <b>52</b> intelligently directs hardware processing of the headers by categorization of selected bytes from a single stream of bytes, with the status of the packet being built from classifications determined on the fly. Once the packet control sequencer <b>510</b> detects that all of the packet has been processed by the fly-by sequencer <b>502</b>, the packet control sequencer <b>510</b> adds the status information generated by the fly-by sequencer <b>502</b> and any status information generated by the packet control sequencer <b>510</b>, and prepends (adds to the front) that status information to the packet, for convenience in handling the packet by the processor <b>44</b>. The additional status information generated by the packet control sequencer <b>510</b> includes media access controller <b>60</b> status information and any errors discovered, or data overflow in either the assembly register or DRAM buffer, or other miscellaneous information regarding the packet. The packet control sequencer <b>510</b> also stores entries into a receive buffer queue and a receive statistics queue via the queue manager <b>520</b>.

0076An advantage of processing a packet by hardware logic is that the packet does not, in contrast with conventional sequential software protocol processing, have to be stored, moved, copied or pulled from storage for processing each protocol layer header, offering dramatic increases in processing efficiency and savings in processing time for each packet. The packets can be processed at the rate bits are received from the network, for example 100 megabits/second for a 100 baseT connection. The time for categorizing a packet received at this rate and having a length of sixty bytes is thus about 5 microseconds. The total time for processing this packet with the hardware logic and sending packet data to its host destination via the fast-path may be an order of magnitude less than that required by a conventional CPU employing conventional sequential software protocol processing, without even considering the additional time savings afforded by the reduction in CPU interrupts and host bus bandwidth savings. For the case in which the destination resides in the INIC cache, additional bandwidth savings for host bus <b>35</b> and I/O bus <b>40</b> are achieved.

0077The processor <b>44</b> chooses, for each received message packet held in frame buffers <b>77</b>, whether that packet is a candidate for the fast-path and, if so, checks to see whether a fast-path has already been set up for the connection to which the packet belongs. To do this, the processor <b>44</b> first checks the header status summary to determine whether the packet headers are of a protocol defined for fast-path candidates. If not, the processor <b>44</b> commands DMA controllers in the INIC <b>22</b> to send the packet to the host for slow-path processing. Even for a slow-path processing of a message, the INIC <b>22</b> thus performs initial procedures such as validation and determination of message type, and passes the validated message at least to the data link layer of the host.

0078For fast-path candidates, the processor <b>44</b> checks to see whether the header status summary matches a CCB held by the INIC. If so, the data from the packet is sent along the fast-path to the destination <b>168</b> in the host. If the fast-path candidate's packet summary does not match a CCB held by the INIC, the packet may be sent to the host for slow-path processing to create a CCB for the message. The fast-path may also not be employed for the case of fragmented messages or other complexities. For the vast majority of messages, however, the INIC fast-path can greatly accelerate message processing. The INIC <b>22</b> thus provides a single state machine processor <b>44</b> that decides whether to send data directly to its destination, based upon information gleaned on the fly, as opposed to the conventional employment of a state machine in each of several protocol layers for determining the destiny of a given packet.

0079Caching the CCBs in a hash table in the INIC provides quick comparisons with words summarizing incoming packets to determine whether the packets can be processed via the fast-path, while the full CCBs are also held in the INIC for processing. Other ways to accelerate this comparison include software processes such as a B-tree or hardware assists such as a content addressable memory (CAM). When INIC microcode or comparator circuits detect a match with the CCB, a DMA controller places the data from the packet in the destination in host memory <b>33</b> or INIC File cache <b>80</b>, without any interrupt by the CPU, protocol processing or copying. Depending upon the type of message received, the destination of the data may be the session, presentation or application layers in the host <b>20</b>, or host file cache <b>24</b> or INIC file cache <b>80</b>.

0080One of the most commonly used network protocols for large messages such as file transfers is server message block (SMB) over TCP/IP. SMB can operate in conjunction with redirector software that determines whether a required resource for a particular operation, such as a printer or a disk upon which a file is to be written, resides in or is associated with the host from which the operation was generated or is located at another host connected to the network, such as a file server. SMB and server/redirector are conventionally serviced by the transport layer; in the present invention SMB and redirector can instead be serviced by the INIC. In this case, sending data by the DMA controllers from the INIC buffers when receiving a large SMB transaction may greatly reduce interrupts that the host must handle. Moreover, this DMA generally moves the data to its destination in the host file cache <b>24</b> or INIC file cache <b>80</b>, from which it is then flushed in blocks to the host storage unit <b>66</b> or INIC storage unit <b>70</b>, respectively.

0081An SMB fast-path transmission generally reverses the above described SMB fast-path receive, with blocks of data read from the host storage unit <b>66</b> or INIC storage unit <b>70</b> to the host file cache <b>24</b> or INIC file cache <b>80</b>, respectively, while the associated protocol headers are prepended to the data by the INIC, for transmission via a network line to a remote host. Processing by the INIC of the multiple packets and multiple TCP, IP, NetBios and SMB protocol layers via custom hardware and without repeated interrupts of the host can greatly increase the speed of transmitting an SMB message to a network line. As noted above with regard to <figref idref="DRAWINGS">FIG. 4</figref>, for the case in which the transmitted file blocks are stored on INIC storage unit <b>70</b>, additional savings in host bus <b>35</b> bandwidth and I/O bus bandwidth <b>40</b> can be achieved.

0082<figref idref="DRAWINGS">FIG. 12</figref> shows the Alacritech protocol stack <b>38</b> employed by the host in conjunction with INIC, neither of which are shown in this figure, for processing network messages. An INIC device driver <b>560</b> links the INIC to the operating system of the host, and can pass communications between the INIC and the protocol stack <b>38</b>. The protocol stack <b>38</b> in this embodiment includes data link layer <b>562</b>, network layer <b>564</b>, transport layer <b>566</b>, upper layer interface <b>568</b> and upper layer <b>570</b>. The upper layer <b>570</b> may represent a session, presentation and/or application layer, depending upon the particular protocol employed and message communicated. The protocol stack <b>38</b> processes packet headers in the slow-path, creates and tears down connections, hands out CCBs for fast-path connections to the INIC, and receives CCBs for fast-path connections being flushed from the INIC to the host <b>20</b>. The upper layer interface <b>568</b> is generally responsible for assembling CCBs based upon connection and status information created by the data link layer <b>562</b>, network layer <b>564</b> and transport layer <b>566</b>, and handing out the CCBs to the INIC via the INIC device driver <b>560</b>, or receiving flushed CCBs from the INIC via the INIC device driver <b>560</b>.

0083<figref idref="DRAWINGS">FIG. 13</figref> shows another embodiment of the Alacritech protocol stack <b>38</b> that includes plural protocol stacks for processing network communications in conjunction with a Microsoft® operating system. A conventional Microsoft® TCP/IP protocol stack <b>580</b> includes MAC layer <b>582</b>, IP layer <b>584</b> and TCP layer <b>586</b>. A command driver <b>590</b> works in concert with the host stack <b>580</b> to process network messages. The command driver <b>590</b> includes a MAC layer <b>592</b>, an IP layer <b>594</b> and an Alacritech TCP (ATCP) layer <b>596</b>. The conventional stack <b>580</b> and command driver <b>590</b> share a network driver interface specification (NDIS) layer <b>598</b>, which interacts with an INIC device driver <b>570</b>. The INIC device driver <b>570</b> sorts receive indications for processing by either the conventional host stack <b>580</b> or the ATCP driver <b>590</b>. A TDI filter driver and upper layer interface <b>572</b> similarly determines whether messages sent from a TDI user <b>575</b> to the network are diverted to the command driver and perhaps to the fast-path of the INIC, or processed by the host stack.

0084<figref idref="DRAWINGS">FIG. 14</figref> depicts an SMB exchange between a server <b>600</b> and client <b>602</b>, both of which have INICs, each INIC holding a CCB defining its connection and status for fast-path movement of data over network <b>604</b>, which may be Gigabit Ethernet compliant. The client <b>602</b> includes INIC <b>606</b>, 802.3 compliant data link layer <b>608</b>, IP layer <b>610</b>, TCP layer <b>611</b>, ATCP layer <b>612</b>, NetBios layer <b>614</b>, and SMB layer <b>616</b>. The client has a slow-path <b>618</b> and fast-path <b>620</b> for communication processing. Similarly, the server <b>600</b> includes INIC <b>622</b>, 802.3 compliant data link layer <b>624</b>, IP layer <b>626</b>, TCP layer <b>627</b>, ATCP layer <b>628</b>, NetBios layer <b>630</b>, and SMB layer <b>632</b>. A server attached storage unit <b>634</b> is connected to the server <b>600</b> over a parallel channel <b>638</b> such as a SCSI channel, which is connected to an I/O bus <b>639</b> that is also connected to INIC <b>622</b>. A network storage unit <b>640</b> is connected to INIC <b>622</b> over network line <b>644</b>, and a NAS storage unit <b>642</b> is attached to the same network <b>644</b>, which may be Gigabit Ethernet compliant. Server <b>600</b> has a slow-path <b>646</b> and fast-path <b>648</b> for communication processing that travels over the I/O bus <b>638</b> between INIC <b>622</b> and a file cache, not shown in this figure.

0085A storage fast-path is provided by the INIC <b>622</b>, under control of the server, for data transferred between network storage units <b>640</b> or <b>642</b> and client <b>602</b> that does not cross the I/O bus. Data is communicated between INIC <b>622</b> and network storage unit <b>640</b> in accordance with a block format, such as SCSI/TCP or ISCSI, whereas data is communicated between INIC <b>622</b> and NAS storage unit <b>642</b> in accordance with a file format, such as TCP/NetBios/SMB. For either storage fast-path the INIC <b>622</b> may hold another CCB defining a connection with storage unit <b>640</b> or <b>642</b>. For convenience in the following discussion, the CCB held by INIC <b>606</b> defining its connection over network <b>604</b> with server <b>600</b> is termed the client CCB, the CCB held by INIC <b>622</b> defining its connection over network <b>604</b> with client <b>602</b> is termed the server CCB. A CCB held by INIC <b>622</b> defining its connection over network <b>644</b> with network storage unit <b>640</b> is termed the SAN CCB, and a CCB held by INIC <b>622</b> defining its connection over network <b>644</b> with NAS storage unit <b>642</b> is termed the NAS CCB. Additional network lines <b>650</b> and <b>652</b> may be connected to other communication and/or storage networks.

0086Assuming that the client <b>602</b> wishes to read a 100 KB file on the server <b>600</b> that is stored in blocks on network storage unit <b>640</b>, the client may begin by sending a SMB read request across network <b>604</b> requesting the first 64 KB of that file on the server. The request may be only 76 bytes, for example, and the INIC <b>622</b> on the server recognizes the message type (SMB) and relatively small message size, and sends the 76 bytes directly to the ATCP filter layer <b>628</b>, which delivers the request to NetBios <b>630</b> of the server. NetBios <b>630</b> passes the session headers to SMB <b>632</b>, which processes the read request and determines whether the requested data is held on a host or INIC file cache. If the requested data is not held by the file caches, SMB issues a read request to the file system to read the data from the network storage unit <b>640</b> into the INIC <b>622</b> file cache.

0087To perform this read, the file system instructs INIC <b>622</b> to fetch the 64 KB of data from network storage unit <b>640</b> into the INIC <b>622</b> file cache. The INIC <b>622</b> then sends a request for the data over network <b>644</b> to network storage unit <b>640</b>. The request may take the form of one or more SCSI commands to the storage unit <b>640</b> to read the blocks, with the commands attached to TCP/IP headers, according to ISCSI or similar protocols. A controller on the storage unit <b>640</b> responds to the commands by reading the requested blocks from its disk drive or drives, adding ISCSI or similar protocol headers to the blocks or frame-sized portions of the blocks, and sending the resulting frames over network <b>644</b> to INIC <b>622</b>. The frames are received by the INIC <b>622</b>, processed by the INIC <b>622</b> sequencers, matched with the storage CCB, and reassembled as a 64 KB file stream in the INIC file cache that forms part of the requested 100 KB file. Once the file stream is stored on INIC <b>622</b> file cache, SMB constructs a read reply and sends a scatter-gather list denoting that file stream to INIC <b>622</b>, and passes the reply to the INIC <b>622</b> to send the data over the network according to the server CCB. The INIC <b>622</b> employs the scatter-gather list to read data packets from its file cache, which are prepended with IP/TCP/NetBios/SMB headers created by the INIC based on the server CCB, and sends the resulting frames onto network <b>604</b>. The remaining 36 KB of the file is sent by similar means. In this manner a file on a network storage unit may be transferred under control of the server without any of the data from the file encountering the I/O bus or server protocol stack.

0088For the situation in which the data requested by client <b>602</b> is stored on NAS storage unit <b>642</b>, the request may be forwarded from server <b>600</b> to that storage unit <b>642</b>, which replies by sending the data with headers addressed to client <b>602</b>, with server <b>600</b> serving as a router. For an embodiment in which server <b>600</b> is implemented as a proxy server or as a web cache server, the data from NAS storage unit <b>642</b> may instead be sent to server <b>600</b>, which stores the data in its file cache to offer quicker response to future requests for that data. In this implementation, the file system on server <b>600</b> directs INIC <b>622</b> to request the file data on NAS storage unit <b>642</b>, which responds by sending a number of approximately 1.5 KB packets containing the first 64 KB of file data. The packets containing the file data are received by INIC <b>622</b>, categorized by INIC receive sequencer and matched with the NAS CCB, and a session layer header from an initial packet is processed by the host stack, which obtains from the file system a scatter-gather list of addresses in INIC <b>622</b> file cache to store the data from the packets. The scatter-gather list is sent by the host stack to the INIC <b>622</b> and stored with the NAS CCB, and the INIC <b>622</b> begins to DMA data from any accumulated packets and subsequent packets corresponding to the NAS CCB into the INIC <b>622</b> file cache as a file stream according to the scatter-gather list. The host file system then directs the INIC <b>622</b> to create headers based on the client CCB and prepend the headers to packets of data read from the file stream, for sending the data to client <b>602</b>. The remaining 36 KB of the file is sent by similar means, and may be cached in the INIC <b>622</b> file cache as another file stream. With the file streams maintained in the INIC <b>622</b> file cache, subsequent requests for the file from clients such as client <b>606</b> may be processed more quickly.

0089For the situation in which the file requested by client <b>602</b> was not present in a cache, but instead stored as file blocks on the server attached storage unit <b>634</b>, the server <b>622</b> file system instructs a host SCSI driver to fetch the 100 KB of data from server attached storage unit <b>634</b> into the server <b>600</b> file cache (assuming the file system does not wish to cache the data on INIC <b>622</b> file cache). The host SCSI driver then sends a SCSI request for the data over SCSI channel <b>638</b> to server attached storage unit <b>634</b>. A controller on the server attached storage unit <b>634</b> responds to the commands by reading the requested blocks from its disk drive or drives and sending the blocks over SCSI channel <b>639</b> to the SCSI driver, which interacts with the cache manager under direction of the file system to store the blocks as file streams in the server <b>600</b> file cache. A file system redirector then directs SMB to send a scatter-gather list of the file streams to INIC <b>622</b>, which is used by the INIC <b>622</b> to read data packets from the server <b>600</b> file streams. The INIC <b>622</b> prepends the data packets with headers it created based on the server CCB, and sends the resulting frames onto network <b>604</b>.

0090With INIC <b>606</b> operating on the client <b>602</b> when this reply arrives, the INIC <b>606</b> recognizes from the first frame received that this connection is receiving fast-path <b>620</b> processing (TCP/IP, NetBios, matching a CCB), and the SMB <b>616</b> may use this first frame to acquire buffer space for the message. The allocation of buffers can be provided by passing the first 192 bytes of the of the frame, including any NetBios/SMB headers, via the ATCP fast-path <b>620</b> directly to the client NetBios <b>614</b> to give NetBios/SMB the appropriate headers. NetBios/SMB will analyze these headers, realize by matching with a request ID that this is a reply to the original Read connection, and give the ATCP command driver a 64K list of buffers in a client file cache into which to place the data. At this stage only one frame has arrived, although more may arrive while this processing is occurring. As soon as the client buffer list is given to the ATCP command driver <b>628</b>, it passes that transfer information to the INIC <b>606</b>, and the INIC <b>606</b> starts sending any frame data that has accumulated into those buffers by DMA.

0091Should the client <b>602</b> wish to write an SMB file to a server <b>600</b>, a write request is sent over network <b>604</b>, which may be matched with a CCB held by INIC <b>622</b>. Session layer headers from an initial packet of the file write are processed by server SMB <b>632</b> to allocate buffers in the server <b>600</b> or INIC <b>622</b> file cache, with a scatter-gather list of addresses for those buffers passed back to INIC <b>622</b>, assuming fast-path processing is appropriate. Packets containing SMB file data are received by INIC <b>622</b>, categorized by INIC receive sequencer and placed in a queue. The INIC <b>622</b> processor recognizes that the packets correspond to the server CCB and DMAs the data from the packets into the INIC <b>622</b> or server <b>600</b> file cache buffers according to the scatter-gather list to form a file stream.

0092The file system then orchestrates sending the file stream to server storage unit <b>634</b>, network storage unit <b>640</b> or NAS storage unit <b>642</b>. To send the file stream to server storage unit <b>634</b>, the file system commands a SCSI driver in the server <b>600</b> to send the file stream as file blocks to the storage unit <b>634</b>. To send the file stream to network storage unit <b>640</b>, the file system directs the INIC to create ISCSI or similar headers based on the SAN CCB, and prepend those headers to packets read from the file stream according to the scatter-gather list, sending the resulting frames over network <b>644</b> to storage unit <b>640</b>. To send the file stream to NAS storage unit <b>642</b>, which may for example be useful in distributed file cache or proxy server implementations, the file system redirector prepends appropriate NetBios/SMB headers and directs the INIC to create IP/TCP headers based on the NAS CCB, and prepend those headers to packets read from the file stream according to the scatter-gather list, sending the resulting frames over network <b>644</b> to storage unit <b>642</b>.

0093<figref idref="DRAWINGS">FIG. 15</figref> illustrates a system similar to that shown in <figref idref="DRAWINGS">FIG. 14</figref>, but <figref idref="DRAWINGS">FIG. 15</figref> focuses on a User Datagram Protocol (UDP) implementation of the present invention, particularly in the context of audio and video communications that may involve Realtime Transport Protocol (RTP) and Realtime Transport Control Protocol (RTCP). Server <b>600</b> includes, in addition to the protocol layers shown in <figref idref="DRAWINGS">FIG. 14</figref>, a UDP layer <b>654</b>, an AUDP layer <b>655</b>, an RTP/RTCP layer <b>656</b> and an application layer <b>657</b>. Similarly, client <b>602</b> includes, in addition to the protocol layers shown in <figref idref="DRAWINGS">FIG. 14</figref>, a UDP layer <b>660</b>, an AUDP layer <b>661</b>, an RTP/RTCP layer <b>662</b> and an application layer <b>663</b>. Although RTP/RTCP layers <b>656</b> and <b>662</b> are shown in <figref idref="DRAWINGS">FIG. 15</figref>, other session and application layer protocols may be employed above UDP, such as session initiation protocol (SIP) or media gateway control protocol (MGCP).

0094An audio/video interface (AVI) <b>666</b> or similar peripheral device is coupled to the I/O bus <b>639</b> of server <b>600</b>, and coupled to the AVI <b>666</b> is a speaker <b>668</b>, a microphone <b>670</b>, a display <b>672</b> and a camera <b>674</b>, which may be a video camera. Although shown as a single interface for clarity, AVI <b>666</b> may alternatively include separate interfaces, such as a sound card and a video card, that are each connected to I/O bus <b>639</b>. In another embodiment, AVI interface is connected to a host bus instead of an I/O bus, and may be integrated with a memory controller or I/O controller of the host CPU. AVI <b>666</b> may include a memory that functions as a temporary storage device for audio or video data. Client <b>602</b> also has an I/O bus <b>675</b>, with an AVI <b>677</b> that is coupled to I/O bus <b>675</b>. Coupled to the AVI <b>677</b> is a speaker <b>678</b>, a microphone <b>680</b>, a display <b>682</b> and a camera <b>684</b>, which may be a video camera. Although shown as a single interface for clarity, AVI <b>666</b> may alternatively include separate interfaces, such as a sound card and a video card, that are each connected to I/O bus <b>675</b>.

0095Unlike TCP, UDP does not offer a dependable connection. Instead, UDP packets are sent on a best efforts basis, and packets that are missing or damaged are not resent, unless a layer above UDP provides for such services. UDP provides a way for applications to send data via IP without having to establish a connection. A socket, however, may initially be designated in response to a request by UDP or another protocol, such as network file system (NFS), TCP, RTCP, SIP or MGCP, the socket allocating a port on the receiving device that is able to accept a message sent by UDP. A socket is an application programming interface (API) used by UDP that denotes the source and destination IP addresses and the source and destination UDP ports.

0096To conventionally transmit communications via UDP, datagrams up to 64 KB, which may include session or application layer headers and are commonly NFS default-size datagrams of up to about 8 KB, are prepended with a UDP header by a host computer and handed to the IP layer. The UDP header includes the source and destination ports and an optional checksum. For Ethernet transmission, the UDP datagrams are divided, if necessary, into approximately 1.5 KB fragments by the IP layer, prepended with an IP header, and given to the MAC layer for encapsulation with an Ethernet header and trailer, and sent onto the network. The IP headers contain an IP identification field (IP ID) that is unique to the UDP datagram, a flags field that indicates whether more fragments of that datagram follow and a fragment offset field that indicates which 1.5 KB fragment of the datagram is attached to the IP header, for reassembly of the fragments in correct order.

0097For fast-path UDP data transfer from client <b>602</b> to server <b>600</b>, file streams of data from client application <b>663</b> or audio/video interface <b>677</b>, for example, may be stored on a memory of INIC <b>606</b>, under direction of the file system. The application <b>663</b> can arrange the file streams to contain about 8 KB for example, which may include an upper layer header acquired by INIC <b>606</b> under direction of application <b>663</b>, each file stream received by INIC <b>606</b> being prepended by INIC <b>606</b> with a UDP header according to the socket that has been designated, creating UDP datagrams. The UDP datagrams are divided by INIC <b>606</b> into six 1.5 KB message fragments that are each prepended with IP and MAC layer headers to create IP packets that are transmitted on network <b>604</b>.

0098INIC <b>622</b> receives the Ethernet frames from network <b>604</b> that were sent by INIC <b>606</b>, checksums and processes the headers to determine the protocols involved, and sends the UDP and upper layer headers to the AUDP layer <b>655</b> to obtain a list of destination addresses for the data from the packets of that UDP datagram. The UDP and upper layer headers are contained in one packet of the up to six packets from the UDP datagram, and that packet is usually received prior to other packets from that datagram. For the case in which the packets arrive out of order, the INIC <b>622</b> queues the up to six packets from the UDP datagram in a reassembly buffer. The packets corresponding to the UDP datagram are identified based upon their IP ID, and concatenated based upon the fragment offsets. After the packet containing the UDP and upper layer headers has been processed to obtain the destination addresses, the queued data can be written to those addresses. To account for the possibility that not all packets from a UDP datagram arrive, the INIC <b>622</b> may use a timer that triggers dropping the received data.

0099For realtime voice or video communication, a telecom connection is initially set up between server <b>600</b> and client <b>602</b>. For communications according to the International Telecommunications Union (ITU) H.323 standard, the telecom connection setup is performed with a TCP dialog that designates source and destination UDP ports for data flow using RTP. Another TCP dialog for the telecom connection setup designates source and destination UDP ports for monitoring the data flow using RTCP. SIP provides another mechanism for initiating a telecom connection. After the UDP sockets have been designated, transmission of voice or video data from server <b>600</b> to client <b>602</b> in accordance with the present invention may begin.

0100For example, audio/video interface <b>666</b> can convert sounds and images from microphone <b>670</b> and camera <b>674</b> to audio/video (AV) data that is available to INIC <b>622</b>. Under direction of server <b>600</b> file system, INIC <b>622</b> can acquire 8 KB file streams of the AV data including RTP headers and store that data in an INIC file cache. In accordance with the telecom connection, INIC <b>622</b> can prepend a UDP header to each file stream, which is then fragmented into 1.5 KB fragments each of which is prepended with IP and Ethernet headers and transmitted on network <b>604</b>. Alternatively, the INIC <b>622</b> can create 1.5 KB UDP datagrams from the AV data stored on INIC memory, avoiding fragmentation and allowing UDP, IP and MAC layer headers to be created simultaneously from a template held on INIC <b>622</b> corresponding to the telecom connection. It is also possible to create UDP datagrams larger than 8 KB with the AV data, which creates additional fragmenting but can transfer larger blocks of data per datagram. The RTP header contains a timestamp that indicates the relative times at which the AV data is packetized by the audio/video interface <b>666</b>.

0101In contrast with conventional protocol processing of AV data by a host CPU, INIC <b>622</b> can offload the tasks of UDP header creation, IP fragmentation and IP header creation, saving the host CPU multiple processing cycles, multiple interrupts and greatly reducing host bus traffic. In addition, the INIC <b>622</b> can perform header creation tasks more efficiently by prepending plural headers at one time. Moreover, the AV data may be accessed directly by INIC <b>622</b> on I/O bus <b>639</b>, rather than first being sent over I/O bus <b>639</b> to the protocol processing stack and then being sent back over I/O bus <b>639</b> as RTP/UDP/IP packets. These advantages in efficiency can also greatly reduce delay in transmitting the AV data as compared to conventional protocol processing.

0102An object of realtime voice and video communication systems is that delays and jitter in communication are substantially imperceptible to the people communicating via the system. Jitter is caused by variations in the delay at which packets are received, which results in variations in the tempo at which sights or sounds are displayed compared to the tempo at which they were recorded. The above-mentioned advantage of reduced delay in transmitting packetized voice and/or video can also be used to reduce jitter as well via buffering at a receiving device, because the reduced delay affords increased time at the receiving device for smoothing the jitter. To further reduce delay and jitter in communicating the AV data, IP or MAC layer headers prepended to the UDP datagram fragments by INIC <b>622</b> include a high quality of service (QOS) indication in their type of service field. This indication may be used by network <b>604</b> to speed transmission of high QOS frames, for example by preferentially allocating bandwidth and queuing for those frames.

0103When the frames containing the AV data are received by INIC <b>606</b>, the QOS indication is flagged by the INIC <b>606</b> receive logic and the packets are buffered in a high-priority receive queue of the INIC <b>606</b>. Categorizing and validating the packet headers by hardware logic of INIC <b>606</b> reduces delay in receiving the AV data compared with conventional processing of IP/UDP headers. A UDP header for each datagram may be sent to AUDP layer, which processes the header and indicates to the application the socket involved. The application then directs INIC <b>606</b> to send the data corresponding to that UDP header to a destination in audio/video interface <b>677</b>. Alternatively, after all the fragments corresponding to a UDP datagram have been concatenated in the receive queue, the datagram is written as a file stream without the UDP header to a destination in audio/video interface <b>677</b> corresponding to the socket. Optionally, the UDP datagram may first be stored in another portion of INIC memory. The AV data and RTP header is then sent to audio/video interface <b>677</b>, where it is decoded and played on speaker <b>678</b> and display <b>682</b>.

0104Note that the entire AV data flow and most protocol processing of received IP/UDP packets can be handled by the INIC <b>606</b>, saving the CPU of client <b>602</b> multiple processing cycles and greatly reducing host bus traffic and interrupts. In addition, the specialized hardware logic of INIC <b>606</b> can categorize headers more efficiently than the general purpose CPU. The AV data may also be provided directly by INIC <b>602</b> to audio/video interface <b>677</b> over I/O bus <b>675</b>, rather than first being sent over I/O bus <b>675</b> to the protocol processing stack and then being sent back over I/O bus <b>675</b> to audio/video interface <b>677</b>.

0105<figref idref="DRAWINGS">FIG. 16</figref> provides a diagram of the INIC <b>22</b>, which combines the functions of a network interface, storage controller and protocol processor in a single ASIC chip <b>700</b>. The INIC <b>22</b> in this embodiment offers a full-duplex, four channel, 10/100-Megabit per second (Mbps) intelligent network interface controller that is designed for high speed protocol processing for server and network storage applications. The INIC <b>22</b> can also be connected to personal computers, workstations, routers or other hosts anywhere that TCP/IP, TTCP/IP or SPX/IPX protocols are being utilized. Description of such an INIC is also provided in the related applications listed at the beginning of the present application.

0106The INIC <b>22</b> is connected by network connectors to four network lines <b>702</b>, <b>704</b>, <b>706</b> and <b>708</b>, which may transport data along a number of different conduits, such as twisted pair, coaxial cable or optical fiber, each of the connections providing a media independent interface (MII) via commercially available physical layer chips <b>712</b>, <b>714</b>, <b>716</b> and <b>718</b>, such as model 80220/80221 Ethernet Media Interface Adapter from SEEQ Technology Incorporated, 47200 Bayside Parkway, Fremont, Calif. 94538. The lines preferably are 802.3 compliant and in connection with the INIC constitute four complete Ethernet nodes, the INIC supporting 10Base-T, 10Base-T2, 100Base-TX, 100Base-FX and 100Base-T4 as well as future interface standards. Physical layer identification and initialization is accomplished through host driver initialization routines. The connection between the network lines <b>702</b>, <b>704</b>, <b>706</b> and <b>708</b>, and the INIC <b>22</b> is controlled by MAC units MAC-A <b>722</b>, MAC-B <b>724</b>, MAC-C <b>726</b> and MAC-D <b>728</b> which contain logic circuits for performing the basic functions of the MAC sublayer, essentially controlling when the INIC accesses the network lines <b>702</b>, <b>704</b>, <b>706</b> and <b>708</b>. The MAC units <b>722</b>, <b>724</b>, <b>726</b> and <b>728</b> may act in promiscuous, multicast or unicast modes, allowing the INIC to function as a network monitor, receive broadcast and multicast packets and implement multiple MAC addresses for each node. The MAC units <b>722</b>, <b>724</b>, <b>726</b> and <b>728</b> also provide statistical information that can be used for simple network management protocol (SNMP).

0107The MAC units <b>722</b>, <b>724</b>, <b>726</b> and <b>728</b> are each connected to transmit and receive sequencers, XMT &amp; RCV-A <b>732</b>, XMT &amp; RCV-B <b>734</b>, XMT &amp; RCV-C <b>736</b> and XMT &amp; RCV-D <b>738</b>. Each of the transmit and receive sequencers can perform several protocol processing steps on the fly as message frames pass through that sequencer. In combination with the MAC units, the transmit and receive sequencers <b>732</b>, <b>734</b>, <b>736</b> and <b>738</b> can compile the packet status for the data link, network, transport, session and, if appropriate, presentation and application layer protocols in hardware, greatly reducing the time for such protocol processing compared to conventional sequential software engines. The transmit and receive sequencers <b>732</b>, <b>734</b>, <b>736</b> and <b>738</b> are connected to an SRAM and DMA controller <b>740</b>, which includes DMA controllers <b>742</b> and SRAM controller <b>744</b>, which controls static random access memory (SRAM) buffers <b>748</b>. The SRAM and DMA controllers <b>740</b> interact with external memory control <b>750</b> to send and receive frames via external memory bus <b>752</b> to and from dynamic random access memory (DRAM) buffers <b>755</b>, which is located adjacent to the IC chip <b>700</b>. The DRAM buffers <b>755</b> may be configured as 4 MB, 8 MB, 16 MB or 32 MB, and may optionally be disposed on the chip. The SRAM and DMA controllers <b>740</b> are connected to an I/O bridge that in this case is a PCI Bus Interface Unit (BIU) <b>756</b>, which manages the interface between the INIC <b>22</b> and the PCI interface bus <b>757</b>. The 64-bit, multiplexed BIU <b>756</b> provides a direct interface to the PCI bus <b>757</b> for both slave and master functions. The INIC <b>22</b> is capable of operating in either a 64-bit or 32-bit PCI environment, while supporting 64-bit addressing in either configuration.

0108A microprocessor <b>780</b> is connected to the SRAM and DMA controllers <b>740</b> and to the PCI BIU <b>756</b>. Microprocessor <b>780</b> instructions and register files reside in an on chip control store <b>781</b>, which includes a writable on-chip control store (WCS) of SRAM and a read only memory (ROM). The microprocessor <b>780</b> offers a programmable state machine which is capable of processing incoming frames, processing host commands, directing network traffic and directing PCI bus traffic. Three processors are implemented using shared hardware in a three level pipelined architecture that launches and completes a single instruction for every clock cycle. A receive processor <b>782</b> is primarily used for receiving communications while a transmit processor <b>784</b> is primarily used for transmitting communications in order to facilitate full duplex communication, while a utility processor <b>786</b> offers various functions including overseeing and controlling PCI register access.

0109Since instructions for processors <b>782</b>, <b>784</b> and <b>786</b> reside in the on-chip control-store <b>781</b>, the functions of the three processors can be easily redefined, so that the microprocessor <b>780</b> can be adapted for a given environment. For instance, the amount of processing required for receive functions may outweigh that required for either transmit or utility functions. In this situation, some receive functions may be performed by the transmit processor <b>784</b> and/or the utility processor <b>786</b>. Alternatively, an additional level of pipelining can be created to yield four or more virtual processors instead of three, with the additional level devoted to receive functions.

0110The INIC <b>22</b> in this embodiment can support up to 256 CCBs which are maintained in a table in the DRAM <b>755</b>. There is also, however, a CCB index in hash order in the SRAM <b>748</b> to save sequential searching. Once a hash has been generated, the CCB is cached in SRAM, with up to sixteen cached CCBs in SRAM in this example. Allocation of the sixteen CCBs cached in SRAM is handled by a least recently used register, described below. These cache locations are shared between the transmit <b>784</b> and receive <b>786</b> processors so that the processor with the heavier load is able to use more cache buffers. There are also eight header buffers and eight command buffers to be shared between the sequencers. A given header or command buffer is not statically linked to a specific CCB buffer, as the link is dynamic on a per-frame basis.

0111<figref idref="DRAWINGS">FIG. 17</figref> shows an overview of the pipelined microprocessor <b>780</b>, in which instructions for the receive, transmit and utility processors are executed in three alternating phases according to Clock increments I, II and III, the phases corresponding to each of the pipeline stages. Each phase is responsible for different functions, and each of the three processors occupies a different phase during each Clock increment. Each processor usually operates upon a different instruction stream from the control store <b>781</b>, and each carries its own program counter and status through each of the phases.

0112In general, a first instruction phase <b>800</b> of the pipelined microprocessors completes an instruction and stores the result in a destination operand, fetches the next instruction, and stores that next instruction in an instruction register. A first register set <b>790</b> provides a number of registers including the instruction register, and a set of controls <b>792</b> for the first register set provides the controls for storage to the first register set <b>790</b>. Some items pass through the first phase without modification by the controls <b>792</b>, and instead are simply copied into the first register set <b>790</b> or a RAM file register <b>833</b>. A second instruction phase <b>860</b> has an instruction decoder and operand multiplexer <b>798</b> that generally decodes the instruction that was stored in the instruction register of the first register set <b>490</b> and gathers any operands which have been generated, which are then stored in a decode register of a second register set <b>796</b>. The first register set <b>790</b>, second register set <b>796</b> and a third register set <b>801</b>, which is employed in a third instruction phase <b>900</b>, include many of the same registers, as will be seen in the more detailed views of <figref idref="DRAWINGS">FIGS. 18A–C</figref>. The instruction decoder and operand multiplexer <b>798</b> can read from two address and data ports of the RAM file register <b>833</b>, which operates in both the first phase <b>800</b> and second phase <b>860</b>. A third phase <b>900</b> of the processor <b>780</b> has an arithmetic logic unit (ALU) <b>902</b> which generally performs any ALU operations on the operands from the second register set, storing the results in a results register included in the third register set <b>801</b>. A stack exchange <b>808</b> can reorder register stacks, and a queue manager <b>803</b> can arrange queues for the processor <b>780</b>, the results of which are stored in the third register set.

0113The instructions continue with the first phase then following the third phase, as depicted by a circular pipeline <b>805</b>. Note that various functions have been distributed across the three phases of the instruction execution in order to minimize the combinatorial delays within any given phase. With a frequency in this embodiment of 66 MHz, each Clock increment takes 15 nanoseconds to complete, for a total of 45 nanoseconds to complete one instruction for each of the three processors. The rotating instruction phases are depicted in more detail in <figref idref="DRAWINGS">FIG. 18A–C</figref>, in which each phase is shown in a different figure.

0114More particularly, <figref idref="DRAWINGS">FIG. 18A</figref> shows some specific hardware functions of the first phase <b>800</b>, which generally includes the first register set <b>790</b> and related controls <b>792</b>. The controls for the first register set <b>792</b> includes an SRAM control <b>802</b>, which is a logical control for loading address and write data into SRAM address and data registers <b>820</b>. Thus the output of the ALU <b>902</b> from the third phase <b>900</b> may be placed by SRAM control <b>802</b> into an address register or data register of SRAM address and data registers <b>820</b>. A load control <b>804</b> similarly provides controls for writing a context for a file to file context register <b>822</b>, and another load control <b>806</b> provides controls for storing a variety of miscellaneous data to flip-flop registers <b>825</b>. ALU condition codes, such as whether a carried bit is set, get clocked into ALU condition codes register <b>828</b> without an operation performed in the first phase <b>800</b>. Flag decodes <b>808</b> can perform various functions, such as setting locks, that get stored in flag registers <b>830</b>.

0115The RAM file register <b>833</b> has a single write port for addresses and data and two read ports for addresses and data, so that more than one register can be read from at one time. As noted above, the RAM file register <b>833</b> essentially straddles the first and second phases, as it is written in the first phase <b>800</b> and read from in the second phase <b>860</b>. A control store instruction <b>810</b> allows the reprogramming of the processors due to new data in from the control store <b>781</b>, not shown in this figure, the instructions stored in an instruction register <b>835</b>. The address for this is generated in a fetch control register <b>811</b>, which determines which address to fetch, the address stored in fetch address register <b>838</b>. Load control <b>815</b> provides instructions for a program counter <b>840</b>, which operates much like the fetch address for the control store. A last-in first-out stack <b>844</b> of three registers is copied to the first register set without undergoing other operations in this phase. Finally, a load control <b>817</b> for a debug address <b>848</b> is optionally included, which allows correction of errors that may occur.

0116<figref idref="DRAWINGS">FIG. 18B</figref> depicts the second microprocessor phase <b>860</b>, which includes reading addresses and data out of the RAM file register <b>833</b>. A scratch SRAM <b>865</b> is written from SRAM address and data register <b>820</b> of the first register set, which includes a register that passes through the first two phases to be incremented in the third. The scratch SRAM <b>865</b> is read by the instruction decoder and operand multiplexer <b>798</b>, as are most of the registers from the first register set, with the exception of the stack <b>844</b>, debug address <b>848</b> and SRAM address and data register mentioned above. The instruction decoder and operand multiplexer <b>798</b> looks at the various registers of set <b>790</b> and SRAM <b>865</b>, decodes the instructions and gathers the operands for operation in the next phase, in particular determining the operands to provide to the ALU <b>902</b> below. The outcome of the instruction decoder and operand multiplexer <b>798</b> is stored to a number of registers in the second register set <b>796</b>, including ALU operands <b>879</b> and <b>882</b>, ALU condition code register <b>880</b>, and a queue channel and command <b>887</b> register, which in this embodiment can control thirty-two queues. Several of the registers in set <b>796</b> are loaded fairly directly from the instruction register <b>835</b> above without substantial decoding by the decoder <b>798</b>, including a program control <b>890</b>, a literal field <b>889</b>, a test select <b>884</b> and a flag select <b>885</b>. Other registers such as the file context <b>822</b> of the first phase <b>800</b> are always stored in a file context <b>877</b> of the second phase <b>860</b>, but may also be treated as an operand that is gathered by the multiplexer <b>872</b>. The stack registers <b>844</b> are simply copied in stack register <b>894</b>. The program counter <b>840</b> is incremented <b>868</b> in this phase and stored in register <b>892</b>. Also incremented <b>870</b> is the optional debug address <b>848</b>, and a load control <b>875</b> may be fed from the pipeline <b>805</b> at this point in order to allow error control in each phase, the result stored in debug address <b>898</b>.

0117<figref idref="DRAWINGS">FIG. 18C</figref> depicts the third microprocessor phase <b>900</b>, which includes ALU and queue operations. The ALU <b>902</b> includes an adder, priority encoders and other standard logic functions. Results of the ALU are stored in registers ALU output <b>918</b>, ALU condition codes <b>920</b> and destination operand results <b>922</b>. A file context register <b>916</b>, flag select register <b>926</b> and literal field register <b>930</b> are simply copied from the previous phase <b>860</b>. A test multiplexer <b>904</b> is provided to determine whether a conditional jump results in a jump, with the results stored in a test results register <b>924</b>. The test multiplexer <b>904</b> may instead be performed in the first phase <b>800</b> along with similar decisions such as fetch control <b>811</b>. A stack exchange <b>808</b> shifts a stack up or down by fetching a program counter from stack <b>794</b> or putting a program counter onto that stack, results of which are stored in program control <b>934</b>, program counter <b>938</b> and stack <b>940</b> registers. The SRAM address may optionally be incremented in this phase <b>900</b>. Another load control <b>910</b> for another debug address <b>942</b> may be forced from the pipeline <b>805</b> at this point in order to allow error control in this phase also. A QRAM &amp; QALU <b>906</b>, shown together in this figure, read from the queue channel and command register <b>887</b>, store in SRAM and rearrange queues, adding or removing data and pointers as needed to manage the queues of data, sending results to the test multiplexer <b>904</b> and a queue flags and queue address register <b>928</b>. Thus the QRAM &amp; QALU <b>906</b> assume the duties of managing queues for the three processors, a task conventionally performed sequentially by software on a CPU, the queue manager <b>906</b> instead providing accelerated and substantially parallel hardware queuing.

0118<figref idref="DRAWINGS">FIG. 19</figref> depicts two of the thirty-two hardware queues that are managed by the queue manager <b>906</b>, with each of the queues having an SRAM head, an SRAM tail and the ability to queue information in a DRAM body as well, allowing expansion and individual configuration of each queue. Thus FIFO <b>1000</b> has SRAM storage units, <b>1005</b>, <b>1007</b>, <b>1009</b> and <b>1011</b>, each containing eight bytes for a total of thirty-two bytes, although the number and capacity of these units may vary in other embodiments. Similarly, FIFO <b>1002</b> has SRAM storage units <b>1013</b>, <b>1015</b>, <b>1017</b> and <b>1019</b>. SRAM units <b>1005</b> and <b>1007</b> are the head of FIFO <b>1000</b> and units <b>1009</b> and <b>1011</b> are the tail of that FIFO, while units <b>1013</b> and <b>1015</b> are the head of FIFO <b>1002</b> and units <b>1017</b> and <b>1019</b> are the tail of that FIFO. Information for FIFO <b>1000</b> may be written into head units <b>1005</b> or <b>1007</b>, as shown by arrow <b>1022</b>, and read from tail units <b>1011</b> or <b>1009</b>, as shown by arrow <b>1025</b>. A particular entry, however, may be both written to and read from head units <b>1005</b> or <b>1007</b>, or may be both written to and read from tail units <b>1009</b> or <b>1011</b>, minimizing data movement and latency. Similarly, information for FIFO <b>1002</b> is typically written into head units <b>1013</b> or <b>1015</b>, as shown by arrow <b>1033</b>, and read from tail units <b>1017</b> or <b>1019</b>, as shown by arrow <b>1039</b>, but may instead be read from the same head or tail unit to which it was written.

0119The SRAM FIFOS <b>1000</b> and <b>1002</b> are both connected to DRAM <b>755</b>, which allows virtually unlimited expansion of those FIFOS to handle situations in which the SRAM head and tail are full. For example a first of the thirty-two queues, labeled Q-zero, may queue an entry in DRAM <b>755</b>, as shown by arrow <b>1027</b>, by DMA units acting under direction of the queue manager, instead of being queued in the head or tail of FIFO <b>700</b>. Entries stored in DRAM <b>755</b> return to SRAM unit <b>1009</b>, as shown by arrow <b>1030</b>, extending the length and fall-through time of that FIFO. Diversion from SRAM to DRAM is typically reserved for when the SRAM is full, since DRAM is slower and DMA movement causes additional latency. Thus Q-zero may comprise the entries stored by queue manager <b>803</b> in both the FIFO <b>1000</b> and the DRAM <b>755</b>. Likewise, information bound for FIFO <b>1002</b>, which may correspond to Q-twenty-seven, for example, can be moved by DMA into DRAM <b>755</b>, as shown by arrow <b>1035</b>. The capacity for queuing in cost-effective albeit slower DRAM <b>803</b> is user-definable during initialization, allowing the queues to change in size as desired. Information queued in DRAM <b>755</b> is returned to SRAM unit <b>1017</b>, as shown by arrow <b>1037</b>.

0120Status for each of the thirty-two hardware queues is conveniently maintained in and accessed from a set <b>1040</b> of four, thirty-two bit registers, as shown in <figref idref="DRAWINGS">FIG. 20</figref>, in which a specific bit in each register corresponds to a specific queue. The registers are labeled Q-Out_Ready <b>1045</b>, Q-In_Ready <b>1050</b>, Q-Empty <b>1055</b> and Q-Full <b>1060</b>. If a particular bit is set in the Q-Out_Ready register <b>1050</b>, the queue corresponding to that bit contains information that is ready to be read, while the setting of the same bit in the Q-In_Ready <b>1052</b> register means that the queue is ready to be written. Similarly, a positive setting of a specific bit in the Q-Empty register <b>1055</b> means that the queue corresponding to that bit is empty, while a positive setting of a particular bit in the Q-Full register <b>1060</b> means that the queue corresponding to that bit is full. Thus Q-Out_Ready <b>1045</b> contains bits zero <b>1046</b> through thirty-one <b>1048</b>, including bits twenty-seven <b>1052</b>, twenty-eight <b>1054</b>, twenty-nine <b>1056</b> and thirty <b>1058</b>. Q-In_Ready <b>1050</b> contains bits zero <b>1062</b> through thirty-one <b>1064</b>, including bits twenty-seven <b>1066</b>, twenty-eight <b>1068</b>, twenty-nine <b>1070</b> and thirty <b>1072</b>. Q-Empty <b>1055</b> contains bits zero <b>1074</b> through thirty-one <b>1076</b>, including bits twenty-seven <b>1078</b>, twenty-eight <b>1080</b>, twenty-nine <b>1082</b> and thirty <b>1084</b>, and Q-full <b>1060</b> contains bits zero <b>1086</b> through thirty-one <b>1088</b>, including bits twenty-seven <b>1090</b>, twenty-eight <b>1092</b>, twenty-nine <b>1094</b> and thirty <b>1096</b>.

0121Q-zero, corresponding to FIFO <b>1000</b>, is a free buffer queue, which holds a list of addresses for all available buffers. This queue is addressed when the microprocessor or other devices need a free buffer address, and so commonly includes appreciable DRAM <b>755</b>. Thus a device needing a free buffer address would check with Q-zero to obtain that address. Q-twenty-seven, corresponding to FIFO <b>1002</b>, is a receive buffer descriptor queue. After processing a received frame by the receive sequencer the sequencer looks to store a descriptor for the frame in Q-twenty-seven. If a location for such a descriptor is immediately available in SRAM, bit twenty-seven <b>1066</b> of Q-In_Ready <b>1050</b> will be set. If not, the sequencer must wait for the queue manager to initiate a DMA move from SRAM to DRAM, thereby freeing space to store the receive descriptor.

0122Operation of the queue manager, which manages movement of queue entries between SRAM and the processor, the transmit and receive sequencers, and also between SRAM and DRAM, is shown in more detail in <figref idref="DRAWINGS">FIG. 21</figref>. Requests that utilize the queues include Processor Request <b>1102</b>, Transmit Sequencer Request <b>1104</b>, and Receive Sequencer Request <b>1106</b>. Other requests for the queues are DRAM to SRAM Request <b>1108</b> and SRAM to DRAM Request <b>1110</b>, which operate on behalf of the queue manager in moving data back and forth between the DRAM and the SRAM head or tail of the queues. Determining which of these various requests will get to use the queue manager in the next cycle is handled by priority logic Arbiter <b>1115</b>. To enable high frequency operation the queue manager is pipelined, with Register A <b>1118</b> and Register B <b>1120</b> providing temporary storage, while Status Register <b>1122</b> maintains status until the next update. The queue manager reserves even cycles for DMA, receive and transmit sequencer requests and odd cycles for processor requests. Dual ported QRAM <b>1125</b> stores variables regarding each of the queues, the variables for each queue including a Head Write Pointer, Head Read Pointer, Tail Write Pointer and Tail Read Pointer corresponding to the queue's SRAM condition, and a Body Write Pointer and Body Read Pointer corresponding to the queue's DRAM condition and the queue's size.

0123After Arbiter <b>1115</b> has selected the next operation to be performed, the variables of QRAM <b>825</b> are fetched and modified according to the selected operation by a QALU <b>1128</b>, and an SRAM Read Request <b>1130</b> or an SRAM Write Request <b>1140</b> may be generated. The variables are updated and the updated status is stored in Status Register <b>1122</b> as well as QRAM <b>1125</b>. The status is also fed to Arbiter <b>1115</b> to signal that the operation previously requested has been fulfilled, inhibiting duplication of requests. The Status Register <b>1122</b> updates the four queue registers Q-Out_Ready <b>1045</b>, Q-In_Ready <b>1050</b>, Q-Empty <b>1055</b> and Q-Full <b>1060</b> to reflect the new status of the queue that was accessed. Similarly updated are SRAM Addresses <b>1133</b>, Body Write Request <b>1135</b> and Body Read Requests <b>1138</b>, which are accessed via DMA to and from SRAM head and tails for that queue. Alternatively, various processes may wish to write to a queue, as shown by Q Write Data <b>1144</b>, which are selected by multiplexer <b>1146</b>, and pipelined to SRAM Write Request <b>1140</b>. The SRAM controller services the read and write requests by writing the tail or reading the head of the accessed queue and returning an acknowledge. In this manner the various queues are utilized and their status updated. Structure and operation of queue manager <b>803</b> is also described in U.S. patent application Ser. No. 09/416,925, entitled “Queue System For Microprocessors”, filed Oct. 13, 1999, by Daryl D. Starr and Clive M. Philbrick (the subject matter of which is incorporated herein by reference).

0124<figref idref="DRAWINGS">FIGS. 22A–D</figref> show a least-recently-used register <b>1200</b> that is employed for choosing which contexts or CCBs to maintain in INIC cache memory. The INIC in this embodiment can cache up to sixteen CCBs in SRAM at a given time, and so when a new CCB is cached an old one must often be discarded, the discarded CCB usually chosen according to this register <b>1200</b> to be the CCB that has been used least recently. In this embodiment, a hash table for up to two hundred fifty-six CCBs is also maintained in SRAM, while up to two hundred fifty-six full CCBs are held in DRAM. The least-recently-used register <b>1200</b> contains sixteen four-bit blocks labeled R<b>0</b>–R<b>15</b>, each of which corresponds to an SRAM cache unit. Upon initialization, the blocks are numbered <b>0</b>–<b>15</b>, with number <b>0</b> arbitrarily stored in the block representing the least recently used (LRU) cache unit and number <b>15</b> stored in the block representing the most recently used (MRU) cache unit. <figref idref="DRAWINGS">FIG. 22A</figref> shows the register <b>1200</b> at an arbitrary time when the LRU block R<b>0</b> holds the number <b>9</b> and the MRU block R<b>15</b> holds the number <b>6</b>.When a different CCB than is currently being held in SRAM is to be cached, the LRU block R<b>0</b> is read, which in <figref idref="DRAWINGS">FIG. 22A</figref> holds the number <b>9</b>, and the new CCB is stored in the SRAM cache unit corresponding to number <b>9</b>. Since the new CCB corresponding to number <b>9</b> is now the most recently used CCB, the number <b>9</b> is stored in the MRU block, as shown in <figref idref="DRAWINGS">FIG. 22B</figref>. The other numbers are all shifted one register block to the left, leaving the number <b>1</b> in the LRU block. The CCB that had previously been cached in the SRAM unit corresponding to number <b>9</b> has been moved to slower but more cost-effective DRAM.

0125<figref idref="DRAWINGS">FIG. 22C</figref> shows the result when the next CCB used had already been cached in SRAM. In this example, the CCB was cached in an SRAM unit corresponding to number <b>10</b>, and so after employment of that CCB, number <b>10</b> is stored in the MRU block. Only those numbers which had previously been more recently used than number <b>10</b> (register blocks R<b>9</b>–R<b>15</b>) are shifted to the left, leaving the number <b>1</b> in the LRU block. In this manner the INIC maintains the most active CCBs in SRAM cache.

0126In some cases a CCB being used is one that is not desirable to hold in the limited cache memory. For example, it is preferable not to cache a CCB for a context that is known to be closing, so that other cached CCBs can remain in SRAM longer. In this case, the number representing the cache unit holding the decacheable CCB is stored in the LRU block R<b>0</b> rather than the MRU block R<b>15</b>, so that the decacheable CCB will be replaced immediately upon employment of a new CCB that is cached in the SRAM unit corresponding to the number held in the LRU block R<b>0</b>. <figref idref="DRAWINGS">FIG. 22D</figref> shows the case for which number <b>8</b> (which had been in block R<b>9</b> in <figref idref="DRAWINGS">FIG. 22C</figref>) corresponds to a CCB that will be used and then closed. In this case number <b>8</b> has been removed from block R<b>9</b> and stored in the LRU block R<b>0</b>. All the numbers that had previously been stored to the left of block R<b>9</b> (R<b>1</b>–R<b>8</b>) are then shifted one block to the right.

0127<figref idref="DRAWINGS">FIG. 23</figref> shows some of the logical units employed to operate the least-recently-used register <b>1200</b>. An array of sixteen, three or four input multiplexers <b>1210</b>, of which only multiplexers MUX<b>0</b>, MUX<b>7</b>, MUX<b>8</b>, MUX<b>9</b> and MUX<b>15</b> are shown for clarity, have outputs fed into the corresponding sixteen blocks of least-recently-used register <b>1200</b>. For example, the output of MUX<b>0</b> is stored in block R<b>0</b>, the output of MUX<b>7</b> is stored in block R<b>7</b>, etc. The value of each of the register blocks is connected to an input for its corresponding multiplexer and also into inputs for both adjacent multiplexers, for use in shifting the block numbers. For instance, the number stored in R<b>8</b> is fed into inputs for MUX<b>7</b>, MUX<b>8</b> and MUX<b>9</b>. MUX<b>0</b> and MUX<b>15</b> each have only one adjacent block, and the extra input for those multiplexers is used for the selection of LRU and MRU blocks, respectively. MUX<b>15</b> is shown as a four-input multiplexer, with input <b>1215</b> providing the number stored on R<b>0</b>.

0128An array of sixteen comparators <b>1220</b> each receives the value stored in the corresponding block of the least-recently-used register <b>1200</b>. Each comparator also receives a signal from processor <b>780</b> along line <b>1235</b> so that the register block having a number matching that sent by processor <b>780</b> outputs true to logic circuits <b>1230</b> while the other fifteen comparators output false. Logic circuits <b>1230</b> control a pair of select lines leading to each of the multiplexers, for selecting inputs to the multiplexers and therefore controlling shifting of the register block numbers. Thus select lines <b>1239</b> control MUX<b>0</b>, select lines <b>1244</b> control MUX<b>7</b>, select lines <b>1249</b> control MUX<b>8</b>, select lines <b>1254</b> control MUX<b>9</b> and select lines <b>1259</b> control MUX<b>15</b>.

0129When a CCB is to be used, processor <b>780</b> checks to see whether the CCB matches a CCB currently held in one of the sixteen cache units. If a match is found, the processor sends a signal along line <b>1235</b> with the block number corresponding to that cache unit, for example number <b>12</b>. Comparators <b>1220</b> compare the signal from that line <b>1235</b> with the block numbers and comparator C<b>8</b> provides a true output for the block R<b>8</b> that matches the signal, while all the other comparators output false. Logic circuits <b>1230</b>, under control from the processor <b>780</b>, use select lines <b>1259</b> to choose the input from line <b>1235</b> for MUX<b>15</b>, storing the number <b>12</b> in the MRU block R<b>15</b>. Logic circuits <b>1230</b> also send signals along the pairs of select lines for MUX<b>8</b> and higher multiplexers, aside from MUX<b>15</b>, to shift their output one block to the left, by selecting as inputs to each multiplexer MUX<b>8</b> and higher the value that had been stored in register blocks one block to the right (R<b>9</b>–R<b>15</b>). The outputs of multiplexers that are to the left of MUX<b>8</b> are selected to be constant.

0130If processor <b>780</b> does not find a match for the CCB among the sixteen cache units, on the other hand, the processor reads from LRU block R<b>0</b> along line <b>1266</b> to identify the cache corresponding to the LRU block, and writes the data stored in that cache to DRAM. The number that was stored in R<b>0</b>, in this case number <b>3</b>, is chosen by select lines <b>1259</b> as input <b>1215</b> to MUX<b>15</b> for storage in MRU block R<b>15</b>. The other fifteen multiplexers output to their respective register blocks the numbers that had been stored each register block immediately to the right.

0131For the situation in which the processor wishes to remove a CCB from the cache after use, the LRU block R<b>0</b> rather than the MRU block R<b>15</b> is selected for placement of the number corresponding to the cache unit holding that CCB. The number corresponding to the CCB to be placed in the LRU block R<b>0</b> for removal from SRAM (for example number <b>1</b>, held in block R<b>9</b>) is sent by processor <b>780</b> along line <b>1235</b>, which is matched by comparator C<b>9</b>. The processor instructs logic circuits <b>1230</b> to input the number <b>1</b> to R<b>0</b>, by selecting with lines <b>1239</b> input <b>1235</b> to MUX<b>0</b>. Select lines <b>1254</b> to MUX<b>9</b> choose as input the number held in register block R<b>8</b>, so that the number from R<b>8</b> is stored in R<b>9</b>. The numbers held by the other register blocks between R<b>0</b> and R<b>9</b> are similarly shifted to the right, whereas the numbers in register blocks to the right of R<b>9</b> are left constant. This frees scarce cache memory from maintaining closed CCBs for many cycles while their identifying numbers move through register blocks from the MRU to the LRU blocks.

0132<figref idref="DRAWINGS">FIG. 24</figref> illustrates additional details of INIC <b>22</b>, focusing in this description on a single network connection. INIC <b>22</b> includes PHY chip <b>712</b>, ASIC chip <b>700</b> and DRAM <b>755</b>. PHY chip <b>712</b> couples INIC card <b>22</b> to network line <b>2102</b> via a network connector <b>2101</b>. INIC <b>22</b> is coupled to the CPU of the host (for example, CPU <b>30</b> of host <b>20</b> of <figref idref="DRAWINGS">FIG. 1</figref>) via card edge connector <b>2107</b> and PCI bus <b>757</b>. ASIC chip <b>700</b> includes a Media Access Control (MAC) unit <b>722</b>, a sequencers block <b>732</b>, SRAM control <b>744</b>, SRAM <b>748</b>, DRAM control <b>742</b>, a queue manager <b>803</b>, a processor <b>780</b>, and a PCI bus interface unit <b>756</b>. Sequencers block <b>732</b> includes a transmit sequencer <b>2104</b>, a receive sequencer <b>2105</b>, and configuration registers <b>2106</b>. A MAC destination address is stored in configuration register <b>2106</b>. Part of the program code executed by processor <b>780</b> is contained in ROM (not shown) and part is located in a writeable control store SRAM (not shown). The program may be downloaded into the writeable control store SRAM at initialization from the host <b>20</b>.

0133<figref idref="DRAWINGS">FIG. 25</figref> is a more detailed diagram of the receive sequencer <b>2105</b> of <figref idref="DRAWINGS">FIG. 24</figref>. Receive sequencer <b>2105</b> includes a data synchronization buffer <b>2200</b>, a packet synchronization sequencer <b>2201</b>, a data assembly register <b>2202</b>, a protocol analyzer <b>2203</b>, a packet processing sequencer <b>2204</b>, a queue manager interface <b>2205</b>, and a Direct Memory Access (DMA) control block <b>2206</b>. The packet synchronization sequencer <b>2201</b> and data synchronization buffer <b>2200</b> utilize a network-synchronized clock of MAC <b>722</b>, whereas the remainder of the receive sequencer <b>2105</b> utilizes a fixed-frequency clock. Dashed line <b>2221</b> indicates the clock domain boundary.

0134Operation of receive sequencer <b>2105</b> of <figref idref="DRAWINGS">FIGS. 24 and 25</figref> is now described in connection with the receipt onto INIC <b>22</b> of a TCP/IP packet from network line <b>2102</b>. At initialization time, processor <b>780</b> partitions DRAM <b>755</b> into buffers. Receive sequencer <b>2105</b> uses the buffers in DRAM <b>755</b> to store incoming network packet data as well as status information for the packet. Processor <b>780</b> creates a 32-bit buffer descriptor for each buffer. A buffer descriptor indicates the size and location in DRAM of its associated buffer. Processor <b>780</b> places these buffer descriptors on a “free-buffer queue” <b>2108</b> by writing the descriptors to the queue manager <b>803</b>. Queue manager <b>803</b> maintains multiple queues including the “free-buffer queue” <b>2108</b>. In this implementation, the heads and tails of the various queues are located in SRAM <b>748</b>, whereas the middle portion of the queues are located in DRAM <b>755</b>.

0135Lines <b>2229</b> comprise a request mechanism involving a request line and address lines. Similarly, lines <b>2230</b> comprise a request mechanism involving a request line and address lines. Queue manager <b>803</b> uses lines <b>2229</b> and <b>2230</b> to issue requests to transfer queue information from DRAM to SRAM or from SRAM to DRAM.

0136The queue manager interface <b>2205</b> of the receive sequencer always attempts to maintain a free buffer descriptor <b>2207</b> for use by the packet processing sequencer <b>2204</b>. Bit <b>2208</b> is a ready bit that indicates that free-buffer descriptor <b>2207</b> is available for use by the packet processing sequencer <b>2204</b>. If queue manager interface <b>2205</b> does not have a free buffer descriptor (bit <b>2208</b> is not set), then queue manager interface <b>2205</b> requests one from queue manager <b>803</b> via request line <b>2209</b>. (Request line <b>2209</b> is actually a bus that communicates the request, a queue ID, a read/write signal and data if the operation is a write to the queue.)

0137In response, queue manager <b>803</b> retrieves a free buffer descriptor from the tail of the “free buffer queue” <b>2108</b> and then alerts the queue manager interface <b>2205</b> via an acknowledge signal on acknowledge line <b>2210</b>. When queue manager interface <b>2205</b> receives the acknowledge signal, the queue manager interface <b>2205</b> loads the free buffer descriptor <b>2207</b> and sets the ready bit <b>2208</b>. Because the free buffer descriptor was in the tail of the free buffer queue in SRAM <b>748</b>, the queue manager interface <b>2205</b> actually receives the free buffer descriptor <b>2207</b> from the read data bus <b>2228</b> of the SRAM control block <b>744</b>. Packet processing sequencer <b>2204</b> requests a free buffer descriptor <b>2207</b> via request line <b>2211</b>. When the queue manager interface <b>2205</b> retrieves the free buffer descriptor <b>2207</b> and the free buffer descriptor <b>2207</b> is available for use by the packet processing sequencer, the queue manager interface <b>2205</b> informs the packet processing sequencer <b>2204</b> via grant line <b>2212</b>. By this process, a free buffer descriptor is made available for use by the packet processing sequencer <b>2204</b> and the receive sequencer <b>2105</b> is ready to processes an incoming packet.

0138Next, a TCP/IP packet is received from the network line <b>2105</b> via network connector <b>2101</b> and Physical Layer Interface (PHY) <b>712</b>. PHY <b>712</b> supplies the packet to MAC <b>722</b> via a Media Independent Interface (MII) parallel bus <b>2109</b>. MAC <b>722</b> begins processing the packet and asserts a “start of packet” signal on line <b>2213</b> indicating that the beginning of a packet is being received. When a byte of data is received in the MAC and is available at the MAC outputs <b>2215</b>, MAC <b>722</b> asserts a “data valid” signal on line <b>2214</b>. Upon receiving the “data valid” signal, the packet synchronization sequencer <b>2201</b> instructs the data synchronization buffer <b>2200</b> via load signal line <b>2222</b> to load the received byte from data lines <b>2215</b>. Data synchronization buffer <b>2200</b> is four bytes deep. The packet synchronization sequencer <b>2201</b> then increments a data synchronization buffer write pointer. This data synchronization buffer write pointer is made available to the packet processing sequencer <b>2204</b> via lines <b>2216</b>. Consecutive bytes of data from data lines <b>2215</b> are clocked into the data synchronization buffer <b>2200</b> in this way.

0139A data synchronization buffer read pointer available on lines <b>2219</b> is maintained by the packet processing sequencer <b>2204</b>. The packet processing sequencer <b>2204</b> determines that data is available in data synchronization buffer <b>2200</b> by comparing the data synchronization buffer write pointer on lines <b>2216</b> with the data synchronization buffer read pointer on lines <b>2219</b>.

0140Data assembly register <b>2202</b> contains a sixteen-byte long shift register <b>2217</b>. This register <b>2217</b> is loaded serially a single byte at a time and is unloaded in parallel. When data is loaded into register <b>2217</b>, a write pointer is incremented. This write pointer is made available to the packet processing sequencer <b>2204</b> via lines <b>2218</b>. Similarly, when data is unloaded from register <b>2217</b>, a read pointer maintained by packet processing sequencer <b>2204</b> is incremented. This read pointer is available to the data assembly register <b>2202</b> via lines <b>2220</b>. The packet processing sequencer <b>2204</b> can therefore determine whether room is available in register <b>2217</b> by comparing the write pointer on lines <b>2218</b> to the read pointer on lines <b>2220</b>.

0141If the packet processing sequencer <b>2204</b> determines that room is available in register <b>2217</b>, then packet processing sequencer <b>2204</b> instructs data assembly register <b>2202</b> to load a byte of data from data synchronization buffer <b>2200</b>. The data assembly register <b>2202</b> increments the data assembly register write pointer on lines <b>2218</b> and the packet processing sequencer <b>2204</b> increments the data synchronization buffer read pointer on lines <b>2219</b>. Data shifted into register <b>2217</b> is examined at the register outputs by protocol analyzer <b>2203</b> which verifies checksums, and generates “status” information <b>2223</b>.

0142DMA control block <b>2206</b> is responsible for moving information from register <b>2217</b> to buffer <b>2114</b> via a sixty-four byte receive FIFO <b>2110</b>. DMA control block <b>2206</b> implements receive FIFO <b>2110</b> as two thirty-two byte ping-pong buffers using sixty-four bytes of SRAM <b>748</b>. DMA control block <b>2206</b> implements the receive FIFO using a write-pointer and a read-pointer. When data to be transferred is available in register <b>2217</b> and space is available in FIFO <b>2110</b>, DMA control block <b>2206</b> asserts an SRAM write request to SRAM controller <b>744</b> via lines <b>2225</b>. SRAM controller <b>744</b> in turn moves data from register <b>2217</b> to FIFO <b>2110</b> and asserts an acknowledge signal back to DMA control block <b>2206</b> via lines <b>2225</b>. DMA control block <b>2206</b> then increments the receive FIFO write pointer and causes the data assembly register read pointer to be incremented.

0143When thirty-two bytes of data has been deposited into receive FIFO <b>2110</b>, DMA control block <b>2206</b> presents a DRAM write request to DRAM controller <b>742</b> via lines <b>2226</b>. This write request consists of the free buffer descriptor <b>2207</b> ORed with a “buffer load count” for the DRAM request address, and the receive FIFO read pointer for the SRAM read address. Using the receive FIFO read pointer, the DRAM controller <b>742</b> asserts a read request to SRAM controller <b>744</b>. SRAM controller <b>744</b> responds to DRAM controller <b>742</b> by returning the indicated data from the receive FIFO <b>2110</b> in SRAM <b>748</b> and asserting an acknowledge signal. DRAM controller <b>742</b> stores the data in a DRAM write data register, stores a DRAM request address in a DRAM address register, and asserts an acknowledge to DMA control block <b>2206</b>. The DMA control block <b>2206</b> then decrements the receive FIFO read pointer. Then the DRAM controller <b>742</b> moves the data from the DRAM write data register to buffer <b>2114</b>. In this way, as consecutive thirty-two byte chunks of data are stored in SRAM <b>748</b>, DRAM control block <b>2206</b> moves those thirty-two byte chunks of data one at a time from SRAM <b>748</b> to buffer <b>2214</b> in DRAM <b>755</b>. Transferring thirty-two byte chunks of data to the DRAM <b>755</b> in this fashion allows data to be written into the DRAM using the relatively efficient burst mode of the DRAM.

0144Packet data continues to flow from network line <b>2105</b> to buffer <b>2114</b> until all packet data has been received. MAC <b>722</b> then indicates that the incoming packet has completed by asserting an “end of frame” (i.e., end of packet) signal on line <b>2227</b> and by presenting final packet status (MAC packet status) to packet synchronization sequencer <b>2204</b>. The packet processing sequencer <b>2204</b> then moves the status <b>2223</b> (also called “protocol analyzer status”) and the MAC packet status to register <b>2217</b> for eventual transfer to buffer <b>2114</b>. After all the data of the packet has been placed in buffer <b>2214</b>, status <b>2223</b> and the MAC packet status is transferred to buffer <b>2214</b> so that it is stored prepended to the associated data as shown in <figref idref="DRAWINGS">FIG. 23</figref>.

0145After all data and status has been transferred to buffer <b>2114</b>, packet processing sequencer <b>2204</b> creates a summary <b>2224</b> (also called a “receive packet descriptor”) by concatenating the free buffer descriptor <b>2207</b>, the buffer load-count, the MAC ID, and a status bit (also called an “attention bit”). If the attention bit is a one, then the packet is not a “fast-path candidate”; whereas if the attention bit is a zero, then the packet is a “fast-path candidate”. The value of the attention bit represents the result of a significant amount of processing that processor <b>780</b> would otherwise have to do to determine whether the packet is a “fast-path candidate”. For example, the attention bit being a zero indicates that the packet employs both TCP protocol and IP protocol. By carrying out this significant amount of processing in hardware beforehand and then encoding the result in the attention bit, subsequent decision making by processor <b>780</b> as to whether the packet is an actual “fast-path packet” is accelerated.

0146Packet processing sequencer <b>2204</b> then sets a ready bit (not shown) associated with summary <b>2224</b> and presents summary <b>2224</b> to queue manager interface <b>2205</b>. Queue manager interface <b>2205</b> then requests a write to the head of a “summary queue” <b>2112</b> (also called the “receive descriptor queue”). The queue manager <b>803</b> receives the request, writes the summary <b>2224</b> to the head of the summary queue <b>2212</b>, and asserts an acknowledge signal back to queue manager interface via line <b>2210</b>. When queue manager interface <b>2205</b> receives the acknowledge, queue manager interface <b>2205</b> informs packet processing sequencer <b>2204</b> that the summary <b>2224</b> is in summary queue <b>2212</b> by clearing the ready bit associated with the summary. Packet processing sequencer <b>2204</b> also generates additional status information (also called a “vector”) for the packet by concatenating the MAC packet status and the MAC ID. Packet processing sequencer <b>2204</b> sets a ready bit (not shown) associated with this vector and presents this vector to the queue manager interface <b>2205</b>. The queue manager interface <b>2205</b> and the queue manager <b>803</b> then cooperate to write this vector to the head of a “vector queue” <b>2113</b> in similar fashion to the way summary <b>2224</b> was written to the head of summary queue <b>2112</b> as described above. When the vector for the packet has been written to vector queue <b>2113</b>, queue manager interface <b>2205</b> resets the ready bit associated with the vector.

0147Once summary <b>2224</b> (including a buffer descriptor that points to buffer <b>2114</b>) has been placed in summary queue <b>2112</b> and the packet data has been placed in buffer <b>2144</b>, processor <b>780</b> can retrieve summary <b>2224</b> from summary queue <b>2112</b> and examine the “attention bit”.

0148If the attention bit from summary <b>2224</b> is a digital one, then processor <b>780</b> determines that the packet is not a “fast-path candidate” and processor <b>780</b> need not examine the packet headers. Only the status <b>2223</b> (first sixteen bytes) from buffer <b>2114</b> are DMA transferred to SRAM so processor <b>780</b> can examine it. If the status <b>2223</b> indicates that the packet is a type of packet that is not to be transferred to the host (for example, a multicast frame that the host is not registered to receive), then the packet is discarded (i.e., not passed to the host). If status <b>2223</b> does not indicate that the packet is the type of packet that is not to be transferred to the host, then the entire packet (headers and data) is passed to a buffer on host <b>20</b> for “slow-path” transport and network layer processing by the protocol stack of host <b>20</b>.

0149If, on the other hand, the attention bit is a zero, then processor <b>780</b> determines that the packet is a “fast-path candidate”. If processor <b>780</b> determines that the packet is a “fast-path candidate”, then processor <b>780</b> uses the buffer descriptor from the summary to DMA transfer the first approximately 96 bytes of information from buffer <b>2114</b> from DRAM <b>755</b> into a portion of SRAM <b>748</b> so processor <b>780</b> can examine it. This first approximately 96 bytes contains status <b>2223</b> as well as the IP source address of the IP header, the IP destination address of the IP header, the TCP source address of the TCP header, and the TCP destination address of the TCP header. The IP source address of the IP header, the IP destination address of the IP header, the TCP source address of the TCP header, and the TCP destination address of the TCP header together uniquely define a single connection context (TCB) with which the packet is associated. Processor <b>780</b> examines these addresses of the TCP and IP headers and determines the connection context of the packet. Processor <b>780</b> then checks a list of connection contexts that are under the control of INIC <b>22</b> and determines whether the packet is associated with a connection context (TCB) under the control of INIC <b>22</b>.

0150If the connection context is not in the list, then the “fast-path candidate” packet is determined not to be a “fast-path packet.” In such a case, the entire packet (headers and data) is transferred to a buffer in host <b>20</b> for “slow-path” processing by the protocol stack of host <b>20</b>.

0151If, on the other hand, the connection context is in the list, then software executed by processor <b>780</b> including software state machines <b>2231</b> and <b>2232</b> checks for one of numerous exception conditions and determines whether the packet is a “fast-path packet” or is not a “fast-path packet”. These exception conditions include: 1) IP fragmentation is detected; 2) an IP option is detected; 3) an unexpected TCP flag (urgent bit set, reset bit set, SYN bit set or FIN bit set) is detected; 4) the ACK field in the TCP header is before the TCP window, or the ACK field in the TCP header is after the TCP window, or the ACK field in the TCP header shrinks the TCP window; 5) the ACK field in the TCP header is a duplicate ACK and the ACK field exceeds the duplicate ACK count (the duplicate ACK count is a user settable value); and 6) the sequence number of the TCP header is out of order (packet is received out of sequence). If the software executed by processor <b>780</b> detects one of these exception conditions, then processor <b>780</b> determines that the “fast-path candidate” is not a “fast-path packet.” In such a case, the connection context for the packet is “flushed” (the connection context is passed back to the host) so that the connection context is no longer present in the list of connection contexts under control of INIC <b>22</b>. The entire packet (headers and data) is transferred to a buffer in host <b>20</b> for “slow-path” transport layer and network layer processing by the protocol stack of host <b>20</b>.

0152If, on the other hand, processor <b>780</b> finds no such exception condition, then the “fast-path candidate” packet is determined to be an actual “fast-path packet”. The receive state machine <b>2232</b> then processes of the packet through TCP. The data portion of the packet in buffer <b>2114</b> is then transferred by another DMA controller (not shown in <figref idref="DRAWINGS">FIG. 21</figref>) from buffer <b>2114</b> to a host-allocated file cache in storage <b>35</b> of host <b>20</b>. In one embodiment, host <b>20</b> does no analysis of the TCP and IP headers of a “fast-path packet”. All analysis of the TCP and IP headers of a “fast-path packet” is done on INIC card <b>20</b>.

0153<figref idref="DRAWINGS">FIG. 26</figref> is a diagram illustrating the transfer of data of “fast-path packets” (packets of a 64k-byte session layer message <b>2300</b>) from INIC <b>22</b> to host <b>20</b>. The portion of the diagram to the left of the dashed line <b>2301</b> represents INIC <b>22</b>, whereas the portion of the diagram to the right of the dashed line <b>2301</b> represents host <b>20</b>. The 64 k-byte session layer message <b>2300</b> includes approximately forty-five packets, four of which (<b>2302</b>, <b>2303</b>, <b>2304</b> and <b>2305</b>) are labeled on <figref idref="DRAWINGS">FIG. 24</figref>. The first packet <b>2302</b> includes a portion <b>2306</b> containing transport and network layer headers (for example, TCP and IP headers), a portion <b>2307</b> containing a session layer header, and a portion <b>2308</b> containing data. In a first step, portion <b>2307</b>, the first few bytes of data from portion <b>2308</b>, and the connection context identifier <b>2310</b> of the packet <b>2300</b> are transferred from INIC <b>22</b> to a 256-byte buffer <b>2309</b> in host <b>20</b>. In a second step, host <b>20</b> examines this information and returns to INIC <b>22</b> a destination (for example, the location of a file cache <b>2311</b> in storage <b>35</b>) for the data. Host <b>20</b> also copies the first few bytes of the data from buffer <b>2309</b> to the beginning of a first part <b>2312</b> of file cache <b>2311</b>. In a third step, INIC <b>22</b> transfers the remainder of the data from portion <b>2308</b> to host <b>20</b> such that the remainder of the data is stored in the remainder of first part <b>2312</b> of file cache <b>2311</b>. No network, transport, or session layer headers are stored in first part <b>2312</b> of file cache <b>2311</b>. Next, the data portion <b>2313</b> of the second packet <b>2303</b> is transferred to host <b>20</b> such that the data portion <b>2313</b> of the second packet <b>2303</b> is stored in a second part <b>2314</b> of file cache <b>2311</b>. The transport layer and network layer header portion <b>2315</b> of second packet <b>2303</b> is not transferred to host <b>20</b>. There is no network, transport, or session layer header stored in file cache <b>2311</b> between the data portion of first packet <b>2302</b> and the data portion of second packet <b>2303</b>. Similarly, the data portion <b>2316</b> of the next packet <b>2304</b> of the session layer message is transferred to file cache <b>2311</b> so that there is no network, transport, or session layer headers between the data portion of the second packet <b>2303</b> and the data portion of the third packet <b>2304</b> in file cache <b>2311</b>. In this way, only the data portions of the packets of the session layer message are placed in the file cache <b>2311</b>. The data from the session layer message <b>2300</b> is present in file cache <b>2311</b> as a block such that this block contains no network, transport, or session layer headers.

0154In the case of a shorter, single-packet session layer message, portions <b>2307</b> and <b>2308</b> of the session layer message are transferred to 256-byte buffer <b>2309</b> of host <b>20</b> along with the connection context identifier <b>2310</b> as in the case of the longer session layer message described above. In the case of a single-packet session layer message, however, the transfer is completed at this point. Host <b>20</b> does not return a destination to INIC <b>22</b> and INIC <b>22</b> does not transfer subsequent data to such a destination.

0155All told, the above-described devices and systems for processing of data communication provide dramatic reductions in the time and host resources required for processing large, connection-based messages. Protocol processing speed and efficiency is tremendously accelerated by an intelligent network interface card (INIC) containing specially designed protocol processing hardware, as compared with a general purpose CPU running conventional protocol software, and interrupts to the host CPU are also substantially reduced. These advantages are magnified for network storage applications, in which case data from file transfers may also avoid both the host memory bus and host I/O bus, with control of the file transfers maintained by the host.