Elevated source drain disposable spacer CMOS

CROSS-REFERENCES TO RELATED APPLICATIONS

0001This application is a divisional application of U.S. application Ser. No. 10/172,649, filed Jun. 14, 2002, now U.S. Pat. No. 6,777,298, the priority of which is hereby claimed.

0002This application is related to U.S. patent application Ser. No. 09/736,877, titled: SACRIFICIAL POLYSILICON SIDEWALL PROCESS AND RAPID THERMAL SPIKE ANNEALING FOR ADVANCE CMOS FABRICATION, filed Dec. 14, 2000, hereby incorporated by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

0003Not Applicable

BACKGROUND OF THE INVENTION

00041. Field of the Invention

0005The present invention relates to a method of making CMOS devices, and more particularly, to one with an elevated source and drain and optionally having a halo region.

00062. Description of the Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98

0007As CMOS technology becomes smaller, e.g., less than 50 nm gate length, it becomes more and more difficult to improve the short channel device performance and at the same time maintain acceptable values for off-state leakage current.

0008One technique for trying to achieve this is the halo technique wherein extra dopant implant regions are next to the sources and drain extension regions. For this to work the junctions must be abrupt, see “CMOS Devices below 0.1 nm: How High Will Performance Go?”, by Y. Taur, et al., pp. 1–4. In particular, for sub 50 nm devices, not only the extension regions near the channel must be abrupt, i.e., less than 4 nm/decade, but the halo profile in proximity to the extension junction must be abrupt, i.e., less than 20 nm/decade.

0009Most of the prior art for the halo formation used a general approach wherein halo dopants are implanted at an angle ranging from 0° to 70° into the channel region. This prior art varied either the dose, halo dopants, or angle of halo implants for improving the device performance. The article “Halo Doping Effects in Submicron DI-LDD Device Design” by Christopher Codella et al., pp. 230–233, describes the optimum halo doses for improving the threshold voltage and the punch-through device characteristics. Punch-through stoppers was also discussed in the U.S. Pat. No. 5,320,974 by Atsushi Hori et al. which is similar to the conventional halo arrangements. The article “A 0.1 nm IHLATI (Indium Halo by Large Angle Tilt Implant) MOSFET for 1.0V Low Power Application” by Young Jin Choi et al. described the use of an indium halo and a large angle tilt for indium halo implants for improving the short channel characteristics. Other articles are “High Carrier velocity and Reliability of Quarter-Micron SPI (Self-Aligned Pocket Implantation) MOSEFETs” by A. Hori et al. and “A 0.1-μm CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS)” by T. Hori.

0010None of the prior art focused attention on improving the abruptness of the halo dopant profiles in the area next to the channel. In these prior art situations, the halo dopants would have suffered enhanced transient diffusion and/or deactivation during contact and extension junction formation, and high thermal budget deep source/dran rapid thermal anneal (RTA) (typically 1000° C. for 5 seconds). Consequently, these much degraded halos severely compromised their usefulness for improving the short channel device characteristics, and this is especially the case for device channel width below 50 nm. Thus all the prior art approaches provide no means to minimize transient enhanced diffusion and/or deactivation of the halo dopants and hence cannot be used to create the abrupt super-halo (<20 nm/decade) in the region next to the channel area.

0011It is therefore desirable to have a process for making abrupt shallow PN junctions and haloes which does not cause dopant diffusion or deactivation.

BRIEF SUMMARY OF THE INVENTION

0012A method comprises forming source and drain regions; and thereafter forming source and drain extension regions.

0013A method comprises forming elevated and deep source and drain regions; forming source and drain extension regions; and thereafter forming source and drain contact regions at a temperature up to about 600° C. and an annealing time up to about one minute.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

0014<figref idref="DRAWINGS">FIGS. 1–6</figref> show a process in accordance with first embodiment of the invention;

0015<figref idref="DRAWINGS">FIGS. 7(</figref><i>a</i>) and <b>7</b>(<i>b</i>) are graphs of etch rates;

0016<figref idref="DRAWINGS">FIGS. 8(</figref><i>a</i>) and <b>8</b>(<i>b</i>) are graphs of resistance verses RTA times;

0017<figref idref="DRAWINGS">FIGS. 9–13</figref> show a second embodiment of the invention;

0018<figref idref="DRAWINGS">FIGS. 14–16</figref> show a third embodiment of the invention;

0019<figref idref="DRAWINGS">FIGS. 17 and 18</figref> show a fourth embodiment of the invention;

0020<figref idref="DRAWINGS">FIGS. 19–21</figref> show a fifth embodiment of the invention;

0021<figref idref="DRAWINGS">FIGS. 22–24</figref> show a sixth embodiment;

0022<figref idref="DRAWINGS">FIGS. 25–27</figref> show a seventh embodiment;

0023<figref idref="DRAWINGS">FIGS. 28–31</figref> show an eighth embodiment;

0024<figref idref="DRAWINGS">FIGS. 32</figref> shows a ninth embodiment;

0025<figref idref="DRAWINGS">FIGS. 33–36</figref> show a tenth embodiment; and

0026<figref idref="DRAWINGS">FIGS. 37–39</figref> show an eleventh embodiment.

DETAILED DESCRIPTION OF THE INVENTION

0027As shown in <figref idref="DRAWINGS">FIG. 1</figref>, silicon oxide with a thickness of between about 500 to 1000 nm as an insulating film for separating elements is formed in an element separation shallow trench isolation (STI) regions <b>10</b><i>a </i>and <b>10</b><i>b </i>of a P-type single crystal silicon semiconductor substrate <b>12</b>. Silicon oxide film with a thickness of between about 1 to 3 nm as a gate insulating film is formed on an active region of the substrate <b>10</b>. Then it is etched using known techniques to form the gate insulating layer <b>14</b>. Then a gate electrode <b>16</b> with a thickness of between about 100 to 150 nm is formed by etching a deposited polycrystalline silicon film in ordinary photolithography and etching processes. A reoxidation is then done to form layer <b>18</b>. Upon gate <b>16</b> is deposited the thin insulator first layer <b>20</b>, preferably silicon nitride, which can be produced by chemical vapor deposition, sputtering, or related techniques. The layer <b>20</b> has a thickness of between about 5 nm to 50 nm, preferably between about 10–30 nm. Upon the layer <b>20</b> is deposited a second layer of material, such as SiO_x, a-Si, or polysilicon. In particular, this layer has a thickness of about between about 50 to 150 nm. This second layer is then defined by reactive ion etching (RIE) using a highly selective etch, e.g., p-Si etches at a rate about 200 times faster than Si₃N₄, thereby resulting in sidewalls <b>22</b><i>a </i>and <b>22</b><i>b </i>(<figref idref="DRAWINGS">FIG. 2</figref>) without damaging layer <b>20</b>. During these etching steps, layer <b>20</b> acts as an etch stop layer.

0028After spacer formation, ion implantation is performed to introduce dopants into substrate <b>12</b> forming regions <b>24</b><i>a </i>and <b>24</b><i>b</i>, (<figref idref="DRAWINGS">FIG. 3</figref>), which are spaced away from the edge of the gate <b>16</b> by a distance defined by the width of spacers <b>22</b> and layer <b>20</b>. In one particular method, arsenic (As) ions are implanted into the substrate <b>12</b> at a dose of between about 3 to 10×10¹⁵/cm²at about 50 KeV using the gate electrode <b>16</b> and the side wall spacers <b>22</b> as a mask, thereby forming an N⁺-type deep source <b>24</b><i>a </i>and drain deep <b>24</b><i>b </i>regions. During this step, gate <b>16</b> is also ion implanted to make it a good conductor. For P⁺ source/drain formation, B ions may be implanted at about 10 KeV with a dose of about 3 to 10×10¹⁵/cm².

0029After formation of doped source/drain contact regions <b>24</b>, the sidewall spacers <b>22</b> are selectively removed by well known methods such as reactive ion etching, or wet methods, the later preferably using a solution of KOH in the case of a polysilicon spacer, or HF in the case of an oxide spacer. The resulting structure, as shown in <figref idref="DRAWINGS">FIG. 4</figref>, contains implanted liner layer areas <b>20</b><i>a </i>as well as unimplanted liner layer areas <b>20</b><i>b</i>, which remain substantially unimplanted because of absorption of ions in the spacers <b>22</b> during the implantation step.

0030The next step comprises selective removal of the implanted liner areas <b>20</b><i>a</i>, leaving the unimplanted liner <b>20</b><i>b </i>intact. This is preferably accomplished by using hot phosphoric acid (H₃PO₄) at about 160° C. for between about 1 to 5 minutes, in the case where the liner <b>20</b> is silicon nitride. As <figref idref="DRAWINGS">FIG. 7(</figref><i>a</i>) shows, the etch rate <b>702</b> of the implanted and unannealed nitride is much greater than the etch rate <b>704</b> for unimplanted nitride for both N-type and P-type dopants, while the etch rate <b>706</b> for implanted and annealled nitride is about the same as the etch rate <b>704</b> for unimplanted nitride. <figref idref="DRAWINGS">FIG. 7(</figref><i>b</i>) shows that the nitride etch rate <b>708</b> for rapid thermal chemical vapor deposition (RTCVD) is about the same as the etch rate <b>710</b> for plasma enhanced chemical vapor deposition (PECVD). Thus, either RTCVD or PECVD can be used as a suitable layer in which the implantation causes a large increase in etch rate. Hence, removal of 200 Å layer <b>20</b><i>a </i>of N^→ or P⁺ implanted nitride at 160° C., would only remove about 35 Å or so Å, respectively, of the unimplanted layer <b>20</b><i>b</i>. A similar procedure could be performed using HF to selectively remove an implanted oxide layer with respect to an unimplanted oxide liner.

0031After selective removal of areas <b>20</b><i>a</i>, then the structure may be annealed between about 1000° C. and 1100° C., preferably about 1000° C., for between about 1 to 10 seconds, preferably about 5 seconds, to activate the source/drain <b>24</b> and gate <b>16</b> regions.

0032Any residual thin layer, such as less than 50 Å of oxide layers <b>14</b> and <b>18</b> is removed from on top of regions <b>16</b> and <b>24</b> by etching in HF. Subsequently, as shown in <figref idref="DRAWINGS">FIG. 5</figref>, silicide contacts <b>32</b><i>a</i>, <b>32</b><i>b</i>, and <b>32</b><i>c </i>are formed on the gate <b>16</b> (in the case of polysilicon gate) and source and drain regions <b>24</b> by well known self-aligned processes, such as salicide or direct selective CVD. Both processes are selective such that no silicide or metal remains on liner <b>20</b><i>b</i>, which is subsequently removed by wet etching using phosphoric acid in the case of nitride. Final steps involve ion implantation of shallow source/drain extension regions <b>26</b><i>a </i>and <b>26</b><i>b </i>(<figref idref="DRAWINGS">FIG. 6</figref>), with or without halo regions <b>28</b><i>a </i>and <b>28</b><i>b</i>, followed by high temperature annealing to activate the extension <b>26</b> and halo regions <b>28</b>, if present.

0033In particular, arsenic (As) ions are implanted at a dose of 1 to 4×10¹⁵cm⁻²at an energy of between about 2 to 10 KeV using the gate electrode <b>16</b> as a mask thereby forming an N⁺-type source extension region <b>26</b><i>a </i>and an N⁺-type drain extension region <b>26</b><i>b</i>. Thereafter an optional annealing step of between about 1000° C. and 1050° C., preferably about 1000° C., for about 0 to 5 seconds, preferably about 1 second, is done in order to activate extension regions <b>26</b>.

0034Optionally, boron (B) is then implanted at an energy of between about 3 to 10 KeV at a tilt angle between about 10 to 30 degrees with respect to a normal line of a main surface of substrate <b>12</b> and with four rotation around the normal axis and with a total areal dosage of between about 5×10¹³/cm²to 5×10¹⁴/cm²to form optional halo regions <b>28</b><i>a </i>and <b>28</b><i>b</i>. The condition of the ion implantation for forming the P⁺ type halo regions <b>28</b> may be adjusted depending upon various factors such as an impurity concentration of the substrate <b>12</b>, a desired value of the inversion threshold voltage, a minimum gate length and a drain structure. A dosage and a tilt angle of the ion implantation can be selected from a wide range. Boron fluoride ions (BF₂⁺) and indium (In⁺) ions are appropriate besides boron ions. Further the shape of halo regions <b>28</b> can be other than that shown as known in the art. For P⁺ extension regions, BF₂⁺ ions may be implanted at 1 to 10 KeV at an anneal dosage of between about 5×10¹⁴/cm²to 3×10¹⁵/cm². Thereafter, As is optionally implanted to an energy of about 3 to 30 KeV at a tilt angle of between about 10° to 30° to form N⁺-type halo regions.

0035Thereafter an optional spike annealing, e.g., a ramp up rate of greater than about 100° C./s, a hold time of about zero seconds at a target temperature between about 800° to 1050° C., and a ramp down rate greater than about 50° C./s, is performed thus activating the dopants in the haloes <b>28</b> and, if said optional annealing steps were not done, also activate regions <b>24</b>, <b>26</b>, and gate <b>16</b>. However, other types of annealing can be used. Further, separate annealing steps can be used for extensions <b>26</b> and haloes <b>28</b>.

0036Spike annealing can be done by high powered tungsten (w) lamps, arc lamps, or excimer laser operating in the non-melting mode, e.g. less than 750 mJ/cm². Spike annealing has two advantages. One is that the wafer can get up to the high target temperature quickly so that the defect annealing with a higher activation energy (−5 ev) can be carried out with less time spent for undesirable halo dopant annealing with less activation energy (&lt;4 eV). The second advantage of the spike anneal is the obvious advantage of much reduced thermal cycle due to the rapid thermal anneal cycle. As a result, the halo dopant motion during rapid thermal annealing is much reduced.

0037Conventional silicide of thickness less than 40 nm (11 nm Co thickness since the silicide thickness is 3.6 times the Co thickness) as shown in <figref idref="DRAWINGS">FIG. 8(</figref><i>a</i>) is not stable, i.e., its resistivity increases with RTA hold time. Hence, if conventional silicide is used, it must be thicker than 40 nm to be stable during the extension anneal, which occurs subsequent to silicide formation. In order to form such a thick silicide, thick source and drain regions <b>24</b> and <b>26</b> must be used since they are partially consumed in silicide formation, or otherwise they will have an undesirably high resistance. But, if regions <b>24</b> and <b>26</b> are thick, then larger sidewall spacers <b>22</b> are needed, thereby resulting in an undesirably larger device. The current embodiment uses a high temperature-stable conductor, e.g. a silicide, which may comprise a ternary Si alloy, which is stable during high temperature annealing, such that the silicide layer <b>32</b> remains intact and still highly conductive after the final annealing steps are performed. As shown in <figref idref="DRAWINGS">FIG. 8(</figref><i>b</i>), a known 5% Re alloy in Co as disclosed in U.S. patent application Ser. No. 09/519,898, filed Mar. 6, 2000, hereby incorporated by reference, is effective in accomplishing this. A key device advantage of the process and structure described in <figref idref="DRAWINGS">FIGS. 1 to 6</figref> is that the silicide processing takes place before regions <b>24</b>, <b>26</b>, and, if present, <b>28</b> are formed, so that no high temperature steps which could degrade regions <b>24</b>, <b>26</b> and <b>28</b> take place subsequent to formation of the latter.

0038In a second embodiment of the invention, the process is the same as in the first embodiment up to <figref idref="DRAWINGS">FIG. 4</figref>. Thereafter, regions <b>20</b><i>a </i>are selectively removed as shown in <figref idref="DRAWINGS">FIG. 9</figref> Regions <b>33</b><i>a</i>, <b>33</b><i>b</i>, and <b>33</b><i>c </i>comprising a selective silicon (or SiGe), preferably having a thickness of between about 50–1000 Å, are then formed on the source and drain regions <b>24</b> and on the gate <b>16</b>, instead of silicide as describe in the first embodiment (<figref idref="DRAWINGS">FIG. 10</figref>). This is accomplished by well known CVD techniques at temperatures ranging from between about 550° C.–1000° C. preferably between about 700 and 900° C. An advantage of the current invention is that formation of regions <b>33</b>, which often takes place at temperatures in excess of 900° C., occurs before formation of regions <b>24</b>, <b>26</b>, and <b>28</b> so that these regions <b>24</b>, <b>26</b> and <b>28</b> are not degraded by high temperature processing after initial formation. Subsequent to selective silicon deposition to form an elevated source and drain structure, a shallow implant is done in regions <b>33</b> (<figref idref="DRAWINGS">FIG. 11</figref>). Then silicide formation takes place as in the first embodiment (<figref idref="DRAWINGS">FIG. 12</figref>), i.e., forming silicide within regions <b>33</b> and possibly extending into region <b>24</b>. Then follows formation of regions <b>26</b><i>a </i>and <b>26</b><i>b </i>after removal of spacer <b>20</b><i>b </i>(<figref idref="DRAWINGS">FIG. 13</figref>). The advantage of the process of the second embodiment is that an elevated source/drain device is formed with all high temperature processes (generally defined as between about 600–1000° C. for silicide and selective silicon) taking place before regions <b>26</b> formation, ensuring maximum abruptness and activation of these regions. Another advantage of the present structure is that it provides a source for extra-thick silicide (in this embodiment the preferred silicide thickness is between about 40–60 nm) without penetration far into the regions <b>24</b>, thus providing a more stable silicide layer for subsequent high temperature annealing.

0039In a third embodiment, the process starts as in the second embodiment up to <figref idref="DRAWINGS">FIG. 10</figref>. The next step is removal of layer <b>20</b><i>b </i>(<figref idref="DRAWINGS">FIG. 14</figref>). Thereafter regions <b>26</b> and simultaneously contacts <b>33</b> are implanted (<figref idref="DRAWINGS">FIG. 15</figref>). Annealing to activate the dopants is done, and then permanent spacers <b>22</b><i>a </i>and <b>22</b><i>b </i>are formed using a typical material such as oxide or nitride, and subsequent silicide formation by known methods (<figref idref="DRAWINGS">FIG. 16</figref>). The advantage of this embodiment is that it does not require the silicide to withstand high temperature SDE/halo dopant activation anneals, but a preferred silicide material for this embodiment is NiSi, which forms at between about 400° C. to 600° C., for between 10 to 60 seconds, and does not deleteriously affect the SDE/Halo even though it occurs after halo formation.

0040A fourth embodiment follows the sequence of the second embodiment up to all of the steps of <figref idref="DRAWINGS">FIG. 12</figref>. The next step is selective removal of the horizontal portion of layer <b>20</b><i>b</i>, which is accomplished preferably by reactive ion etching, leaving the vertical portion of the layer <b>20</b> in place as sidewalls <b>20</b><i>c </i>(<figref idref="DRAWINGS">FIG. 17</figref>). Subsequent ion implantation of regions <b>24</b> and <b>26</b> is performed and junctions are activated (<figref idref="DRAWINGS">FIG. 18</figref>). The advantage of this process is that it allows the dopants to be implanted at some distance laterally away from the gate edge, defined by the width of the nitride spacer <b>20</b><i>c</i>. This would be useful for fast-diffusing dopants such as B, where formation might result in too much overlap of regions <b>24</b> and <b>26</b> under the gate <b>16</b> after annealing, resulting in higher overlap capacitance.

0041In a fifth embodiment the previous steps are followed up to <figref idref="DRAWINGS">FIG. 10</figref>. Then the horizontal portion of nitride layer <b>20</b><i>b </i>is removed (<figref idref="DRAWINGS">FIG. 19</figref>) resulting in sidewalls <b>20</b><i>c</i>, followed by SDE/halo formation of region <b>26</b> (<figref idref="DRAWINGS">FIG. 20</figref>), permanent spacer <b>22</b> having portions <b>22</b><i>a </i>and <b>22</b><i>b</i>, (<figref idref="DRAWINGS">FIG. 21</figref>) and low temperature silicide contacts <b>32</b>. This process differs from the fourth embodiment only in the use of a low temperature silicide at the end, and removes the need of ensuring high temperature silicide stability, and is preferably accomplished using low temperature silicide such as NiSi or PtSi.

0042In a sixth embodiment, the previous steps are followed up to <figref idref="DRAWINGS">FIG. 20</figref>, after which a second selective layer <b>34</b>, having sections <b>34</b><i>a</i>, <b>34</b><i>b</i>, and <b>34</b><i>c</i>, preferably Si or SiGe, of preferably between about 10–50 μm thickness, is grown, resulting in a stepped elevated source drain structure. The growth is preferably done using low temperature Si or SiGe, which can be done at between about 500–650° C., causing minimal impact on the regions <b>24</b> and <b>26</b> (<figref idref="DRAWINGS">FIG. 22</figref>). The second silicon layer <b>34</b> can subsequently be implanted (<figref idref="DRAWINGS">FIG. 23</figref>), followed by activation annealing forming regions <b>26</b> in the elevated region near the gate <b>16</b>, and ending with the formation of permanent spacer <b>22</b> with portions <b>22</b><i>a </i>and <b>22</b><i>b </i>(<figref idref="DRAWINGS">FIG. 24</figref>) and low temperature silicide. This technique produces a structure which has low SDE resistance because of the elevation near the gate <b>16</b>, but decouples the amount of silicon used to form the silicide contacts <b>32</b> with the amount of silicon near the gate <b>16</b>, and thereby allows the overlap capacitance to be less than in a non-stepped structure.

0043A seventh embodiment of the current invention involves following the preceding steps up to <figref idref="DRAWINGS">FIG. 19</figref>, but then depositing (<figref idref="DRAWINGS">FIG. 25</figref>), the second selective Si layer <b>34</b> having sections <b>34</b><i>a</i>, <b>34</b><i>b</i>, and <b>34</b><i>c </i>before implantation of regions <b>24</b> and <b>26</b>, using etch to remove remaining nitride layer <b>20</b> (<figref idref="DRAWINGS">FIG. 26</figref>) next to the gate <b>16</b>, and SDE formation, such that SDE ions can be located adjacent to the gate <b>16</b> edge with very low energy implant. This is followed by permanent sidewall spacer <b>22</b> having portions <b>22</b><i>a </i>and <b>22</b><i>b </i>formation (<figref idref="DRAWINGS">FIG. 27</figref>) and low temperature silicide contacts <b>32</b> formation, preferably using NiSi, PtSi, or related materials.

0044An eighth embodiment involves following the preceding steps up to <figref idref="DRAWINGS">FIG. 17</figref>, followed by selective deposition of silicon layer <b>35</b> (<figref idref="DRAWINGS">FIG. 28</figref>), which in addition to growing in the exposed Si area immediately adjacent to the gate <b>16</b>, also may grow on the already present silicide in the source and drain <b>26</b> and <b>24</b> and gate <b>16</b> areas, since selective Si processes are selective to nitride and oxide, but may typically grow on silicide. The subsequent structure may be then implanted and annealed (<figref idref="DRAWINGS">FIG. 29</figref>). Then the thin nitride layer <b>20</b> removed (<figref idref="DRAWINGS">FIG. 30</figref>), followed by implantation of regions <b>27</b> for formation closer to the gate <b>16</b> (<figref idref="DRAWINGS">FIG. 31</figref>). The silicide layer <b>32</b> is buried before SDE anneal and will be more thermally stable, while the structure resulting is ideal from an electrical design, with low SDE resistance, low overlap capacitance, and ability to form ultra shallow junctions immediately adjacent to the gate <b>16</b> with no subsequent high temperature processing. The buried silicide layer <b>32</b> can easily be contacted by usual lithography and etch steps which will selectively remove the silicon layer <b>35</b> and leave the silicide layer <b>32</b> intact.

0045A ninth embodiment involves the previous steps up to <figref idref="DRAWINGS">FIG. 29</figref>, followed by ion implantation to form regions <b>28</b>. In this embodiment, the vertical spacer <b>20</b><i>c </i>is retained in order to keep fast moving dopants from diffusing too far under gate <b>16</b> (<figref idref="DRAWINGS">FIG. 32</figref>).

0046In the tenth embodiment, the steps are the same up to <figref idref="DRAWINGS">FIG. 4</figref> followed by RIE to remove the horizontal portion of spacer <b>20</b><i>b </i>(<figref idref="DRAWINGS">FIG. 33</figref>). This is followed by selective Si growth (<figref idref="DRAWINGS">FIG. 34</figref>), implantation into region <b>33</b> and annealing (<figref idref="DRAWINGS">FIG. 35</figref>). Then permanent spacer <b>22</b> formation and low temperature silicide formation (<figref idref="DRAWINGS">FIG. 36</figref>) is done.

0047In the eleventh embodiment the steps are the same up to <figref idref="DRAWINGS">FIG. 35</figref>. Layer <b>20</b><i>b </i>is then selectively removed (<figref idref="DRAWINGS">FIG. 37</figref>), followed by implantation and annealing, which forms regions <b>27</b> near the edge of gate <b>16</b> (<figref idref="DRAWINGS">FIG. 38</figref>). This is followed by permanent spacer <b>22</b> and silicide formation (<figref idref="DRAWINGS">FIG. 39</figref>).

0048It will be appreciated that substrate <b>12</b> can also be of other group IV materials, e.g., C, Ge, SiGe alloy, Si-on-insulator (SOI), etc,; a group III–V material, e.g. GaAs, InP, AlGaAs, etc.; or a group II–VI material. Also for the P-type dopant B, In, Al and Ga can be used, while for the N-type dopant P, As, Sb can be used. Further, although most of the description is directed to N-channel devices, the present invention can be used to make P-channel devices by reversing conductivity types.

0049For the conductors, including gate <b>16</b>, W, Al, Cu, Ti, Ni, P-SiGe alloy, heavily doped p-Si or a-Si, and combinations thereof can be used.

0050Further, the present invention can also be used in any device with a PN junction, e.g., diodes, bipolar transistors, etc.

0051While the present invention has been particularly described with respect to preferred embodiments, it will be understood that the invention is not limited to these particular preferred embodiments, the process steps, the sequence, or the final structures depicted in the drawings. On the contrary, it is intended to cover all alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention defined by the appended claims. In addition, other methods and/or devices may be employed in the method and apparatus of the instant invention as claimed with similar results.