Idle power reduction for state machines

CROSS-REFERENCE TO RELATED APPLICATION

0001This is a continuation-in-part of “General Purpose State Machine,” U.S. patent application Ser. No. 10/056,326, filed Jan. 23, 2002.

BACKGROUND OF THE INVENTION

0002This invention relates to state machines, and in particular to reducing the power consumption of state machines which are implemented as a portion of an integrated circuit or in other formats.

0003A state machine, also known as a finite state machine, responds to events by moving from state to state according to a formal set of rules. These rules are typically customized for the particular problem to be solved. State machines can be used generally in any electronic system, for example, a general purpose computer system, a special purpose computer system, or a control system that control products such as home appliances or industrial products. The state machine typically includes three components: (1) a set of states, (2) a set of events, and (3) a mapping from each state or event to a corresponding action. This set of states requires that in any given time the machine be in a single state. The events are then actions which the machine recognizes. Typically, an event will represent an external input. The state machine, however, may also generate events internally which cause changes of state. Finally, the mapping from each state to a corresponding action means that the action may cause a transition to a different state, provide a particular output signal, or otherwise indicate transition to the successor state.

0004Computation by the state machine begins in the start state, but then the state machine will change to a new state caused by external signals provided to the state machine or an internal transition. There are many variants of state machines, for example, state machines can have actions or provide outputs which are based on transitions (Mealy machine) or based upon states (Moore machine). A state machine can be considered to be an abstract model of a system, for example, a physical, biological, mechanical, electronic, or software system.

0005A state machine can be used to model interaction between a system and its environment. Its state is a way of remembering what has occurred so far. A transition occurs when an event in the environment causes the system to change state. Given a sequence of inputs, a state machine will produce a sequence of outputs that is dependent upon the initial state, the transition function which maps each current state and input to a next state, and an output function that maps each current state to an output. In Moore machines the output is a function of only the current state, while in Mealy machines the output is a function of the current state and the input.

0006It has been common in integrated circuit technology since the 1980's for distributed state machines to be used rather than a central control engine. This has resulted primarily because of the availability of integrated circuit technology and increasing performance requirements. By distributing state machines across an integrated circuit with appropriate control points in appropriate locations, shorter electrical connections for critical paths results, improving performance.

0007In most state machines a control RAM or ROM allows programming the state machine. This memory typically loops in the same state waiting for an external signal to change or some internal condition to change to cause the state machine to transition to the next state. In many applications for state machines, because the speed of the integrated circuit is so fast in comparison to the external events triggering changes in state, a significant amount of time is spent in this idle loop. In this loop, usually the state machine keeps accessing the same memory location. This usually causes all of the bit lines to be precharged at the beginning of each clock cycle, and then the selected lines are discharged. In addition, other elements of the state machine may also need to be activated, further dissipating power. Because the output data remains the same, these actions dissipates unnecessary power.

0008What is needed is a state machine which can be operated in a manner so that when the input data has not changed, and therefore the state of the machine will not transition to a new state, power consumption is reduced.

BRIEF SUMMARY OF THE INVENTION

0009This need in the prior art is addressed by implementation of a general purpose state machine which has a power saving circuit and is readily useful for many different integrated circuit based systems. The state machine provided employs general purpose components such as flags, counters, and programmable logic, enabling it to be easily reused, even if maintained in hard form. In a preferred embodiment the state machine includes a programmable memory, operating in response to a first clock signal, which stores a plurality of words and supplies one of those words in response to an address signal. The state machine also includes a control circuit operating in response to a second clock signal. The control circuit receives first and second address signals from a word in the programmable memory, and receives signals from an external circuit. The signals from the external circuit cause the control circuit to select either the first address or the second address. Of course in simpler embodiments, the state machine may not have the capability of branching, and thus receive only one address. In these type state machines the choice will be whether to move to the new address or remain at the present address for another cycle.

0010A clock circuit, which in a preferred embodiment is connected to be controlled by an output signal on one of the lines from the control circuit, detects when the signal selecting one of the words in the programmable memory changes (or does not change). If the selection signal does not change, the clock circuit disables the first clock signal, thereby reducing power consumption. On the other hand, if the signal from the control circuit does change, the clock circuit enables the first clock to allow the state machine to operate normally.

0011Typically the memory is a programmable memory, for example a ROM, PROM, SRAM, DRAM, or other memory, which has a plurality of rows. Each row stores a word (sequence of bits), and a word in the programmable memory is supplied to the output terminals of the memory in response to an address signal selecting that word (row). Some bits from the output signal are used for control of the state machine, while other bits are provided to the external circuit.

0012The control circuit receives the output signal from the first multiplexer and also receives at least one sets of bits from the programmable memory, each set representing an address of another word in the memory. In response to the signals from the multiplexer, the control circuit provides a signal which selects one of the words in the programmable memory. The word selected corresponds to the address provided by some of the bits in the addressed word (or other signals indicative of a request that the state not change). Other bits from the selected word are then provided on various output lines to control the external circuit and control the state machine.

0013In general, the sizes of the multiplexers, sizes of the programmable memory, and other associated circuitry will be optimized for the particular application within which the state machine is employed. The state machine itself may be maintained in a “soft” or “hard” form. Examples of soft form are RTL and some HDL formats in which no physical information about the layout is maintained. In contrast, in hard form the state machine is maintained as a collection of polygons representing the shapes of regions for an integrated circuit. In soft form the particular state machine may be optimized for area, speed, power consumption, or other desired variables. In hard form the layout can be manually optimized for reuse in the same or similar technologies.

0014The invention provides substantial power saving in comparison to prior art state machines. Because the design is generally optimized to that required by a specific application, it is faster than previous state machines. It is also more flexible because it allows any number of external inputs, either by expanding the size of the first multiplexer, or supplying such additional inputs to programmable logic or other pre-state machine logic. The state machine also provides the ability to perform branch operations. It can change state without relying on hardwired logic. Further description of the advantages and structure of the state machine of this invention is found below.

BRIEF DESCRIPTION OF THE DRAWINGS

0015<figref idref="DRAWINGS">FIG. 1</figref> is a simplified block diagram of a general purpose state machine according to a preferred embodiment;

0016<figref idref="DRAWINGS">FIG. 2</figref> is a more detailed block diagram;

0017<figref idref="DRAWINGS">FIG. 3</figref> illustrates branch conditions and address selection by the system of <figref idref="DRAWINGS">FIG. 2</figref>;

0018<figref idref="DRAWINGS">FIG. 4</figref> illustrates details of the counter of <figref idref="DRAWINGS">FIG. 2</figref>;

0019<figref idref="DRAWINGS">FIG. 5</figref> is a diagram illustrating the programmable logic of <figref idref="DRAWINGS">FIG. 2</figref>;

0020<figref idref="DRAWINGS">FIG. 6</figref> illustrates details of the flags;

0021<figref idref="DRAWINGS">FIG. 7</figref> is a more detailed diagram of the power saving circuitry; and

0022<figref idref="DRAWINGS">FIG. 8</figref> is a diagram illustrating an alternate embodiment of <figref idref="DRAWINGS">FIG. 7</figref>.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0023<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of the general purpose state machine as implemented according to a preferred embodiment of this invention. As will be described below, the embodiment depicted enables a five-bit state machine, that is, one with thirty-two states. Of course, greater or lesser numbers of states may be implemented by making appropriate changes in the depicted components. On the other hand, because one of the advantages of the state machine described herein is its ability to function in many different environments, once the hardware layout is optimized for power consumption, speed, or other variable, use of less than all of the circuitry depicted may be advantageous, in contrast generating a new layout for the integrated circuit.

0024The basic components depicted in <figref idref="DRAWINGS">FIG. 1</figref> will be described generally, as to their function, and then more details provided as to the implementation. Particularly important components for an understanding of <figref idref="DRAWINGS">FIG. 1</figref> are memory <b>10</b>, a first multiplexer <b>20</b> and a control circuit <b>30</b>. These will be explained first, followed by a discussion of the remaining components depicted.

0025Memory <b>10</b> is a programmable memory which may be volatile or nonvolatile. In the depicted embodiment, memory <b>10</b> is a ROM programmable by a mask during the semiconductor fabrication process used to manufacture the circuit shown in <figref idref="DRAWINGS">FIG. 1</figref>. In one embodiment the ROM consists of 32 rows (words) of information, with each row having 48 columns (bits), to thereby provide storage for 32 48-bit words. Each row in the memory corresponds to a state in the state machine. The particular state selected, that is, the particular word addressed, is controlled by control and multiplexer circuit <b>30</b> in response to signals received on line <b>31</b>. The signal on line <b>31</b> will cause control circuit <b>30</b> to select one of the two inputs <b>32</b> or <b>33</b> and provide the information from the selected input to the register/decoder <b>40</b> as an address over line <b>34</b>. (As described below, input terminals <b>33</b> may provide more than one address.) In the example depicted in <figref idref="DRAWINGS">FIG. 1</figref>, selection of input <b>32</b> results in one address being provided via register/decoder <b>40</b> to ROM <b>10</b>, while selection of line <b>33</b> results in a different address being provided via control circuit <b>30</b>, decoder <b>40</b>, and line <b>35</b> to ROM <b>10</b>. The received address is provided to ROM <b>10</b> via register/decoder <b>40</b>. While the discussion above used the term “row” to describe the “state” of the state machine, the memory may be organized in any desired manner so portions of the memory other than rows may represent the “state” of the state machine.

0026In response to the address, the register/decoder selects one of the rows of ROM <b>10</b>. For the example depicted, assume control circuit <b>30</b> placed the address “row <b>25</b>” on input line <b>34</b>, then register/decoder <b>40</b> will cause the next address provided to ROM <b>10</b> to be row (word) <b>25</b>. In other words, the input signal on line <b>31</b> to control circuit <b>30</b> will cause the ROM <b>10</b> to change states from the state represented by the previously addressed row to the state represented by the word stored in row <b>25</b>. This change in state will result in new output data being provided on line <b>12</b>, as well as on lines <b>33</b>, <b>36</b> and <b>37</b>. Typically, the output signals will be provided to drivers <b>15</b> for supply either in pulse form or latched form to various external circuitry coupled to the drivers <b>15</b> by lines <b>18</b>.

0027As mentioned, the output signal on line <b>34</b> from control circuit <b>30</b> provides the next address for the state machine. Control circuit <b>30</b> itself is controlled by multiplexer <b>20</b>, and by counters, flip-flops and programmable logic circuitry <b>50</b>. The mux and control circuit <b>20</b> receives external input signals <b>38</b>, signals from circuitry <b>50</b>, and internal control signals from memory <b>10</b> over lines <b>36</b>. Similarly, circuitry <b>50</b> receives external input signals <b>39</b> and internal input signals from memory <b>10</b> over lines <b>37</b>. The combination of all of the external and internal input signals to mux <b>20</b> and circuitry <b>50</b> determine the selection signal on line <b>31</b>.

0028In some applications for the state machine depicted in <figref idref="DRAWINGS">FIG. 1</figref>, the external signals provided on lines <b>38</b> and <b>39</b> will not change frequently, or at least not change as frequently as the clock signals being provided to control the overall system. For example, if the state machine depicted is being used for control of an appliance or a machine, there will be a considerable delay, from the perspective of the clock signals provided to the state machine, between changes on the external input lines <b>38</b> and <b>39</b>. In this situation, the state of the state machine will remain unchanged from one clock cycle to the next. Although the state itself does not change, the state machine will be consuming considerable electrical power.

0029The power consumption occurs because the memory <b>10</b>, which allows programming the state machine, will loop in the same state waiting for an external signal to change or some internal condition to change to cause the state machine to transition to the next state. In this loop, the state machine will repeatedly access the same memory location. This usually causes all of the bit lines to be precharged at the beginning of each clock cycle, and then the selected lines are discharged. In addition, the word lines and the decoders must be activated, also dissipating power.

0030<figref idref="DRAWINGS">FIG. 2</figref> is a more detailed block diagram illustrating one implementation of the conceptual level diagram of <figref idref="DRAWINGS">FIG. 1</figref>, and illustrating the power reduction circuitry. Components in <figref idref="DRAWINGS">FIG. 2</figref> have been given numerical designations to reflect corresponding components in <figref idref="DRAWINGS">FIG. 1</figref>. In <figref idref="DRAWINGS">FIG. 2</figref>, the register/decoder <b>40</b> is shown in more detail to consist of register <b>41</b> and decoder <b>42</b> coupled to each other by interconnection <b>43</b>. As shown by the diagram, interconnection <b>43</b> is a five-bit signal provided from register <b>41</b> to decoder <b>42</b>. The corresponding “width” of other interconnections shown in <figref idref="DRAWINGS">FIG. 2</figref> is designated in the same manner throughout the diagram. Of course, more or fewer bits may be provided among the various interconnections, and serial connections can be employed in place of the parallel connections depicted.

0031Decoder <b>42</b> is coupled to ROM <b>10</b> with 32 address lines designated 0 to 31 in the diagram. The five-bit address signal supplied on line <b>43</b> to decoder <b>42</b> results in the selection of one of lines 0 to 31. The 48 bits of the selected word are then applied to the 48 output lines from the ROM <b>10</b>. These 48 output lines include a five-bit signal branch a “bra” on lines <b>51</b> and a five-bit signal branch b “brb” on lines <b>52</b>. Signal branch c “brc” indicative of remaining in the previous state is also supplied to mux <b>30</b> on line <b>32</b>. As explained in conjunction with <figref idref="DRAWINGS">FIG. 1</figref>, the three control wires <b>31</b> will cause multiplexer <b>30</b> to select among input signals <b>32</b>, <b>51</b> and <b>52</b>. ROM <b>10</b> also provides a two-bit signal Y on lines <b>53</b> to control circuit <b>60</b>. As will be discussed this signal enables different branching operations. In addition, five-bit signals X and Z are provided on lines <b>54</b> and <b>55</b>, respectively, to partially control multiplexer A <b>70</b> and multiplexer B <b>80</b>. This control is discussed further below.

0032The particular manner in which control circuit <b>60</b> provides the output signals on line <b>31</b> to control mux <b>30</b> is discussed next. Muxes <b>70</b> and <b>80</b> are coupled to receive external input signals A and B directly and external input signals C applied to counters <b>90</b>, flags <b>100</b>, and programmable logic <b>110</b>. In addition, mux <b>70</b> receives the X input signals from ROM <b>10</b>, while mux <b>80</b> receives the Z input signals from ROM <b>10</b>. Thus, muxes <b>70</b> and <b>80</b> are controlled by “internal” signals from ROM <b>10</b>, to select desired ones of the external signals. Of course other, or additional, signals from other types of input logic such as filters, memories, converters, etc. can also be provided to muxes <b>70</b> and <b>80</b>.

0033The combination of external and internal input signals to mux <b>70</b> causes it to provide an output signal “a” on line <b>71</b>. Similarly, the combination of external and internal input signals to mux <b>80</b> cause it to provide an output signal “b” on line <b>72</b>. In a manner described further below, the combination of signals a and b on lines <b>71</b> and <b>72</b>, together with signal Y on line <b>53</b>, causes control circuit <b>60</b> to produce an appropriate output signal on lines <b>31</b>. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, lines <b>31</b> preferably consists of three lines. This output signal causes mux <b>30</b> to select among its various input signals <b>32</b>, <b>51</b>, and <b>52</b> and supply it over lines <b>34</b> to register <b>41</b>, one of these addresses. In a preferred embodiment, a signal on one of lines <b>31</b> selects input bra <b>51</b>, a signal on another of lines <b>31</b> selects input brb <b>52</b>, while a signal on the other of the three lines <b>31</b> selects input brc—indicating that the state of the state machine is to remain unchanged. This results in the selection of a particular word within ROM <b>10</b> on the next clock signal.

0034The particular manner in which mux <b>70</b> and <b>80</b> provide the output signals on lines <b>71</b> and <b>72</b> is discussed next. As depicted, each of muxes <b>70</b> and <b>80</b> is coupled to receive external signals which arrive on lines <b>45</b>, <b>46</b>, <b>47</b>, <b>44</b> (mux A only), and <b>48</b> (mux B only). In the example of <figref idref="DRAWINGS">FIG. 2</figref>, there are 16 lines designated by reference numerals <b>44</b> and <b>48</b>, two lines by reference numeral <b>45</b>, four lines designated by reference numeral <b>46</b>, and six lines designated by reference numeral <b>47</b>. Of course, it will be appreciated that more or fewer lines may be employed. In addition to receiving these external signals, muxes <b>70</b> and <b>80</b> also receive “internal” select signals over lines <b>54</b> and <b>55</b>. The internal select signals arriving at the muxes <b>70</b> and <b>80</b> over lines <b>54</b> and <b>55</b> are control signals supplied directly from ROM <b>10</b>.

0035The input signals on lines <b>45</b> originate from counters <b>90</b>. The initial count values and control information are provided over lines <b>91</b>. These are discussed in <figref idref="DRAWINGS">FIG. 4</figref>. The programmable logic provides signals on lines <b>47</b>, and is discussed in conjunction with <figref idref="DRAWINGS">FIG. 5</figref>. The input signals to muxes <b>70</b> and <b>80</b> arriving on lines <b>46</b> originate from flag circuits <b>100</b>. The flag circuits are discussed in <figref idref="DRAWINGS">FIG. 6</figref>. The result of all of the external input signals and the internal input signals causes control circuit <b>60</b> to provide an output signal on line <b>31</b> which selects one of the three addresses on lines <b>32</b>, <b>51</b> and <b>52</b> provided to mux <b>30</b>.

0036The idle power reduction circuitry in <figref idref="DRAWINGS">FIG. 2</figref> operates by detecting the state of the signal <b>31</b> supplied from control circuit <b>60</b> to mux <b>30</b>. As described, signal <b>31</b> is indicative of whether the next state of the state machine is to be state bra, brb, or brc. As shown by <figref idref="DRAWINGS">FIG. 2</figref>, state brc is an output signal from register <b>41</b> indicative that the state of the state machine is not to change in the next cycle. In other words, in the preferred embodiment, the state of the line <b>31</b> selecting brc is monitored. A more detailed explanation of the operation of the power reduction circuitry is provided below in conjunction with <figref idref="DRAWINGS">FIG. 7</figref>.

0037The flexibility of the general purpose state machine described herein can be better understood with reference to <figref idref="DRAWINGS">FIG. 3</figref>. <figref idref="DRAWINGS">FIG. 3</figref> illustrates the branch conditions implemented by the system illustrated in <figref idref="DRAWINGS">FIG. 2</figref>. In <figref idref="DRAWINGS">FIG. 3</figref> there are four different branch operations provided by the general purpose state machine, and the choice of the particular branch operation is determined by the Y0 and Y1 bits stored in ROM <b>10</b>. A branch unconditional operation as shown in the upper left portion of <figref idref="DRAWINGS">FIG. 3</figref>. If each of Y0 and Y1 are 0, an unconditional branch operation is performed to select address bra.

0038In the upper right portion of <figref idref="DRAWINGS">FIG. 3</figref>, a two-way conditional branch operation is illustrated. This operation occurs when Y0 is 0 and Y1 is 1. In this circumstance the a output of multiplexer <b>70</b> (<figref idref="DRAWINGS">FIG. 2</figref>) will cause control circuit <b>60</b> to supply a signal on line <b>31</b> to mux <b>30</b> which selects either branch a (line <b>51</b>), and therefore next address bra, or branch b (line <b>52</b>) and therefore address brb.

0039The lower left corner of <figref idref="DRAWINGS">FIG. 3</figref> illustrates a three-way condition branch operation in which one of address bra, address brb, or address brc (return to the same state) is selected. In this circumstance the output signal a on line <b>71</b> from mux <b>70</b> and the output signal b on line <b>72</b> from mux <b>80</b> are both used.

0040Finally, in the lower right portion of <figref idref="DRAWINGS">FIG. 3</figref> a wait until conditional branch is depicted. There, as shown, if Y0 and Y1 are each 1, the state machine shifts to address bra or address brc, depending upon the a signal on line <b>71</b>.

0041Thus, in summary, the state machine provides state control in the manner of enabling unconditional branches, conditional branches either two ways or three ways, and branches under control of the counters, flags or external inputs. The machine also enables the state machine to change states upon receipt of an external input.

0042The structure depicted in <figref idref="DRAWINGS">FIGS. 1 and 2</figref> enables a state machine with 32 states, with additional states being provided if a larger ROM is employed in place of the 32-word ROM <b>10</b> depicted. As discussed, the choice of states is determined by all of the external and internal inputs. In particular, the output of the state machine is determined as follows, where a and b are the signals on lines <b>71</b> and <b>72</b>, and Y₀Y₁are the signals on lines <b>53</b>:

0043<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="offset" colwidth="21pt" align="left" /><colspec colname="1" colwidth="21pt" align="center" /><colspec colname="2" colwidth="70pt" align="center" /><colspec colname="3" colwidth="35pt" align="center" /><colspec colname="4" colwidth="70pt" align="center" /><thead><row><entry /><entry namest="offset" nameend="4" align="center" rowsep="1" /></row><row><entry /><entry>Y₀Y₁</entry><entry>Select bra</entry><entry>Select brb</entry><entry>Select brc</entry></row><row><entry /><entry namest="offset" nameend="4" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>00</entry><entry>1</entry><entry>—</entry><entry>—</entry></row><row><entry /><entry>01</entry><entry>a</entry><entry>ā</entry><entry>—</entry></row><row><entry /><entry>10</entry><entry>āb</entry><entry>a{overscore (b)}</entry><entry>{overscore (ab)}+ ab</entry></row><row><entry /><entry>11</entry><entry>a</entry><entry>—</entry><entry>ā</entry></row><row><entry /><entry namest="offset" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0044Of course, other codes can be used in place of those described above.

0045Some states for the state machine can be selected in multiple ways. The equations below illustrate the different conditions that can be used to select a particular word. For example, as shown in the first equation, the select input on line <b>31</b> will choose the address bra in each of three conditions, that is, if Y0 and Y1 are 0, or if Y1 is 1 and input a is 1, or if Y0 is 1, Y1 is 0, input a is 0 and input b is 1. The remainder of the equations can be similarly understood. <br />select <i>bra={overscore (Y)}</i>₀<i>{overscore (Y)}</i>₁<i>+Y</i>₁<i>a+Y</i>₀<i>{overscore (Y)}</i>₁<i>āb</i><br />select <i>brb={overscore (Y)}</i>₀<i>Y</i>₁<i>ā+Y</i>₀<i>{overscore (Y)}</i>₁<i>a{overscore (b)}</i><br />select <i>brc=Y</i>_{0{overscore (Y)}}₁(<i>ā{overscore (b)}+ab)+</i><i>Y</i>₀<i>Y</i>₁<i>ā</i>

0046<figref idref="DRAWINGS">FIG. 4</figref> is a more detailed diagram of counter <b>90</b> shown in block form in <figref idref="DRAWINGS">FIG. 2</figref>. The combination of the circuitry shown in <figref idref="DRAWINGS">FIG. 4</figref> forms counters <b>90</b>. As shown in <figref idref="DRAWINGS">FIG. 4</figref>, a counter <b>120</b> is coupled to receive eight bits of data over lines <b>91</b>. This data includes three bits of control information provided to control circuit <b>122</b>. As shown by the lower right-hand corner of <figref idref="DRAWINGS">FIG. 4</figref>, the control information received on lines <b>91</b> to control circuit <b>122</b> will cause the eight bits of data provided to counter <b>120</b> to cause no change by the counters <b>120</b> (if the control bits are 000). If the control bits are 001, then counter <b>120</b> will be loaded with the bits received on lines <b>91</b>. A control circuit output of <b>010</b> will cause the counter <b>120</b> to begin decrementing, while a control signal of <b>011</b> will cause the counter to begin incrementing. The counter output is provided to a comparator <b>125</b> which compares its stored value of 0 with the data received from counter <b>120</b>. When counter <b>120</b> reaches a count of 0, comparator <b>125</b> will record the correct comparison and provide an output signal on line <b>45</b>. Counter <b>130</b> and its comparison circuit <b>135</b> operate in the same manner as counter <b>120</b> and its control circuit <b>125</b>.

0047<figref idref="DRAWINGS">FIG. 5</figref> illustrates an implementation of programmable logic <b>110</b> depicted in block diagram form in <figref idref="DRAWINGS">FIG. 2</figref>. As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the programmable logic preferably consists of a series of six multiplexers <b>140</b>, configured logically as two PLA circuits, one having four product term outputs and one having two product term outputs. Each of the two circuits receives four input signals. Each multiplexer has 16 input terminals, and each multiplexer receives a four-bit input signal from the external input c. The four-bit input signals selects a particular input from each multiplexer and supplies that as an output signal, one output signal being supplied from each mux <b>140</b> on a corresponding output line <b>143</b>. The programmability is achieved by connecting each of the input terminals of each multiplexer to either ground or a potential source.

0048<figref idref="DRAWINGS">FIG. 6</figref> illustrates the operation of the flags <b>100</b> shown in block form in <figref idref="DRAWINGS">FIG. 2</figref>. As shown in <figref idref="DRAWINGS">FIG. 6</figref>, four control bits select the operation of the flags <b>100</b>. If all control bits are 0, then no action occurs. If only the least significant bit is a 1, then all flags are reset. If the next least significant bit is a 1, then all flags are set. The bottom four rows of <figref idref="DRAWINGS">FIG. 6</figref> show the addressing of a specific flag and the setting or resetting of a specific flag based upon the least significant bit. For example, to address flag <b>2</b>, the most significant bits will be 110, with the setting or resetting of the flag controlled by the fourth bit, as also shown in <figref idref="DRAWINGS">FIG. 6</figref>.

0049<figref idref="DRAWINGS">FIG. 7</figref> is a diagram illustrating in more detail the power reduction circuitry. The components in <figref idref="DRAWINGS">FIG. 7</figref> have been given reference numerals to match those of the corresponding components of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, control circuit <b>60</b> controls mux <b>30</b> to cause it to select one of the three input signals bra, brb, and brc, supplied to mux <b>30</b>. The mux selects one of those signals and provides it on output line <b>34</b> to register <b>40</b>, where it thereby selects the next state to be output from memory <b>10</b>. Control circuit <b>60</b> selects the state by applying a signal on one of the three control lines <b>31</b> designated select bra, select brb, and select brc in <figref idref="DRAWINGS">FIG. 7</figref>. Importantly, if control circuit <b>60</b> selects brc, it is indicative that the state of the state machine is not to change. In other words, control <b>60</b> providing a signal on the brc line to mux <b>30</b> indicates that the state machine is to remain in the same state as before.

0050The signal on line <b>150</b> is used to control switch <b>152</b>. Switch <b>152</b>, which can consist of a simple logic gate, or provide more complex functionality, enables clock signal CLK <b>155</b> to be gated to control memory <b>10</b>. When enabled, this clock signal is designated CLK <b>1</b> and has a reference number <b>157</b>. Thus, when line <b>150</b> is active, no clock signal is provided to the memory <b>10</b>, thereby reducing its power consumption. When line <b>150</b> is not active, then CLK<b>1</b> is provided to the memory.

0051Of course, the polarities of the signals described may be reversed. In the previous description the clock signal is always provided except when a signal is present on line <b>150</b>. In an alternate embodiment, line <b>150</b> may be active as long as no signal is present on the select brc line between control <b>60</b> and mux <b>30</b>. In such circumstances, then the gate <b>152</b> will always pass the clock signal CLK except when the state of line <b>150</b> is “off.” Furthermore, if it is desired to allow the memory to remain active in the same state for more than one cycle before being disabled, a counter or other logic can be incorporated within the switch <b>152</b>. Of course, other approaches are also possible by comparing the states of the select bra, select brb, and select brc line to determine whether the control signal from the control circuit <b>60</b> to mux <b>30</b> is of an appropriate nature to disable clocking of memory <b>10</b>.

0052The controlled CLK<b>1</b> signal can also be used as the clock signal for other components, such as decoder <b>40</b>, or even external circuits if power is to be further conserved. This option is illustrated in <figref idref="DRAWINGS">FIG. 7</figref> by the second arrow designating that CLK<b>1</b> may be provided “to other circuits.” Note that in <figref idref="DRAWINGS">FIG. 7</figref> the regular clock signal CLK is used to drive the MUX circuit <b>30</b> and the control circuit <b>60</b>, so they are not disabled. This permits them to detect whether the address for the “next” word has changed or not.

0053In an alternate embodiment, detection of whether the address for the “next” word has changed or is to remain at the same word is determined by an additional bit added to each word in the memory. For those states of the state machine where the machine is to “loop” until an event happens this extra bit can be used to control the switch <b>152</b>. This embodiment is shown in <figref idref="DRAWINGS">FIG. 8</figref>.

0054In <figref idref="DRAWINGS">FIG. 8</figref> the extra bit is shown by column <b>156</b>. The output state of this bit is provided over line <b>159</b> and used to control switch <b>152</b>. For example, if the designer of the control system within which the system shown in <figref idref="DRAWINGS">FIG. 8</figref> wishes for the state machine to remain in a loop at a particular word until a particular event occurs, the bit may be set to “1.” This will disable the switch <b>152</b> and power down those portions of the system connected to receive the CLK<b>1</b> signal until some other event occurs to choose an address for a different word in the memory.

0055Because when the memory is not receiving clock signals, its state would not be detectable, a register <b>160</b> is provided in conjunction with memory <b>10</b> to store the state of the memory. Thus, the contents of register <b>160</b> provide the output signal <b>12</b> indicative of the state of the state machine. The contents of register <b>160</b> are latched, so that they are available even when memory <b>10</b> is not being clocked.

0056A general purpose state machine has been described which can be implemented as a portion of a larger integrated circuit. The state machine can be optimized for particular applications, for example, by reduction of area of the resulting integrated circuit, power consumption, or a combination of factors. The general purpose state machine can be implemented in software, firmware or hardware form.

0057The preceding has been a description of the preferred embodiment of a general purpose state machine. It will be appreciated that numerous modifications may be made from the described implementation, for example, by using the controlled clock signal to control the power consumption of other components in addition to the memory, all without departing from the scope of the invention as defined by the appended claims.