Nova Patents
US7035948B1

System and method for USB controllers

Summary by NHIP

USB Controller with Dual Buffers

The method transfers information between a host system and a USB device using a controller with shared logic channels and dataports. It partitions local memory into two buffers programmed by the host to hold specific packet counts, writing to the first buffer until full before transferring data while simultaneously writing to the second buffer.

Claim Score by NHIP

Read claim 9, the broadest

Abstract

A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. Also provided is a data packet format for transferring data, which comprises of an Endpoint Transfer Descriptor (“ETD”) that includes an EndPoint Descriptor and a Transfer Descriptor, wherein the host system programs the parameters of a communication channel for a particular Endpoint. Also included is a technique for partitioning a memory storage device into a first memory buffer and a second memory buffer; wherein the size of the first and second memory buffer may be programmed by the host system and the first and/or second memory buffer may contain more than one USB packet.

US7035948B1, drawing sheet 1
Sheet 1 of 46

Term

Term ended

Expired 31 August 2022, 4.1 years ago.

  1. Priority
  2. Filed
  3. Granted
  4. Expired
  5. Today

9 claims: 3 independent, 6 dependent

  1. 1
    A method for transferring information between a host system and a Universal Bus System (USB) device via a USB Host Controller, comprising:creating an endpoint and transfer descriptor (“ETD”) data structure, wherein an endpoint descriptor and a transfer descriptor are placed in an ETD table located in an ETD memory in a local memory accessible to the USB Host Controller, and a host system processing unit sets up the ETD table and downloads ETDs from a host system memory to the local memory;assigning a buffer memory in the local memory for each ETD;partitioning the buffer memory into a first memory buffer and a second memory buffer, wherein the first memory buffer size and the second memory buffer size is programmed by the host system processing unit to hold a certain number of packets, wherein the number of packets depend on a size and type of a transaction descriptor;writing data packets in the first memory buffer until the first memory buffer is full;transferring data packets from the first memory buffer after the first memory buffer is full;writing data packets in the second memory buffer, while data packets are being read from the first memory buffer;wherein during a direct memory access (DMA) mode, the host system processing unit enables an ETD and the USB Host Controller maintains a data byte counter whose count indicates a byte count and a packet count for packets that have been written to local memory and a DMA control logic in the Host Controller by setting a bit indicates when the first memory buffer and the second memory buffer are filled.
  2. 8
    A system for transferring information between a host system and a Universal Serial Bus (“USB”) device via a USB Host Controller, comprising:a host central processing unit (“CPU”) for setting up an endpoint and transfer descriptor (“ETD”) data structure in an ETD table, wherein the CPU sets up the ETD table and downloads ETDs from a host system memory to a local memory;wherein each ETD is assigned a memory buffer by the CPU such that the memory buffer can hold certain number of packets and the memory buffer space is partitioned into a first memory buffer and a second memory buffer, wherein the size of the first memory buffer and the second memory buffer is programmed by the CPU depending on a size and type of a transaction descriptor, and data packets are written in the first memory buffer until the first memory buffer is full, and data packets are written in the second memory buffer, while data packets are being read from the first memory buffer after the first memory buffer is full;and in a programmable input/output (“PIO”) mode, the CPU keeps track of the data written in the memory buffer and after the first memory buffer and/or the second memory buffer are full, the CPU allows the USB Host Controller to switch between the first memory buffer and the second memory buffer to read and write data packets;logic for maintaining a first pointer based on which an address from where data is to be read can be determined, and a second pointer based on which an address where data is to be written can be determined;and logic that updates the first and second pointer such that data is read/written in a specified sequence.
  3. 9
    Broadest claimClaim Score 27, narrow(NHIP)An apparatus for transferring information between a host system and a Universal Serial Bus (“USB”) device via a USB Host Controller, comprising:a host central processing unit (“CPU”) for setting up an endpoint and transfer descriptor (“ETD”) data structure in an ETD table, wherein the CPU sets up the ETD table and downloads ETDs from a host system memory to a local memory;wherein each ETD is assigned a memory buffer by the CPU such that the memory buffer can hold certain number of packets, and the memory buffer is partitioned into a first memory buffer and a second memory buffer, wherein the size of the first memory buffer and the second memory buffer is programmed by the CPU depending on a size and type of a transaction descriptor, and data packets are written in the first memory buffer until the first memory buffer is full;and data packets are written in the second memory buffer, while data packets are being read from the first memory buffer after the first memory buffer is full: and in a programmable input/output (“PIO”) mode, the CPU keeps track of the data written in the memory buffer and after the first memory buffer and/or the second memory buffer are full, the CPU allows the USB Host Controller to switch between the first memory buffer and the second memory buffer to read and write data packets;logic for maintaining a first pointer based on which an address from where data is to be read can be determined, and a second pointer based on which an address where data is to be written can be determined;and logic that updates the first and second pointer such that data is read/written in a specified sequence.
Independent claims3