US7005331B2

Method of manufacturing a thin film transistor array

Summary by NHIP

Thin film transistor array manufacturing

The method sequentially forms multiple metal, insulating, and semiconductor layers over a substrate to create a thin film transistor array. Distinctive steps include forming a photoresist layer with a thinner second area, etching uncovered layers to define a TFT area, and subsequently creating contact holes and electrodes through three patterning processes.

Claim Score by NHIP

Read claim 19, the broadest

Abstract

A method for manufacturing a thin film transistor array substrate is disclosed. A first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer are sequentially formed over a substrate, and a first patterning process is carried out to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area. An interlayer insulating layer is formed, and a second patterning process is implemented to form a source/drain contact hole, a scan line contact hole and a terminal contact hole. A transparent conductive layer, a third metal layer and a passivation layer are sequentially formed over the substrate to achieve electrical contacts among above-mentioned contact holes, and a third patterning process is then implemented to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.

US7005331B2, drawing sheet 1 — Sheet 1 of 17

Term

Term ended

Expired 29 June 2024, 2.2 years ago.

20 claims: 4 independent, 16 dependent

1
A method for manufacturing a thin film transistor array substrate, comprising the steps of:providing a substrate;forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area;forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to define a source/drain contact hole, a data line contact hole and a terminal contact hole;and forming a transparent conductive layer, a third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the data line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.
8
A method for manufacturing a thin film transistor array substrate, comprising the steps of:providing a substrate;forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area;forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to form a source/drain contact hole, a scan line contact hole and a terminal contact hole;and forming a transparent conductive layer, a third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the scan line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.
15
A method for manufacturing a thin film transistor array substrate, comprising the steps of:providing a substrate;forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area;forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to form a source/drain contact hole, a data line contact hole and a terminal contact hole;and forming a third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the data line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a reflective pixel electrode.
19
Broadest claimClaim Score 33, narrow(NHIP)A method for manufacturing a TFT array substrate, comprising the steps of:providing a substrate;forming a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer over the substrate, and then carrying out a first patterning process to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area;forming an interlayer insulating layer over the substrate, and carrying out a second patterning process to form a source/drain contact hole, a scan line contact hole and a terminal contact hole;and forming at third metal layer and a passivation layer to protect over the substrate and achieve electrical connections among the source/drain contact hole, the scan line contact hole and the terminal contact hole, and then carrying out a third patterning process to form a thin film transistor, a scan line, a data line, a terminal contact and a reflective pixel electrode.

Independent claims4

68 paragraphs in 4 sections, as filed

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention relates to a method for manufacturing a thin film transistor (TFT) array substrate and, more particularly, to a method for manufacturing a TFT array substrate that has reduced photolithography steps.

00032. Description of Related Art

0004The thin film transistor liquid crystal display (TFT-LCD) is mainly composed of a TFT array substrate, a color filter (CF) array substrate, and a liquid crystal layer interposed therebetween. On the TFT array substrate, a plurality of TFTs arranged in an array and a plurality of pixel electrodes, each corresponding to one of the TFTs, form a plurality of pixel structures. Moreover, each of the TFTs is composed of a gate, a channel, a drain electrode and a source electrode, and acts as a switch element of a liquid crystal displaying pixel unit.

0005In general, a TFT array substrate is manufactured by using five photolithography steps. The first photolithography step defines the first metal layer and thereby forms the scan line and the gate of the thin film transistor. The second photolithography step defines the channel and the ohmic contact layer of the thin film transistor. The third photolithography step is used to define the second metal layer and thereby to form the data line and the source/drain electrodes of the thin film transistor. The fourth photolithography step patterns the passivation layer. As for the fifth photolithography step, it patterns the transparent conductive layer and thereby forms the pixel electrode.

0006However, as the development of the TFT-LCD device is directed towards a bigger and bigger active area, the manufacturing method of the TFT array substrate currently used will encounter lots of problems in the future. For example, it may suffer a low yield and a low production rate. Therefore, if the photolithography steps used in the manufacturing of TFTs can be lowered, i.e. the frequency of exposure process when manufacturing the TFTs is reduced, the production time can be reduced, the production rate can be increased, and thereby the manufacturing cost can be lowered.

0007U.S. Pat. No. 6,255,130 disclosed a method for manufacturing a TFT array substrate using four photolithography steps. With reference to <figref idref="DRAWINGS">FIGS. 1 to 4</figref>, there are shown schematic views of the manufacturing process of a TFT. First, a glass substrate 10 is provided, and a gate electrode 12 made of copper or aluminum is formed on the glass substrate 10, as shown in <figref idref="DRAWINGS">FIG. 1</figref>. Next, a gate insulating layer 14, an amorphous silicon layer 16 and a metal layer 18 are formed sequentially on the gate electrode 12. Thereafter, a halftone photolithography process or a photoresist reflow process is carried out to form a photoresist layer 20 having a slit 22 on the glass substrate 10. The halftone photolithography process uses a mask having a substantially transparent area, a partially transparent area and a substantially opaque area. The substantially opaque area is corresponding to an area, on which a thicker photoresist will be formed, and the partially transparent area is corresponding to another area, on which the slit 22 or a thinner photoresist will be formed.

0008With reference to <figref idref="DRAWINGS">FIG. 2</figref>, a first etching process is subsequently carried out to remove the metal layer 18 and the amorphous silicon layer 16 which are not covered by the photoresist layer 20. Then, the photoresist layer 20 in the slit 22 is wholly removed, and the remaining photoresist layer 20 is thinned simultaneously. Afterward, with reference to <figref idref="DRAWINGS">FIG. 3</figref>, a second etching process is carried out to remove the metal layer 18 that is not covered by the remaining photoresist layer 20, then a source 24 and a drain 26 of a TFT are therefore formed.

0009Finally, a passivation layer 28 made of silicon oxide or silicon nitride is formed over the glass substrate 10 after the photoresist layer 20 is removed, as shown in <figref idref="DRAWINGS">FIG. 4</figref>. Accordingly, the TFT is completed.

0010The prior art forms a ladder shape photoresist layer having more than two thicknesses by applying the halftone photolithography process or the photoresist reflow process. If the halftone photolithography process or the photoresist reflow process can be applied to form other structures of the thin film transistor, the photolithography steps will be further reduced. Also, the yield and production rate can thus be increased.

0011Therefore, the present invention provides a method for manufacturing a TFT array substrate using three photolithography steps only to mitigate the aforementioned problems.

SUMMARY OF THE INVENTION

0012The object of the present invention is to provide a method for manufacturing a TFT array substrate, which utilizes the halftone photolithography technique or the photoresist reflow technique to carry out the patterning of the TFT array substrate in three photolithography steps, and can thus achieve the efficiencies of high yield and high production rate.

0013Another object of the present invention is to provide a method for manufacturing a TFT array substrate used in a transmissive type, a reflective type or a transflective type liquid crystal display device. The method utilizes the halftone photolithography technique or the photoresist reflow technique to carry out the patterning of the TFT array substrate in three photolithography steps, and can thus achieve the efficiencies of high yield and high production rate.

0014The objects, novel features, and advantages of the present invention will become more apparent for those skilled in the art by means of the following detailed description that is taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0015<figref idref="DRAWINGS">FIGS. 1 to 4</figref> are schematic views showing the process flow of the manufacturing of the TFT in the prior art;

0016<figref idref="DRAWINGS">FIG. 5</figref> is a top view showing the layout on the substrate of the first patterning process in the first embodiment of the present invention;

0017<figref idref="DRAWINGS">FIGS. 6A to 6D</figref> are schematic views showing the process flow of the first patterning process in the first embodiment of the present invention;

0018<figref idref="DRAWINGS">FIG. 7</figref> is a top view showing the layout on the substrate of the second patterning process in the first embodiment of the present invention;

0019<figref idref="DRAWINGS">FIGS. 8A to 8D</figref> are schematic views showing the process flow of the second patterning process in the first embodiment of the present invention;

0020<figref idref="DRAWINGS">FIG. 9</figref> is a top view showing the layout on the substrate of the third patterning process in the first embodiment of the present invention;

0021<figref idref="DRAWINGS">FIGS. 10A to 10G</figref> are schematic views showing the process flow of the third patterning process in the first embodiment of the present invention;

0022<figref idref="DRAWINGS">FIGS. 11A to 11D</figref> are schematic views showing the process flow of the third patterning process in the second embodiment of the present invention; and

0023<figref idref="DRAWINGS">FIG. 12</figref> is a top view showing the layout on the substrate of the first patterning process in the third embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

0024To achieve the above-mentioned objects, features and advantages, the present invention provides a method for manufacturing a thin film transistor (TFT) array substrate using three photolithography steps only. The method mainly includes the following steps. First, a first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer are formed sequentially over the substrate. Then, a first patterning process is carried out to define a source/drain electrodes area, a scan line/gate line area, a data line area, a terminal contact area and a pixel area. Afterward, an interlayer insulating layer is formed over the substrate, and then a second patterning process is carried out to define a source/drain contact hole, a data line or scan line contact hole and a terminal contact hole. Thereafter, a transparent conductive layer (being formed optionally depending on the LCD device), a third metal layer and a passivation layer are formed sequentially over the substrate. Thus, the source/drain contact hole, the scan line contact hole and the terminal contact hole are electrically contacted to each other and can be well protected. Subsequently, a third patterning process is carried out to form a TFT, a scan line/gate line, a data line, a terminal contact and a pixel electrode. The first, the second and the third patterning processes mentioned above use the halftone photolithography process or the photoresist reflow process to form a photoresist layer having two areas, which have different thicknesses in a photolithography step.

0025The present invention will be explained in detail via the accompanying drawings. People skilled in the art should understand that those drawings intend to illustrate the present invention but not to limit the scope thereof.

0000Embodiment 1

0026With reference to <figref idref="DRAWINGS">FIGS. 5 to 10</figref>, there are shown the schematic views of the process flow of the present embodiment. <figref idref="DRAWINGS">FIGS. 5 and 6A</figref> to 6D show the process flow of the first patterning process of the method for manufacturing a TFT array substrate. In particular, <figref idref="DRAWINGS">FIG. 5</figref> is a top view showing the layout on the TFT array substrate of the first patterning process in the present embodiment, and <figref idref="DRAWINGS">FIGS. 6A to 6D</figref> are sectional views showing the process flow of the first patterning process in the present embodiment.

0027With reference to <figref idref="DRAWINGS">FIG. 6A</figref>, a substrate 30 is provided, first. The substrate 30 can be a glass substrate, a quartz substrate, or a plastic substrate. Next, a first metal layer 32 is deposited on the substrate 30. The first metal layer 32 is used to form the gate electrode of the thin film transistor, and can be made of aluminum (Al), tungsten (W), chromium (Cr), copper (Cu), titanium (Ti), titanium nitride (TiNx), aluminum alloy, chromium alloy, or molybdenum (Mo). Also, the first metal layer 32 can have a single-layered or a multiple-layered structure. Afterward, a gate insulating layer 34, a semiconductor layer 36, and an ohmic contact layer 38 are sequentially formed on the first metal layer 32. The gate insulating layer 34 can be made of silicon oxide (SiOx), silicon nitride (SiNy), or Silicon oxynitride. The semiconductor layer 36 can be made of the amorphous silicon (α-Si). The ohmic contact layer 38 can be made of, for example, the n-type doped silicon (n+-Si). Moreover, the above-mentioned layers can be formed by using a chemical vapor deposition (CVD) process. Thereafter, a second metal layer 40 is formed on the ohmic contact layer 38. The material of the second metal layer 40 is the same as that of the first metal layer 32, and can be aluminum, tungsten, chromium, copper, titanium, titanium nitride, aluminum alloy, chromium alloy, or molybdenum. Similarly, the structure of the second metal layer 40 can be a single-layered or a multiple-layered structure.

0028Next, a first patterning process is carried out. With reference to <figref idref="DRAWINGS">FIGS. 5 and 6A</figref>, a photoresist layer43 is formed on the second metal layer 40, and then a halftone photolithography process or a non-halftone photolithography process with a following photoresist reflow process is carried out to form the first photoresist layer, which has a first area 42 and a second area 44. The thickness of the second area 44 is thinner than that of the first area 42. Furthermore, the halftone photolithography process uses a mask that has a substantially transparent area, a partially transparent area, and a substantially opaque area. The substantially opaque area is corresponding to the first area 42, and the partially transparent area is corresponding to the second area 44. Hence, the single photolithography process can form the ladder shape photoresist layer that has two areas, which have different thickness from each other.

0029Afterward, the second metal layer 40 that is not covered by the first photoresist layer43, and the ohmic layer 38, the semiconductor layer 36, the gate insulating layer 34, and the first metal layer 32 under the uncovered second metal layer 40 are etched sequentially, as shown in <figref idref="DRAWINGS">FIG. 6B</figref>. Consequently, a predetermined TFT area 41, a scan line area 45, a data line area 47, and a pixel area 49 as shown in <figref idref="DRAWINGS">FIG. 5</figref> are defined.

0030Subsequently, the photoresist in the second area 44 is removed by ashing, and thus the second metal layer 40 covered by the second area 44 is exposed, as shown in <figref idref="DRAWINGS">FIG. 6C</figref>. Simultaneously, the photoresist in the first area 42 becomes thinner, but remains resistant to the etching process. Further, with reference to <figref idref="DRAWINGS">FIG. 6D</figref>, the exposed second metal layer 40 and the ohmic contact layer 38 thereunder are etched to define a source electrode area 51, a drain electrode area 53, and a terminal contact area 55 in <figref idref="DRAWINGS">FIG. 5</figref>.

0031So far the first patterning process has been finished. As shown in <figref idref="DRAWINGS">FIG. 5</figref>, the data line area 47 is predetermined to form the data line of the TFT array. At the intersection of the data line area 47 and the scan line area 45, the data line area 47 does not connect with the scan line area 45. In addition, the data line area 47 does not connect with the source electrode area 51, either. With reference to <figref idref="DRAWINGS">FIG. 6D</figref> again, all of the gate electrode 32′, the ohmic contact layer 38, the gate insulating layer 34, the channel 37, the source electrode 52, and the drain electrode 54 which compose the TFT have been formed already.

0032With reference to <figref idref="DRAWINGS">FIGS. 7 and 8A</figref> to 8D, there are schematic views showing the process flow of the second patterning process of the present invention. In particular, <figref idref="DRAWINGS">FIG. 7</figref> shows the layout on the substrate when the second patterning process is carried out, and <figref idref="DRAWINGS">FIGS. 8A to 8D</figref> show the sectional views thereof.

0033With reference to <figref idref="DRAWINGS">FIG. 8A</figref>, an interlayer insulating layer 60 is formed over the substrate 30. The same as the gate insulating layer 34, the interlayer insulating layer 60 can be made of silicon oxide, silicon nitride, or silicon oxynitride, and similarly can be formed by chemical vapor deposition.

0034Afterward, the second patterning process is carried out. As shown in <figref idref="DRAWINGS">FIGS. 7 and 8A</figref>, a photoresist layer 63 is formed on part of the interlayer insulating layer 60, and then like the first patterning process, a halftone photolithography process or a non-halftone photolithography process with a photoresist reflow process is implemented to form the second photoresist layer 63. Similarly, the second photoresist layer 63 has a third area 62 and a fourth area 64, of which the thickness is thinner than that of the third area 62.

0035Next, the interlayer insulating layer 60 that is not covered by the second photoresist layer 63 and the semiconductor layer 38 under the abovementioned interlayer insulating layer 60 are etched sequentially to define a predetermined terminal contact hole area 65, as shown in <figref idref="DRAWINGS">FIG. 8B</figref>.

0036With reference to <figref idref="DRAWINGS">FIG. 8C</figref>, the fourth area 64 of the second photoresist layer 63 is then removed by ashing in order to expose the interlayer insulating layer 60. Thereafter, the exposed interlayer insulating layer 60 is etched to exposed the second metal layer 52, 54 thereunder and thereby forms the source/drain contact hole 66 and the data line contact hole 68, as shown in <figref idref="DRAWINGS">FIG. 8D</figref>. Simultaneously, the gate insulating layer 34 at the predetermined terminal contact hole area 65 is etched to expose the first metal layer 32 and thereby forms the terminal contact hole 67. In addition, part of the interlayer insulating layer 60 at the scan line area 45 and at the predetermined disconnection area 69 between the TFTs is removed, as shown in <figref idref="DRAWINGS">FIG. 8C</figref>. With reference to <figref idref="DRAWINGS">FIG. 8D</figref>, taking the metal layers as the etching stopper, the semiconductor layer 38 below the interlayer insulating layer at the predetermined disconnection area 69 can be further removed. As a result, the semiconductor layer 38 that constitutes the TFT is separated from the semiconductor layer 38 at the scan line area 45, so electric leakage issue will not happen between the scan line and the channel 37 of the TFT. Moreover, the predetermined disconnection area 69 above the first metal layer 32 that serves as the gate electrode 33 still can be protected by the gate insulating layer 34.

0037So far, the second patterning process has been completed.

0038On the other hand, part of the process flow of the second patterning process can also be replaced by other etching sequence. However, the accompanying drawings are omitted here.

0039Similarly, the interlayer insulating layer 60 that is not covered by the second photoresist layer 63 is etched except that the semiconductor layer 38 that is below the predetermined terminal contact hole area 65 is not etched immediately in order to shorten the etching time.

0040Thereafter, the fourth area of the second photoresist layer is removed by ashing, and then the interlayer insulating layer 60 that was covered by the fourth area is etched to expose the second metal layer 40 and thereby to form the contact holes 66, 68. Simultaneously, the interlayer insulating layer 60 at the predetermined disconnection area 69 and the semiconductor layer 38 thereunder will be removed by etching sequentially. Moreover, the semiconductor layer 38 at the predetermined terminal contact hole area 65 and the gate insulating layer thereunder are etched to expose the second metal 40 and the first metal 32 and to form the terminal contact hole 67.

0041As a result, the second patterning process can also be completed.

0042With reference to <figref idref="DRAWINGS">FIGS. 9 and 10A</figref> to 10G, there are schematic views showing the process flow of the third patterning process of the present invention. In particular, <figref idref="DRAWINGS">FIG. 9</figref> shows the layout on the substrate when the third patterning process is carried out, and <figref idref="DRAWINGS">FIGS. 10A to 10D</figref> show the sectional views thereof.

0043With reference to <figref idref="DRAWINGS">FIG. 10A</figref>, a transparent conductive layer 72, a third metal layer 74, and a passivation layer 76 are formed sequentially over the substrate. The transparent conductive layer 72 can be made of indium tin oxide or indium zinc oxide. As the metal layers 32, 40, the third metal layer 74 can be made of aluminum, tungsten, chromium, copper, titanium, titanium nitride, aluminum alloy, chromium alloy, or molybdenum. Also, the structure of the third metal layer 74 can be a single-layered or a multiple-layered structure. Besides, the material of the passivation layer 76 can be the same as that of the interlayer insulating layer 60 and that of the gate insulating layer 34. Therefore, the electrical contact among the source/drain contact hole, the scan line contact hole and the terminal contact hole are completed, and the metal layers are well protected.

0044Afterward, the third patterning process is implemented. As shown in <figref idref="DRAWINGS">FIGS. 9 and 10A</figref>, a third photoresist layer 83 is formed on part of the passivation layer 76. The third photoresist layer 83 has a fifth area 82 and a sixth area 84, of which the thickness is thinner than that of the fifth area 82.

0045Next, the exposed passivation layer 76 and the third metal layer 74 thereunder are removed sequentially by etching to expose the transparent conductive layer 72 and thereby to define a predetermined source/drain disconnection area 85, as shown in <figref idref="DRAWINGS">FIG. 10B</figref>.

0046Thereafter, the sixth area 84 of the third photoresist layer 83 is removed by ashing to expose the passivation layer 76, as shown in <figref idref="DRAWINGS">FIG. 10C</figref>. Then, the exposed passivation layer 76 is etched to expose the third metal layer 74 thereunder, as shown in <figref idref="DRAWINGS">FIG. 10D</figref>.

0047Afterward, a high metal-transparent conductive material selectivity etchant is used to remove the exposed transparent conductive layer 72 at the predetermined source/drain disconnection area 85 with non-destruction of the metal layer. As a result, the electrical connection between the source electrode and the drain electrode is terminated. Also, the electrical connection at the predetermined disconnection area 69 is obviated to avoid the electrical conduction between the scan line and the channel 37 of the TFT.

0048Next, the exposed third metal layer 74 is removed by etching to expose the transparent conductive layer 72 at both the terminal contact area 55 and the pixel area 49. Finally, the fifth area 82 of the third photoresist layer is removed to form the TFT1, the scan line 2, the data line 3, the terminal contact 4, and the pixel electrode 5, as shown in <figref idref="DRAWINGS">FIG. 10F</figref>.

0049Otherwise, the TFT1, the scan line 2, the data line 3, the terminal contact 4, and the pixel electrode 5 can be formed by removing the fifth area 82 of the third photoresist layer before the exposed third metal layer 74, as shown in <figref idref="DRAWINGS">FIG. 10G</figref>.

0050So far, the third patterning process has been completed, and the TFT array substrate is also finished.

0051The TFT array substrate manufactured in Embodiment 1 is useful and can be applied to the liquid crystal display device, especially to the transmissive liquid crystal display device. In addition, if the scopes or the ratio of the fifth area 82 and the sixth area 84 covered by the drain electrode area 53 and the pixel area 49 can be well adjusted in the third patterning process, then the pixel electrode 5 will have a reflective surface that is partially covered by the third metal layer 74 and a transmissive electrode that has a partially exposed transparent conductive layer 72. Consequently, the TFT array substrate can be used in the semi-transmissive liquid crystal display deice. The third metal layer of such a TFT array can also have a single layer or a multi-layered structure, but its top layer must be made of metal with good reflectivity, such as aluminum, chromium, aluminum alloy, chromium alloy, or silver.

0000Embodiment 2

0052Furthermore, the pixel electrode can be made of metal materials when the TFT array is used for a reflective type liquid crystal display device. The manufacturing method for the above-mentioned TFT array is generally the same as Embodiment 1 except that the third patterning process is slightly different and described as the following. Reference is made again to the same drawings, and the related symbols are used again.

0053With reference to <figref idref="DRAWINGS">FIGS. 9 and 11A</figref> to 11D, there are schematic views showing the process flow of the third patterning process of the present embodiment. <figref idref="DRAWINGS">FIG. 9</figref> shows the top view of the layout on the substrate when the third patterning process is carried out, and <figref idref="DRAWINGS">FIGS. 11A to 11D</figref> show the sectional views thereof.

0054With reference to <figref idref="DRAWINGS">FIG. 11A</figref>, a third metal layer 74 and a passivation layer 76 are sequentially deposited over the substrate. The third metal layer 74 can be made of aluminum, tungsten, chromium, copper, titanium, titanium nitride, molybdenum, aluminum alloy, chromium alloy, or silver, and the structure thereof can be a single-layered or a multiple-layered structure, which has the proviso that the top layer must be made of metal with good reflectivity, such as aluminum, chromium, aluminum alloy, chromium alloy, or silver. As for the passivation layer 76, its material can be the same as the materials of the interlayer insulating layer 60 or the gate insulating layer 34. Consequently, the electrical connections among all the contact holes are achieved, and the metal lines serving as circuits are well protected. In the present embodiment, for the subsequent multi-etching, the thickness of the passivation layer 76 must be less than a specific thickness T, which is the thinner between half the thickness of the interlayer insulating layer 60 and half the thickness of the gate insulating layer 34. Why the thickness of the passivation layer 76 must be less than half the thickness of the interlayer insulating layer 60 and half the thickness of the gate insulating layer will be explained later.

0055Next, a third patterning process is carried out. As shown in <figref idref="DRAWINGS">FIGS. 9 and 11A</figref>, a third photoresist layer 83 is formed on part of the passivation layer 76, and is composed of a fifth area 82 and a sixth area 84, of which the thickness is thinner than that of the fifth area 82.

0056Afterward, the passivation layer 76 that is not covered by the third photoresist layer 83 and the third metal layer 74 are sequentially etched to expose the interlayer insulating layer 60 and thereby to terminate the electrical connection between the source electrode and the drain electrode as well as the electrical connection at the area 69, as shown in <figref idref="DRAWINGS">FIG. 11B</figref>. Therefore, the electric conduction between the scan line and the channel 37 of the TFT is avoided.

0057Thereafter, the sixth area 84 of the third photoresist layer 83 is removed by ashing to expose part of the passivation layer 76, as shown in <figref idref="DRAWINGS">FIG. 11C</figref>. Then, the exposed passivation layer 76 is etched to expose the third metal layer 74 at both the terminal contact area 55 and the pixel area 49, as shown in <figref idref="DRAWINGS">FIG. 5</figref>. Certainly, part of the uncovered interlayer insulating layer 60 at the scan line area 45 and part of the uncovered gate insulating layer 34 at the predetermined disconnection area 69 are etched simultaneously. However, the remaining insulating layers are thicker than half their original thickness and are still protective for the thin film transistors and the scan lines.

0058Finally, the fifth area 82 of the third photoresist layer 83 is removed to form the TFT1, the scan line 2, the data line 3, the terminal contact 4, and the reflective type pixel electrode 6 having the third metal layer 74 that is reflective.

0000Embodiment 3

0059Most of the present embodiment is the same as Embodiment 1, except that the pattern of the masks used in the patterning processes are slightly changed as the following. Similarly, reference is made again to the same drawings, and the symbols are used again.

0060<figref idref="DRAWINGS">FIG. 12</figref> is the top view showing the layout on the substrate when the first patterning process is carried out in the present embodiment. The scan line area 45 is predetermined to form the scan line of the TFT array. The scan line area 45 is terminated when it comes across the data line area 47, which is different from Embodiment 1 and will affect the mask patterns used in the second and third patterning processes. After the first patterning process, the source/drain electrode area, the scan line area, the data line area, the terminal contact area, and the pixel area are defined.

0061Next, the interlayer insulating layer is formed over the substrate. By the second patterning process, the source/drain contact holes, the scan line contact hole, and the terminal contact hole are formed.

0062Finally, a transparent conductive layer is optionally formed over the substrate depending on the type of the LCD device, and then a third metal layer and a passivation layer are sequentially formed. As a result, the electrical connections among those contact holes are achieved, and those contact holes are well protected. Afterward, the TFT, the scan line, the data line, the terminal contact, and the pixel electrode are formed by the third patterning process.

0063So far, another TFT array is completed.

0064From the above-mentioned embodiments, the present invention provides a progressive method for manufacturing the TFT array substrate by using three photolithography processes only. In addition, the yield of the TFT array substrate is increased, and thereby the displaying quality is effectively guaranteed.

0065Although the present invention has been explained in relation to the above-mentioned preferred embodiment, it is to be understood that those embodiments are illustrative only, and various changes in form and details can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Contents4

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US2011233551A1	Cited by	United States of America	Pre-grant
US8803154B2	Cited by	United States of America	Search report
US2014087510A1	Cited by	United States of America	Pre-grant
US8603843B2	Cited by	United States of America	Search report
US2003193056A1	Cites	United States of America	Search report
US2003232454A1	Cites	United States of America	Search report
US4738749A	Cites	United States of America	Search report
US6255130B1	Cites	United States of America	Search report
US6444505B1	Cites	United States of America	Search report
US6537840B1	Cites	United States of America	Search report
US6744486B1	Cites	United States of America	Search report
US6833896B1	Cites	United States of America	Search report
US6869833B1	Cites	United States of America	Search report
US20030193056A1	Cites	United States of America	Search report
US20030232454A1	Cites	United States of America	Search report

4 members in 2 offices; this record represents the family

This recordMember, by publication datePriority claim

Priority claims2

Priority claims
Document	Office	Kind	Date
92134265A	Taiwan Province of China	–	2003-12-03
92134265	Taiwan Province of China	A	2003-12-03

Members4

Family members, oldest first
Document	Office	Kind
US2005124088A1	United States of America	A1	2005-06-09
TW200520230A	Taiwan Province of China	A	2005-06-16
US7005331B2This record	United States of America	B2	2006-02-28
TWI261927B	Taiwan Province of China	B	2006-09-11

28 transactions on the USPTO file

Allowed after 1 non-final rejection.

Non-final rejections: 1
Final rejections: 0
RCEs: 0
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2006-02-28	Recordation of Patent Grant MailedPGM/	PGM/
2006-02-28	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2006-02-08	Issue Notification MailedAllowedWPIR	WPIR
2006-01-04	Dispatch to FDCD1935	D1935
2005-12-20	Application Is Considered Ready for IssuePILS	PILS
2005-12-13	Issue Fee Payment VerifiedN084	N084
2005-12-13	Issue Fee Payment ReceivedIFEE	IFEE
2005-09-22	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2005-09-20	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2005-09-20	Case Docketed to Examiner in GAUDOCK	DOCK
2005-09-15	Date Forwarded to ExaminerFWDX	FWDX
2005-09-09	Response after Non-Final ActionA...	A...
2005-06-09	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2005-06-07	Non-Final RejectionNon-final rejectionCTNF	CTNF
2005-01-25	Case Docketed to Examiner in GAUDOCK	DOCK
2004-10-13	IFW TSS Processing by Tech Center CompleteTSSCOMP	TSSCOMP
2004-10-13	Case Docketed to Examiner in GAUDOCK	DOCK
2004-08-17	Application Is Now CompleteCOMP	COMP
2004-08-16	Application Return from OIPEWROIPE	WROIPE
2004-08-16	Application Return TO OIPEROIPE	ROIPE
2004-08-16	Application Return from OIPEWROIPE	WROIPE
2004-08-16	Application Return TO OIPEROIPE	ROIPE
2004-08-16	Application Dispatched from OIPEOIPE	OIPE
2004-08-16	Application Is Now CompleteCOMP	COMP
2004-08-04	Cleared by OIPE CSRL194	L194
2004-07-17	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2004-06-29	Request for Foreign Priority (Priority Papers May Be Included)RQPR	RQPR
2004-06-29	Initial Exam Team nnIEXX	IEXX

6 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2017-08-17	Fee paymentFPAY	FPAY
2013-03-14	Fee paymentFPAY	FPAY
2009-08-28	Fee paymentFPAY	FPAY
2007-01-16	AssignmentAS	AS
2006-02-08	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2004-06-29	AssignmentAS	AS