High density laminated substrate structure and manufacture method thereof

CROSS REFERENCE TO RELATED APPLICATIONS

0001This application claims the priority benefit of Taiwan application serial no. 91111329, filed May 28, 2002.

BACKGROUND OF INVENTION

00021. Field of Invention

0003The present invention generally relates to a laminated substrate structure and the manufacture method thereof, and more particularly, to a package substrate or Printed Circuit Board (PCB) structure and the manufacture method thereof.

00042. Description of Related Art

0005In line with fast growth and the high demand for electronic technology, the development of electronic products tends towards miniaturization and high density integration. In the packaging field, the development of the Ball Grid Array (BGA) and Chip Scale Package (CSP) is targeted at the market requirements for miniaturization and high-density integration. For the Printed Circuit Board (PCB), in order to minimize the circuit area used, the technology of the multi-layered structure is applied. However, the substrate used in BGA, CSP and the manufacture of PCB all uses vias that are made of conductive material to connect between layer circuits. Therefore, the fine trace circuit on the laminated substrate and the small dimension vias can improve the package density and the PCB integration.

0006The conventional laminated substrate manufacture method is mainly divided into two categories: lamination process and build up process. The lamination process provides a plurality of isolation layers first, then forms a circuit layer on the surface of the isolation layers, and performs the drill, plate, and hole plugging process on each isolation layer to form a plating through hole (PTH), so that the circuit layer on the surface of the isolation layer is electrically coupled by the plating through hole formed by the via process. After the via is formed in each isolation layer, the conductive circuit is subsequently formed on the laminated surface copper layer. Afterwards, the substrate or the circuit board is made by repeatedly performing a process that comprises aligning a determined number of the isolation layers to the surface copper layer, laminating them into a laminated substrate, and forming a conductive circuit.

0007When the laminated substrate is made by using the conventional lamination process, the via forming, plating through hole and the isolation material hole plugging operations must be performed on the isolation layer, and the process is rather sophisticated and time consuming. Moreover, the process difficulty and unit cost significantly increase accordingly when the isolation layer via dimension approaches 100 micrometers or below. When the via dimension is less than 100 micrometers or below, there is as yet no mass production product provided by vendors. Therefore, there is a mass production technology bottleneck problem when the plating through hole is less than 100 micrometers.

0008Besides the lamination process, the build up process is also broadly adopted by vendors. The build up process mainly forms the dielectric layer, the inter-layer via in the dielectric layer, and the circuit layer on the surface of the dielectric layer sequentially from bottom to over both sides of the laminated core substrate. The dielectric layer in the laminated substrate is mainly formed by using the lamination or coating method. After the dielectric layer is formed, an opening is formed in the dielectric layer by using the image forming/etching process or the laser/plasma etch method, and the inter-layer via is formed by filling the conductive material into the opening or by using the plating method. After the inter-layer via is formed, a sophisticated chemical surface process is performed and the circuit layer is formed on the surface of the dielectric layer. The laminated substrate is formed by repeatedly performing the sophisticated and difficult manufacture steps of the dielectric layer, inter-layer via, chemical surface process, and forming the circuit layer.

0009In the substrate formed by the build up process, each dielectric layer and circuit layer has to be formed sequentially, so that the whole process is too lengthy. Moreover, the quality of forming each dielectric layer and circuit layer directly impacts the yield of the whole building substrate, thus it is not easy to control the process yield. When the substrate is formed by the build up process, besides the problem of the lengthy process and the low process yield, it also has the problems of high process cost and big equipment investment cost, or the reliability deteriorates due to the process not being easy to control.

0010<figref idref="DRAWINGS">FIG. 1</figref> schematically shows a sketch view of the contact position of the circuit layer and the via in the conventional laminated substrate structure, wherein the contact position has a via land. Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a circuit <b>100</b><i>a </i>and a via land <b>102</b><i>a </i>are isolated from a circuit <b>100</b><i>b </i>and a via land <b>102</b><i>b </i>by a dielectric layer (not shown). The dimensions of the via land <b>102</b><i>a</i>, <b>102</b><i>b </i>are usually designed to be wider than the linewidth of the circuit <b>100</b><i>a</i>, <b>100</b><i>b</i>, so as to assure that two circuit layers are electrically coupled by the via <b>104</b> in the dielectric layer. However, the via land <b>102</b><i>a </i>and the via land <b>102</b><i>b </i>usually reduce the layout space of the circuit layer, so that the circuit density in the laminated substrate cannot be efficiently improved.

SUMMARY OF INVENTION

0011Therefore, the object of the present invention is to provide a laminated substrate structure, in which a landless design is applied onto the contact position of its circuit layer and its via to improve the circuit density in the laminated substrate.

0012Another object of the present invention is to provide a laminated substrate structure, wherein the structure has good electrical performance and good thermal performance.

0013Another object of the present invention is to provide a laminated substrate manufacture method, wherein the manufacture method is characterized by high process yield, high production capacity, ease of manufacture, high density and low manufacture cost.

0014In order to achieve the objects of the present invention mentioned above, a laminated substrate structure is provided. The laminated substrate structure is composed of a plurality of dielectric layers and a plurality of circuit layers stacked with each other. A plurality of vias exists in the dielectric layer, and the circuit layers are electrically coupled to each other through the vias in the dielectric layer. The laminated substrate structure of the present invention is characterized by the circuit layer pattern between the dielectric layers being a landless design. The landless design circuit layer pattern can efficiently improve the circuit integration in the laminated substrate.

0015The laminated substrate structure of the present invention further comprises at least a via opening layer arranged on the two most exterior dielectric layers. The via opening layer has a plurality of openings corresponding to two vias in the most exterior of the dielectric layers. Moreover, this most exterior dielectric layer or a solder mask layer may be applied or may not be applied to the via opening layer depending on the requirement.

0016In order to achieve the objectives of the present invention mentioned above, a laminated substrate manufacture method is provided. There are two groups divided as forming of the dielectric layer having a patterned circuit and the dielectric layer having a via are performed first. After the forming of the dielectric layer having the patterned circuit and the dielectric layer having the via finishes, the alignment is performed onto them, and finally laminates them to form the laminated substrate. The dielectric layer having the patterned circuit and the dielectric layer having the via are laminated by using the method such as the vacuum thermal lamination. Moreover, after the alignment and lamination of the dielectric layer having the patterned circuit and the dielectric layer having the via, a curing step is performed to cure the dielectric material in the dielectric layer having the patterned circuit and the dielectric layer having the via.

0017In order to achieve the objectives of the present invention mentioned above, a laminated substrate manufacture method is provided. The forming of the dielectric layer having a patterned circuit, the dielectric layer having a via, and the via opening layer optionally applied are performed first. After the forming of the dielectric layer having the patterned circuit, the dielectric layer having the via, and the via opening layer, the alignment is performed onto them, finally laminating them to form the laminated substrate. The dielectric layer having the patterned circuit and the dielectric layer having the via are laminated by using a method such as the vacuum thermal lamination. Moreover, after the alignment and lamination of the dielectric layer having the patterned circuit and the dielectric layer having the via, a curing step is performed to cure the dielectric material in the dielectric layer having the patterned circuit and the dielectric layer having the via, and form the electrical connection at appropriate via circuit position.

0018The present invention provides a first supporter first, a patterned circuit is subsequently formed on the first supporter, and a first dielectric layer is formed on the first supporter finally to cover the patterned circuit. Therefore, a dielectric layer having the patterned circuit can be formed on the first supporter.

0019The present invention provides a second supporter first, a plurality of via studs subsequently formed on the second supporter, and finally a second dielectric layer is formed on the second supporter, wherein the via studs extrude from the surface of the second dielectric layer. Therefore, a dielectric layer having via studs can be formed on the second supporter.

0020The patterned circuit of the present invention is formed by using the method such as the metal etching, pattern plating, semi-additive, or full-additive. Moreover, the first dielectric layer and the second dielectric layer are formed by using film, or by the coating, spray coating, or agglutinate method.

0021The opening in the via opening layer of the present invention is formed by using the mechanical drilling, laser drilling, or hole punch method.

BRIEF DESCRIPTION OF DRAWINGS

0022The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention. In the drawings,

0023<figref idref="DRAWINGS">FIG. 1</figref> schematically shows a sketch map of the contact position of the circuit layer and the via in the conventional laminated substrate structure, wherein the contact position has a via land;

0024<figref idref="DRAWINGS">FIGS. 2A–2D</figref> schematically shows a sectional sketch map of the manufacture process of a dielectric layer that has a patterned circuit in the laminated substrate of the first embodiment according to the present invention;

0025<figref idref="DRAWINGS">FIGS. 3A–3D</figref> schematically shows a sectional sketch map of the manufacture process of a dielectric layer that has a via in the laminated substrate of the first embodiment according to the present invention;

0026<figref idref="DRAWINGS">FIG. 4A</figref> and <figref idref="DRAWINGS">FIG. 4B</figref> schematically show the sectional sketch maps of the manufacture process of the via opening layer in the laminated substrate of the first embodiment according to the present invention;

0027<figref idref="DRAWINGS">FIG. 5A</figref> and <figref idref="DRAWINGS">FIG. 5B</figref> schematically show the sectional sketch maps of the lamination process performed onto the laminated substrate of the first embodiment according to the present invention;

0028<figref idref="DRAWINGS">FIGS. 6A–6D</figref> schematically shows a sectional sketch map of the manufacture process of a dielectric layer that has a patterned circuit in the laminated substrate of the second embodiment according to the present invention; and

0029<figref idref="DRAWINGS">FIG. 7</figref> schematically shows a sketch map of the contact position of the circuit layer and the via in the laminated substrate structure of the first embodiment and the second embodiment according to the present invention, wherein the contact position has a landless design.

DETAILED DESCRIPTION

0030The First Embodiment

0031<figref idref="DRAWINGS">FIGS. 2A–2D</figref> schematically show a sectional sketch views of the manufacture process of the circuit parts that have a patterned circuit in the laminated substrate of the first embodiment according to the present invention. The patterned circuit in the laminated substrate of the present invention is formed by using a method such as metal etching, pattern plating, semi-additive, or full-additive. Metal etching is used in the present embodiment for description. Referring to <figref idref="DRAWINGS">FIG. 2A</figref> first, a supporter <b>202</b> is provided, and a conductive layer <b>204</b> is subsequently formed on the supporter <b>202</b>. The conductive layer <b>204</b> is made of material such as copper, and the conductive layer <b>204</b> is formed on the supporter <b>202</b> by using a method such as sputtering, lamination adherence or deposition.

0032Referring to both <figref idref="DRAWINGS">FIG. 2B</figref> and <figref idref="DRAWINGS">FIG. 2C</figref> simultaneously, a patterned photoresist <b>206</b> is subsequently formed on the conductive layer <b>204</b>, the patterned photoresist <b>206</b> is used to define the pattern of the conductive layer <b>204</b> below it. The patterned photoresist <b>206</b> is formed on the conductive layer <b>204</b> through the steps of the photoresist coating, exposure, and developing. After the patterned photoresist <b>206</b> is formed, the patterned photoresist <b>206</b> is used as a mask to etch the conductive layer <b>204</b> below it, so that a portion of the conductive layer <b>204</b> that is not covered by the patterned photoresist <b>206</b> is removed to form the patterned circuit <b>204</b><i>a</i>. Afterwards, the patterned photoresist <b>206</b> is stripped from the conductive layer <b>204</b> surface.

0033Then, referring to <figref idref="DRAWINGS">FIG. 2D</figref>, after the patterned circuit <b>204</b><i>a </i>is formed, a dielectric layer <b>208</b> is subsequently formed on the supporter <b>202</b> covering the patterned circuit <b>204</b><i>a</i>. The patterned circuit <b>204</b><i>a </i>and the dielectric layer <b>208</b> constitute a part <b>200</b> having embedded patterned circuits.

0034<figref idref="DRAWINGS">FIGS. 3A–3D</figref> schematically shows a sectional sketch map of the manufacture process of parts containing via and via pad in the laminated substrate of the first embodiment according to the present invention. Referring to <figref idref="DRAWINGS">FIG. 3A</figref> first, a supporter <b>302</b> is provided, and a conductive layer <b>304</b> is subsequently formed over the supporter <b>302</b>, which is peelable from the conductive metal and the dielectric regions. Wherein, the conductive layer <b>304</b> is made of a material such as copper, and the conductive layer <b>304</b> is formed over the supporter <b>302</b> by using a method such as sputtering, lamination adherence or deposition.

0035Referring to both <figref idref="DRAWINGS">FIG. 3B</figref> and <figref idref="DRAWINGS">FIG. 3C</figref> simultaneously, a patterned photoresist <b>306</b> is subsequently formed on the conductive layer <b>304</b>, the patterned photoresist <b>306</b> is used to define the pattern of the conductive layer <b>304</b> below it. The patterned photoresist <b>306</b> is formed on the conductive layer <b>304</b> through the steps of the photoresist coating, exposure, and developing. After the patterned photoresist <b>306</b> is formed, the patterned photoresist <b>306</b> is used as a mask to etch the conductive layer <b>304</b> below it, so that a portion of the conductive layer <b>304</b> that is not covered by the patterned photoresist <b>306</b> is removed to form the via studs <b>304</b><i>a</i>. Afterwards, the patterned photoresistor <b>306</b> is stripped from the conductive layer <b>304</b>.

0036Referring to <figref idref="DRAWINGS">FIG. 3D</figref>, after the via stud <b>304</b><i>a </i>is formed, a dielectric layer <b>308</b> is subsequently formed on the supporter <b>302</b> to cover the via studs <b>304</b><i>a</i>. The via studs <b>304</b><i>a </i>and the dielectric layer <b>308</b> constitute a part <b>300</b> having via studs. <figref idref="DRAWINGS">FIG. 3D</figref> shows that the dimension of the via studs <b>304</b><i>a </i>can vary depending on the process requirement.

0037<figref idref="DRAWINGS">FIG. 4A</figref> and <figref idref="DRAWINGS">FIG. 4B</figref> schematically show the sectional sketch views of the manufacture process of the via opening layer in the laminated substrate of the first embodiment according to the present invention. Referring to both <figref idref="DRAWINGS">FIG. 4A</figref> and <figref idref="DRAWINGS">FIG. 4B</figref> simultaneously, a supporting layer <b>400</b> is provided first, and an opening <b>402</b> is formed in the supporting layer <b>400</b> to form a via opening layer <b>400</b><i>a</i>. The opening <b>402</b> in the via opening layer <b>400</b><i>a </i>could be formed by using mechanical drilling, laser drilling, or hole punch method.

0038<figref idref="DRAWINGS">FIG. 5A</figref> and <figref idref="DRAWINGS">FIG. 5B</figref> schematically show the sectional sketch views of the lamination process performed onto the laminated substrate of the first embodiment according to the present invention. Referring to both <figref idref="DRAWINGS">FIG. 5A</figref> and <figref idref="DRAWINGS">FIG. 5B</figref> simultaneously, first aligning a plurality of dielectric layers <b>200</b> having patterned circuits with a plurality of dielectric layers <b>300</b> having via studs and a plurality of via opening layer <b>400</b><i>a </i>as shown in <figref idref="DRAWINGS">FIG. 5A</figref>. After the alignment, the dielectric layers <b>200</b> having patterned circuits, dielectric layers <b>300</b> having via studs, and the via opening layer <b>400</b><i>a </i>are laminated together to complete the forming of the laminated substrate. The dielectric layers <b>200</b> having patterned circuits, the dielectric layer <b>300</b> having via studs, and the via opening layers <b>400</b><i>a </i>are laminated by using the vacuum thermal lamination method.

0039Referring to <figref idref="DRAWINGS">FIG. 5A</figref> and <figref idref="DRAWINGS">FIG. 5B</figref>, in the manufacture process of the laminated substrate, the via opening layer <b>400</b><i>a </i>is an optional component. In other words, the present invention may align and laminate the plurality of parts <b>200</b> having patterned circuits with a plurality of parts <b>300</b> having via studs only. Therefore, the via opening layer <b>400</b><i>a </i>can be saved in the manufacture process of the laminated substrate, so that the whole process can be further simplified.

0040The Second Embodiment

0041The present embodiment is the same as the first embodiment in forming the dielectric layer having the via studs and the via opening layer. The difference between the present embodiment and the first embodiment is in the manufacture method of the dielectric layer having the patterned circuit.

0042<figref idref="DRAWINGS">FIGS. 6A–6D</figref> schematically shows sectional sketch views of the manufacture process of the dielectric layer that has a patterned circuit in the laminated substrate of the second embodiment according to the present invention. Referring to <figref idref="DRAWINGS">FIG. 6A</figref> first, a supporter <b>602</b> is provided, and a conductive layer <b>604</b> is subsequently formed on the supporter <b>602</b>. The conductive layer <b>604</b> is made of material such as copper, and the conductive layer <b>604</b> is formed on the supporter <b>602</b> by using a method such as sputtering, lamination adherence or deposition.

0043Then, referring to both <figref idref="DRAWINGS">FIG. 6B</figref> and <figref idref="DRAWINGS">FIG. 6C</figref> simultaneously, a patterned photoresist <b>606</b> is subsequently formed on the conductive layer <b>604</b>, and the patterned photoresist <b>606</b> has a plurality of openings <b>607</b>. The patterned photoresist <b>606</b> is formed on the conductive layer <b>604</b> through the steps of the photoresist coating, exposure, and developing. After the patterned photoresist <b>606</b> is formed, the conductive layer <b>608</b> is filled into the opening <b>607</b> of the patterned photoresist <b>606</b>. Since the opening <b>607</b> has a specific pattern, the conductive layer <b>608</b> filled into the opening <b>607</b> is consistent with the specific pattern mentioned above. Afterwards, the patterned photoresist <b>606</b> is stripped from the conductive layer <b>604</b> to expose the conductive layer <b>604</b> below it.

0044Referring to <figref idref="DRAWINGS">FIG. 6C</figref> and <figref idref="DRAWINGS">FIG. 6D</figref>, after the patterned photoresistor <b>606</b> is stripped from the conductive layer <b>604</b>, a non-optional step of micro etching is subsequently performed to remove the conductive layer <b>604</b>. In the process of removing the conductive layer <b>604</b>, a portion of the conductive layer <b>608</b> thickness is etched to form a patterned circuit <b>608</b><i>a</i>. After the patterned circuit <b>608</b><i>a </i>is formed, a dielectric layer <b>610</b> is subsequently formed on the supporter <b>602</b> covering the patterned circuit <b>608</b><i>a</i>. The patterned circuit <b>608</b><i>a </i>and the dielectric layer <b>610</b> constitute parts <b>600</b> having a patterned circuit.

0045In the manufacture process of <figref idref="DRAWINGS">FIG. 6A</figref> to <figref idref="DRAWINGS">FIG. 6D</figref> mentioned above, a thin trace circuit can be formed in the laminated substrate. The fine trace circuit manufacture process (<figref idref="DRAWINGS">FIG. 6A</figref> to <figref idref="DRAWINGS">FIG. 6D</figref>) efficiently improves the circuit density in the laminated substrate, and is also helpful to the layout flexibility of the circuit layer in the laminated substrate.

0046<figref idref="DRAWINGS">FIG. 7</figref> schematically shows a sketch view of the contact position of the circuit layer and the via in the laminated substrate structure of the first embodiment and the second embodiment according to the present invention, wherein the contact position has a landless design. Referring to <figref idref="DRAWINGS">FIG. 7</figref>, the circuit <b>700</b><i>a </i>is isolated from the circuit <b>700</b><i>b </i>by a dielectric layer (not shown), and the circuit <b>700</b><i>a </i>is electrically coupled to the circuit <b>700</b><i>b </i>by a via hole <b>702</b>.

0047Referring to both <figref idref="DRAWINGS">FIG. 1</figref> and <figref idref="DRAWINGS">FIG. 7</figref> simultaneously, in the present embodiment, the circuit <b>700</b><i>a </i>and circuit <b>700</b><i>b </i>are electrically coupled to the via stud <b>702</b> directly without the help of the conventional via land <b>102</b><i>a </i>and <b>102</b><i>b </i>(as shown in <figref idref="DRAWINGS">FIG. 1</figref>). Therefore, the layout space of the circuit layer in the present embodiment is not reduced by the limitation of the via land <b>102</b><i>a </i>and <b>102</b><i>b. </i>

0048In summary, the laminated substrate structure of the present invention and the manufacture method thereof at least has the following advantages:

00491. In the laminated substrate structure of the present invention, the contact position of the circuit layer and the via adopts a landless design, so that the circuit integration in the laminated substrate is significantly improved.

00502. In the laminated substrate structure of the present invention, the via stud adopts a solid via design to give it good electrical performance and good thermal performance.

00513. In the laminated substrate structure of the present invention, the laminated substrate is formed by using the methods of pattern process and simultaneous lamination, so that the manufacture time can be efficiently reduced, and the productivity is further improved.

00524. In the laminated substrate structure of the present invention, the laminated substrate is formed by using the method of pattern process and synchronous lamination, so that the conventional investment in other equipment can be saved.

00535. In the laminated substrate structure of the present invention, before each layer (the dielectric layer having the patterned circuit, the dielectric layer having the via stud, and the via opening layer) is laminated, the confirmation of acceptable quality can be made onto each layer respectively, so that the yield of the laminated substrate can be easily controlled and the manufacture cost can be efficiently reduced.

0054Although the invention has been described with reference to a particular embodiment thereof, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed description.