Diversity receiver with joint automatic gain control signal processing

0001This is a divisional of application Ser. No. 09/363,813, filed on Jul. 30, 1999 now U.S. Pat. No. 6,560,299.

FIELD OF THE INVENTION

0002The present invention relates to diversity receivers.

BACKGROUND OF THE INVENTION

0003Conventional television signals transmit video information in analog form by modulating the amplitude and frequency of a carrier signal. Digital television systems convert an analog video signal into digital information, which is transmitted by pulse modulating the amplitude and phase of a carrier signal. For example, in broadcasting high definition television (HDTV), digital information is transmitted by an 8 level amplitude modulation technique, known as 8VSB (vestigial sideband). In 8 VSB, modulation of a carrier to one of 8 levels (i.e., one of 8 symbols) defines 3 bits of digital information for each symbol clock interval. While analog television signals degrade gracefully in the presence of interference, digital broadcast systems can fail completely when the bit error rate overcomes the error tolerance of the system. Bit errors result from weak signals, noisy signals or signals subject to fading and distortion.

0004In an ideal radio wave propagation environment, there exists an unobstructed line-of-sight path between the transmitting and receiving antennas. Additionally, no other objects exist which may reflect the transmitted wave along another path to the receiving antenna. As is more often the case, however, there is no direct line of sight between the antennas. In an outdoor environment, natural or artificial obstructions, such as buildings, hills, and trees block the direct line of sight. Furthermore, these obstructions reflect the transmitted signal such that multiple versions with varying amplitudes, phases and time delays are simultaneously received.

0005The indoor environment is even more complicated since there is rarely an unobstructed path between the transmitter and receiver antennas. Furthermore, objects causing signal reflection and absorbtion are numerous and are often in motion.

0006Reception of the transmitted signal along multiple paths from the transmitter to the receiver causes signal distortion which manifests itself in a variety of ways. The different paths have different delays that cause replicas of the same signal to arrive at different times (like an echo) and sum at the receiver antenna, causing inter-symbol interference. The phases of these multipath signals may combine constructively or destructively resulting in large range of possible signal strengths. Additionally, this signal strength may vary with time or antenna location, and is known as signal fading. Signal fading can range from frequency selective fades to a flat fade over the entire frequency spectrum of interest. Indoor signals typically have severe multi-path distortions and are changing rapidly in time, ranging from flat fades to deep in-band nulls to relatively unimpaired signals. Conventional indoor TV antennas and outdoor antennas used with existing 8VSB receivers often do not produce reliable and uninterrupted reception of digital broadcast HDTV signals.

0007To mitigate the adverse effects of multiple path (multipath) distortion and signal fading, it is known to use a diversity receiver. In a diversity receiver, two (or more) independent antennas are used to receive two (or more) separate versions of the same signal. Each independent antenna provides a signal with different (ideally, uncorrelated) noise, fading and multi-path factors. These different signals may be obtained through various forms of diversity including spatial, temporal, polarization and direction-of-arrival diversity.

0008A diversity receiver has a plurality of receiver channels to process the plurality of antenna signals. By appropriate combining of the information extracted from each signal by each channel of the diversity receiver, a diversity receiver provides equal or superior performance compared to a non-diversity receiver operating on the “best” of the received signals alone.

0009In the prior art, the received signals in each of the individual receiver channels of a diversity receiver are processed separately and then combined. That is, each of the multiple receiver channels in a prior art diversity receiver is an independent receiver. Each of the respective diversity antenna signals is processed in one of the independent receiver channels of the diversity receiver.

0010Each receiver channel is independent in the sense that each includes a respective separate tuner, front-end function (such as for baud clock recovery and carrier recovery) and separate equalizer filter. The separate receiver channels of the prior art provide separate signal outputs, which are then combined in some manner.

0011In one prior art approach, the output of the separate diversity receiver channel having the stronger input signal (i.e., the higher signal to noise ratio) is selected over the output of the diversity receiver channel having the weaker input signal. In a second prior art approach, the outputs of the two diversity receiver channels are combined equally, regardless of input signal strength. In a third prior art approach, the outputs of the two receiver channels are combined in a maximal ratio combiner in accordance with the respective signal to noise ratio of each signal. In a maximal ratio combiner, the receiver channel with the highest signal to noise ratio provides the greatest contribution to the final output. In general, a prior art diversity receiver processes the received diversity signals in separate receiver channels with regard to receiver functions such as tuning, automatic gain control (AGC), baud clock recovery, RF carrier recovery, and forward equalization.

SUMMARY OF THE INVENTION

0012In one embodiment of a diversity antenna system for use in conjunction with the present invention, first and second identical antennas are separated, but oriented identically within a plane. The first and second antennas are separated by several wavelengths to provide respective first and second RF signals. The first and second RF signals are said to be reception by the use of spatial diversity since it is known that the multipath propagation channels (in a parameterized sense) from the transmitter to the first antenna and from the transmitter to the second antenna are nearly uncorrelated.

0013The present invention is embodied in a multiple channel diversity receiver with joint signal processing. In particular, the first and second RF signals are processed jointly in a multiple channel diversity receiver with respect to tuning, automatic gain control (AGC), baud clock recovery, RF carrier recovery and forward equalization. Joint processing, as compared to independent processing of the prior art, means that the multiple channels of the diversity receiver are linked or cross coupled to each other through various joint processing circuitry.

Tuning

0014In accordance with the present invention, the first and second RF signals are processed jointly in the multiple channel diversity receiver with respect to tuning. In particular, the first and second tuners in the first and second channels of the multiple channel diversity receiver share at least one joint local oscillator. In the case of a dual conversion tuner, first and second joint local oscillators are shared. A first joint local oscillator is shared in the RF stage of the first and second tuners, and a second joint local oscillator is shared in the IF stage of the first and second tuners. By sharing one or more joint local oscillators in separate tuners, the first and second channels of the multiple channel diversity receivers will therefore be coherent in frequency and phase and thus have common phase noise characteristics.

Automatic Gain Control (AGC)

0015In accordance with the present invention, the first and second RF signals are processed jointly in the multiple channel diversity receiver with respect to AGC. In particular, the respective tuners in the first and second channels of the multiple channel diversity receiver share at least one joint AGC loop. The maximum difference between the AGC feedback signal in the control loop for the first channel and the AGC feedback control signal in the control loop for the second channel is limited to a selectable maximum differential.

0016For example, suppose that the first RF signal in the first channel is a much stronger signal as compared to the second RF signal in the second channel. The first AGC loop amplifies the first RF signal very little, if at all, because it is already a strong signal. The second RF signal in the second channel is likely to be noisy because it is a relatively weak signal. In the prior art, the weaker noisy signal in the second channel would be greatly amplified by the AGC control loop of the second channel. Noise amplified in the AGC control loop second channel increases the noise problems and worsens the overall bit error rate when the first and second channels of the diversity receiver are combined equally.

0017In accordance with the present invention, the AGC control loop with the stronger first RF signal limits the maximum amount that the weaker signal is amplified in the AGC control loop with the weaker second RF signal. By limiting the AGC feedback signal in the control loop of the second channel to a maximum differential with respect to the AGC feedback signal in the control loop of the first channel, the weaker signal is not overly amplified. In such manner, the noise in the weaker noisy signal in the second channel would not be as greatly amplified by the joint AGC control loop of the second channel, as it would be in the case of an independent AGC loop.

Joint Timing Loop—Baud Clock Recovery

0018The baud clock is roughly equivalent to the data symbol clock. As in the above example for 8VSB each data symbol is 3 bits. The baud clock timing determines the point in time when the received signal is “sampled” to determine which of the 8 levels is represented by the current data symbol. In a diversity receiver, there is a separate baud clock recovery mechanism for each channel, each respective recovered baud clock representing the regular points in time at which the received signal is sampled to recover a data symbol in that respective channel. Known prior art techniques for recovering the baud clock include adaptive algorithms for estimating the energy at the edge of the data spectrum. In the general case, the baud clock timing will fall somewhere in between actual signal samples. An interpolator is used to interpolate between actual signal samples to obtain a signal “sample” at the baud clock timing.

0019The first and second RF signals are processed jointly in the multiple channel diversity receiver with respect to individual baud clock recovery. Although separate baud clocks are recovered for each channel, the baud clocks are recovered in a joint timing loop shared by both channels.

0020In accordance with the present invention, the respective front ends in the first and second channels of the multiple channel diversity receiver share a joint timing loop filter for baud clock recovery. The baud clock for each channel is synthesized in a respective phase locked loop (PLL) for each channel. Since both channels are assumed to be receiving the same signal, the received signal frequency in both channels is the same. The primary timing difference between the signals in the first and second channels is in the phase of each respective baud clock.

0021In accordance with the present invention, the timing loop filters of each channel are cross coupled to create a joint timing loop between both channels. By cross coupling the two PLL's in a joint loop filter, one channel (with the stronger signal) provides a dominant influence on the frequency of the synthesized baud clock in the other channel (with the weaker signal). By sharing a joint loop filter, the baud clock PLL in both channels will tend to be frequency locked to the frequency of the stronger signal, leaving the respective PLL's to make an individual phase adjustment for each channel. In such manner, the stronger signal in the first channel is used to determine the frequency of the baud clock for the weaker signal in the second channel.

0022In addition, the respective front ends in the first and second channels of the multiple channel diversity receiver share a skew corrector for baud clock recovery. A skew correction is needed when the multipath delay between the first and second RF signals in the two channels is greater than one whole baud clock period. That is, even though the frequency and phase of the respective baud clock for received signals in the first and second channels is determined in the joint timing loop, there may be whole baud skews between the two received signals. The purpose of the whole baud skew corrector is to align the received data bits in the first channel with the received data bits in the second channel.

0023In accordance with the present invention, a whole baud skew corrector is provided, which couples the first and second channels of the diversity receiver in a joint timing loop for baud clock recovery. In particular, after the joint loop filter of the joint timing loop settles down near steady state frequency and phase for each respective baud clock, the whole baud skew corrector is enabled.

0024The whole baud skew corrector computes the correlation between the first and second received signals. First and second signals without any skew (i.e., properly aligned signals) show high correlation values. First and second signals with substantial skew between the two signals show low correlation values. The first and second signals are then shifted by one whole baud period with respect to each other in a variable delay memory and the correlation is recomputed. The process of shifting the first and second received signals and computing the correlation function is repeated for various whole baud shifts in accordance with a search strategy to find the best (highest) correlation. The whole baud skew corrector shifts one or both channels in respective variable delay memories to properly align the received first and second signals in accordance with the whole baud skew delay that produced the best correlation between the first and second received signals.

Joint Pilot Loop—RF Carrier Recovery

0025In order to demodulate (de-rotate) the received signal, the original RF carrier is recovered at the receiver. A separate RF carrier is recovered for each of the first and second channels in the diversity receiver and used to de-rotate each of the first and second received signals.

0026In accordance with the present invention, the respective front ends in the first and second channels of the multiple channel diversity receiver share a joint pilot loop filter for RF carrier recovery. The RF carrier signal for each channel is synthesized in a respective phase locked loop (PLL) for each channel. However, since both channels are assumed to be receiving different (multipath) versions of the same signal, the frequency of the RF carrier is the same in both channels. The difference between synthesis of the RF carrier in the two channels is the phase of each respective synthesized RF carrier in each respective channel.

0027In accordance with the present invention, the respective front ends of the multiple channel diversity receiver share a joint pilot loop filter in the respective PLL for RF carrier clock recovery in the first and second channels. In particular, the pilot loop filters of each channel are cross coupled to create a joint pilot loop between both channels.

0028By cross coupling the two RF carrier recovery PLL's in a joint loop filter, the channel with the stronger signal provides a dominant influence on the frequency of the synthesized recovered RF carrier in the channel with the weaker signal. By sharing a joint loop filter, the phase locked pilot loops in both channels will tend to be frequency locked to the stronger signal, leaving the respective phase locked pilot loops to make an individual phase adjustment for each channel. In such manner, the stronger signal in one channel is used to determine the frequency of the recovered RF carrier signal for the weaker signal in the other channel.

Forward Equalization

0029In accordance with another aspect of the present invention, the first and second RF signals are processed jointly in the multiple channel diversity receiver with respect to forward equalization. In particular, the respective first and second channels of the multiple channel diversity receiver share a common equalization filter tap allocation scheme. That is, the number of available equalization filter taps is allocated to either the first channel or the second channel on the basis of relative need.

0030By way of background review, it is known to use an equalizer to mitigate the signal corruption introduced by the communications channel. An equalizer is a filter that has the inverse characteristics of the communication channel. In situations where the communication channel is not characterized in advance, or changes with time, an adaptive equalizer is used. The variable parameters (filter coefficients) of the adaptive equalizer are calculated at the receiver. After the filter parameters are properly adjusted, the equalizer filter compensates for transmission channel distortion and noise. The problem to be solved in an adaptive equalizer is how to adjust the equalizer filter parameters in order to restore signal quality to a performance level that is acceptable by subsequent error correction decoding.

0031A critical factor in an adaptive equalization system is to complete all the required multiplication operations within the time available: i.e., a single symbol interval. In particular, the calculation of filter parameters requires successive multiply operations for each equalizer parameter. Since a typical equalizer filter may have up to 512 filter coefficients (the number of equalizer filter parameters), the total time required to complete all the required multiplication operations with full precision often exceeds one symbol interval.

0032Using an equalization filter with fewer taps (coefficients) requires less computation time, but a filter with fewer coefficients is a poorer approximation to the inverse of the communication channel distortion. On the other hand, the communication channel typically introduces distortion which is clustered around certain time delays, so that most of the filter coefficients will be set to zero or near zero anyway. Therefore, an equalization filter with fewer taps could be used, provided the nonzero taps are at the correct positions.

0033The present invention is embodied in a tap allocation mechanism in a diversity receiver to allocate more of the available filter taps to the channel with the greater distortion and noise. The total numbers of taps to be allocated between both the first and second channels is fixed. At the start of adaptation, each equalization filter is initialized with an equal number of taps. The taps are thereafter dynamically allocated to the equalization filters of either the first or second channels on the basis of actual received signals. Thus, if both channels have equal signal path distortions, the number taps will be equally allocated to the equalization filter in each channel. On the other hand, if the signal in the first channel has greater signal path distortion than the signal in the second channel, then more equalizer taps will be allocated to the equalization filter of the first channel (and less equalizer taps allocated to the equalization filter of the second channel). In such manner, equalizer taps are efficiently allocated to the equalization filter in the channel where it is most needed.

BRIEF DESCRIPTION OF THE FIGURES

<figref idref="DRAWINGS">FIG. 1</figref> is a system block diagram of a multiple channel diversity receiver embodying the joint signal processing of the present invention.

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of a prior art diversity receiver.

<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram of a joint tuner for use in a multiple channel diversity receiver in accordance with the present invention.

<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram of a joint AGC loop for use in a multiple channel diversity receiver in accordance with the present invention.

<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram of a joint receiver front end for use in a multiple channel diversity receiver in accordance with the present invention.

<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of a joint timing loop for baud clock recovery for use in a multiple channel diversity receiver in accordance with the present invention.

<figref idref="DRAWINGS">FIG. 6A</figref> is a block diagram of an interpolator/variable delay <b>514</b>A, <b>514</b>B in the joint timing loop for baud clock recovery of <figref idref="DRAWINGS">FIG. 6</figref> for use in conjunction with the present invention.

<figref idref="DRAWINGS">FIG. 6B</figref> is a block diagram of the enable control logic <b>618</b> in the joint timing loop for baud clock recovery of <figref idref="DRAWINGS">FIG. 6</figref> for use in conjunction with the present invention.

<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram of a joint pilot loop for RF carrier recovery for use in a multiple channel diversity receiver in accordance with the present invention.

<figref idref="DRAWINGS">FIG. 8A</figref> is a block diagram of a generalized joint loop filter in accordance with the present invention for use in the joint timing loop of <figref idref="DRAWINGS">FIG. 6</figref> and joint pilot loop of <figref idref="DRAWINGS">FIG. 7</figref>.

<figref idref="DRAWINGS">FIG. 8B</figref> is a block diagram of a specific joint loop filter in accordance with the present invention for use in the joint timing loop of <figref idref="DRAWINGS">FIG. 6</figref> and joint pilot loop of <figref idref="DRAWINGS">FIG. 7</figref>.

<figref idref="DRAWINGS">FIG. 9A</figref> is a block diagram partially in flow chart form of the skew corrector logic <b>614</b> in <figref idref="DRAWINGS">FIG. 6</figref> in accordance with the present invention.

<figref idref="DRAWINGS">FIG. 9B</figref> is a flow chart diagram of the control logic <b>926</b> in <figref idref="DRAWINGS">FIG. 9A</figref> embodying the present invention.

<figref idref="DRAWINGS">FIG. 9C</figref> is an illustration of time shift values for successive iterations for use in conjunction with skew correction the present invention.

<figref idref="DRAWINGS">FIG. 10</figref> is a block diagram of a forward equalizer with dynamic tap allocation in accordance with the present invention.

DETAILED DESCRIPTION

System

0049A prior art diversity receiver with two channels responsive to first and second antennas <b>202</b>, <b>218</b> is shown in <figref idref="DRAWINGS">FIG. 2</figref>. The first channel includes a tuner <b>204</b>, a front end signal processor <b>206</b> and a forward equalizer <b>208</b>. The second channel includes a separate tuner <b>220</b>, a separate front end signal processor <b>222</b> and a separate forward equalizer <b>224</b> each of which are independent of the corresponding functions in the first channel. The respective output of each of the two separate and independent channels of the diversity receiver are combined together in combiner <b>210</b>, which combines the first and second channels of the diversity receiver into a single channel containing one combined signal. As indicated, there are numerous strategies in the prior art for combining the output signals from the channels of a multiple channel diversity receiver. The output of combiner <b>210</b> is coupled to a feedback equalization filter, comprising adder <b>212</b>, slicer <b>214</b> and decision feedback equalizer (DFE) filter <b>216</b>.

0050A multiple channel diversity receiver system with joint processing of first and second signals in respective first and second channels in accordance with the present invention is shown in <figref idref="DRAWINGS">FIG. 1</figref>. Joint processing of first and second signals shall mean herein that the processing of the first signal shall effect or influence the processing of the second signal with respect to the same signal processing function. Also, as used herein, the terms, “channel”, “receiver channel”, “channel A” and “first channel”, and “channel B” and “second channel” are equivalent terms. A diversity receiver has at least two channels. Each channel begins at the respective antenna input terminal and continues to process separate first and second RF (radio frequency) signals up to the point where the signals in the two channels are combined into one combined signal, which is thereafter processed in a single combined channel. After forming the one combined signal in the single combined channel, the signal contributions from the original first and second RF signals can no longer be separately and independently processed.

0051With reference to <figref idref="DRAWINGS">FIG. 1</figref>, the diversity receiver has first and second channels coupled to respective first and second antennas <b>10</b>. A compound antenna <b>10</b> is comprised of two separate antennas loops A and B, which are positioned within a plane, oriented identically, and separated by several wavelengths. While <figref idref="DRAWINGS">FIG. 1</figref> illustrates a two channel, two dimensional diversity receiver system, a three dimensional system may be created by the addition of a third spatially separated and a third receiver channel. Higher order dimensions may be created by adding additional antennas and additional receiver channels.

0052A first channel of the diversity receiver consists of a tuner <b>12</b>A, a front end <b>18</b>A and a forward equalizer <b>24</b>A. A second channel of the diversity receiver consists of a tuner <b>12</b>B, a front end <b>18</b>B and a forward equalizer <b>24</b>B. The first and second channels of the diversity receiver are not independent, but include joint signal processing as described below.

0053The first and second tuners <b>12</b>A, <b>12</b>B process signals jointly by sharing a joint local oscillator <b>14</b> and a joint AGC loop <b>16</b>. After the tuning stages, the first and second signals at the output of tuners <b>12</b>A and <b>12</b>B are converted from analog to digital in respective A/D converters (not shown). The resulting streams of digital samples are input to respective first and second front ends <b>18</b>A, <b>18</b>B. The first front end <b>18</b>A and the second front end <b>18</b>B process signals jointly by sharing a joint timing loop <b>20</b> for baud clock recovery and a joint pilot loop <b>22</b> for carrier recovery. After the front end processing, the first and second signals of the first and second channels are coupled to an equalizer with joint signal processing. In particular, the first and second signals at the output of the first and second front ends <b>18</b>A, <b>18</b>B are coupled to respective forward equalizer filters <b>24</b>A, <b>24</b>B. The first and second signals are further processed jointly in the forward equalizer filters <b>24</b>A, <b>24</b>B by dynamically allocating <b>26</b> equalization filter taps among the first and second forward equalizers <b>24</b>A, <b>24</b>B.

0054The first and second signals at the respective outputs of the first and second equalizer filters <b>24</b>A, <b>24</b>B are added in combiner <b>28</b> and processed in a joint feedback equalization filter, which comprises adder <b>30</b>, slicer <b>32</b> and decision feedback equalizer filter <b>34</b>. Joint processing of the first and second channels is achieved by dynamic tap allocation <b>33</b> to allocate equalization filter taps of the DFE <b>34</b> among the signal samples of the first and second channels.

Joint Tuner, Shared Local Oscilators—FIG.

3

0055A joint dual channel, dual conversion tuner with shared local oscillators, is shown in <figref idref="DRAWINGS">FIG. 3</figref>. Respective inputs from antenna A and antenna B are coupled to each of first and second channels. Each joint tuner channel includes an RF conversion stage with an RF band pass filter <b>302</b>, <b>320</b>, an RF AGC stage <b>304</b>, <b>322</b>, a mixer <b>306</b>, <b>324</b> and a first IF (intermediate frequency) band pass filter <b>308</b>, <b>326</b>. Each joint tuner channel further includes a second conversion stage with a second mixer <b>310</b>, <b>328</b>, second IF SAW filter <b>312</b>, <b>330</b> and IF AGC stage <b>314</b>, <b>332</b>. The first and second tuner channels share a joint first (RF) local oscillator <b>316</b> coupled to mixers <b>306</b> and <b>324</b>. In addition, the first and second tuner channels share a joint second (IF) local oscillator <b>318</b> coupled to mixers <b>310</b> and <b>328</b>.

Joint Tuner, Shared Automatic Gain Control (AGC)—FIG.

4

0056The joint AGC loop <b>16</b> of <figref idref="DRAWINGS">FIG. 1</figref> is shown in further detail in <figref idref="DRAWINGS">FIG. 4</figref>. The joint AGC includes a power estimator <b>402</b>, <b>412</b> for each channel, a reference <b>408</b>, integrators <b>414</b>, <b>416</b> and adders <b>404</b>, <b>410</b>, <b>420</b>, <b>426</b> and <b>428</b>. A power estimator is a signal level sensing circuit, which provides a measure of the signal level (in this case, power) for comparison with a target reference level <b>402</b>, <b>412</b>. In addition there is provided a signed comparator <b>406</b>, cross multiplexors <b>418</b>, <b>424</b> and an asymmetrical clipper <b>422</b>. A cross multiplexor is a switching device for connecting two inputs to two outputs. Responsive to a control input, a cross multiplexor either directly connects, or cross connects (swaps) its two inputs and two outputs. An asymmetrical clipper <b>422</b> limits the most negative excursion of an input signal to a predetermined value at the output of the asymmetrical clipper.

0057The joint AGC of <figref idref="DRAWINGS">FIG. 4</figref> jointly processes AGC signals so as to limit the amount that the weaker signal will be boosted by AGC action as compared to the AGC boost of the stronger signal. The joint AGC detects the channel with stronger signal and adjusts the AGC for that channel so as to meet the target reference level in that channel. The joint AGC then limits the maximum difference for the AGC adjustment level in the other channel. Initially a target reference <b>408</b> is set to the desired signal power level.

0058In operation, a power estimate for signal output from tuner A (and tuner B) is made in a power estimator <b>402</b> (<b>412</b>). The output of the power estimator is subtracted from the target reference level <b>408</b> (which represents the desired signal power level of the stronger signal). The error at the output of adder <b>404</b> (<b>410</b>) is integrated <b>414</b> (<b>416</b>) to form Gain A signal (Gain B signal). Gain A and Gain B are inputs to comparator <b>406</b> and to cross multiplexor <b>418</b>. Comparator <b>406</b> determines which receiver channel has a greater Gain signal (in a signed magnitude sense).

0059If Gain A is greater than Gain B, then the comparator <b>406</b> causes cross multiplexors <b>418</b> and <b>424</b> to switch their respective inputs to their respective outputs. The greater Gain signal (most positive) is always on the negative input to adder <b>420</b>. Alternatively, the positive input to adder <b>420</b> always has the smaller (more negative) Gain signal. The output of adder <b>420</b> represents the Gain difference (between channel A and channel B), and is always a negative number. The asymmetric clipper in <b>422</b> limits the most negative excursion of the Gain difference between channel A and channel B. The value of the clipped level in the asymmetrical clipper <b>422</b> represents the maximum permissible difference in the AGC Gain signals for channel A and channel B.

0060To adjust the AGC gain in channel A and channel B, cross multiplexor <b>424</b>, responsive to the decision made by comparator <b>406</b>, outputs either a 0 or the clipped value of the Gain difference from asymmetrical clipper <b>422</b>. Cross multiplexor <b>424</b> selects a zero value to be added to the Gain signal of the receiver channel that has the lesser Gain signal. In such manner, the channel with the greater received signal power has zero added to its respective AGC Gain signal in one of adders <b>426</b> or <b>428</b>. Cross multiplexor <b>424</b> selects the clipped Gain difference (a negative number at the output of asymmetrical clipper <b>422</b>) to be added (signed addition) to the Gain signal of the receiver channel that has the greater Gain signal. In such manner, the channel with the smaller received signal power has the clipped gain difference added (by signed addition) to its respective AGC Gain signal in one of adders <b>426</b> or <b>428</b>.

0061The desired AGC Gain signal for channel A (B) is provided at the output of adder <b>426</b> (<b>428</b>). The total desired AGC gain is divided between RF AGC and IF AGC. In particular, a splitter <b>430</b> (<b>432</b>) divides the desired AGC Gain signal between RF AGC Gain and IF AGC Gain.

Joint Front End—FIG.

5

0062A joint front end processor with dual joint channels is shown in <figref idref="DRAWINGS">FIG. 5</figref>. The dual joint channels in the joint front end processor include a dual channel joint timing loop <b>510</b> and a dual channel joint pilot loop <b>512</b>. As indicated, the purpose of the joint timing loop <b>510</b> is to recover the baud clock timing in each respective channel. The purpose of the joint pilot loop <b>512</b> is to recover the carrier signal which is used for demodulating (derotating) the received signal in each respective channel. Both the baud clock and the carrier signal are recovered in respective phase locked loops using respective joint loop filters.

Joint Loop Filter for use in PLL's—FIGS.

8

A,

8

B

0063A key element for use in the joint front end of <figref idref="DRAWINGS">FIG. 5</figref>, by which joint processing is implemented, is the joint loop filter illustrated in the general case in <figref idref="DRAWINGS">FIG. 8A</figref> and in the special case of <figref idref="DRAWINGS">FIG. 8B</figref>. <figref idref="DRAWINGS">FIG. 5</figref> incorporates the joint loop filters of <figref idref="DRAWINGS">FIG. 8A</figref> or <b>8</b>B by reference. That is, the block diagram of <figref idref="DRAWINGS">FIG. 5</figref> references <figref idref="DRAWINGS">FIG. 6</figref> and <figref idref="DRAWINGS">FIG. 7</figref> for further detail. However <figref idref="DRAWINGS">FIGS. 6 and 7</figref> both reference <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> for further details of a joint loop filter. Therefore, the joint loop filter of either of <figref idref="DRAWINGS">FIG. 8A</figref> or <b>8</b>B is incorporated by reference into <figref idref="DRAWINGS">FIG. 5</figref>.

0064By way of brief review, a loop filter is used in the feedback path of a phase locked loop (PLL). A PLL is closed loop feedback control system for controlling the frequency and phase of an oscillator. The controlled oscillator may be a numerically controlled oscillator (NCO) responsive to a numerical input that counts out the period of the desired sine wave or cosine wave (as in <figref idref="DRAWINGS">FIG. 6</figref>). The controlled oscillator may alternatively be a sine/cosine generator that directly synthesizes a sine wave or cosine wave responsive to a numerical input (as in <figref idref="DRAWINGS">FIG. 7</figref>). The controlled oscillator may also be a voltage controlled oscillator (VCO) responsive to an input voltage.

0065In the prior art, a separate and independent PLL operates as follows: The phase error estimate of the output signal to be controlled is detected in a phase detector. The PLL loop filter is responsive to the phase error signal from the phase detector to determine a value for the numerical control signal to the controlled oscillator. The output of the loop filter thus controls the frequency and phase of the controlled oscillator. The controlled oscillator in turn changes its output responsive to the control input. The new (changed) phase error is measured by the phase detector, which changes the input to the loop filter. The process continues until the PLL converges (and locks) to a stable tracking state reducing (and keeping) the frequency and phase error of the controlled oscillator to an acceptably low value.

0066The joint loop filter of the present invention is used to cross couple two phase locked loops together for joint signal processing. A joint loop filter with a variable coupling factor (alpha) is shown in <figref idref="DRAWINGS">FIG. 8A</figref>. A first loop filter includes multiplication by constants K<b>1</b>A (<b>802</b>A) and K<b>2</b>A (<b>804</b>A), a delay element <b>808</b>A, and adders <b>806</b>A and <b>810</b>A. A second loop filter includes multiplication by constants K<b>1</b>B (<b>802</b>B) and K<b>2</b>B (<b>804</b>B), a delay element <b>808</b>B, and adders <b>806</b>B and <b>810</b>B.

0067The first loop filter and the second loop filter are joined together to form a joint loop filter by the addition of adders <b>812</b>A, <b>812</b>B and multipliers <b>811</b>A, <b>811</b>B which multiply by the cross coupling factor, alpha. The cross coupling factor, alpha, determines the amount of cross coupling between the first loop filter and the second loop filter. If alpha <b>811</b>A is set to zero, then adder <b>812</b>A does not add anything to the first loop filter output. Therefore, when alpha=0, the first loop filter <b>802</b>A, <b>804</b>A, <b>806</b>A, <b>808</b>A, <b>810</b>A form an independent PLL loop filter. Similarly, when alpha=0, the second loop filter <b>802</b>B, <b>804</b>B, <b>806</b>B, <b>808</b>B, <b>810</b>B form an independent PLL loop filter.

0068However, when alpha is non-zero, a portion of the output of adder <b>806</b>B in the second loop filter is introduced into the first loop filter through adder <b>812</b>A. At the same time, a portion of the output of adder <b>806</b>A in the first loop filter is introduced into the second loop filter through adder <b>812</b>B. Thus, the first and second loop filters are cross coupled, whereby each loop filter contributes to a portion of the output of the other loop filter. Setting alpha equal to 1 represents full coupling between the first loop filter and the second loop filter. The special case of full coupling (alpha=1) is shown in <figref idref="DRAWINGS">FIG. 8B</figref>.

0069In <figref idref="DRAWINGS">FIG. 8B</figref>, a first loop filter comprises multiplication by constant K<b>1</b>A (<b>814</b>A) and constant K<b>2</b> (<b>816</b>), adder <b>818</b>, a delay element <b>822</b>, and adder <b>824</b>A. A second loop filter comprises multiplication by constant K<b>1</b>B (<b>814</b>B) and constant K<b>2</b> (<b>816</b>), adder <b>818</b>, a delay element <b>822</b>, and adder <b>824</b>B. Thus, the first loop filter and the second loop filter share a common multiply factor K<b>2</b><b>816</b>, adder <b>818</b>, adder <b>820</b> and delay element <b>822</b>. The joint loop filter (<figref idref="DRAWINGS">FIGS. 8A</figref>, <b>8</b>B) is used in both the joint timing loop (<b>616</b> in <figref idref="DRAWINGS">FIG. 6</figref>) and the joint pilot loop (<b>716</b> in <figref idref="DRAWINGS">FIG. 7</figref>).

0070Each joint loop filter has two constants K<b>1</b> (K<b>1</b>A or K<b>1</b>B) and K<b>2</b> and a delay <b>822</b>. The delay <b>822</b> is a one sample memory, which, together with adder <b>820</b> forms an integrator common to channel A and channel B. Constants K<b>1</b>A, K<b>1</b>B, and K<b>2</b> are parametric values which are changed as necessary. For example, one set of values for K<b>1</b>A, K<b>1</b>B and K<b>2</b> is used during signal acquisition, and a different set of values is used during signal tracking after acquisition.

0071Multiplication of the input phase error by constant K<b>1</b> (K<b>1</b>A or K<b>1</b>B) represents the phase offset, or proportional phase error, in the output of the loop filter. Multiplication of the input phase error by constant K<b>2</b>, integrated in the integrator formed by adder <b>820</b> and delay <b>822</b> represent the frequency offset, or instantaneous frequency error, in the output of the loop filter. However, the input to the integrator (scaled first by K<b>2</b>) is the sum of the input phase error in channels A and B, which sum, formed in adder <b>818</b>, links the signal processing in channels A and B. Channel A and channel B thus share a common constant K<b>2</b> and common integrator (adder <b>820</b> and delay <b>822</b>). Furthermore, the frequency error at the output of adder <b>820</b> is added to both the channel A control signal via adder <b>824</b>A, and also added to the channel B control signal via adder <b>824</b>B.

0072In such manner, the dual phase locked loops of a joint phase locked loop are linked through the joint loop filter to share a common frequency. Since the dual channels of the diversity receiver are receiving different versions of the same signal (via multipath), the common frequency of each of the phase locked loops is assumed to be correct and the same in each channel. The remaining job of each of the phase locked loops is to adjust for phase error (via K<b>1</b>A, K<b>1</b>B) in each of the dual channels of the diversity receiver.

0073Since the frequency of the signal in both channels must be the same, a shared constant K<b>2</b> helps the phase locked loops track each other. By sharing constant K<b>2</b> and integrator <b>820</b>, <b>822</b>, the channel with the stronger signal tends to frequency lock the phase locked loop in the channel with the weaker signal. In such manner, the first and second signals in the first and second channels of the diversity receiver are frequency locked but not phase locked.

0074In operation, phase error estimates from each channel are summed in added <b>818</b>, scaled <b>816</b> by the constant K<b>2</b> (integral parameter) and accumulated in the integral portion (delay <b>822</b>) of the joint loop filter. The individual phase estimates are also scaled by the respective K<b>1</b>A, K<b>1</b>B (proportional parameter) and combined with the common integral value from adder <b>820</b> in adders <b>824</b>A and <b>824</b>B. The output of the respective adders <b>824</b>A and <b>824</b>B are applied to the respective NCO's of the first and second channels respectively, of the diversity receiver.

0075Returning to <figref idref="DRAWINGS">FIG. 5</figref>, a joint timing loop <b>510</b> comprises a first interpolator/variable delay <b>514</b>A, coupled to receive an output (output A) from the joint tuner, and having an output coupled to a Matched filter/Pre filter <b>516</b>A. The second channel of the joint timing loop <b>510</b> comprises a second interpolator/variable delay <b>514</b>B, coupled to receive the other output (output B) from the joint tuner, and having an output coupled to a Matched filter/Pre filter <b>516</b>B. A description of the Matched filter/Pre filter <b>526</b>A, <b>516</b>B and its operation may be found in U.S. Pat. No. 5,872,815. The signal nomenclature for the Matched filter/Pre filter output signals is that Mf=Matched Filter, pb=passband, bb=baseband, a=channel A, and b=channel B.

0076A joint timing control <b>520</b> is coupled to the Mf_—pb_—a and Pf_—pb_—a outputs of Matched filter/Pre filter <b>516</b>A, and to the Mf_—pb_—b and Pf_—pb_—b outputs of Matched filter/Pre filter <b>516</b>B. Finally, the joint timing control <b>520</b> is coupled to, and controls both interpolator/variable delays <b>514</b>A and <b>514</b>B. A joint pilot loop <b>512</b> includes a first derotator (demodulator) <b>518</b>A coupled to receive the respective Mf_—pb_—a and Pf_—pb_—a outputs from Matched filter/Pre filter <b>516</b>A. The second channel of the joint pilot loop <b>512</b> includes a second derotator (demodulator) <b>518</b>B coupled to receive the respective Mf_—pb_—b and Pf_—pb_—b outputs from Matched filter/Pre filter <b>516</b>B. The outputs of the derotators <b>518</b>A, <b>518</b>B are the baseband versions of the respective input passband signals. Thus, the output for one channel of the joint pilot loop is Mf_—bb_—a, while the output for the other channel of the joint pilot loop is Mf_—bb_—b. A joint pilot loop control <b>522</b> is coupled to receive the Pf_—bb_—a output of derotator <b>518</b>A and the Pf_—bb_—b output of derotator <b>518</b>B. The joint pilot loop control <b>522</b> provides a recovered carrier signal to derotators <b>518</b>A and <b>518</b>B.

0077In operation, the two outputs from the dual tuner of <figref idref="DRAWINGS">FIG. 3</figref> (output A and output B) are input to the dual channel joint front end of <figref idref="DRAWINGS">FIG. 5</figref>. The joint timing loop <b>510</b> recovers the baud clock for each respective channel by jointly using signals from both receiver channels. The recovered baud clock timing is further used to shift the signal in channel A and channel B into relative time alignment by adjusting the amount of respective delays in the interpolator/variable delays <b>514</b>A and <b>514</b>B. Then, the joint pilot loop <b>512</b> generates a recovered carrier signal by using signals from both receiver channels to provide respective demodulated baseband outputs, Mf_—bb_—a and Mf_—bb_—b.

Front End, Joint Timing Loop (Baud Clock Recovery)—FIGS.

6

,

6

A,

6

B

0078The joint timing loop control <b>520</b> in <figref idref="DRAWINGS">FIG. 5</figref> is shown in further detail in <figref idref="DRAWINGS">FIG. 6</figref>. The first interpolator/variable delay <b>514</b>A and the first Matched filter/Pre filter element <b>516</b>A in <figref idref="DRAWINGS">FIG. 6</figref> correspond to the first receiver channel A. The second interpolator/variable delay <b>514</b>B and the second Matched filter/Pre filter element <b>516</b>B in <figref idref="DRAWINGS">FIG. 6</figref> correspond to the second receiver channel B. The remainder of <figref idref="DRAWINGS">FIG. 6</figref> within the dotted box <b>520</b> comprises the joint timing loop control <b>520</b> (from <figref idref="DRAWINGS">FIG. 5</figref>).

0079The joint timing loop control <b>520</b> comprises phase detectors <b>612</b>A, <b>612</b>B, NCO's <b>610</b>A, <b>610</b>B adders <b>622</b>A, <b>622</b>B, a joint loop filter <b>616</b>, a skew corrector <b>614</b>, a reference counter <b>620</b> and enable control logic <b>618</b>. However, to better understand the operation of the joint timing loop control <b>520</b> in <figref idref="DRAWINGS">FIG. 6</figref>, it is useful to first consider the internal structure of the interpolator/variable delay <b>514</b>A, <b>514</b>B, which is illustrated in further detail in <figref idref="DRAWINGS">FIG. 6A</figref>.

0080In <figref idref="DRAWINGS">FIG. 6A</figref>, an interpolator/variable delay <b>514</b> includes a circular ring buffer <b>634</b>, an 8-sample interpolator <b>632</b>, a FIFO length counter <b>630</b> and an AND gate <b>644</b>. The circular ring buffer <b>634</b> has a write pointer <b>636</b> and a read pointer <b>638</b>. A write data input terminal <b>640</b> provides data values to be stored at the memory location defined by the write pointer <b>636</b> in the circular ring buffer. The data values <b>633</b> from the circular buffer <b>634</b> are input to the 8-sample interpolator <b>632</b>, which computes an interpolated value over 8 samples, for output to be applied to one input of AND gate <b>644</b>. The other input to AND gate <b>644</b> is data valid indication <b>646</b>. When the data valid indication <b>646</b> is high, an interpolated value of data is read from the circular ring buffer <b>634</b> to the read data output <b>642</b>.

0081The 8-sample interpolator uses 4 samples from the circular ring buffer <b>634</b> prior to the current read pointer position <b>638</b> and 4 samples from the circular ring buffer <b>634</b> subsequent to the current read pointer position <b>638</b>. The interpolator <b>632</b> computes a current output value by interpolation over 8 samples. The interpolated output value is coupled via AND gate <b>644</b> to the read data output terminal <b>642</b>.

0082The circular ring buffer <b>634</b> functions as a low-power, variable length, first in, first out (FIFO) buffer. The variable length FIFO is formed by the portion of the circular ring buffer between the read/write pointers <b>638</b> and <b>636</b>. The length of the FIFO buffer thus is the number of memory locations between the write pointer <b>636</b> position and the read pointer <b>638</b> position. The dynamic FIFO buffer length is computed <b>630</b> and output as a FIFO count <b>631</b>. The write pointer <b>636</b> is positioned by a write pointer position control, which is coupled to the output of a reference counter <b>620</b>. The integer portion <b>609</b> of NCO <b>610</b> positions the read pointer <b>638</b>.

0083The fractional portion <b>611</b> of the NCO <b>610</b> to the interpolator <b>632</b> represents the baud timing point between actual data samples. The fractional portion <b>611</b>, is point at which the interpolated value over 8 samples is to be computed.

0084Returning to <figref idref="DRAWINGS">FIG. 6</figref>, the joint timing loop operates as follows: Reference counter <b>620</b> provides a constant sine/cosine output at a frequency slightly greater than the baud clock. The write pointers of both interpolator/variable delays <b>514</b>A, <b>514</b>B are driven from the reference counter <b>620</b> and are therefore locked in frequency and phase. All read and write pointers of both interpolator/variable delays <b>514</b>A, <b>514</b>B rotate in the clockwise direction. The read pointer of each circular buffer is controlled by the output of the respective NCO <b>610</b>A, <b>610</b>B. The read pointer of interpolator/variable delay <b>514</b>A is driven from the integer portion of NCO <b>610</b>A. In the other channel, the read pointer of interpolator/variable delay <b>514</b>B is driven from the integer portion of NCO <b>610</b>B. The fractional portion of NCO <b>610</b>A is used to adjust the interpolation phase (i.e., the sub-sample delay) in interpolator/variable delay <b>514</b>A. Similarly, the fractional portion of NCO <b>610</b>B is used to adjust the interpolation phase (i.e., the sub-sample delay) in interpolator/variable delay <b>514</b>B.

0085The joint timing loop control <b>520</b> operates in two distinct timed phases, termed part I an part II. In part I, the baud clock timing in the first channel A and the baud clock timing in second channel B are recovered to within one baud clock period. The variable delays <b>514</b>A, <b>514</b>B are adjusted to align the data in both channels with the respective baud clocks to within one baud clock period. However, the data in the first and second channels may still be skewed with respect to each other by one or more baud clock periods (i.e., shifted by one or more whole baud skews). In part II, the whole baud skew between baud clocks in channel A and channel B is determined. The variable delays <b>514</b>A, <b>514</b>B are then adjusted by the appropriate number of whole baud delays to align the data in both channels so as to eliminate the respective whole baud skew between channel A and channel B.

Joint Timing Loop—FIGS.

6

,

6

A,

6

B—Part I

0000Baud Clock Recovery Using Interpolation and Skew within One Baud Clock Period

0086In operation in <figref idref="DRAWINGS">FIG. 6</figref>, a pair of cross coupled phase locked loops is used to recover the baud clock timing. Methods for recovering the baud clock timing in separate channels of a diversity receiver using separate phase locked loops are known. In <figref idref="DRAWINGS">FIG. 6</figref>, the phase locked loops are cross coupled by operation of the joint loop filter <b>616</b>, which has been described above in conjunction with <figref idref="DRAWINGS">FIGS. 8A and 8B</figref>. Phase detector <b>612</b>A (or <b>612</b>B) is responsive to the Pf_—pb_—a (or Pf_—pb_—b) output of the Matched filter/Pre filter <b>516</b>A, <b>516</b>B to provide a measure of phase error to the joint loop filter <b>616</b>. The output of the joint loop filter <b>616</b> controls NCO <b>610</b>A, <b>610</b>B via adder <b>622</b><i>a</i>, <b>622</b>B. The NCO <b>610</b>A, <b>610</b>B responds to the closed loop input controls by adjusting the read pointer position of interpolator/variable delay <b>514</b>A, <b>514</b>B so as to minimize phase error to the phase detector <b>612</b>A, <b>612</b>B. An enable control <b>618</b> monitors the FIFO count A and FIFO count B from interpolator/variable delays <b>514</b>A and <b>514</b>B, and provides a data valid signal back to interpolator/variable delays <b>514</b>A and <b>514</b>B.

0087The enable control logic <b>618</b> is shown in further detail in <figref idref="DRAWINGS">FIG. 6B</figref>. The length of FIFO A and the length of FIFO B must each be greater than a minimum threshold in order for the data output of either circular buffer to be valid. The logic is carried out by comparing FIFO count A <b>658</b> to a buffer length of L=8 in a first comparator <b>650</b>, and by comparing FIFO count B <b>660</b> to a buffer length of L=8 in a second comparator <b>654</b>. If the FIFO count A is >L and FIFO count B is >L, then AND gate <b>652</b> output is high, indicating a data valid output <b>622</b>.

Joint Timing Loop—FIGS.

6

,

6

A,

6

B—Part II

0000Baud Clock Recovery Using Whole Baud Skew Correction

0088After a given time interval corresponding to a sufficiently large number of data samples, the PLL's for both channels tend to converge to a minimum phase error. At this point, the skew corrector <b>614</b> in the joint timing loop is enabled. The skew corrector <b>614</b> is responsive to the Matched filter/Pre filter <b>516</b>A, <b>516</b>B outputs Mf_—pb_—a and Mf_—pb_—b to compute a correlation function between the signals in the first and second channels of the diversity receiver. In response to correlation measurement, the skew corrector <b>614</b> injects whole baud time shifts into channel A and channel B by adding whole baud increments to the NCO <b>610</b>A and/or NCO <b>610</b>B via respective adders <b>622</b>A and <b>622</b>B.

0089The logic and flow diagrams for the whole baud skew corrector <b>614</b> in <figref idref="DRAWINGS">FIG. 6</figref> is shown in <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>. <figref idref="DRAWINGS">FIG. 9A</figref> illustrates the process by which the whole baud skew corrector computes the correlation between the output signals from the Matched filters, Mf_—pb_—a and Mf_—pb_—b, which correspond to the signals in channel A and channel B, respectively. First, the complex conjugate of Mf_—pb_—b is computed at step <b>910</b>, and then multiplied by Mf_—pb_—a in multiplier <b>911</b>. The result is integrated over a number of samples by integrator <b>912</b> and counter <b>920</b>. Counter <b>920</b> periodically resets integrator <b>912</b> every n samples and closes switch <b>914</b>. Thus, integrator <b>912</b> computes a numerical integration by summation over n samples, and presents the result to switch <b>914</b>. The absolute value of the integral from step <b>912</b> is taken at step <b>916</b>. The value at the output of step <b>916</b> represents the amount of correlation between input signals Mf_—pb_—a and Mf_—pb_—b.

0090The amount of correlation between the signal in channel A and the signal in channel B is then compared to a threshold value, t, at step <b>918</b>. The signals in the first and second channels are supposed to be the same signal arriving through different antennas. Therefore, a high correlation value (> or =t) indicates that the signals in the first and second channels are properly aligned, and no further (whole baud) skew correction is needed. Switches <b>922</b> and <b>944</b> are responsive to a threshold decision <b>918</b> on correlation. Thus, switches <b>922</b> and <b>924</b>, are responsive to a “yes” decision at step <b>918</b>, to select “0” for the value of A_—inc (channel A NCO increment) and “0” for the value of B_—inc (channel B NCO increment). In other words, if the signal in channel A correlates highly (>t) with the signal in channel B, the skew corrector <b>614</b> in <figref idref="DRAWINGS">FIG. 6</figref> provides no increment to adder, <b>622</b>A, <b>622</b>B, which does not introduce an increment to NCO <b>610</b>A, <b>610</b>B.

0091Referring back to <figref idref="DRAWINGS">FIG. 9A</figref>, if the correlation does not exceed the threshold t, then control logic <b>926</b> is activated to compute a value for the channel A, NCO increment, A_—inc, and a value for the channel B, NCO increment, B_—inc. A low correlation value (<t) indicates that the signals in the first and second channels are not properly aligned, and further (whole baud) skew correction is needed. Switches <b>922</b> and <b>924</b>, are responsive to a “no” decision at step <b>918</b>, to select the output of control logic <b>926</b> for the value of A_—inc (channel A NCO increment) and also for the value of B_—inc (channel B NCO increment). In other words, the skew corrector <b>614</b> in <figref idref="DRAWINGS">FIG. 6</figref> provides first and second computed increments, A_—inc, B_—inc, to adders <b>622</b>A and <b>622</b>B, which introduces respective increments to NCO <b>610</b>A and NCO <b>610</b>B. The introduction of whole baud skews by the delay elements <b>514</b>A and <b>514</b>B changes the filter outputs, Mf_—pb_—a and Mf_—pb_—b to the skew corrector <b>614</b>, which in turn computes new increments A_—inc and B_—inc. The process continues until a whole baud skew correction is found which provides acceptable correlation (>t) between the signals at the filter outputs, Mf_—pb_—a and Mf_—pb_—b.

0092A flow diagram for computing the value of A_—inc and B_—inc (by logic control <b>926</b> in <figref idref="DRAWINGS">FIG. 9A</figref>) is shown in <figref idref="DRAWINGS">FIG. 9B</figref>. The goal is to find values of A_—inc and B_—inc that result in a high correlation between Mf_—pb_—a and Mf_—pb_—b. Small skews, both plus and minus, are searched first. The search strategy is based on the assumption that channel A and channel B are more likely to be skewed by a smaller amount than by a larger amount. That is, 0 skew is more likely than plus or minus 1 baud skew, which is more likely than plus or minus 2 whole baud skews, etc. Search is performed by enumeration in the following order: 0 skew, +1 skew, −1 skew, +2 skew, −2 skew, +3 skew, −3 skew and so on up to a maximum skew (the extreme end of the adjustment range).

0093<figref idref="DRAWINGS">FIGS. 9B and 9C</figref> illustrate the skew search sequence. Parameter T is the time interval corresponding to one baud skew. Variables x and y are internal program states, where x is the previous value of baud shift and y is the current value of the baud shift. Initially x and y are set to zero.

0094The initialization condition for zero skew where no NCO increment is introduced into either channel A or channel B, is shown in the initialization skew chart. The initialization condition corresponds to the initial state at the entry step <b>930</b> (from comparator test step <b>918</b> in <figref idref="DRAWINGS">FIG. 9A</figref>). Positive values for x are shown in the skew graphs for x=1, x=2, x=3 in <figref idref="DRAWINGS">FIG. 9C</figref>, and correspond to steps <b>936</b> and <b>938</b> in <figref idref="DRAWINGS">FIG. 9B</figref>. Negative values for x are shown in the skew graphs for x=−1, x=−2, in <figref idref="DRAWINGS">FIG. 9C</figref>, and correspond to steps <b>940</b> and <b>942</b> in <figref idref="DRAWINGS">FIG. 9B</figref>. The maximum negative value for x is shown in the skew graph for x=−3 in <figref idref="DRAWINGS">FIG. 9C</figref>, and corresponds to step <b>944</b> in <figref idref="DRAWINGS">FIG. 9B</figref>.

0095In operation, after the initialization entry step <b>930</b>, x is compared to zero at step <b>932</b>. On the first pass, x is 0, so that step <b>934</b> sets A_—inc to 1 and B_—inc to 0. The system state at this step corresponds to x=0 in <figref idref="DRAWINGS">FIG. 9C</figref>. Upon exit step <b>946</b>, x is set to the current value of y, which is equal to 1. On the second pass, x is not zero at step <b>932</b>, so test step <b>936</b> is entered. Step <b>936</b> tests for polarity. For positive polarity of x, step <b>938</b> sets y equal to −x, and changes A_—inc, and B_—inc to yT and −yT, respectively. Upon exit step <b>946</b>, x is set to y, which is now equal −1. On the third pass, x is not zero at step <b>932</b>, so a polarity test step <b>936</b> is entered. Now x is negative, so step <b>940</b> is performed. Step <b>940</b> tests for the maximum negative skew (extreme end of the adjustment range). If skew is not maximum negative, step <b>942</b> is performed (setting y to 1−x, and setting A_—inc, and B_—inc to (y−1)T and −yT, respectively), otherwise step <b>944</b> is performed. At each time upon exit step <b>946</b>, a new value for x (previous value of skew shift) is set equal to y (current value of skew shift), and updated values of A_—inc, and B_—inc are generated.

0096Thus, by operation of the flow chart in <figref idref="DRAWINGS">FIG. 9B</figref>, after 0 skew is tested (initialization), +1 skew is tested. Then −1 skew is tested, and then +2, −2, +3 and −3 in that order. The <figref idref="DRAWINGS">FIG. 9C</figref> graph for x=0 shows channel A advanced one baud skew relative to channel B. The graph for x=1 shows channel B advanced one baud skew relative to channel A. The graph for x=−1 shows channel A advanced two baud skews relative to channel B. The graph for x=+2 shows channel B advanced two baud skews relative to channel A. Finally, the graph for x=−2 shows channel A advanced three baud skews relative to channel B. The graph for x=+3 shows channel B advanced three baud skews relative to channel A. For x=−3, channel A and channel B are both advanced one baud skew.

0097An alternative embodiment for the search strategy is to search starting from an extreme end of the adjustable range such as −3 skew and search linearly across the range as follows: −3 skew, &lt;2 skew, −1 skew, 0 skew+1 skew, +2 skew and +3 skew. Another embodiment is to search from 0 skew, to one extreme end of the range and then reverse and search to the other extreme end of the range. Although the latter test duplicates computations, programming code may be more compact and easier to implement. The additional computation burden for whole baud skew correction is slight since the whole baud skew calculation is performed primarily on receiver's initial adaptation sequences. Once adjusted for whole baud skews, the whole baud clock timing is not likely to change for a given antenna location.

0098As indicated, the recovered baud clock represents the timing signal for sampling the received signal to recover digital data. The recovered baud clock timing typically does not fall exactly on one of the sampled values of the received signal. A sampled value of each received signal corresponding to the recovered baud clock timing is computed using an interpolator (<b>632</b> in <figref idref="DRAWINGS">FIG. 6A</figref>). The interpolator computes the desired sampled data value by using earlier and later actual samples of the received signal. The received signal samples are interpolated over 8 signal samples (4 samples after and 4 samples before the current baud clock time).

Joint Front End, Joint Pilot Loop

0000RF Carrier Recovery—<figref idref="DRAWINGS">FIGS. 5 and 7</figref>

0099After the baud clock is recovered in the joint timing loop <b>510</b> of <figref idref="DRAWINGS">FIG. 5</figref>, the joint pilot loop <b>512</b> recovers the carrier signal which is used to demodulate (derotate) each of the signals received in channel A and channel B. The carrier signals for channel A and channel B are recovered by jointly processing signals from both channel A and channel B in the joint pilot loop control <b>522</b>. Further details of the joint pilot loop <b>512</b> are shown in <figref idref="DRAWINGS">FIG. 7</figref>.

0100The joint pilot loop control <b>522</b> comprises phase detectors <b>712</b>A, <b>712</b>B, sine/cosine generators <b>710</b>A, <b>710</b>B, and a joint loop filter <b>716</b>. A sine/cosine generator is similar to a numerically controlled oscillator (NCO) in that both are responsive to a numerical input to generate the frequency and phase of an output signal. The difference is in the implementation methodology, in that a sine/cosine generator calculates output values of a desired sinusoidal function, while an NCO counts time intervals.

0101In operation, a pair of cross coupled phase locked loops is used to recover the carrier clock. The phase locked loops are cross coupled by operation of the joint loop filter <b>716</b>, which has been described above in conjunction with <figref idref="DRAWINGS">FIGS. 8A and 8B</figref>. For each of channel A and B, a phase detector <b>712</b>A (<b>712</b>B) is responsive to the Pf_—bb_—a (or Pf_—bb_—b) output of the Matched filter/Pre filter <b>516</b>A (<b>516</b>B) to provide a measure of phase error to the joint loop filter <b>716</b>. The output of the joint loop filter <b>716</b> controls sine/cosine generator <b>710</b>A (<b>710</b>B). The sine/cosine generator <b>710</b>A (<b>710</b>B) responds to the closed loop input controls by adjusting its output signal so as to reduce the phase error to the phase detector <b>712</b>A (<b>712</b>B). The changed phase error in the derotator <b>518</b>A (<b>518</b>B) output is measured by the phase detector <b>712</b>A (<b>712</b>B), which changes the input to the loop filter <b>716</b>. The closed loop process continues until the PLL converges (and locks) to a stable state reducing (and keeping) the phase error to an acceptably low value. The derotated outputs for channel A and channel B, Mf_—bb_—a, and Mf_—bb_—b, are input to the joint equalizer.

Forward Equalization

0102A further aspect of the diversity receiver of the present invention is the use of sparse equalization to determine the optimum coefficients for both blind and decision directed modes. A joint equalizer having both forward and feedback portions is shown in <figref idref="DRAWINGS">FIG. 10</figref>. An equalization filter technique for use with the present joint equalizer is found in copending patent application Ser. No. 09/100,705, filed Jun. 19, 1998, entitled “REDUCED COMPLEXITY BLIND EQUALIZER FOR DUAL MODE (QAM/VSB) SIGNALLING”, and assigned to assignee of the present application. The disclosed equalizer of the above cited patent application discloses a technique of “sparse equalization” in which an equalizer is formed using a “sparse equalization filter”.

0103Briefly, in the above cited sparse equalizer patent application, only 32 out of 256 taps of an equalization filter are used. The equalization technique is termed “sparse” because only the most significant 32 filter taps are used and the remaining filter taps are set to zero. That is, the 224 smallest filter coefficients are set to zero, leaving only the 32 most significant filter coefficients remaining non-zero.

0104To find the 32 most significant coefficients out of the total 256 taps, the first 32 coefficients are calculated for taps 0 to 31 (forming a first set of 32 taps). Then, the smallest of the 32 coefficients is set to zero (leaving 31 non-zero taps), and a coefficient value for tap 32 is calculated (creating a second set of 32 taps). The smallest coefficient among the second set of 32 taps is then set to zero, and a coefficient for tap <b>33</b> is calculated (creating a new third set of 32 taps). The process is repeated until the most significant 32 taps are allocated (selected) among the 256 total taps.

0105In the above cited patent application, the sparse equalization technique is used to improve operational speed by reducing the number of necessary calculations in order to adjust the equalization filter coefficients. In the present application, the sparse equalization is used to dynamically allocate equalization filter taps among first and second channels of a diversity receiver.

0106The joint forward equalizer in <figref idref="DRAWINGS">FIG. 10</figref> comprises combiner <b>1002</b>, A/B selector <b>1012</b>, forward spare selector/equalizer <b>1004</b> and forward sparse controller <b>1014</b>, which form the forward equalizer portion of the joint equalizer. The joint forward equalizer further comprises a feedback equalizer portion formed by adder <b>1006</b>, slicer <b>1008</b>, decision feedback equalizer filter (DFE) <b>1010</b> and feedback sparse controller <b>1016</b>.

0107In operation, the output of the front end of channels A and B are input to the combiner <b>1002</b> which multiplexes one sample from each joint front end under the control of the A/B selector <b>1012</b>. One sample from channel A is alternated with one sample from channel B and the multiplexed result is input to the joint forward sparse selector/equalizer <b>1004</b>.

0108The data stream derived from the multiplexed channel A and channel B signals at the output of the forward sparse selector/equalizer <b>1004</b> are input to adder <b>1006</b>. The output from adder <b>1006</b> goes to the slicer <b>1008</b>, which makes a hard decision of the data symbol value by comparison of the input signal to an internal reference level. After the slicer <b>1008</b> output, the hard decision values are coupled to a decision feedback equalization filter (DFE) <b>1010</b> that is further coupled to the adder <b>1006</b> in a feedback loop. In a manner similar to tap allocation scheme for the forward sparse selector/equalizer <b>1004</b>, the DFE filter <b>1010</b> is coupled to the feedback sparse controller <b>1016</b>, which allocates 32 taps out of 256 taps of the DFE filter <b>1010</b>.

0109Under ideal channel conditions, in which both channels A and B are exactly the same (i.e., no differences due to multiple signal paths) a tap allocation equalizer should use equal amounts from each channel by splitting the two center tap values equally to 0.5 and 0.5. Under real channel conditions, the equalizer combines the two channels in inverse proportion to the MSE error (mean square error) in each channel where the coefficients for each respective channel will be distributed along the respective channel's tapped delay line. In accordance with the present invention, since the samples from channel A and channel B are interleaved, the operation of the sparse equalizer is to effectively allocate taps between the equalizer for channel A the equalizer for channel B, in both blind and decision directed modes. The multiple channels are combined into one tapped delay line and the sparse equalization technique selects tap weights without bias.

0110While the foregoing embodiment of a multiple channel diversity receiver illustrates a two channel diversity receiver having two antennas, the invention described herein is generally applicable to a multiple channel diversity receiver having three or more antennas with joint signal processing.