Latency control circuit and method of latency control

RELATED APPLICATION DATA

0001This is a continuation-in-part of application Ser. No. 10/283,124 filed Oct. 30, 2002, now U.S. Pat. No. 6,707,759; the contents of which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

0002<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block diagram of a prior art memory device. The memory device <b>100</b> includes a memory cell array <b>110</b>, a clock synchronizing circuit block <b>120</b>, a read command path block <b>130</b>, a data output buffer <b>140</b>, a mode register <b>150</b> and a latency circuit <b>160</b>. In operation, data is written into the memory cell array <b>110</b> and read out from the memory cell array <b>110</b>. If a read command is asserted to the memory device <b>100</b>, data is read out from the memory cell array <b>110</b> according to an externally received address. A buffer <b>116</b> receives and temporarily stores the address. A row decoder <b>112</b> receives the stored address and decodes a row address of the memory cell array <b>110</b> from the address. A column decoder <b>114</b> receives the stored address and decodes a column address of the memory cell array <b>110</b> from the address. The memory cell array <b>110</b> outputs the data addressed by the row and column addresses. The data output buffer <b>140</b> receives the data output from the memory cell array <b>110</b>, and outputs the data based on a latency signal from the latency circuit <b>160</b> and an internal data output clock signal CLKDQ.

0003The clock synchronizing circuit block <b>120</b> generates the data output clock signal CLKDQ based on an external clock signal ECLK. The external clock signal ECLK serves as a reference clock signal for most commands of the memory device <b>100</b>. Specifically, most commands are asserted to the memory device <b>100</b> in synchronization with the external clock signal ECLK. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the clock synchronizing circuit block <b>120</b> is a delay locked loop (DLL) circuit. The DLL circuit <b>120</b> includes a variable delay <b>122</b>, a data output buffer replica <b>124</b> and a phase detector <b>126</b>. The DLL circuit <b>120</b> is a well known circuit such as described in U.S. Pat. No. 5,614,855; and therefore, will not be described in detail. The DLL circuit <b>120</b> generates the data output clock signal CLKDQ as a phase lead version of the external clock ECLK. Namely, the data output clock signal CLKDQ has the same frequency as the external clock ECLK, but the pulses of the data output clock signal CLKDQ precede the pulses of the external clock signal ECLK by a data output time tSAC. The data output time is a measurement of the time it takes the data output buffer <b>140</b> to output data. Accordingly, the DLL circuit <b>120</b> causes data to be output from the data output buffer <b>140</b> in synchronization with the external clock ECLK.

0004The read command path block <b>130</b> receives the read command and the external clock signal ECLK. An internal clock generator <b>132</b> receives the external clock signal ECLK and generates an internal clock signal PCLK from the external clock signal ECLK. Specifically, the internal clock signal PCLK is a buffered version of the external clock signal ECLK. Therefore, the internal clock signal PCLK has the same frequency as the external clock signal ECLK and the level of the internal clock signal PCLK swing is a CMOS level (VSS−VCC) buffered signal delayed from the external clock signal ECLK. The internal clock signal PCLK is used to control peripheral circuits (not shown) such as data sense amplifiers, data multiplexers, etc., in the memory device <b>100</b>. A read command buffer <b>134</b> in the read command path block <b>130</b> receives the read command and the internal clock signal PCLK. The read command buffer <b>134</b> inputs the read command synchronized with the internal clock signal PCLK, and outputs an internal read signal PREAD, which is supplied to the latency circuit <b>160</b>.

0005The memory device <b>100</b> has several modes of operation. The mode register <b>150</b> stores a mode register set (MRS) command asserted to the memory device <b>100</b>. The MRS command indicates the mode of the memory device <b>100</b>. CAS latency information is determined by the MRS command. The CAS latency information indicates the CAS latency mode, which is the number of clock cycles of the external clock signal ECLK that should occur between the receipt of a read command or column address until data is output by the memory device <b>100</b>. Stated another way, data is output from the memory device in a CAS latency number of clock cycles after receipt of the read command (a column address being asserted together with the read command).

0006The latency circuit <b>160</b> receives the CAS latency information from the mode register <b>150</b> and generates a latency signal such that the data output buffer <b>140</b> is enabled to output the data according to the desired CAS latency. More specifically, the data output buffer <b>140</b> outputs the stored data in response to the data output clock signal CLKDQ while the latency signal is enabled.

0007<figref idref="DRAWINGS">FIG. 2</figref> illustrates a prior art latency circuit <b>160</b>. As shown, the latency circuit <b>160</b> includes first, second and third D-flip flops <b>215</b>, <b>225</b> and <b>235</b> connected in cascade. Each D-flip flop receives the data output clock signal CLKDQ at its clock input. The internal read signal PREAD is supplied to the D input of the first D-flip flop <b>215</b>. The internal read signal PREAD and Q output of each of the first-third D-flip flops <b>215</b>, <b>225</b> and <b>235</b> are respectively connected to first-fourth switches <b>210</b>, <b>220</b>, <b>230</b> and <b>240</b>. The first-fourth switches <b>210</b>, <b>220</b>, <b>230</b> and <b>240</b> are respectively controlled by a CAS latency indicator CL<b>1</b>, CL<b>2</b>, CL<b>3</b> and CL<b>4</b> decoded from the CAS latency information. Namely, the CAS latency information is N bits that indicate the CAS latency mode. The N bits are decoded by a simple logic decoder (not shown) to produce the CAS latency indicators CL<b>1</b>-CL<b>4</b> associated with each CAS latency mode. As will be appreciated, the CAS latency indicator for the activated CAS latency mode will be, for example, logic high, while the other CAS latency indicators will be logic low. The output of the first-fourth switches <b>210</b>, <b>220</b>, <b>230</b> and <b>240</b> serve as the latency signal. In operation, only one of the CAS latency modes will be logic high; therefore, only one of the first-fourth switches <b>210</b>, <b>220</b>, <b>230</b> and <b>240</b> will transfer a signal for output as the latency signal. For example, when the CAS latency is 1, CL<b>1</b> is logic high and turns on first switch <b>210</b>. At this time, the other CAS latency indicators CL<b>2</b>, CL<b>3</b>, and CL<b>4</b> are logic low. The internal read signal is then transferred as the latency signal via the first switch <b>210</b>. When the CAS latency is two (i.e., CL equals 2), then CL<b>2</b> is logic high, while CL<b>1</b>, CL<b>3</b> and CL<b>4</b> are logic low. Thus, the internal read signal PREAD is transferred as the latency signal via the first D-flip flop <b>215</b> and the second switch <b>220</b>. The first D-flip flop <b>215</b> is triggered by the data output clock signal CLKDQ and delays the internal read signal PREAD being output as the latency signal by about one clock cycle. The operation when the CAS latency is three or four is similar to that discussed above with respect to the CAS latency of two, and therefore will not be repeated for the sake of brevity. Additionally, it will be understood that CAS latencies greater than four could be handled by the addition of more D-flip flops and switches.

0008<figref idref="DRAWINGS">FIG. 3A</figref> illustrates a timing diagram of the read operation when the CAS latency is 1. At a clock cycle C<b>0</b>, a read command <b>310</b> is asserted, and an internal read signal PREAD is generated by the read command path block <b>130</b> after an internal delay time tREAD. The latency signal is then enabled in response to the internal read signal PREAD as discussed above with respect to FIG. <b>2</b>. As further shown in <figref idref="DRAWINGS">FIG. 3A</figref>, the DLL circuit <b>120</b> generates the data output clock signal CLKDQ such that the rising edge of the data output clock signal CLKDQ precedes the rising edge of the external clock signal ECLK by a period of time tSAC, where the time period tSAC equals the delay between enabling data output from the data output buffer <b>140</b> and the actual output of data from the memory device <b>100</b>. As further discussed above with respect to <figref idref="DRAWINGS">FIG. 1</figref>, the data output buffer <b>140</b> outputs data when triggered by the data output clock signal CLKDQ only when the latency signal is enabled. Because the CAS latency has been set to 1 in this example, the latency signal is enabled prior to receipt of the data output clock signal CLKDQ. As a result, data is output from the memory device <b>100</b> in synchronization with the first clock pulse C<b>1</b> of the external clock signal ECLK following the clock pulse C<b>0</b> of the external clock signal ECLK when the read command <b>310</b> was received. The time delays tREAD and tSAC are internal delays set according to current process technology. Minimizing these delays improves the timing margin as to when the latency signal must be enabled before receipt of the data output clock signal CLKDQ. As the frequency of operation increases (i.e., the frequency of the external clock signal ECLK increases), the period between clock pulses of the external clock signal ECLK decreases. This reduces the timing margin for supplying the latency signal. Consequently, above a certain operating frequency, the latency signal enables after the data output clock signal CLKDQ, and the data is no longer output at the desired CAS latency. This results in a data read operation failure.

0009<figref idref="DRAWINGS">FIG. 3B</figref> illustrates another example of where the operation frequency is low enough such that a proper data read operation takes place for a CAS latency of 2. However, <figref idref="DRAWINGS">FIG. 3C</figref> shows the operation of the memory device <b>100</b> during a high frequency operation, wherein a data read operation failure takes place. As shown in this example, tREAD plus tSAC is greater than the period tCC of the external clock signal ECLK such that the internal read signal PREAD is asserted after the rising edge of a pulse CDQ<b>1</b> of the data output clock signal CLKDQ. The latency signal thus becomes enabled after a pulse CDQ<b>4</b> of the data output clock signal CLKDQ for the desired CAS latency. In the example of <figref idref="DRAWINGS">FIG. 3C</figref>, the desired CAS latency is 4, and as is shown, data is output according to a CAS latency of 5 instead of a CAS latency of 4. As a result, a data read operation failure takes place.

SUMMARY OF THE INVENTION

0010The memory device according to the present invention includes a memory cell array from which data is read. Read data is stored in an output buffer, which outputs data based on a latency signal generated in accordance with the desired CAS latency of the memory device. The memory device includes a latency circuit that permits a desired CAS latency of the memory device to be achieved without read operation error even when the memory device is operating at high frequency.

0011More specifically, the latency circuit selectively associates at least one transfer signal with at least one sampling signal based on the desired CAS latency to create a desired timing relationship between the associated sampling and transfer signals. Read information is stored by the latency circuit in accordance with at least one of the sampling signals, and the latency signal is generated based on the transfer signal associated with the sampling signal used in storing the read information.

0012The arrangement and methodology of the latency circuit in the present invention allows for pointing or identifying a point in time as to when the memory cell array of the memory device is being read, and for pointing or identifying a point in time when to generate the latency signal with respect to the first pointer. By establishing the relationship between the first and second pointers based on the desired CAS latency, a read operation according to the desired CAS latency is achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

0013The present invention will become more fully understood from the detailed description given below and the accompanying drawings, wherein like elements are represented by like reference numerals, which are given by way of illustration only and thus are not limitative of the present invention and wherein:

0014<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block diagram of a prior art memory device;

0015<figref idref="DRAWINGS">FIG. 2</figref> illustrates a prior art latency circuit;

0016<figref idref="DRAWINGS">FIG. 3A</figref> illustrates a timing diagram of the read operation when the CAS latency is 1 for the memory device of <figref idref="DRAWINGS">FIG. 1</figref>;

0017<figref idref="DRAWINGS">FIG. 3B</figref> illustrates a timing diagram of the read operation when the CAS latency is 2 for the memory device of <figref idref="DRAWINGS">FIG. 1</figref>;

0018<figref idref="DRAWINGS">FIG. 3C</figref> illustrates a timing diagram of the read operation when the CAS latency is 4 for the memory device of <figref idref="DRAWINGS">FIG. 1</figref>;

0019<figref idref="DRAWINGS">FIGS. 4A-4C</figref> illustrate exemplary embodiments of the memory device according to the present invention;

0020<figref idref="DRAWINGS">FIG. 5</figref> illustrates an embodiment of the latency signal generator in <figref idref="DRAWINGS">FIGS. 4A-4C</figref>;

0021<figref idref="DRAWINGS">FIG. 6</figref> illustrates an embodiment of the sample clock signal generator and the transfer signal generator of <figref idref="DRAWINGS">FIG. 5</figref>;

0022<figref idref="DRAWINGS">FIG. 7</figref> illustrates an embodiment of the master clock generator in <figref idref="DRAWINGS">FIGS. 4A-4C</figref>;

0023<figref idref="DRAWINGS">FIG. 8</figref> illustrates the operation of the master clock generator in <figref idref="DRAWINGS">FIG. 7</figref>;

0024<figref idref="DRAWINGS">FIGS. 9A-9T</figref> illustrate the waveforms of the signals generated by or received by the memory device of <figref idref="DRAWINGS">FIGS. 4A</figref>, <b>4</b>B or <b>4</b>C having a latency signal generator as illustrated in <figref idref="DRAWINGS">FIG. 5</figref>;

0025<figref idref="DRAWINGS">FIG. 10A</figref> illustrates an embodiment of the multiplexers in <figref idref="DRAWINGS">FIG. 5</figref>;

0026<figref idref="DRAWINGS">FIG. 10B</figref> illustrates the mapping of transfer signals to output transfer clock signals for the embodiment of the multiplexers illustrated in <figref idref="DRAWINGS">FIG. 10A</figref>;

0027<figref idref="DRAWINGS">FIG. 11</figref> illustrates another embodiment of the latency signal generator in <figref idref="DRAWINGS">FIGS. 4A-4C</figref>;

0028<figref idref="DRAWINGS">FIGS. 12A-12S</figref> illustrate the waveforms of the signals generated by or received by the memory device of <figref idref="DRAWINGS">FIGS. 4A</figref>, <b>4</b>B or <b>4</b>C having a latency signal generator as illustrated in <figref idref="DRAWINGS">FIG. 11</figref>;

0029<figref idref="DRAWINGS">FIG. 13A</figref> illustrates an embodiment of the multiplexers in <figref idref="DRAWINGS">FIG. 11</figref>;

0030<figref idref="DRAWINGS">FIG. 13B</figref> illustrates the mapping of sampling signals to output sampling clock signals for the embodiment of the multiplexers illustrated in <figref idref="DRAWINGS">FIG. 13A</figref>;

0031<figref idref="DRAWINGS">FIG. 14</figref> illustrates another embodiment of the latency signal generator in <figref idref="DRAWINGS">FIGS. 4A-4C</figref>;

0032<figref idref="DRAWINGS">FIG. 15</figref> illustrates an embodiment of the sample clock signal generator and the transfer signal generator of <figref idref="DRAWINGS">FIG. 14</figref>;

0033<figref idref="DRAWINGS">FIG. 16</figref> illustrates tables for CAS latency modes two-five that demonstrate which of the first-fourth transfer clock signals TCLK<b>1</b>-TCLK<b>4</b> and which of the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b> become active for each CAS latency mode in the embodiment of <figref idref="DRAWINGS">FIG. 15</figref>;

0034<figref idref="DRAWINGS">FIGS. 17A-17S</figref> illustrate the waveforms of the signals generated by or received by the memory device of <figref idref="DRAWINGS">FIGS. 4A</figref>, <b>4</b>B or <b>4</b>C having a latency signal generator as illustrated in <figref idref="DRAWINGS">FIG. 14</figref> when the CAS latency mode is four; and

0035<figref idref="DRAWINGS">FIGS. 18 and 19</figref> illustrates waveforms as shown in <figref idref="DRAWINGS">FIG. 17</figref> for CAS latency modes three and five, respectively.

DETAILED DESCRIPTION OF THE EMBODIMENTS

0036<figref idref="DRAWINGS">FIG. 4A</figref> illustrates an embodiment of the memory device according to the present invention. As shown, the memory device <b>400</b> includes a memory cell array <b>110</b>, a clock synchronizing circuit block <b>120</b>, a read command path block <b>130</b>, a data output buffer <b>140</b>, a mode register <b>150</b>, and a latency circuit <b>500</b>. Like reference numerals have been used to designate like components between the memory device <b>400</b> and the prior art memory device <b>100</b> described in the Background of the Invention section. Accordingly, a description of these same components will not be repeated for the sake of brevity.

0037<figref idref="DRAWINGS">FIG. 4B</figref> illustrates one embodiment of the latency circuit <b>500</b> in greater detail. As shown, the latency circuit <b>500</b> includes a latency signal generator <b>502</b> generating the latency signal based on the data output clock CLKDQ, a master clock signal PCLKD, the internal read signal PREAD, and the CAS latency information. A read command path block replica <b>460</b> in the latency circuit <b>500</b> generates the master clock signal PCLKD based on a buffered version of the data output clock signal CLKDQ, which is generated by the data output buffer replica <b>124</b> in the clock synchronizing circuit block <b>120</b>. As such, the latency circuit <b>500</b> has been illustrated as sharing the data output buffer replica <b>124</b> with the clock synchronizing circuit block <b>120</b>. The operation of the read command path block replica <b>460</b> and the latency signal generator <b>502</b> will described in greater detail below after the discussion of a second embodiment of the latency circuit <b>500</b>.

0038<figref idref="DRAWINGS">FIG. 4C</figref> illustrates a second embodiment of the latency circuit <b>500</b>. In this embodiment, the latency circuit <b>500</b> does not include the data output buffer replica <b>124</b> or the read command path block replica <b>460</b>. Instead, as shown in <figref idref="DRAWINGS">FIG. 4C</figref>, these elements are external to the latency circuit <b>500</b>.

0039Next, the read command path block replica <b>460</b> and the latency signal generator <b>502</b> will be described in detail.

0040The read command path block replica <b>460</b> includes an internal clock generator replica <b>462</b> that receives a buffered version of the data output clock signal CLKDQ from the data output buffer replica <b>124</b>. The data output buffer replica <b>124</b> replicates the output delay of the data output buffer <b>140</b>. Accordingly, the buffered clock signal CLKF is a delayed version of the data output clock signal CLKDQ. The internal clock generator replica <b>462</b> is a replica of the internal clock generator <b>132</b>, and generates a replica internal clock signal PCLKR. A master clock generator <b>700</b> receives the internal clock signal PCLK and the replica internal clock signal PCLKR and generates a master clock signal PCLKD.

0041<figref idref="DRAWINGS">FIG. 7</figref> illustrates an embodiment of the master clock generator <b>700</b>. As shown, an inverter <b>704</b> receives the replica internal clock signal PCLKR. The output of the inverter <b>704</b> controls the operation of a PMOS transistor <b>706</b>, which is connected in series with an NMOS transistor <b>708</b> between a power supply voltage VCC and a reference or ground voltage VSS. The operation of the NMOS transistor <b>708</b> is controlled by a reset signal. An enable signal is generated at the node connecting the PMOS transistor <b>706</b> and the NMOS transistor <b>708</b>. This enable signal is latched by a latch <b>720</b>, which is comprised of inverters <b>722</b> and <b>724</b> connected in a loop configuration to the enable signal node EN. An AND gate <b>710</b> receives the enable signal and a delayed internal clock signal PCLK<b>2</b>. A delay unit <b>702</b> receives and delays the internal clock signal PCLK to generate the delayed internal clock signal PCLK<b>2</b>. The period of the delay substantially equals the period of time to generate the enable signal based on the replica internal clock signal PCLKR. The output of the AND gate <b>710</b> serves as the master clock signal PCLKD.

0042<figref idref="DRAWINGS">FIG. 8</figref> illustrates the operation of the master clock generator <b>700</b>. As shown, when the reset signal is enabled, the NMOS transistor <b>708</b> pulls the enable signal to logic low. As a result, the AND gate <b>710</b> generates a logic low master clock signal PCLKD. When the reset signal is no longer enabled, the replica internal clock signal PCLKR controls the state of the enable signal such that at the rising edge of the replica internal clock signal PCLKR, the enable signal transitions to a logic high state. As a result, the AND gate <b>710</b> will output the delayed internal clock signal PCLK<b>2</b> as the master clock signal PCLKD. The replica internal clock signal PCLKR is generated from output of the DLL circuit <b>120</b>. As a result, the replica internal clock signal PCLKR experiences some jitter, which decreases the frequency performance of the memory device. By using the replica internal clock signal PCLKR to enable the master clock signal PCLKD and by outputting the master clock signal PCLKD as a delayed version of the internal clock signal PCLK, which has not experienced such jitter, the master clock generator <b>700</b> generates a master clock signal PCLKD without jitter. Furthermore, because the internal clock signal PCLK is used as an internal clock signal for many of the peripheral circuits in the memory device <b>400</b>, the internal clock signal PCLK experiences a large load. By contrast, the master clock signal PCLKD is not as loaded, and therefore can be used as a clock signal of the latency circuit <b>500</b> as described in detail below.

0043<figref idref="DRAWINGS">FIG. 5</figref> illustrates an exemplary embodiment of the latency signal generator <b>502</b>. As shown, the latency signal generator <b>502</b> includes a sampling signal generator <b>510</b> generating first-fourth sampling signals S<b>1</b>-S<b>4</b> that, in this embodiment, serve as first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b>, respectively. Accordingly, in this embodiment, the sampling signal generator <b>510</b> serves as a sampling clock signal generator, which generates the sampling clock signals based on the master clock signal PCLKD. Similarly, a transfer signal generator <b>550</b> generates first-fourth transfer signals T<b>1</b>-T<b>4</b> based on the data output clock signal CLKDQ. The sampling clock signal generator <b>510</b> and the transfer signal generator <b>550</b> include first and second ring shift registers <b>520</b> and <b>560</b>, respectively, such as illustrated in FIG. <b>6</b>.

0044As shown in <figref idref="DRAWINGS">FIG. 6</figref>, first-fourth D-flip flops <b>521</b>-<b>524</b> are connected in cascade. First-fourth AND gates <b>525</b>-<b>528</b> have one input connected to a Q output of the first-fourth D-flip flops <b>521</b>-<b>524</b>, respectively. The other input of the first-fourth AND gates <b>525</b>-<b>528</b> and the clock inputs of the first-fourth D-flip flops <b>521</b>-<b>524</b> receive the master clock signal PCLKD in the case of the sampling clock signal generator <b>510</b> or the data output clock signal CLKDQ in the case of the transfer signal generator <b>550</b>. Also as shown, the Q output of the fourth and final D-flip flop <b>524</b> is fed to the D input of the first D-flip flop <b>521</b>. The outputs of the first-fourth AND gates <b>525</b>-<b>528</b> supply the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b> in the case of the sampling clock signal generator <b>510</b> or supply the first-fourth transfer signals T<b>1</b>-T<b>4</b> in the case of the transfer signal generator <b>550</b>. Lastly, the reset inputs of the first-fourth D-flip flops <b>521</b>-<b>524</b> receive the reset signal. The first D-flip flop <b>521</b> is a settable D-flip flop and the second-fourth D-flip flops <b>522</b>-<b>524</b> are resettable D-flip flops. The reset signal enables the pre-setting of the shift register such that the first D-flip flop is SET(logic high state) and the others are RESET(logic low state).

0045The logic high signal will load into the first D-flip flop <b>521</b> on the rising edge of the received clock signal, and this pulse will be transferred to the second-fourth D-flip flops <b>522</b>-<b>524</b> as each clock signal pulse is received. Accordingly, when the logic high signal resides in a respective one of the first-fourth D-flip flops <b>521</b>-<b>524</b>, the corresponding one of the first-fourth AND gates <b>525</b>-<b>528</b> outputs a logic high pulse in synchronization with the received clock signal. This operation is illustrated in <figref idref="DRAWINGS">FIGS. 9A</figref>, <b>9</b>D, and <b>9</b>E-<b>9</b>M. <figref idref="DRAWINGS">FIG. 9A</figref> illustrates the reset signal, <figref idref="DRAWINGS">FIGS. 9D and 9E</figref> illustrate the data output clock signal CLKDQ and the master clock signal PCLKD, respectively. <figref idref="DRAWINGS">FIGS. 9F-9I</figref> illustrate the first-fourth transfer signals T<b>1</b>-T<b>4</b>, and <figref idref="DRAWINGS">FIGS. 9J-9M</figref> illustrate the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b>.

0046Returning to <figref idref="DRAWINGS">FIG. 5</figref>, the latency signal generator <b>502</b> further includes a read information storage unit <b>530</b>. The read information storage unit <b>530</b> includes first-fourth latches <b>531</b>-<b>534</b>. The first-fourth latches <b>531</b>-<b>534</b> receive the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b>, respectively, at their clock inputs, receive the internal read signal PREAD at their latch input, have their reset input connected to the reset signal, and generate first-fourth output signals LS<b>1</b>-LS<b>4</b>, respectively. Each latch will latch the internal read signal PREAD on the rising edge of the respectively received sampling clock signal. This operation is illustrated in <figref idref="DRAWINGS">FIGS. 9N-9R</figref>.

0047<figref idref="DRAWINGS">FIG. 9N</figref> illustrates the internal read signal PREAD, and <figref idref="DRAWINGS">FIGS. 9O-9R</figref> illustrate the output signals LS<b>1</b>-LS<b>4</b>. As shown, if the PREAD signal is logic high when the third sampling clock SCLK<b>3</b> illustrated in <figref idref="DRAWINGS">FIG. 9L</figref> transitions to logic high, the third latch <b>533</b> latches the logic high PREAD signal and generates a logic high output signal LS<b>3</b>.

0048<figref idref="DRAWINGS">FIG. 5</figref> further illustrates that the first-fourth output signals LS<b>1</b>-LS<b>4</b> are received by first-fourth switches <b>535</b>-<b>538</b>, respectively. The outputs of the switches are each connected to an output latch <b>539</b>. Whether the first-fourth switches <b>535</b>-<b>538</b> transfer the respectively received first-fourth output signals LS<b>1</b>-LS<b>4</b> to the output latch <b>539</b> depends upon the state of the transfer signal received by that switch as will be described in more detail below. For example, if the third switch <b>537</b> receives a logic high transfer signal when the third output signal LS<b>3</b> is logic high as shown in <figref idref="DRAWINGS">FIG. 9Q</figref>, then the logic high output signal LS<b>3</b> is transferred to the latch <b>539</b> and a logic high latency signal is generated as shown in FIG. <b>9</b>S. As with the first-fourth latches <b>531</b>-<b>534</b>, the reset input of the output latch <b>539</b> is also connected to the reset signal, and the state thereof is reset to zero when the reset signal is enabled.

0049The latency signal generator <b>502</b> illustrated in <figref idref="DRAWINGS">FIG. 5</figref> further includes a mapping unit <b>540</b>. The mapping unit <b>540</b> includes first-fourth multiplexers <b>541</b>-<b>544</b>, which are four input by one output multiplexers. Each of the first-fourth multiplexers <b>541</b>-<b>544</b> receives each of the first-fourth transfer signals T<b>1</b>-T<b>4</b>, and outputs one of the first-fourth transfer signals T<b>1</b>-T<b>4</b> to a respective one of the first-fourth switches <b>535</b>-<b>538</b> in the read information storage unit <b>530</b>. The selection made by each of the first-fourth multiplexers <b>541</b>-<b>544</b> is controlled by the CAS latency information as discussed in greater detail below.

0050The latency signal generator <b>502</b> illustrated in <figref idref="DRAWINGS">FIG. 5</figref> supports four CAS latency modes as evidenced by the four D-flip flops, latches, switches and multiplexers in the circuits forming the latency signal generator <b>502</b>. However, the present invention is not limited to supporting four CAS latency modes, and could support greater or fewer CAS latency modes by increasing or decreasing the number of D-flip flops, latches, switches and multiplexers forming the latency circuit <b>500</b>.

0051<figref idref="DRAWINGS">FIG. 10A</figref> illustrates an embodiment of the first-fourth multiplexers <b>541</b>-<b>544</b> wherein the four CAS latency modes supported are modes <b>2</b>-<b>5</b>. As shown, each of the first-fourth multiplexers <b>541</b>-<b>544</b> maps one of the first-fourth transfer signals T<b>1</b>-T<b>4</b> into an output transfer signal TCLK<b>1</b>-TCLK<b>4</b>, respectively. Here, the N bits forming the CAS latency information may be used as the selection signal of the first-fourth multiplexers <b>541</b>-<b>544</b> as illustrated in FIG. <b>10</b>A. Alternatively, as illustrated in <figref idref="DRAWINGS">FIG. 10A</figref> as well, gates in each of the first-fourth multiplexers <b>541</b>-<b>544</b> are controlled by a respective CAS latency indicator CL<b>2</b>-CL<b>5</b>. The CAS latency indicators are decoded from the CAS latency information in the manner discussed in the Background of the Invention section. Each gate selectively transfers one of the transfer signals T<b>1</b>-T<b>4</b> as a transfer clock signal TCLK<b>1</b>-TCLK<b>4</b> based on the respective CAS latency indicator. <figref idref="DRAWINGS">FIG. 10B</figref> illustrates which of the first-fourth transfer signals T<b>1</b>-T<b>4</b> is mapped to the first-fourth output transfer signals TCLK<b>1</b>-TCLK<b>4</b> for the embodiment of the multiplexers illustrated in FIG. <b>10</b>A.

0052Next, a high frequency operation of the memory device according to the embodiment illustrated in one of <figref idref="DRAWINGS">FIGS. 4A-4C</figref> and <figref idref="DRAWINGS">FIGS. 5</figref>, <b>6</b>, <b>7</b>, <b>10</b>A and <b>10</b>B will be described with respect to <figref idref="DRAWINGS">FIGS. 9A-9T</figref>. <figref idref="DRAWINGS">FIG. 9A</figref> illustrates the reset signal. When enabled, the reset signal resets the DLL circuit <b>120</b>, the read command path block <b>130</b>, the master clock generator <b>700</b> and the latency circuit <b>500</b>. As a result, as shown in <figref idref="DRAWINGS">FIGS. 9D-9M</figref> and <b>9</b>S, the data output clock signal CLKDQ, the master clock signal PCLKD, the first-fourth transfer signals T<b>1</b>-T<b>4</b>, the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b>, and the latency signal are reset to a logic low or zero state.

0053<figref idref="DRAWINGS">FIG. 9B</figref> illustrates the external clock signal ECLK. Pulses of the external clock signal ECLK have been labeled <b>1</b>, <b>2</b>, <b>3</b>, etc., in order to provide an understanding of the relationship between the external clock signal ECLK and both the data output clock signal CLKDQ and the master clock signal PCLKD. As shown in <figref idref="DRAWINGS">FIG. 9D</figref>, after a first internal delay period tRS<b>1</b>, the DLL circuit <b>120</b> begins generating the output clock signal CLKDQ. As shown in <figref idref="DRAWINGS">FIG. 9E</figref>, after a second internal delay period tRS<b>2</b>, the master clock generator <b>700</b> begins generating the master clock signal PCLKD. As was described previously, the output data clock signal CLKDQ precedes the external clock signal ECLK by a time period tSAC. The clock pulses of the output data clock signal CLKDQ have also been numbered <b>1</b>, <b>2</b>, <b>3</b>, etc., to show the relationship between these clock signal pulses and the clock signal pulses of the external clock signal ECLK. The master clock generator <b>700</b> begins generating the master clock signal PCLKD, a time period equal to tSAC plus tREAD after the output data clock signal CLKDQ is generated. The time period tSAC has been discussed in detail above. The time period tREAD is the period of time between receipt of the read command and generation of the internal read signal PREAD by the read command buffer <b>134</b>. The pulses of the master clock signal PCLKD illustrated in <figref idref="DRAWINGS">FIG. 9E</figref> have also been labeled <b>1</b>, <b>2</b>, <b>3</b>, etc., to show the correspondence between these clock signal pulses and the clock signal pulses of the data output clock signal CLKDQ and the external clock signal ECLK. Accordingly, it will be understood that the reset operation establishes the timing relationships between these clock signals.

0054As shown in <figref idref="DRAWINGS">FIGS. 9F-9I</figref> with respect to <figref idref="DRAWINGS">FIG. 9D</figref>, once the transfer signal generator <b>550</b> begins receiving clock signal pulses of the output data clock signal CLKDQ, pulses of the first-fourth transfer signals T<b>1</b>-T<b>4</b> are generated. As demonstrated by <figref idref="DRAWINGS">FIGS. 9F-9I</figref>, each transfer signal has a frequency equal to the frequency of the external clock signal ECLK divided by the maximum number of supported CAS latency modes. Namely, it will be appreciated that the frequency of the transfer signals is determined by the number of D-flip flops in the second ring shift register <b>560</b>.

0055<figref idref="DRAWINGS">FIGS. 9J-9M</figref> with respect to <figref idref="DRAWINGS">FIG. 9E</figref> illustrate that the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b> are generated by the sampling clock signal generator <b>510</b> when the master clock generator <b>700</b> begins generating pulses of the master clock signal PCLKD. As with the transfer signals, the sampling clock signals also have a frequency that is equal to the frequency of the external clock signal ECLK divided by the maximum number of supported CAS latency modes. Namely, the frequency of the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b> is determined by the number of D-flip flops in the first ring shift register <b>520</b>.

0056The above discussed operation of the embodiment according to the present invention holds for any of the four possible CAS latency modes two-five, supported by this embodiment of the invention. <figref idref="DRAWINGS">FIGS. 9F-9I</figref> include parentheticals that show which of the first-fourth transfer signals T<b>1</b>-T<b>4</b> are mapped to the first-fourth output transfer signals TCLK<b>1</b>-TCLK<b>4</b> when the CAS latency mode is 4. Also, <figref idref="DRAWINGS">FIGS. 9O-9T</figref> illustrate the output signals LS<b>1</b>-LS<b>4</b>, the latency signal, and the data output from the memory device <b>400</b> when the CAS latency mode is <b>4</b> and a read command is received by the memory device <b>400</b> as illustrated in FIG. <b>9</b>C.

0057As shown in <figref idref="DRAWINGS">FIG. 9C</figref>, in this operational example, the read command signal is received when clock signal pulse <b>3</b> of the external clock signal ECLK transitions to logic high. Consequently, as shown in <figref idref="DRAWINGS">FIG. 9N</figref>, the internal read signal PREAD is generated after an internal delay of tREAD, by the read command path block <b>130</b>.

0058As shown in <figref idref="DRAWINGS">FIGS. 9F-9I</figref>, when the CAS latency is 4, the first-fourth transfer signals T<b>1</b>-T<b>4</b> are mapped by the mapping unit <b>540</b> to the second, third, fourth and first output signals TCLK<b>2</b>, TCLK<b>3</b>, TCLK<b>4</b> and TCLK<b>1</b>. Stated another way, first-fourth switches <b>535</b>-<b>538</b> receive the fourth, first, second and third transfer signals T<b>1</b>-T<b>4</b>, respectively. As such, when the internal read signal PREAD transitions to logic high as shown in <figref idref="DRAWINGS">FIG. 9N</figref>, the third sampling clock signal SCLK<b>3</b> causes the third latch <b>533</b> to latch the logic high PREAD signal. The other latches will have latched logic low PREAD. Accordingly, only the third output signal LS<b>3</b> from the third latch <b>533</b> will have a logic high state as shown in <figref idref="DRAWINGS">FIGS. 9O-9R</figref>.

0059Then, when the second transfer signal T<b>2</b> transitions to logic high, the third switch <b>537</b> supplies a logic high signal to the output latch <b>539</b>, which in turn supplies a logic high latency signal as shown in FIG. <b>9</b>S. Because the latency signal is logic high when the output data clock signal CLKDQ transitions high at pulse <b>7</b> of the output data clock signal CLKDQ, the memory device <b>400</b> will output data D<b>1</b> as shown in <figref idref="DRAWINGS">FIG. 9T</figref> at the rising edge of pulse <b>7</b> of the external clock signal ECLK as shown in FIG. <b>9</b>B. Accordingly, with the read command having been received during pulse <b>3</b> of the external clock signal ECLK and the data being output from the memory device <b>400</b> at pulse <b>7</b> of the external clock signal ECLK, a CAS latency of <b>4</b> is achieved for the high frequency operation shown in FIG. <b>9</b>B. In this embodiment, a single data word is output; however, the present invention is not limited to this embodiment. Instead, by increasing the length of the read command, the number of data words output can be increased.

0060As will be appreciated, the mapping unit <b>540</b> selectively associates the transfer signals with the sampling clock signals based on the CAS latency to create a desired timing relationship between the sampling and transfer signals. This relationship then controls the time period between the receipt of a read command and the output of data by the memory device <b>400</b>. More specifically, this relationship controls the time period between receipt of the internal read signal PREAD and the generation of the latency signal. Here, the sampling clock signals trigger the first-fourth latches <b>531</b>-<b>534</b> and thus serve to designate a point in time when the read command is received. The association of the transfer signals with the sampling clock signals then serves as a second pointer in time as to when the latency signal should be generated. Through this arrangement and methodology, read operation errors during high frequency operation are prevention.

0061<figref idref="DRAWINGS">FIG. 11</figref> illustrates another embodiment of the latency signal generator <b>502</b> according to the present invention. As shown, the latency signal generator <b>502</b> in this embodiment is the same as the embodiment of <figref idref="DRAWINGS">FIG. 5</figref>, except that the mapping unit <b>540</b> has been eliminated and a new mapping unit <b>1100</b> has been added. Also, the reset signal has been deleted, but only to simplify the description. In view of the above, only the differences between the embodiments of <figref idref="DRAWINGS">FIGS. 11 and 5</figref> will be described for the sake of brevity.

0062With the elimination of the mapping unit <b>540</b>, the transfer signals T<b>1</b>-T<b>4</b> generated by the transfer signal generator <b>550</b> are directly supplied to the first-fourth switches <b>535</b>-<b>538</b> as the first-fourth transfer clock signals TCLK<b>1</b>-TCLK<b>4</b>, respectively. Accordingly, in this embodiment, transfer signal generator <b>550</b> serves as a transfer clock signal generator.

0063The mapping unit <b>1100</b> maps the first-fourth sampling signals S<b>1</b>-S<b>4</b> to the first-fourth latches <b>531</b>-<b>534</b> as the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b>. The mapping unit <b>1100</b> includes first-fourth multiplexers <b>1121</b>-<b>1124</b>, which are four input by one output multiplexers, as shown in FIG. <b>13</b>A. Each of the first-fourth multiplexers <b>1121</b>-<b>1124</b> receives each of the first-fourth sampling signals S<b>1</b>-S<b>4</b>, and outputs one of the first-fourth sampling signals S<b>1</b>-S<b>4</b> to a respective one of the first-fourth latches <b>531</b>-<b>534</b> in the read information storage unit <b>530</b>. The selection made by each of the first-fourth multiplexers <b>1121</b>-<b>1124</b> is controlled by the CAS latency information as shown in FIG. <b>13</b>A.

0064The latency signal generator <b>502</b> illustrated in <figref idref="DRAWINGS">FIG. 11</figref> supports four CAS latency modes as evidenced by the four D-flip flops, latches, switches and multiplexers in the circuits forming the latency signal generator <b>502</b>. However, the present invention is not limited to supporting four CAS latency modes, and could support greater or fewer CAS latency modes by increasing or decreasing the number of D-flip flops, latches, switches and multiplexers forming the latency signal generator <b>502</b>.

0065<figref idref="DRAWINGS">FIG. 13A</figref> illustrates an embodiment of the first-fourth multiplexers <b>1121</b>-<b>1124</b> wherein the four CAS latency modes supported are modes <b>2</b>-<b>5</b>. As shown, each of the first-fourth multiplexers <b>1121</b>-<b>1124</b> maps one of the first-fourth sampling signals S<b>1</b>-S<b>4</b> into a sampling clock signal SCLK<b>1</b>-SCLK<b>4</b>, respectively. Here, the N bits forming the CAS latency information may be used as the selection signal of the first-fourth multiplexers <b>1121</b>-<b>1124</b> as illustrated in FIG. <b>10</b>A. Alternatively, as illustrated in <figref idref="DRAWINGS">FIG. 10A</figref> as well, gates in each of the first-fourth multiplexers <b>1121</b>-<b>1124</b> are controlled by a respective CAS latency indicator CL<b>2</b>-CL<b>5</b>. The CAS latency indicators are decoded from the CAS latency information in the manner discussed in the Background of the Invention section. Each gate selectively transfers one of the sampling signals S<b>1</b>-S<b>4</b> as a sampling clock signal SCLK<b>1</b>-SCLK<b>4</b> based on the respective CAS latency indicator. <figref idref="DRAWINGS">FIG. 13B</figref> illustrates which of the first-fourth sampling signals S<b>1</b>-S<b>4</b> is mapped to the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b> for the embodiment of the multiplexers illustrated in FIG. <b>13</b>A.

0066<figref idref="DRAWINGS">FIGS. 12A-12S</figref> illustrate the high frequency operation of the memory device according to the embodiment illustrated in one of <figref idref="DRAWINGS">FIGS. 4A-4C</figref> and <figref idref="DRAWINGS">FIGS. 11</figref>, <b>6</b>, <b>7</b>, <b>13</b>A and <b>13</b>B for the CAS latency mode of four. <figref idref="DRAWINGS">FIGS. 12A-12S</figref> correspond to <figref idref="DRAWINGS">FIGS. 9B-9E</figref>, <b>9</b>N, <b>9</b>F-<b>9</b>M, and <b>9</b>O-<b>9</b>T, respectively. Accordingly, <figref idref="DRAWINGS">FIGS. 12A-12S</figref> will not be described in detail for the sake of brevity.

0067<figref idref="DRAWINGS">FIG. 14</figref> illustrates a further exemplary embodiment of the latency signal generator <b>502</b>. As shown, the latency signal generator <b>502</b> in this embodiment includes a sampling clock signal generator <b>1410</b>, which selectively generates the first-fourth sampling clocks SCLK<b>1</b>-SCLK<b>4</b> based on the CAS latency information, and a transfer clock signal generator <b>1420</b>, which selectively generates the first-fourth transfer clocks TCLK<b>1</b>-TCLK<b>4</b> based on the CAS latency information. The generated sampling clock and transfer clock signals are supplied to the read information storage unit <b>530</b> described in detail above with respect to the embodiment of FIG. <b>5</b>. Accordingly, only the sampling clock signal generator <b>1410</b> and the transfer clock signal generator <b>1420</b> will be described in detail below. Also, as with the embodiment of <figref idref="DRAWINGS">FIG. 11</figref>, the reset signal has been deleted, but only to simplify the description.

0068The sampling clock signal generator <b>1410</b> and the transfer clock signal generator <b>1420</b> include a ring shifter cooperatively associated with control logic such as illustrated in <figref idref="DRAWINGS">FIG. 15</figref> to selectively generate the respective clock signals. As shown in <figref idref="DRAWINGS">FIG. 15</figref>, first-fourth D-flip flops <b>1431</b>-<b>1434</b> are connected in cascade with first-third control logic units <b>1441</b>-<b>1443</b> disposed between the first and second, second and third and third and fourth D-flip flops, respectively.

0069Each of the first-third control logic units <b>1441</b>-<b>1443</b> includes an inverter <b>1451</b> receiving and inverting the Q output of the previous D-flip flop. A NOR gate <b>1453</b> receives the output of the inverter and a respective CAS latency indicator decoded in the well-known manner from the CAS latency information. As shown in <figref idref="DRAWINGS">FIG. 15</figref>, the CAS latency indicators CL<b>2</b>-CL<b>4</b> for the second-fourth CAS latency modes are respectively supplied as an input to the NOR gate <b>1453</b> in the first-third control logic units <b>1441</b>-<b>1443</b>. The output of the NOR gate <b>1453</b> is supplied to D input of the next D-flip flop. The clock inputs of the first-fourth D-flip flops <b>1431</b>-<b>1434</b> receive the master clock signal PCLKD in the case of the sampling clock signal generator <b>1410</b> or the data output clock signal CLKDQ in the case of the transfer clock signal generator <b>1420</b>.

0070The Q outputs of the first-fourth D-flip flops <b>1431</b>-<b>1434</b> are received by first-fourth switches <b>1461</b>-<b>1464</b>. The first-fourth switches <b>1461</b>-<b>1464</b> selectively connect the Q outputs of the first-fourth D-flip flops <b>1431</b>-<b>1434</b> with the D input of the first D-flip flop <b>1431</b> based on the respectively received CAS latency indicators CL<b>2</b>-CL<b>5</b> for the second-fifth CAS latency modes. The Q outputs of the first-fourth D-flip flops supply the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b> in the case of the sampling clock signal generator <b>1410</b> or supply the first-fourth transfer clock signals TCLK<b>1</b>-TCLK<b>4</b> in the case of the transfer clock signal generator <b>1420</b>. Lastly, while not shown, the reset inputs of the first-fourth D-flip flops <b>1431</b>-<b>1434</b> receive the reset signal. The first-fourth D-flip flops <b>1431</b>-<b>1434</b> are resettable D-flip flops. The reset signal enables the pre-setting of the shift register such that the first-fourth D-flip flops are reset (logic low state). Additional control logic well-known in the art (not shown) is connected to the D input of the first D-flip flop <b>1431</b> to load a logic “1” (logic high state) into the first D-flip flop <b>1431</b>.

0071The logic high signal will load into the first D-flip flop <b>1431</b> on the rising edge of the received clock signal (PCLKD or CLKDQ), and this pulse will be transferred to the second-fourth D-flip flops <b>1432</b>-<b>1433</b> depending on the CAS latency information as each clock signal pulse is received. When the logic high signal resides in a respective one of the first-fourth D-flip flops <b>1431</b>-<b>1434</b>, the corresponding sampling clock signal/transfer clock signal is active.

0072When the first-third control logic units <b>1441</b>-<b>1443</b> receive a logic low CAS latency indicator, the first-third control logic units <b>1441</b>-<b>1443</b> transfer the Q output from the previous D-flip flop to the D input of the next D-flip flop. When the first-third control logic units <b>1441</b>-<b>1443</b> receive a logic high CAS latency indicator, the first-third control logic units <b>1441</b>-<b>1443</b> output a logic low state to the next D-flip flop regardless of the Q output of the previous D-flip flop.

0073As will be appreciated, the logic high state loaded into the first D-flip flop <b>1431</b> will only be transferred to a next position in the ring shift register selectively formed by the first-fourth D-flip flops <b>1431</b>-<b>1434</b> based on the CAS latency information. Thus, the CAS latency information controls the number of active sampling clock signals and transfer clock signals.

0074For example, if the CAS latency information indicates CAS latency mode 4, then the CAS latency indicators CL<b>2</b> and CL<b>3</b> are logic low. Accordingly, the logic high state loaded into the first D-flip flop <b>1431</b> will be transferred to the second D-flop flop <b>1432</b> and then the third D-flip flop <b>1433</b> in synchronization with the received clock signal (PCLKD/CLKDQ). But, this logic high state will not be transferred from the third control logic unit <b>1443</b> to the fourth D-flop flop <b>1434</b> by third control logic unit <b>1443</b> because the third control logic unit <b>1443</b> receives a logic high CAS latency indicator CL<b>4</b>. As a result, the first-third sampling clock signal SCLK<b>1</b>-SCLK<b>3</b> and the first-third transfer clock signals TCLK<b>1</b>-TCLK<b>3</b> will be activated, but not the fourth sampling clock signal SCLK<b>4</b> or the fourth transfer clock signal TCLK<b>4</b>.

0075This operation is illustrated in <figref idref="DRAWINGS">FIGS. 17A</figref>, <b>17</b>C-D and <b>17</b>F-M. <figref idref="DRAWINGS">FIG. 17A</figref> illustrates the external clock signal ECLK and <figref idref="DRAWINGS">FIGS. 17C-D</figref> illustrates the data output clock signal CLKDQ and the master clock signal PCLKD generated from the external clock signal ECLK. <figref idref="DRAWINGS">FIGS. 17F-17I</figref> illustrate the first-fourth transfer clock signals TCLK<b>1</b>-TCLK<b>4</b>, and <figref idref="DRAWINGS">FIGS. 17J-17M</figref> illustrates the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b> when the CAS latency mode is 4.

0076As mentioned above, the CAS latency indicators CL<b>2</b>-CL<b>5</b> also respectively control operation of the first-fourth switches <b>1461</b>-<b>1464</b>. When the first-fourth switches <b>1461</b>-<b>1464</b> receive a logic high CAS latency indicator, the first-fourth switches <b>1461</b>-<b>1464</b> connect the respectively received Q output from the first-fourth D-flip flops <b>1431</b>-<b>1434</b> with the D input of the first D-flip flop <b>1431</b>. For example, when the CAS latency information indicates a CAS latency mode of 4, then the CAS latency indicator CL<b>4</b> is a logic high state, and only the third switch <b>1463</b> closes. This connects the Q output of the third D-flip flop <b>1433</b> to the D input of the first D-flip flop <b>1431</b>. As discussed above, the logic high state loaded into the first D-flip flop <b>1431</b> will only propagate up to the third D-flip flop <b>1433</b> when the CAS latency mode is 4. Accordingly, the first-fourth switches <b>1461</b>-<b>1464</b> and the first-third control logic units <b>1441</b>-<b>1443</b> form control logic selectively configuring a ring shifter having a length dependent on the CAS latency information.

0077<figref idref="DRAWINGS">FIG. 16</figref> illustrates tables for CAS latency modes two-five that demonstrate which of the first-fourth transfer clock signals TCLK<b>1</b>-TCLK<b>4</b> and which of the first-fourth sampling clock signals SCLK<b>1</b>-SCLK<b>4</b> become active for each CAS latency mode.

0078Next, a high frequency operation of the memory device according to the embodiment illustrated in <figref idref="DRAWINGS">FIGS. 4A</figref>, B or C and <figref idref="DRAWINGS">FIGS. 14-15</figref> will be described with respect to <figref idref="DRAWINGS">FIGS. 17A-17S</figref>. <figref idref="DRAWINGS">FIG. 17A</figref> illustrates the external clock signal ECLK. Pulses of the external clock signal ECLK have been labeled <b>1</b>, <b>2</b>, <b>3</b>, etc., in order to provide an understanding of the relationship between the external clock signal ECLK and both the data output clock signal CLKDQ and the master clock signal PCLKD. As was described previously, the output data clock signal CLKDQ shown in <figref idref="DRAWINGS">FIG. 17C</figref> precedes the external clock signal ECLK by a time period tSAC. The clock pulses of the output data clock signal CLKDQ have also been numbered <b>1</b>, <b>2</b>, <b>3</b>, etc., to show the relationship between these clock signal pulses and the clock signal pulses of the external clock signal ECLK. As also discussed above, the master clock generator <b>700</b> begins generating the master clock signal PCLKD, a time period equal to tSAC plus tREAD after the output data clock signal CLKDQ is generated as shown in FIG. <b>17</b>D. As shown by <figref idref="DRAWINGS">FIGS. 17B and 17E</figref>, the internal read command PREAD is generated a time period tREAD after receiving the read command. The pulses of the master clock signal PCLKD illustrated in <figref idref="DRAWINGS">FIG. 17D</figref> have also been labeled <b>1</b>, <b>2</b>, <b>3</b>, etc., to show the correspondence between these clock signal pulses and the clock signal pulses of the data output clock signal CLKDQ and the external clock signal ECLK. It will be understood from the description of the previous embodiments, that the reset operation aids in establishing the timing relationships between these clock signals.

0079As shown in <figref idref="DRAWINGS">FIGS. 17F-17H</figref> with respect to <figref idref="DRAWINGS">FIG. 17C</figref>, once the transfer clock signal generator <b>1420</b> begins receiving clock signal pulses of the output data clock signal CLKDQ, pulses of the first-third transfer clock signals TCLK<b>1</b>-TCLK<b>3</b> are generated. For the reasons described in detail above and as shown by <figref idref="DRAWINGS">FIG. 171</figref>, because the CAS latency is four, the transfer clock signal generator <b>1420</b> does not activate the fourth transfer clock signal TCLK<b>4</b>. As demonstrated by <figref idref="DRAWINGS">FIGS. 17F-17H</figref>, each of the active first-third transfer clock signals has a frequency equal to the frequency of the external clock signal ECLK divided by one less than the CAS latency mode. Namely, it will be appreciated that the frequency of the transfer clock signals is determined by the length of ring shift register configured by the control logic in the transfer clock signal generator <b>1420</b> based on the CAS latency mode.

0080<figref idref="DRAWINGS">FIGS. 17J-17L</figref> with respect to <figref idref="DRAWINGS">FIG. 17D</figref> illustrate that the first-third sampling clock signals SCLK<b>1</b>-SCLK<b>3</b> are generated by the sampling clock signal generator <b>1410</b> in synchronization with the pulses of the master clock signal PCLKD. For the reasons described in detail above and as shown by <figref idref="DRAWINGS">FIG. 17M</figref>, because the CAS latency is four, the sampling clock signal generator <b>1410</b> does not activate the fourth sampling clock signal SCLK<b>4</b>. As with the transfer clock signals, the sampling clock signals also have a frequency that is equal to the frequency of the external clock signal ECLK divided by one less than the CAS latency mode. Namely, the frequency of the activated first-third sampling clock signals SCLK<b>1</b>-SCLK<b>3</b> is determined by the length of ring shift register configured by the control logic in the sampling clock signal generator <b>1410</b> based on the CAS latency mode.

0081<figref idref="DRAWINGS">FIGS. 17N-17S</figref> illustrate the output signals LS<b>1</b>-LS<b>4</b>, the latency signal, and the data output from the memory device <b>400</b> when the CAS latency mode is 4 and a read command is received by the memory device <b>400</b> as illustrated in FIG. <b>17</b>B.

0082As shown in <figref idref="DRAWINGS">FIG. 17B</figref>, in this operational example, the read command signal is received when clock signal pulse zero of the external clock signal ECLK transitions to logic high. Consequently, as shown in <figref idref="DRAWINGS">FIG. 17E</figref>, the internal read signal PREAD is generated after an internal delay of tREAD, by the read command path block <b>130</b>. When the internal read signal PREAD transitions to logic high as shown in <figref idref="DRAWINGS">FIG. 17E</figref>, the first sampling clock signal SCLK<b>1</b> causes the first latch <b>531</b> to latch the logic high PREAD signal. The other latches will have latched logic low PREAD. Accordingly, only the first output signal LS<b>1</b> from the third latch <b>531</b> will have a logic high state as shown in <figref idref="DRAWINGS">FIGS. 17N-17Q</figref>.

0083Then, when the first transfer clock signal TCLK<b>1</b> transitions to logic high, the first switch <b>535</b> supplies a logic high signal to the output latch <b>539</b>, which in turn supplies a logic high latency signal as shown in FIG. <b>17</b>R. Because the latency signal is logic high when the output data clock signal CLKDQ transitions high at pulse <b>4</b> of the output data clock signal CLKDQ, the memory device <b>400</b> will output data D<b>0</b> as shown in <figref idref="DRAWINGS">FIG. 9S</figref> at the rising edge of pulse <b>4</b> of the external clock signal ECLK as shown in FIG. <b>9</b>A. Accordingly, a CAS latency of 4 is achieved for the high frequency operation shown in FIG. <b>17</b>A. In this embodiment, a single data word is output; however, the present invention is not limited to this embodiment. Instead, by increasing the length of the read command, the number of data words output can be increased.

0084<figref idref="DRAWINGS">FIGS. 18 and 19</figref> illustrate timing diagrams corresponding to the timing diagrams in <figref idref="DRAWINGS">FIG. 17</figref> for CAS latency modes three and five, respectively. As the timing diagrams of <figref idref="DRAWINGS">FIGS. 18 and 19</figref> are readily understood from the description of the timing diagrams in <figref idref="DRAWINGS">FIG. 17</figref>, the timing diagrams in <figref idref="DRAWINGS">FIGS. 18 and 19</figref> will not be described in detail for the sake of brevity.

0085The latency signal generator <b>502</b> illustrated in <figref idref="DRAWINGS">FIG. 14</figref> supports four CAS latency modes as evidenced by the four D-flip flops, latches, switches and multiplexers in the circuits forming the latency signal generator <b>502</b>. However, the present invention is not limited to supporting four CAS latency modes, and could support greater or fewer CAS latency modes by increasing or decreasing the number of D-flip flops, latches, switches and multiplexers forming the latency circuit <b>500</b>.

0086As will be appreciated, the sampling clock signal generator <b>1410</b> and the transfer clock signal generator <b>1420</b> selectively activate the sampling and transfer clock signals and control the frequency of the activated sampling and transfer clock signals based on the CAS latency to create a desired timing relationship between the sampling and transfer clock signals. This relationship then controls the time period between the receipt of a read command and the output of data by the memory device <b>400</b>. More specifically, this relationship controls the time period between receipt of the internal read signal PREAD and the generation of the latency signal. As with previous embodiments, the sampling clock signals trigger the first-fourth latches <b>531</b>-<b>534</b> and thus serve to designate a point in time when the read command is received. The association of the transfer clock signals with the sampling clock signals then serves as a second pointer in time as to when the latency signal should be generated. Through this arrangement and methodology, read operation errors during high frequency operation are prevention.

0087The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.