Circuit arrangement
Summary by NHIP
LED Current Control Circuit
The circuit arrangement supplies an LED array using a DC-DC up-converter operating in critical discontinuous mode. A control circuit adjusts the switching element's conduction time T on to be proportional to the square of the output voltage divided by the input voltage (V out /V in 2).
Claim Score by NHIP
Abstract
In an up-converter feed forward control of the output current is effected by rendering the conduction time of the switching element proportional to Vout/Vin2. This control is fast and avoids interference and loss of efficiency.

Term
Term ended
Expired 7 July 2023, 3.2 years ago.
- Priority
- Filed
- Granted
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- Today
9 claims: 4 independent, 5 dependent
- 1A circuit arrangement for supplying an LED array comprising:input terminals for connection to a voltage supply source;output terminals for connection to the LED array;a DC—DC-converter coupled between the input terminals and the output terminals, the DC—DC-converter comprising: an inductive element L;a unidirectional element;a switching element coupled to the inductive element and the unidirectional element;and a control circuit coupled to a control electrode of the switching element for generating a high frequency control signal for rendering the switching element conductive and non-conductive at a high frequency to thereby operate the DC—DC-converter in the critical discontinuous mode and equipped with circuitry for controlling the current through the output terminals at a predetermined value, the circuitry for controlling the current through the output terminals comprising: a circuit coupled to the input terminals and the output terminals for controlling a time lapse T on , during which the switching element is maintained in a conductive state during each high frequency period of the control signal, proportional to a mathematical expression that is a function of V in and V out , wherein V in is the voltage present between the input terminals and V out is the voltage present between the output terminals;wherein the DC—DC-converter is an up-converter and the circuit comprises a circuit for controlling T on proportional to V out /V in 2 .
- 2A circuit arrangement for supplying an LED array comprising:input terminals for connection to a voltage supply source;output terminals for connection to the LED array;a DC—DC-converter coupled between the input terminals and the output terminals, the DC—DC-converter comprising: an inductive element L;a unidirectional element;a switching element coupled to the inductive element and the unidirectional element;and a control circuit coupled to a control electrode of the switching element for generating a high frequency control signal for rendering the switching element conductive and non-conductive at a high frequency to thereby operate the DC—DC-converter in the critical discontinuous mode and equipped with circuitry for controlling the current through the output terminals at a predetermined value, the circuitry for controlling the current through the output terminals comprising: a circuit coupled to the input terminals and the output terminals for controlling a time lapse T on , during which the switching element is maintained in a conductive state during each high frequency period of the control signal, proportional to a mathematical expression that is a function of V in and V out , wherein V in is the voltage present between the input terminals and V out , is the voltage present between the output terminals;wherein the DC—DC-converter is a down-converter and the circuit comprises a circuit for controlling T on proportional to V out /((V out −V in ) 2 .
- 3A circuit arrangement for supplying an LED array comprising:input terminals for connection to a voltage supply source;output terminals for connection to the LED array;a DC—DC-converter coupled between the input terminals and the output terminals, the DC—DC-converter comprising: an inductive element L;a unidirectional element;a switching element coupled to the inductive element and the unidirectional element;and a control circuit coupled to a control electrode of the switching element for generating a high frequency control signal for rendering the switching element conductive and non-conductive at a high frequency to thereby operate the DC—DC-converter in the critical discontinuous mode and equipped with circuitry for controlling the current through the output terminals at a predetermined value, the circuitry for controlling the current through the output terminals comprising: a circuit coupled to the input terminals and the output terminals for controlling a time lapse T on , during which the switching element is maintained in a conductive state during each high frequency period of the control signal, proportional to a mathematical expression that is a function of V in and V out , wherein V in is the voltage present between the input terminals and V out is the voltage present between the output terminals;wherein the DC—DC-converter is a flyback-converter comprising a transformer with a transformation ratio N and the circuit comprises a circuit for controlling T on proportional to (V in +V out /N)/V in 2 .
- 4Broadest claimClaim Score 38, average(NHIP)A circuit arrangement for supplying an LED array comprising:input terminals for connection to a voltage supply source;output terminals for connection to the LED array;a DC—DC-converter coupled between the input terminals and the output terminals, the DC—DC-converter comprising: an inductive element L;a unidirectional element;a switching element coupled to the inductive element and the unidirectional element;and a control circuit coupled to a control electrode of the switching element for generating a high frequency control signal for rendering the switching element conductive and non-conductive at a high frequency to thereby operate the DC—DC-converter in the critical discontinuous mode and equipped with circuitry for controlling the current through the output terminals at a predetermined value, the circuitry for controlling the current through the output terminals comprising: a circuit coupled to the input terminals and the output terminals for controlling a time lapse T on , during which the switching element is maintained in a conductive state during each high frequency period of the control signal, proportional to a mathematical expression that is a function of V in and V out , wherein V in is the voltage present between the input terminals and V out is the voltage present between the output terminals;wherein the circuit comprises a current source that generates a current that is proportional to V in 2 .
Independent claims4
32 paragraphs in 4 sections, as filed
BACKGROUND
1. Field of Invention
The invention relates to a circuit arrangement for supplying an LED array.
2. Description of Related Art
A circuit arrangement for supplying an LED array may include input terminals for connection to a voltage supply source, output terminals for connection to the LED array, and a DC—DC-converter coupled between the input terminals and the output terminals and equipped with an inductive element L, a unidirectional element, a switching element coupled to the inductive element and the unidirectional element, and a control circuit coupled to a control electrode of the switching element for generating a high frequency control signal for rendering the switching element conductive and non-conductive at a high frequency to thereby operate the DC—DC-converter in the critical discontinuous mode and equipped with means I for controlling the current through the output terminals at a predetermined value.
Operation in the critical discontinuous mode means that the current through the inductive element L equals zero at the beginning and at the end of each period of the control signal, while it differs from zero during each period of the control signal. This mode of operation ensures a high efficiency since power losses in the unidirectional element are prevented to a large extent. In the known converter the means I for controlling the current through the output terminals consist of a current control loop equipped with feedback. The actual value of the current is measured and compared with a desired value by means of a comparator that generates an error signal that in turn adjusts the control signal in such a way that the actual value of the current through the output terminals substantially equals the desired value. An advantage of such a control loop is that it allows a very accurate control of the value of the current. Disadvantages, however, are that the control loop is expensive since it comprises many components and that the control loop is comparatively slow. Furthermore, in case the actual value of the current is measured by measuring the voltage across an ohmic resistor that is placed in series with the output terminals, the control loop also causes a substantial power dissipation.
SUMMARY
Embodiments of the invention aim to provide a circuit arrangement comprising circuitry for controlling the output current, wherein the disadvantages mentioned above are absent.
In accordance with embodiments of the invention, a circuit arrangement for supplying an LED array may include input terminals for connection to a voltage supply source, output terminals for connection to the LED array, and a DC—DC-converter coupled between the input terminals and the output terminals and equipped with an inductive element L, a unidirectional element, a switching element coupled to the inductive element and the unidirectional element, and a control circuit coupled to a control electrode of the switching element for generating a high frequency control signal for rendering the switching element conductive and non-conductive at a high frequency to thereby operate the DC—DC-converter in the critical discontinuous mode and equipped with circuitry I for controlling the current through the output terminals at a predetermined value.
Circuitry I is coupled to the input terminals and the output terminals for controlling the time lapse T<sub>on</sub>, during which the switching element is maintained in a conductive state during each high frequency period of the control signal, proportional to a mathematical expression that is a function of V<sub>in </sub>and V<sub>out</sub>, wherein V<sub>in </sub>is the voltage present between the input terminals and V<sub>out </sub>is the voltage present between the output terminals.
Circuitry I in a circuit arrangement according to embodiments of the invention can be realized in a comparatively simple and inexpensive way. It has been found that the circuitry I counteracts changes in the input or output voltage of the circuit arrangement relatively fast and controls the current through the output terminals at a substantially constant level. Circuitry I in a circuit arrangement according to embodiments of the invention also do not dissipate a substantial amount of power.
DC—DC-converters of different types can be used in a circuit arrangement according to embodiments of the present invention. Good results have been obtained in case the DC—DC-converter is an up-converter and circuitry I controls T<sub>on </sub>proportional to V<sub>out </sub>/V<sub>in</sub><sup>2</sup>. Similarly, the DC—DC-converter can be implemented as a down-converter while circuitry I controls T<sub>on </sub>proportional to V<sub>out</sub>/((V<sub>out</sub>−V<sub>in</sub>)<sup>2 </sup>Good results have also been obtained in case the DC—DC-converter is a flyback-converter that comprises a transformer with a transformation ratio N and circuitry I controls T<sub>on </sub>proportional to (V<sub>in</sub>+V<sub>out</sub>/N)/V<sub>in</sub><sup>2. </sup>
Good results have been obtained for embodiments of a circuit arrangement according to the invention, wherein circuitry I comprises a current source that generates a current that is proportional to V<sub>in</sub><sup>2</sup>. Such a current source can be realized in a simple and dependable way, in case the current source comprises a first voltage divider coupled to the input terminals, a first zener diode coupled to the first voltage divider and a switching element coupled to the first zener diode. In a preferred embodiment the current source comprises a second zener diode. The second zener diode allows circuitry I to render T<sub>on </sub>proportional to 1/V<sub>in</sub><sup>2 </sup>for two different values of the input voltage (e.g. 12 V and 24 V). In addition to the current source, the control circuit preferably comprises a capacitor coupled to the current source, and a comparator equipped with a first comparator input terminal coupled to the capacitor, a second comparator input terminal coupled to an output terminal of a second voltage divider coupled to the output terminals of the circuit arrangement, and a comparator output terminal coupled to the control electrode of the switching element.
In case it is desirable to control the light output of the LED array operated by a circuit arrangement according to embodiments of the invention, the control circuit is preferably equipped with circuitry III for substantially square wave modulating the amplitude of the current through the output terminals. Circuitry III switches the current through the LEDs off during part of each period of the modulation and on during the remaining part. By adjusting the time lapse in each period of the modulation during which the LEDs carry a current, the light output of the LEDs can be adjusted. It is observed that circuitry III can be incorporated in the control circuit since the feed forward control of I<sub>out </sub>by circuitry I in a circuit arrangement according to embodiments of the invention is comparatively fast. In most known circuit arrangements equipped with a current control loop comprising feedback, circuitry III cannot be comprised in the control circuit since the control loop is too slow. In some embodiments, circuitry for modulating is realized in the form of a “chopper” that usually comprises a (semiconductor) switch and drive circuitry for driving the switch. The switch realizes the modulation by “chopping” the output current of the circuit arrangement. Such a chopper is comparatively expensive, generates interference and decreases the efficiency of the circuit arrangement for instance by hard switching. Furthermore, it is often necessary to take care of for instance interference shielding and dampening, increasing the costs and the complexity of the circuit arrangement even further. The fast control of the output current realized by circuitry I comprised in a circuit arrangement according to embodiments of the present invention allows the modulation of the output current to be effected by circuitry III that is part of the control circuit. As a consequence circuitry III is comparatively cheap, does not cause interference and does not lower the efficiency of the circuit arrangement.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention will be described making reference to a drawing. In the drawings:
<figref idref="DRAWINGS">FIG. 1</figref> shows an embodiment of a circuit arrangement according to the invention with a LED array connected to it and comprising a DC—DC-converter of the up-converter type,
<figref idref="DRAWINGS">FIG. 2</figref> shows part of the embodiment shown in <figref idref="DRAWINGS">FIG. 1</figref> in more detail, and
<figref idref="DRAWINGS">FIG. 3</figref> shows an embodiment of a circuit arrangement according to the invention with a LED array connected to it and comprising a DC—DC-converter.
DETAILED DESCRIPTION
In <figref idref="DRAWINGS">FIG. 1</figref>, K<b>1</b> and K<b>2</b> are input terminals for connection to a voltage supply source. Input terminals K<b>1</b> and K<b>2</b> are connected by means of a series arrangement of inductive element L and switching element Q<b>1</b>. Switching element Q<b>1</b> is shunted by a series arrangement of ohmic resistor R<b>1</b> and capacitor C<b>1</b> and by a series arrangement of diode D<b>1</b> and capacitor C<b>2</b>. In this embodiment diode D<b>1</b> forms a unidirectional element. Respective sides of capacitor C<b>2</b> are connected with output terminal K<b>3</b> and output terminal K<b>4</b>. An LED array LEDA is connected between output terminals K<b>3</b> and K<b>4</b>. A control electrode of switching element Q<b>1</b> is connected to an output terminal of circuit part I via a switching element Q<b>2</b>. Circuit part I forms circuitry I for controlling the current through output terminals K<b>3</b> and K<b>4</b> at a predetermined value. Respective input terminals of circuit part I are connected to input terminal K<b>1</b>, output terminal K<b>3</b> and an output terminal of a circuit part CC. Circuit part CC is a circuit part for controlling when the switching element Q<b>1</b> needs to be rendered conductive. Respective input terminals of the circuit part CC are connected to input terminal K<b>1</b> and a common terminal of inductive element L and switching element Q<b>1</b>. A control electrode of switching element Q<b>2</b> is coupled to an output terminal of circuit part IIIa. In <figref idref="DRAWINGS">FIG. 1</figref> this is indicated by means of a dotted line. An input terminal of circuit part IIIa is coupled to a light sensor LS. The light sensor LS, the circuit part III<i>a </i>and the switching element Q<b>2</b> together form circuitry III for substantially square wave modulating the amplitude of the current through the output terminals. Inductive element L, switching element Q<b>1</b>, capacitors C<b>1</b> and C<b>2</b>, ohmic resistor R<b>1</b>, diode D<b>1</b>, light sensor LS, circuit parts IIIa, CC and I and switching element Q<b>2</b> together form a DC—DC-converter of the up-converter type. The light sensor LS, the circuit parts IIIa, CC, I and the switching element Q<b>2</b> together form a control circuit for generating a high frequency control signal for rendering the switching element Q<b>1</b> conductive and non-conductive at a high frequency to thereby operate the DC—DC-converter in the critical discontinuous mode.
The operation of the circuit arrangement shown in <figref idref="DRAWINGS">FIG. 1</figref> is as follows.
When input terminals K<b>1</b> and K<b>2</b> are connected to a supply voltage source and circuit part IIIa controls switching element Q<b>2</b> in a conductive state, the control circuit renders the switching element Q<b>1</b> conductive and non-conductive at a high frequency in such a way that the DC—DC-converter is operated in the critical discontinuous mode. As pointed out hereabove this means that the amplitude of the current through the inductive element is substantially zero at the beginning and at the end of each period of the control signal. As a result, a DC current flows through the output terminals K<b>3</b> and K<b>4</b> and the LED array LEDA emits light.
The control circuit controls the switching in the following way. Because of the presence of capacitor C<b>1</b> (and the parasitic capacitor that is part of switching element Q<b>1</b>), the direction of the current through the inductive element L changes polarity for a very short time lapse at the end of each period of the control signal. As a consequence a current with a very small amplitude flows from the capacitor C<b>1</b> in the direction of the input terminal K<b>1</b>. This causes the common terminal of switching element Q<b>1</b> and the inductive element L to be at a higher potential than input terminal K<b>1</b>. Circuit part CC detects this situation and activates circuit part I that renders switching element Q<b>1</b> conductive and maintains switching element Q<b>1</b> conductive during a time lapse Ton that is proportional to V<sub>out</sub>/V<sub>in</sub><sup>2</sup>, wherein V<sub>in </sub>is the voltage that is present between the input terminals and V<sub>out </sub>is the voltage between the output terminals. During T<sub>on </sub>the current through inductive element L increases linearly to a value <i>I</i><sub>peak</sub>. For the value of I<sub>peak </sub>the following equation is valid: <br /><i>I</i><sub>peak</sub><i>=V</i><sub>in</sub><i>·T</i><sub>on</sub><i>/L</i><sub>o</sub>,<br /> wherein L<sub>o </sub>is the inductivity of inductive element L.
At the end of the time lapse T<sub>on </sub>the switching element Q<b>1</b> is rendered nonconductive by circuit part I. During the remaining part of the period of the control signal the amplitude of the current through inductive element L decreases linearly to substantially zero. As a consequence the shape of the current through inductive element L is triangular and the average value of the current through inductive element L in each period of the control signal therefore equals I<sub>peak</sub>/2. It follows that for the power Pin that is consumed by the DC—DC-converter the following equation holds: <br /><i>P</i><sub>in</sub><i>=V</i><sub>in</sub><i>·I</i><sub>peak</sub>/2.
When it is assumed that the voltage conversion by the DC—DC-converter is taking place without losses, the power supplied by the DC—DC-converter (V<sub>out</sub>·I<sub>out</sub>) to the LED array equals the power consumed by the DC—DC-converter: <br /><i>V</i><sub>in</sub><i>·I</i><sub>peak</sub>/2<i>=V</i><sub>out</sub><i>·I</i><sub>out</sub>,<br /> wherein I<sub>out </sub>is the current flowing through the output terminals K<b>3</b> and K<b>4</b>.
From the above equations the next equation can easily be derived: <br /><i>T</i><sub>on</sub><i>=I</i><sub>out</sub>·2<i>·L</i><sub>o</sub><i>·V</i><sub>out</sub>/V<sub>in</sub><sup>2</sup>.
From this latter equation it can be seen that the current I<sub>out </sub>can be maintained at a constant value, in case the time lapse T<sub>on </sub>is controlled at a value that is proportional to V<sub>out</sub>/V<sub>in</sub><sup>2</sup>. As a consequence the output current I<sub>out </sub>of the circuit arrangement shown in <figref idref="DRAWINGS">FIG. 1</figref> remains substantially unchanged, when the input voltage V<sub>in </sub>or the output voltage V<sub>out </sub>changes.
DC—DC-converters of different types can be used in a circuit arrangement according to embodiments of the present invention. For example, as illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, which is similar to <figref idref="DRAWINGS">FIG. 1</figref>, the DC—DC-converter, illustrated as box Conv, can be implemented as a down-converter while circuitry I controls T<sub>on </sub>proportional to V<sub>out</sub>/((V<sub>out</sub>−V<sub>in</sub>)<sup>2</sup>. Good results have also been obtained in case the DC—DC-converter Conv is a flyback-converter that comprises a transformer TR with a transformation ratio N and circuitry <b>1</b> controls T<sub>on </sub>proportional to (V<sub>in</sub>+V<sub>out</sub>/N)/V<sub>in</sub><sup>2</sup>. The transformer TR is illustrated in <figref idref="DRAWINGS">FIG. 3</figref> with broken lines as the transformer may not be used with all converters.
During operation switching element Q<b>2</b> is switched on and off at a much lower frequency than the frequency of the control signal that controls switching element Q<b>1</b>. During the part of the modulation period in which switching element Q<b>2</b> is non-conductive the amplitude of the current I<sub>out </sub>through the output terminals is zero. As a result, the amplitude of the current I<sub>out </sub>through the output terminals is substantially square wave modulated. The light output of the LED array is monitored by the light sensor LS and a signal representing the average value of that light output is generated by circuit part IIIa. In circuit part IIIa this value is compared with a reference signal that is also generated by circuit part III<i>a </i>and represents the desired average value of the light output. The duty cycle of the signal controlling the conductive state of switching element Q<b>2</b>, or in other words the duty cycle of the modulation of the output current amplitude, is adjusted in accordance with the outcome of the comparison. As a result, the average value of the light output is controlled at a substantially constant level. It is noted that when switching element Q<b>2</b> is rendered conductive (in each period of the modulation), the feed forward control of the output current effected by circuit part I is fast enough to make sure that the amplitude of I<sub>out </sub>increases from substantially zero to a constant value in a comparatively short time. Unlike a much slower control loop incorporating current feedback, it is this fast control that allows the circuitry III for modulating the amplitude of I<sub>out </sub>to be part of the control circuit so that a “chopper” causing interference and decreased efficiency can be dispensed with.
<figref idref="DRAWINGS">FIG. 2</figref> shows circuit part I of the embodiment shown in <figref idref="DRAWINGS">FIG. 1</figref> in more detail. In <figref idref="DRAWINGS">FIG. 2</figref>, K<b>5</b> is a terminal that is connected to input terminal K<b>1</b> and K<b>6</b> is a terminal that is connected to input terminal K<b>2</b>, so that during operation the voltage V<sub>in </sub>is present between terminals K<b>5</b> and K<b>6</b>. Terminals K<b>5</b> and K<b>6</b> are connected by means of a series arrangement of ohmic resistor R<b>1</b> and R<b>3</b> and by means of a series arrangement of ohmic resistor R<b>5</b>, zener diode D<b>3</b>, transistor Q<b>3</b> and capacitor C<b>3</b>. Ohmic resistor R<b>3</b> is shunted by zener diode D<b>2</b>. A common terminal of ohmic resistor R<b>3</b> and zener diode D<b>2</b> is connected to a basis electrode of transistor Q<b>3</b>. Terminal K<b>5</b> is connected to an emitter electrode of transistor Q<b>3</b> by means of ohmic resistor R<b>2</b>. Capacitor C<b>3</b> is shunted by a switching element Q<b>4</b>. A control electrode of switching element Q<b>4</b> is connected to the output terminal of circuit part CC. Ohmic resistors R<b>1</b>, R<b>2</b>, R<b>3</b> and R<b>5</b>, zener diodes D<b>2</b> and D<b>3</b> and transistor Q<b>3</b> are so dimensioned that together they form a current source that is dimensioned to supply a current that is proportional to V<sub>in</sub><sup>2</sup>. Terminal K<b>8</b> is connected to output terminal K<b>3</b>. Terminal K<b>8</b> is also connected to terminal K<b>6</b> by means of a series arrangement of ohmic resistors R<b>7</b> and R<b>10</b>. During operation the voltage V<sub>out </sub>is present across this series arrangement. A common terminal of ohmic resistor R<b>7</b> and ohmic resistor R<b>10</b> is connected to a first input terminal of comparator COMP. A common terminal of transistor Q<b>3</b> and capacitor C<b>3</b> is connected to a second input terminal of comparator COMP. K<b>7</b> is a comparator output terminal that is coupled to the control electrode of switching element Q<b>1</b>.
The operation of the circuit part I shown in <figref idref="DRAWINGS">FIG. 2</figref> is as follows.
When the circuit part CC detects that the switching element Q<b>1</b> needs to become conductive, the voltage at its output terminal changes from low to high and switching element Q<b>4</b> is rendered conductive so that capacitor C<b>3</b> is discharged. As a result the voltage present at the second input terminal of the comparator COMP becomes lower than the voltage present at the first input terminal of the comparator, so that the voltage present at the comparator output terminal K<b>7</b> becomes high and switching element Q<b>1</b> is rendered conductive. As soon as capacitor C<b>3</b> is discharged switching element Q<b>4</b> is rendered non-conductive again and the current source supplying a current that is proportional to V<sub>in</sub><sup>2 </sup>charges capacitor C<b>3</b>. As long as the voltage over capacitor C<b>3</b> is lower than the voltage at the first input terminal of the comparator COMP, the voltage at the comparator output terminal is high and switching element Q<b>1</b> is maintained in a conductive state. The voltage at the output comparator terminal becomes low and therefore the switching element Q<b>1</b> becomes non-conductive, when the voltage across capacitor C<b>3</b> becomes equal to the voltage at the first input terminal of the comparator COMP. Since the current charging capacitor C<b>3</b> is proportional to V<sub>in</sub><sup>2 </sup>and the voltage at the first input terminal is proportional to V<sub>out</sub>, it follows that T<sub>on </sub>is proportional to V<sub>out</sub>/V<sub>in</sub><sup>2</sup>. The current source is designed in such a way that is suitable for use with two different values of V<sub>in</sub>, such as 12 V and 24 V. At the lowest value of the two different values of V<sub>in</sub>, only zener diode D<b>2</b> and not zener diode D<b>3</b> is conductive. As a consequence the current supplied by the current source is the current through ohmic resistor R<b>2</b>. At the highest of the two different values of V<sub>in</sub>, both zener diodes are conducting and the current supplied by the current source is the sum of the currents through ohmic resistors R<b>2</b> and R<b>5</b>.
It is noteworthy to observe that the current source in circuit part I in <figref idref="DRAWINGS">FIG. 2</figref> is so designed that the current it supplies is proportional to V<sub>in</sub><sup>2 </sup>only to a good approximation and not exactly. Furthermore, V<sub>in </sub>is often supplied by a battery and therefore will only vary over a limited range. As a consequence it is only necessary for the current source to supply a current that is approximately proportional to V<sub>in</sub><sup>2</sup>, for values of V<sub>in </sub>that differ not too much (for instance only 10% or 20% at most) from the average value of V<sub>in</sub>. In case for instance the current source is designed for an average value of V<sub>in </sub>that equals 12 V, it is in most practical cases completely satisfactory when the current source supplies a current that is approximately proportional to V<sub>in</sub><sup>2 </sup>for values of V<sub>in </sub>within the range 10.8V<V<sub>in</sub><13.2V. Similarly, in case the current source is designed for two different average values of V<sub>in </sub>such as 12V and 24 V, satisfactory results are obtained when the current source only supplies a current that is approximately proportional to V<sub>in</sub><sup>2</sup>, for values of V<sub>in </sub>for instance within the range 10.8V<V<sub>in</sub><13.2V and for values of V<sub>in </sub>for instance within the range 21.6V<V<sub>in</sub><26.4V.
In a practical embodiment of the circuitry shown in FIG. <b>1</b> and <figref idref="DRAWINGS">FIG. 2</figref> it was found that a variation by 10% of V<sub>in </sub>caused the output current I<sub>out </sub>to change by less than 3%. Similarly a variation by 20% of V<sub>in </sub>caused the output current I<sub>out </sub>to change by less than 5%. In case circuitry I would be absent, or in other words in case the T<sub>on </sub>of switching element Q<b>1</b> would remain unchanged, a 10% variation in the input voltage V<sub>in </sub>would lead to a 20% change in the output current, while a 20% variation in the input voltage V<sub>in </sub>would lead to a 40% change in the output current I<sub>out</sub>.
Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.
Contents4
4 sheets
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| US2005219872A1 | Cited by | United States of America | Pre-grant |
| US2005213353A1 | Cited by | United States of America | Pre-grant |
| US7557521B2 | Cited by | United States of America | Applicant |
| US7659673B2 | Cited by | United States of America | Applicant |
| US9066381B2 | Cited by | United States of America | Applicant |
| US8894437B2 | Cited by | United States of America | Applicant |
| US7256554B2 | Cited by | United States of America | Applicant |
| US9578703B2 | Cited by | United States of America | Applicant |
| US9485814B2 | Cited by | United States of America | Applicant |
| US9379578B2 | Cited by | United States of America | Applicant |
| US8436553B2 | Cited by | United States of America | Applicant |
| US7459864B2 | Cited by | United States of America | Applicant |
| US9420665B2 | Cited by | United States of America | Applicant |
| US8264172B2 | Cited by | United States of America | Applicant |
| US4648020A | Cites | United States of America | Search report |
| US4683529A | Cites | United States of America | Search report |
| US5235502A | Cites | United States of America | Search report |
| US6487097B2 | Cites | United States of America | Search report |
| US6597155B2 | Cites | United States of America | Search report |
8 members in 5 offices
Priority claims5
| Document | Office | Kind | Date |
|---|---|---|---|
| 02077826 | European Patent Office (EPO) | A | |
| 02077826 | European Patent Office (EPO) | A | |
| 02077826 | European Patent Office (EPO) | – | |
| 02077826 | – | – | – |
| EP20020077826 | – | – | – |
Members8
| Document | Office | Kind | |
|---|---|---|---|
| KR20040005622A | Republic of Korea | A | |
| DE10330135A1 | Germany | A1 | |
| JP2004048011A | Japan | A | |
| TW200405580A | Taiwan Province of China | A | |
| US2004095185A1 | United States of America | A1 | |
| US6933767B2This record | United States of America | B2 | |
| TWI309478B | Taiwan Province of China | B | |
| KR100940462B1 | Republic of Korea | B1 |
43 transactions on the USPTO file
Allowed after 2 non-final rejections.
- Non-final rejections
- 2
- Final rejections
- 0
- RCEs
- 0
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Expire PatentEXP. | EXP. | |
| Post Issue Communication - Certificate of CorrectionN423 | N423 | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Receipt into PubsR1021 | R1021 | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Receipt into PubsR1021 | R1021 | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Response to Reasons for AllowanceREAS | REAS | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Workflow - File Sent to ContractorSENT | SENT | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| New or Additional Drawing FiledC614 | C614 | |
| Response after Non-Final ActionA... | A... | |
| Workflow incoming amendment IFWWAMD | WAMD | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Workflow incoming amendment IFWWAMD | WAMD | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Transfer Inquiry to GAUTI1050 | TI1050 | |
| Application Return from OIPEWROIPE | WROIPE | |
| Application Return TO OIPEROIPE | ROIPE | |
| Application Is Now CompleteCOMP | COMP | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Application Is Now CompleteCOMP | COMP | |
| Additional Application Filing FeesADDFLFEE | ADDFLFEE | |
| A statement by one or more inventors satisfying the requirement under 35 USC 115, Oath of the ApplicOATHDECL | OATHDECL | |
| Notice Mailed--Application Incomplete--Filing Date AssignedINCD | INCD | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Request for Foreign Priority (Priority Papers May Be Included)RQPR | RQPR | |
| Initial Exam Team nnIEXX | IEXX |
9 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Lapsed due to failure to pay maintenance feeLapsedFP | FP | |
| Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH | STCH | |
| Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH | STCH | |
| Lapse for failure to pay maintenance feesLapsedLAPS | LAPS | |
| Maintenance fee reminder mailedREMI | REMI | |
| AssignmentAS | AS | |
| Fee paymentFPAY | FPAY | |
| Certificate of correctionCC | CC | |
| AssignmentAS | AS |
Numbers
- Publication
- 06933767
- Publication, DOCDB
- 6933767
- Publication, EPODOC
- US6933767
- Application
- 10614878
- Application, DOCDB
- 61487803
- Application, EPODOC
- US20030614878
Titles
- English
- Circuit arrangement
Patent term adjustment
- Net adjustment
- 0 days
Classification
- CPC, 6
- H05B45/3725
- H05B45/12
- G02F1/133
- H05B45/375
- H05B45/38
- H05B45/385
- IPC, 9
- G09G3 36
- G02F1 133
- G09G3 14
- G09G3 20
- G09G3 34
- H01L33 00
- H02M3 155
- H02M3 28
- H05B44 00
- USPC, 3
- 327530000
- 363021160
- 363071000