Method and apparatus for providing optimized high speed link utilization

BACKGROUND OF THE INVENTION

The present invention relates, in general, to the field of Fibre Channel switching technology. More particularly, the present invention relates to a port module that is adapted to receive a 10 gigabit-per-second fiber link for use in a Fibre Channel switching environment.

Fibre Channel is a high performance, serial interconnect standard designed for bi-directional, point-to-point communications between servers, storage systems, workstations, switches, and hubs. It offers a variety of benefits over other link-level protocols, including efficiency and high performance, scalability, simplicity, ease of use and installation, and support for popular high level protocols.

Fibre Channel employs a topology known as a “fabric” to establish connections between nodes. A fabric is a network of switches for interconnecting a plurality of devices without restriction as to the manner in which the switch can be arranged. A fabric can include a mixture of point-to-point and arbitrated loop topologies.

In Fibre Channel, a channel is established between two nodes where the channel's primary task is to transport data from one point to another at high speed with low latency. The Fibre Channel switch provides flexible circuit/packet switched topology by establishing multiple simultaneous point-to-point connections. Because these connections are managed by the switches or “fabric elements” rather than the connected end devices or “nodes”, fabric traffic management is greatly simplified from the perspective of the device.

The basic element of a fabric is a switch. In a fibre channel system, data is transported in frames, where each frame has a header identifying, among other things, a destination node. The destination identification is referred to as a “DID”. A switch comprises a plurality of ports that transmit and receive data frames from an external link. The port is implemented by circuitry that receives data from the external link, buffers data as needed, and preferably performs some analysis to ensure integrity of the received data and use header information, such as the DID to process the received frame within the switch.

A switch also includes mechanism such as a crossbar matrix or the like to internally couple each port on the switch to another port on the switch so that frames received on one port (e.g., a receive or RX port) can be communicated to another port (e.g., a transmit or TX port). A switch also includes data processing mechanisms for analyzing the received frame to determine the appropriate TX port that will reach the node specified by the frame's DID. In any given switch, the port electronics have a maximum data rate determined by the hardware components. Typically the port electronics will support data rates lower than the maximum data rate, but not higher.

As Fibre Channel technology advances, an increase in the data transmission speed of the Fibre Channel links becomes increasingly desirable. However, in many cases, the existing hardware is incompatible with advances in the overall speed of the network. As a result, it becomes necessary to either replace the existing hardware, a costly alternative, or gradually transition to the new technology utilizing add-ons that operate to merge new technology and existing technology. If properly configured, add-ons, such as plug-in adapters or the like, allow combinations of current architecture and technological advances with only incremental modifications.

Currently, universal port modules provide a 1 Gb/s and a 2 Gb/s data rate for Fibre Channel switching systems. However, a new Fibre Channel standard exists that discloses an increase to a 10 Gb/s data rate. Most existing architectures are not designed to handle and effectively utilize the increase in data rate without significant modifications and upgrades to hardware components since most systems are designed to handle lower than a maximum data rate but not a higher than a maximum data rate. Hence, there is a need for a port module for use with existing Fibre Channel switching architecture that is capable of utilizing a 10 Gb/s data rate in accordance with the Fibre Channel standard.

SUMMARY OF THE INVENTION

The Fibre Channel port module design of the present invention provides a solution that enables existing hardware to support a data rate increase to ten gigabits per second or higher, and it does so in an extremely efficient manner without requiring significant design changes and with only a relatively straightforward alteration to existing Fibre Channel switching environments. The present invention provides a port module for use in a Fibre Channel switching environment. More particularly, the port module of one aspect of the invention provides using a single ten gigabit per second port to provide higher utilization for multiple lower speed ports. The port module couples to the existing ports of a switching device, such as a crossbar switch in a Fibre Channel fabric, and provides an ANSI 10GFC compliant fibre interface to the port module and support for trunking on the backplane of the port module. In doing so, the invention reuses existing product infrastructure and customer investment to increase overall data throughput.

Particularly disclosed herein is a Fibre Channel port module having a fibre data interface that is adapted to couple to a 10.2 gigabit per second link. The module also has a front end coupled to the fibre data interface for transmitting and receiving Fibre Channel data to and from the fibre data interface. The module provides a route controller coupled to the front end for route processing of the Fibre Channel data. Route processing determines one or more destination ports on a switching element for the Fibre Channel data. The port module has a backplane data interface operative for coupling to a plurality of ports on a switching element.

In another aspect, the present invention provides a method of providing 10.2 gigabits per second throughput from a first port to a second port. The first port receives Fibre Channel data having a first fibre data interface configured for interfacing to a 10.2 gigabit-per-second link and a first backplane data interface having a plurality of port module ports. The port module determines that the Fibre Channel data is destined for a second port that has a second fibre data interface configured for interfacing to a 10.2 gigabit-per-second link and a second backplane data interface having a plurality of port module ports. The plurality of port module ports of said first port are coupled to a first and second switching element using a first plurality of links, wherein said first plurality of links are aggregated to provide a data rate of up to 10.2 gigabits per second. The plurality of port module ports of said second port are coupled to a first and second switching element using a second plurality of links, wherein said second plurality of links are aggregated to provide a data rate of up to 10.2 gigabits per second. Fibre Channel data is then routed from the first port to the second port.

Still further disclosed herein is a method of providing link aggregation at a port. The port comprises a port module having a fibre data interface and a backplane data interface. The fibre data interface is configured for receiving a 10.2 gigabit-per-second link. The backplane data interface is configured for coupling a plurality of port module ports to at least one Fibre Channel switch. The fibre data interface is coupled to a 10.2 gigabit-per-second link. The plurality of port modules are coupled to a plurality of ports on at least one switching element using a plurality of backplane links. Fibre Channel data is then received at the first port. Fibre Channel data is determined as destined for a second port. The Fibre Channel data is routed from the first port to the second port over the plurality of backplane links.

BRIEF DESCRIPTION OF THE DRAWINGS

The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:

<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a prior art fibre universal port module for use with a Fibre Channel switching element;

<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of a ten gigabit per second port module for use with a Fibre Channel switching element;

<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram illustrating the interconnection of a ten gigabit per second port module and a universal port module and a switching element;

<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram illustrating two switching elements and two ten gigabit per second port modules to achieve a ten gigabit per second to ten gigabit per second throughput; and

<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram showing a Fibre Channel fabric with various port module plug-in cards connecting to various ports of a plurality of switching elements.

<figref idref="DRAWINGS">FIG. 6</figref> illustrated both a “basic switching” configuration and an “expanded switching” configuration in accordance with the present invention.

DESCRIPTION OF A PREFERRED EMBODIMENT

<figref idref="DRAWINGS">FIG. 1</figref> (Prior Art) illustrates a typical 1 gigabit-per-second (i.e., 1.0625 gigabits per second) or 2 gigabit-per-second (i.e., 2.125 gigabits per second) universal port module <b>100</b>. More particularly, universal port module <b>100</b> has four G-ports <b>105</b>, <b>110</b>, <b>115</b> and <b>120</b> for receiving Fibre Channel data or frames from a fabric. Fibre port module <b>100</b> also has an Sbar interface (SBI) <b>130</b> for coupling to a switching element (not shown). SBI <b>130</b> has a link for each port, in essence four links for ports <b>105</b>, <b>110</b>, <b>115</b> and <b>120</b>, that operate independently. In operation, a frame appears at one of the ports, for example port <b>105</b>. The frame is transmitted from port <b>105</b> to a link coupled to SBI <b>130</b>. SBI <b>130</b> transmits the frame to the switching element over one of the links coupled to port <b>105</b>.

<figref idref="DRAWINGS">FIG. 2</figref> illustrates one embodiment of a ten gigabit port module <b>200</b> in accordance with the present invention. Port module <b>200</b> is a ten gigabit Fibre Channel compliant G-Port that preferably also supports F_Port or E_Port functionality. Port module <b>200</b> supports 10.2 gigabits per second optics on the Fibre side (generally on the left side in <figref idref="DRAWINGS">FIG. 2</figref>) and a plurality of 1.0625 or 2.125 gigabits per second data transfer rate lanes through backplane data interface <b>270</b>. Fibre port module <b>200</b> also has a plurality of integrated serializer/deserializer(ISD) cores <b>210</b>, <b>215</b>, <b>220</b>, <b>225</b>, <b>230</b> and <b>235</b> to interface to a switching element (not shown) on the backplane side (generally on the right side of FIG. <b>2</b>). Port module <b>200</b> comprises at least one 10 gigabit Fibre Channel Fibre Data Interface <b>205</b> as well as four or six backplane data and control interfaces for receiving and transmitting data to and from an internal switching element. The backplane data and control interfaces operate independent of each other.

Port module <b>200</b> is configurable on the backplane as a four port trunk group (up to 4×2.125=8.5 gigabits per second) or a six port trunk group using frame striping (6×2.125=12.75 gigabits per second for an effective 10.2G data rate). Trunking is defined herein as combining or aggregating bandwidth through the use of multiple connections simultaneously. Frame striping is described in patent application Ser. No. 09/809,996, entitled “Method for Aggregating A Plurality of Links to Simulate a Unitary Connection” filed Mar. 14, 2001, which is hereby incorporated in the present application for all purposes. Traffic flows over the multiple connections simultaneously and together they provide higher bandwidth using lower speed technology. Trunking allows port module <b>200</b> to receive data frames at a 1 or 2 gigabits per second data rate from backplane links coupled to ISD's <b>210</b>, <b>215</b>, <b>220</b>, <b>225</b>, <b>230</b> and <b>235</b>.

Fibre data interface (FDI) <b>205</b> is the interface between front end <b>240</b> and a ten gigabit per second Fibre Channel data link. In one embodiment, FDI <b>205</b> is coupled to an off chip XAUI module. A XAUI module is a ten gigabit attachment unit interface that is specified in the IEEE802.3ae 10G Ethernet specification. The module comprises four lanes of byte striped data each running at 3.125 gigabits per second. In the ANSI 10GFC specification, each lane runs 2% higher(3.1875 Gb/s) to achieve 10.2 gigabits per second data throughput.

More generally, the XAUI functions can be implemented by circuitry provided external to port module <b>200</b> or integrated internally within port module <b>200</b>. The XAUI standard is an example of a particular implementation, but any implementation that performs byte striping to divide a single high data rate frame and spread it across plural lower data rate data lanes is a suitable equivalent. Hence, a generic implementation functions to present plural striped data lanes to FDI <b>205</b>.

Preferably, the byte striping implements a protocol that includes mechanisms such as defined characters to assist with lane de-skew, data alignment and clock recovery functions. In this manner, each data lane includes sufficient information to maintain the integrity of a striped frame so that the frame can be reconstructed at some point in the future. A significant feature of the present invention involves methods and systems for switching the plural data lanes in a coordinated fashion through hardware that is typically configured to switch each of the lower data rate lanes independently.

FDI <b>205</b> has four ISD's <b>201</b>, <b>202</b>, <b>203</b> and <b>204</b> and one extender sublayer (XGXS) block <b>295</b> that performs a data decode/encode function as well as status and control register specific to the four ISD's and XGXS block <b>295</b>. In one embodiment of port module <b>200</b> employing a XAUI module, each Fibre side ISD <b>201</b>, <b>202</b>, <b>203</b> and <b>204</b> operates at 3.1875 gigabits per second to support a XAUI interface at Fibre Channel data rates. Four ISD's operate together to provide 4×3.1875 gigabits per second throughput to the XGXS decoder block <b>295</b> contained within FDI <b>205</b>. In one embodiment, XGXS block <b>295</b> has register interfaces for functions contained in each of the ISD modules such as programmable driver levels and pre-emphasis settings.

XGXS block <b>295</b> receives data from the four ISD's <b>201</b>, <b>202</b>, <b>203</b> and <b>204</b> and performs lane deskew and alignment and <b>8</b>B/<b>10</b>B decode. XGXS block <b>295</b> then outputs four bytes of data. The data received from block <b>295</b> is four lanes of octet data at 318.75 Mhz for a 10.2 Gb/s data rate. XGXS block <b>295</b> also encodes each lane <b>8</b>B/<b>10</b>B data that is provided for transmission by front end <b>240</b> at 318.75 Mhz. Since deskew and alignment is performed on the receive side, each transmit lane operates independently.

Front end (FE) <b>240</b> manages reception and transmission of Fibre Channel FC<b>1</b> and FC<b>2</b> compliant data to/from integrated FDI block <b>205</b>. More particularly, FE <b>240</b> receives byte striped fibre channel frames from FDI <b>205</b> in four lanes. FE <b>240</b> reassembles the four lanes into data words and thereafter performs a Fibre Channel protocol validation operation conforming to the 10GFC specification for link sequencing and control as well as framing protocol.

Route controller (RC) <b>250</b> interfaces to FE <b>240</b> and provides received frame processing, including destination port determination, address validation and route validation. RC <b>250</b> monitors the FE interface <b>240</b> for any newly received frames and extracts information to make a decision as to how the frame should be routed, such as destination identification (DID) or source identification (SID) information. In one embodiment, route controller <b>250</b> handles <b>240</b> tables×256 ports/table, which allows full fabric lookup. RC <b>250</b> contains fields in tables to accommodate the ability to determine that an incoming DID is destined for a 10 gigabit per second port. RC block <b>250</b> has bits in the route tables for each entry that indicates to downstream logic, such as queue manager (QM) <b>245</b>, that an incoming D_ID is destined for a 10 gigabit per second port.

Frame writer (WR) <b>255</b> interfaces to FE <b>240</b> and receives data from FE <b>240</b> and properly formats the data prior to writing onto buffer memory <b>260</b>. In the illustrated example, WR <b>255</b> maintains a list of up to 250 free buffers and their status. In the illustrated example, frame writer <b>255</b> supports up to 10.2 gigabits per second of data throughput.

Buffer memory <b>260</b> provides a minimum throughput of 20.4 gigabits per second. Therefore, buffer memory can handle one write operation at 10.2 gigabits per second and six simultaneous read operations at 1.7 gigabits per second. In a particular embodiment, buffer memory <b>260</b> also supports <b>250</b> buffers that each can support a full length Fibre Channel frame of 2148 bytes. Each word of data written to buffer memory <b>260</b> preferably has parity protection.

Port module <b>200</b> comprises a buffer memory controller <b>265</b> coupled to buffer memory <b>260</b>. Buffer memory controller (BC) <b>265</b> controls the buffer memory elements. Buffer memory controller <b>265</b> supports a simultaneous transfer of data out of all six frame reader (RD) blocks <b>275</b> at the same time, each effectively operating independently. Buffer memory controller <b>265</b> also supports the ability to simultaneously write data into the BM at a 10.2 gigabits per second data rate as fed by the frame writer module <b>255</b> and is designed to allow any BC <b>265</b> to access any buffer in the 250 buffers in buffer memory <b>260</b>. <figref idref="DRAWINGS">FIG. 2</figref> depicts one implementation that allows one frame to be written and six data frames to be read from buffer memory <b>260</b> at the same time resulting in a 20.4 gigabits per second bandwidth through the port.

Queue manager (QM) <b>245</b> is the central core of port module <b>200</b>. QM <b>245</b> is responsible for building queues of received frames for destination ports from information received from frame writer <b>255</b> and route controller <b>250</b>. Queue manager <b>245</b> also interfaces to a switching device through Sbar controller (SB) <b>280</b> to establish connections as both a source and a destination. QM <b>245</b> utilizes reader <b>275</b> and Sbar control interfaces <b>280</b> independently. QM <b>245</b> supports destination port based queuing and Virtual Output Queueing (VOQ). Virtual Output Queueing is a method by which individual queues are created and maintained at the source port for each destination port. This method avoids the typical head of queue blocking issues associated with pure source port queues and the high bandwidth requirements associated with destination queuing. QM <b>245</b> also has an additional 1 bit to be stored in memory that comes from route controller <b>250</b> that signifies the D_ID is a 10 gigabit port. QM <b>245</b> indicates to SB <b>280</b> to initiate a connection request, then passes this bit to SB block <b>280</b> on a signal.

Port module <b>200</b> comprises a frame reader block <b>275</b>. Frame reader block is responsible for reading stored frames from buffer memory <b>260</b> and transferring them to an external switching element coupled to backplane data interface <b>270</b>. QM <b>245</b> passes frame header word information, buffer to access and the switching element path to use to frame reader <b>275</b>. Frame reader <b>275</b> creates and transmits the header word immediately followed by frame data on the selected switching element path. Port module also has an associated transmit handler <b>285</b>. Transmit handler (TH) <b>285</b> provides the interface for transmission of frames at the port.

Transmit scheduler block (TS) <b>290</b> of port module <b>200</b> is responsible for scheduling frame transfers and passing the frame data to FE <b>240</b>. Block <b>290</b> is inserted between TH <b>285</b> and FE <b>240</b> on the transmit side of the TH ports. TS <b>290</b> manages the configured ports busy bits and frame transmission conforming to the 10 gigabit (10G) requirements. TS <b>290</b> has four or six additional buffers, each capable of storing a full frame. TS block <b>290</b> and TH block <b>285</b> are capable of receiving both 1 and 2 gigabits per second frames. TS <b>290</b> queries the status of FE <b>240</b> and, if not busy, begins transferring data out to FE <b>240</b>. TS block <b>290</b> operates to ensure in order delivery of frames.

SBAR control interface (SB) <b>280</b> of port module <b>200</b> supports 10G for request/response operations. SB <b>280</b> processes requests for each of the six channels or lanes of the backplane data interface <b>270</b> independently. When connecting to a destination identification (DID) that is determined to be a 10G destination port, SB <b>280</b> cycles through each of the associated DID addresses based the additional bit passed from QM <b>245</b> indicating that the DID is a 10G destination port. SB cycles through each address one time or until establishing a connection, which ever occurs first. SB <b>280</b> contain a bus that returns to QM <b>245</b> for indicating the identity of the D_ID it was connected as source when attempting to connect to the 10G destination port.

Queue manager <b>245</b> monitors the status of the six backplane resources (SB <b>280</b> and RD <b>275</b>) and utilizes the next available resource to request a connection, so long as the frame is not bound for the same destination as a currently pending request on another channel. QM <b>245</b> operates on destination port based queuing to ensure frames are sent in order. In the case that a DID is a 10G port, SB <b>280</b> is notified by QM <b>245</b> when requesting a connection operation to be encoded. The DID passed from QM <b>245</b> will always be the first port in this 10G port along with the signal indicating to SB <b>280</b> to cycle through each of the DID's until getting a connected as source back or all busy responses. When a connected as source response is received and the DID is part of a 10G port, SB <b>280</b> passes back the DID of the port having the connection. QM <b>245</b> inserts the DID value in the header using RD <b>275</b>. The frame is sent out and RD <b>275</b> indicates completion status. QM <b>245</b> may then submit another connection request operation.

Backplane data interface (BDI) module <b>270</b> comprises associated buffering and re-timing logic required to interface to the integrated ISD modules <b>210</b>, <b>215</b>, <b>220</b>, <b>225</b>, <b>230</b> and <b>235</b>. Each port operates independently, and has one separate ISD module, a backplane data interface transmiter (BDITX“n”) block and backplane data interface receiver (BDIRX“n”) block. Both the BDITX and BDIRX blocks have register interfaces for functions contained in each of the ISD modules, such as programmable driver levels and pre emphasis settings. In port module <b>200</b>, each backplane side ISD <b>210</b>, <b>215</b>, <b>220</b>, <b>225</b>, <b>230</b> and <b>235</b> operates at a data rate up to 2.5 gigabits per second. The BDIRX“n” block in BDI <b>270</b> manages <b>8</b>B/<b>10</b>B decoding operations and primitive character detection. This module will provide indications of character synchronization and receiver reset control. The BDITX“n” block in BDI <b>270</b> manages <b>8</b>B/<b>10</b>B encoding operations and interfacing to the ISD module.

<figref idref="DRAWINGS">FIG. 3</figref> illustrates a typical fabric configuration having a mixture of ten gigabit port modules (XPM's) <b>310</b> and <b>320</b> and a universal port module (UPM) <b>330</b> coupled to an SBAR <b>300</b>. SBAR <b>300</b> is a serial crossbar switch, or switching element, that provides switching paths between all ports. The configuration of <figref idref="DRAWINGS">FIG. 3</figref> illustrates link aggregation on the backplane of XPM <b>310</b> and XPM <b>320</b>. XPM <b>310</b> receives data at a data rate of 10.2 gigabits per second and thereafter transmits the data out either XPM <b>320</b> at a data rate less than 10.2 gigabits per second or UPM <b>330</b> at a data rate of 1 or 2 gigabits per second.

In one embodiment, the fibre channel input to XPM <b>310</b> in <figref idref="DRAWINGS">FIG. 3</figref> is a 10 Gb/s link and the input to UPM <b>330</b> is either a 1 Gb/s link or a 2 Gb/s link. Fibre channel frames may originate at either the 1 Gb/s link or 2 Gb/s link coupled to UPM <b>330</b> destined for the 10 Gb/s link coupled to XPM <b>310</b>. Similarly, fibre channel frames may originate at the 10 Gb/s link coupled to XPM <b>310</b> destined for either the 1 Gb/s link or 2 Gb/s link coupled to UPM <b>330</b>. The configuration of the port modules in <figref idref="DRAWINGS">FIG. 3</figref> allows for a 10G to 1G or 2G data transfer from XPM <b>310</b> to UPM <b>330</b>, or a 1G or 2G to 10G data transfer from UPM <b>330</b> to XPM <b>310</b>.

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a typical fabric configuration having two ten gigabit port modules (XPM's) <b>420</b> and <b>430</b> coupled to SBAR<b>0</b><b>400</b> and SBAR<b>1</b><b>410</b>. The configuration of <figref idref="DRAWINGS">FIG. 4</figref> illustrates 10.2 gigabit to 10.2 gigabit throughput from a first port module XPM <b>420</b> to a second port module XPM <b>430</b>.

For example, a Fibre Channel frame arrives on a 10.2 gigabit link coupled to XPM <b>420</b>. As stated previously, the 10.2 gigabit link is a four lane input to XPM <b>420</b>, wherein each lane operates at 3.1875 for a total data rate of 12.75 Gb/s for a <b>10</b>B encoded data rate. According to the 10GFC standard, the 12.75 gigabit data rate under <b>10</b>B mode equates to a 10.2 gigabit rate in <b>8</b>B mode. XPM <b>420</b> determines the frame is destined for a second 10.2 gigabit link coupled to XPM <b>430</b>. Due to current design limitations, a maximum of four physical links operating at a 2.125 Gb/s data rate may couple SBAR<b>0</b> to both port module <b>420</b> and port module <b>430</b>. Such a design limitation prohibits 10.2 Gb/s to 10.2 Gb/s throughput.

The addition of a second or redundant SBAR, SBAR<b>1</b><b>410</b>, provides 10.2 Gb/s to 10.2 Gb/s throughput from XPM <b>420</b> to XPM <b>430</b>. The addition of two additional physical links operating at 2.125 Gb/s coupling XPM <b>420</b> to SBAR<b>1</b><b>410</b> and XPM <b>430</b> to SBAR<b>1</b><b>410</b> in addition to frame striping among the six links, results in a 6×2.125 Gb/s data rate, which equates to a 10.2 Gb/s data rate with <b>8</b>B/<b>10</b>B decoding/encoding.

<figref idref="DRAWINGS">FIG. 5</figref> illustrates a Fibre Channel fabric having a plurality of ten gigabit port modules (XPM's) <b>520</b>, <b>550</b>, <b>560</b> and <b>580</b> and a plurality of universal port modules (UPM's) <b>530</b>, <b>540</b>, <b>570</b> and <b>590</b> coupled to SBAR<b>1</b><b>500</b> and SBAR<b>2</b><b>510</b>. As illustrated, the use of XPM's minimize the wiring between switches since only a single physical connection is required for four ports on an SBAR instead of four physical connection for four ports on an SBAR using the UPM's. Reducing the number of physical links is a desirable cable management aspect of the present invention.

<figref idref="DRAWINGS">FIG. 6</figref> illustrates both a “basic switching” configuration and an “expanded switching” configuration in accordance with the present invention. SBAR element <b>600</b> consists of 5 crosspoint switch components <b>610</b>, <b>620</b>, <b>630</b>, <b>640</b> and <b>650</b> that each switch 128×128 ports. Coupling four of the crosspoint switch components <b>610</b>, <b>620</b>, <b>640</b> and <b>650</b> (also referred to as the active crosspoint switch components) to XPM <b>200</b> achieves 256×256 switching, which is defined herein as basic switching configuration.

The fifth crosspoint switch component <b>630</b> is redundant, and can be used to replace one of the four active crosspoint switch components if a failure is detected in the basic switching configuration. When not in use, the spare crosspoint switch component <b>630</b> may be used to increase bandwidth, which is defined herein as expanded switching. The additional backplane channels of XPM <b>200</b>, ISD<b>4</b><b>230</b> and ISD<b>5</b><b>235</b> are active when the spare crosspoint switch component <b>630</b> is not being used as part of the basic switching configuration.

When crosspoint switch components <b>610</b>, <b>620</b>, <b>640</b> and <b>650</b> and spare crosspoint switch component <b>630</b> are fully operational, XPM <b>200</b> may support a full 6×2.125 Gb/s throughput or expanded switching mode. Channels ISD<b>4</b><b>230</b> and ISD<b>5</b><b>235</b> couple to another 10G destination port within the switch. When spare crosspoint switch component <b>630</b> is engaged to become active in the basic switching crosspoint system, channels ISD<b>4</b><b>230</b> and ISD<b>5</b><b>235</b> are unavailable for use by the backplane channels. All traffic, whether destined for a 1 gigabit, 2 gigabit or 10 gigabit port would use channels ISD<b>0</b><b>210</b>, ISD<b>1</b><b>215</b>, ISD<b>2</b><b>220</b> and ISD<b>3</b><b>225</b>.

While there have been described above the principles of the present invention in conjunction with a specific embodiment, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein.

Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.