Metal structure for a phase-change memory device

This is a divisional of application Ser. No. 09/745,835, filed Dec. 21, 2000 now U.S. Pat. No. 6,569,705.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a phase-change memory device. More particularly, the present invention relates to an upper electrode in a chalcogenide memory cell. In particular, the present invention relates to a damascene structure select line in a phase-change memory cell structure.

2. Description of Related Art

Typical memory applications include dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM).

Solid state memory devices typically employ micro-electronic circuit elements for each memory bit (e.g., one to four transistors per bit) in memory applications. Since one or more electronic circuit elements are required for each memory bit, these devices may consume considerable chip “real estate” to store a bit of information, which limits the density of a memory chip. The primary “non-volatile” memory element of these devices, such as an EEPROM, typically employ a floating gate field effect transistor device that has limited re-programmability and which holds a charge on the gate of field effect transistor to store each memory bit. These classes of memory devices are also relatively slow to program.

Phase change memory devices use phase change materials, i.e., materials that can be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. One type of memory element originally developed by Energy Conversion Devices, Inc. of Troy, Mich. utilizes a phase change material that can be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. Typical materials suitable for such application include those utilizing various chalcogenide elements. These electrical memory devices typically do not use field effect transistor devices, but comprise, in the electrical context, a monolithic body of thin film chalcogenide material. As a result, very little chip real estate is required to store a bit of information, thereby providing for inherently high density memory chips. The state change materials are also truly non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reset as that value represents a physical state of the material (e.g., crystalline or amorphous). Thus, phase change memory materials represent a significant improvement in non-volatile memory.

One aspect of fabrication deals with the complexity of the chalcogenide material. Because of its unusual behavior in the semiconductor processing regime, measures must be taken to avoid creating a fugitive material during routine thermal processes. Additionally, because it is more chemically reactive than several conventional materials used in the semiconductor processing regime, damage to the chalcogenide material is likely. Other measures must be taken to facilitate the patterning of the memory material.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the manner in which the above-recited and other advantages of the invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention that are not necessarily drawn to scale and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

FIG. 1 is a schematic diagram of an array of memory elements according to an embodiment of the invention;

FIG. 2 schematically illustrates a cross-section elevational view of a portion of a semiconductor substrate having dielectric trenches formed therein defining a z-direction thickness of a memory cell in accordance with one embodiment of the invention of forming a memory element on a substrate;

FIG. 3 shows the structure of FIG. 2, through the same cross-section elevational view, after the introduction of dopants to form an isolation device for a memory element in accordance with one embodiment of the invention;

FIG. 4 shows the structure of FIG. 3 after the introduction of a masking material over the structure in accordance with one embodiment of the invention;

FIG. 5 shows a schematic top view of the structure of FIG. 4.;

FIG. 6 shows the cross-section of the structure of FIG. <b>4</b> through line B-B′;

FIG. 7 shows the structure of FIG. 5, through the same cross-section elevational view, after the patterning of the x-direction thickness of a memory cell, the introduction of a dopant between the cells, and the introduction of a dielectric material over the structure;

FIG. 8 shows the structure of FIG. 7, through the same cross-section elevational view, after the formation of trenches through the dielectric material in accordance with one embodiment of the invention;

FIG. 9 shows the structure of FIG. 8, through the same cross-section elevational view, after the introduction of an electrode material over the structure in accordance with one embodiment of the invention;

FIG. 10 shows the structure of FIG. 9, through the same cross-section elevational view, after planarization and the formation of an optional adhesion layer;

FIG. 11 shows the structure of FIG. 10, through the same cross-section elevational view, after the formation of a dielectric layer that may be referred to as an interlayer dielectric (ILD) layer;

FIG. 12 shows the structure of FIG. <b>11</b> through the same cross-section elevational view, after formation of a recess, and the introduction of a volume of memory material of phasechange type into the recess;

FIGS. 13<i>a</i>, <b>13</b><i>b</i>, and <b>13</b><i>c </i>show detail sections that illustrate alternative processing of the present invention;

FIG. 14 shows the structure of FIG. 12, through the same cross-section elevational view, after the formation of second conductors over the structure, in accordance with one embodiment of the invention;

FIG. 15 shows the structure of FIG. 14, through the same cross-section elevational view, after the introduction of an upper dielectric material over the second conductor and after a third is conductor coupled to the first conductor in accordance with an embodiment of the invention; and

FIG. 16 shows a graphical representation of setting and resetting a volume of a phase change memory material in terms of temperature and time.

DETAILED DESCRIPTION OF THE INVENTION

The invention generally relates to an apparatus used, in one aspect, as a memory structure. In one embodiment, the apparatus includes a volume of memory material between a pair of spacedly disposed conductors or signal lines. The apparatus also includes an electrode coupled to a volume of memory material and disposed between the volume of memory material and one conductor or signal line. The upper electrode is disposed in a damascene structure that simplifies process flow and solves processing problems that existed previously.

The invention also relates to a method, including a method of forming a memory element. In one aspect, the method includes, between contacts formed on a substrate, introducing an upper electrode material into a damascene structure under process conditions that lead to higher product yield and lower field failures.

The following description includes terms, such as upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of an apparatus or article of the present invention described herein can be manufactured, used, or shipped in a number of positions and orientation.

Reference will now be made to the drawings wherein like structures will be provided with like reference designations. In order to show the structures of the present invention most clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated structures, for example in a photonicrograph, may appear different while still incorporating the essential structures of the present invention. Moreover, the drawings show only the structures necessary to understand the present invention. Additional structures known in the art have not been included to maintain the clarity of the drawings.

FIG. 1 shows a schematic diagram of an embodiment of a memory array comprised of a plurality of memory elements presented and formed in the context of the invention. In this example, the circuit of memory array <b>5</b> includes an array with memory element <b>30</b> electrically interconnected in series with isolation device <b>25</b> on a portion of a chip. Address lines <b>10</b> (e.g., columns) and <b>20</b> (e.g., rows) are connected, in one embodiment, to external addressing circuitry in a manner known to those skilled in the art. One purpose of the array of memory elements in combination with isolation devices is to enable each discrete memory element to be read and written without interfering with the information stored in adjacent or remote memory elements of the array.

A memory array such as memory array may be formed in a portion, including the entire portion, of a substrate. A typical substrate includes a semiconductor substrate such as a silicon substrate. Other substrates including, but not limited to, substrates that contain ceramic material, organic material, or glass material as part of the infrastructure are also suitable. In the case of a silicon semiconductor substrate, memory array <b>5</b> may be fabricated over an area of the substrate at the wafer level and then the wafer may be reduced through singulation into discrete die or chips, some or all of the die or chips having a memory array formed thereon. Additional addressing circuitry such as sense amplifiers, decoders, etc. may be formed in a similar fashion as known to those of skill in the art.

FIGS. 2-15 illustrate the fabrication of representative memory element <b>15</b> of FIG. <b>1</b>. FIG. 2 shows a portion of substrate <b>100</b> that is, for example, a semiconductor substrate. In this example, a P-type dopant such as boron is introduced in a deep portion <b>110</b>. In one example, a suitable concentration of P-type dopant is on the order of above 5×10¹⁹-1×10²⁰atoms per cubic centimeters (atoms/cm³) rendering deep portion <b>110</b> of substrate <b>100</b> representatively P⁺⁺. Overlying deep portion <b>110</b> of substrate <b>100</b>, in this example, is an epitaxial portion <b>120</b> of P-type epitaxial silicon. In one example, the dopant concentration in epitaxial portion <b>120</b> is on the order of about 10¹⁶-10¹⁷atoms/cm³. The introduction and formation of epitaxial portion <b>120</b> as P-type, and deep portion <b>110</b> may follow techniques known to those of skill in the art

FIG. 2 also shows first shallow trench isolation (STI) structures <b>130</b> formed in epitaxial portion <b>120</b> of substrate <b>100</b>. As will become apparent in the subsequent discussion, STI structures <b>130</b> serve, in one aspect, to define the z-direction thickness of a memory element cell, with at this point only the z-direction thickness of a memory element cell defined. In another aspect, STI structures <b>130</b> serve to isolate individual memory elements from one another as well as associated circuit elements such as transistor devices formed in and on substrate <b>100</b>. STI structures <b>130</b> are formed according to techniques known to those skilled in the art.

FIG. 3 shows the structure of FIG. 2 after a further fabrication operation in memory cell regions <b>135</b>A and <b>135</b>B. In one embodiment, memory cell regions <b>135</b>A and <b>135</b>B are introduced as strips with the x-direction dimension greater than the z-direction dimension. Overlying epitaxial portion <b>120</b> of substrate <b>100</b> is first conductor or signal line material <b>140</b>. In one example, first conductor or signal line material <b>140</b> is N-type doped polysilicon formed by the introduction of, for example, phosphorous or arsenic to a concentration on the order of about 10¹⁸-10¹⁹atoms/cm³such as N⁺ silicon. In this example, first conductor or signal line material <b>140</b> serves as an address line, a row line such as row line <b>20</b> of FIG. <b>1</b>. Overlying first conductor or signal line material <b>140</b> is an isolation device such as isolation device <b>25</b> of FIG. <b>1</b>. In one example, isolation device <b>25</b> is a PN diode formed of N-type silicon portion <b>150</b> that may have a dopant concentration on the order of about 10¹⁷-10¹⁸atoms/cm³and P-type silicon portion <b>160</b> that may have a dopant concentration on the order of about 10¹⁹-10²⁰atoms/cm³. Although a PN diode is shown, it is to be appreciated that other isolation structures are similarly suitable. Such isolation devices include, but are not limited to, MOS devices.

Referring to FIG. 3, overlying isolation device <b>25</b> in memory cell regions <b>135</b>A and <b>135</b>B is a reducer material <b>170</b> of, in this example, a refractory metal silicide such as cobalt silicide (CoSi₂). Reducer material <b>170</b>, in one aspect, serves as a low resistance material in the fabrication of peripheral circuitry such as addressing circuitry of the circuit structure on the chip. Thus, reducer material <b>170</b> may not be required in terms of forming a memory element as described. Nevertheless, because of its low resistance property, its inclusion as part of the memory cell structure between isolation device <b>25</b> and memory element <b>30</b> is utilized in this embodiment.

FIG. 4 shows the structure of FIG. 3 after the introduction of a masking material <b>180</b>. As will become clear later, masking material <b>180</b> serves, in one sense, as an etch stop for a subsequent etch operation. FIG. 5 schematically shows memory cell regions <b>135</b>A and <b>135</b>B in an xz plane. Overlying the memory cell is masking material <b>180</b>. FIG. 6 shows a cross-sectional side view of memory cell region <b>135</b>A through line B-B′ of FIG. 5 in an xy perspective. In one embodiment, a suitable material for masking material <b>180</b> is a dielectric material such as silicon nitride (Si₃N₄) although other material may be used such as an organic resist.

FIG. 7 shows the structure of FIG. 6 from an xy perspective after patterning of the x-direction thickness of the memory cell material to form a trench <b>190</b>. FIG. 7 shows two memory cells <b>145</b>A and <b>145</b>B patterned from memory cell region <b>135</b>A depicted in FIG. <b>5</b>. The patterning may be accomplished using conventional techniques for etching, in this example, refractory metal silicide and silicon material to the exclusion of masking material <b>180</b>. The definition of the x-direction thickness involves, in one embodiment, an etch to conductive material <b>150</b> (N-type silicon in this embodiment) of the memory line stack to define memory cells <b>145</b>A and <b>145</b>B of memory cell region <b>135</b>A. In the case of an etch, the etch proceeds through the memory line stack to, in this example, a portion of a conductor or signal line that is in this case conductive material <b>150</b>. A timed etch may be utilized to stop an etch at this point.

Following the patterning, N-type dopant is introduced at the base of each trench <b>190</b> to form pockets <b>200</b> having a dopant concentration on the order of about 10¹⁸-10²⁰atoms/cm³to form an N⁺ region between memory cells <b>145</b>A and <b>145</b>B. Pockets <b>200</b> serve, in one sense, to maintain continuity of a row line. Dielectric material <b>210</b> of, for example, silicon dioxide material is then introduced over the structure to a thickness on the order of 100 Å to 50,000 Å.

FIG. 8 shows the structure of FIG. 7 after the formation of trenches <b>220</b> through dielectric materials <b>210</b> and masking material <b>180</b> to reducer material <b>170</b>. The formation of trenches <b>220</b> may be accomplished using etch patterning with an etchant(s) for etching dielectric material <b>210</b> and masking material <b>180</b> and selective to reducer material <b>170</b> such that reducer <b>170</b> may serve as an etch stop.

FIG. 9 shows the structure of FIG. 8 after the conformal introduction of electrode material <b>230</b>. In one example, electrode material <b>230</b> is polycrystalline semiconductor material such as polycrystalline silicon. In another embodiment, the electrode material <b>230</b> is a metal compound film that is made from a refractory metal and at least one of nitrogen and-silicon. The introduction is conformal in the sense that electrode material <b>230</b> is introduced along the side walls and base of trench <b>220</b> such that electrode material <b>230</b> is in contact with reducer material <b>170</b>. The conformal introduction of electrode material <b>230</b> that is a deposition process, may follow conventional introduction techniques known to those skilled in the art including chemical vapor deposition (CVD) techniques and physical vapor deposition (PVD) techniques.

For simplicity, electrode material <b>230</b> is presumed to be deposited and treated, if necessary, such that the inventive process may continue. FIG. 10 is an illustration of substrate <b>100</b> after introducing a second dielectric <b>250</b> into recess <b>280</b>, and after planarization processing such as chemical mechanical planarization (CMP) to form a lower electrode upper surface <b>240</b>. After CMP, an optional adhesion layer <b>260</b> is formed over lower electrode upper surface <b>240</b>. Adhesion layer <b>260</b> may be selected from Ti, Zr, and the like. Adhesion layer <b>260</b> may also be selected from W and the like. Adhesion layer <b>260</b> may also be selected from, TiN, ZrN, WN, and the like. Adhesion layer <b>260</b> may also be selected from TiSiN, ZrSiN, WSiN, and the like.

FIG. <b>11</b>. shows the structure of FIG. 10 after further processing. After the formation of optional adhesion layer <b>260</b>, an ILD layer <b>270</b> is formed over lower electrode upper surface <b>240</b> that will serve as a portion of the damascene structure of the present invention. ILD layer <b>270</b> may be referred to as a dielectric layer <b>270</b>.

FIG. 12 illustrates substrate <b>100</b> after further processing. A recess <b>280</b> is formed in dielectric layer <b>270</b>. Recess <b>280</b> exposes lower-electrode upper surface <b>240</b>. It may also be understood that exposing lower electrode upper surface <b>240</b> may actually be exposing adhesion layer <b>260</b> that may be in direct contact with lower electrode upper surface <b>240</b>. In any event, a phase-change material <b>290</b>, also referred to as a memory material is formed in recess <b>280</b> that is in contact with lower electrode upper surface <b>240</b>. Where adhesion layer <b>260</b> is present, it is understood that phase-change material <b>290</b> is in contact with lower electrode upper surface <b>240</b> through the medium of adhesion layer <b>260</b>.

FIG. 13<i>a </i>is a detail section taken along the line <b>13</b>—<b>13</b> from FIG. <b>12</b>. FIG. 13<i>a </i>illustrates a portion of substrate <b>100</b> after further processing. In FIG. 13<i>a</i>, lower electrode <b>230</b> is depicted disposed in dielectric material <b>210</b>, and lower electrode upper surface <b>240</b> is disposed adjacent the optional adhesion layer <b>260</b>. Recess <b>280</b> in dielectric layer <b>270</b> has been filled with an electrically conductive material <b>315</b> that will become a select line such as a row select or a column select Optionally, recess <b>270</b> is first prepared with at least one barrier layer. In FIG. 13<i>a</i>, a first barrier layer <b>300</b> is conformally deposited in the recess over lower electrode upper surface <b>240</b>. Alternatively, a second barrier layer <b>310</b> is formed over first barrier layer <b>300</b>. The process of forming first barrier layer <b>300</b> and alternatively second barrier layer <b>310</b> may be carried out by CVD or PVD. Where the select line electrode that will be primarily made from electrically conductive material <b>315</b> is aluminum, first barrier layer <b>300</b> is preferably titanium, a titanium alloy, or the like. Second barrier layer <b>310</b> may be titanium nitride Ti_xN_yand may be formed in either stoichiometric or other solid solution ratios. Second barrier layer <b>310</b> may be formed by PVD or CVD, or it may be thermally formed from a portion of first barrier layer <b>300</b>.

In another embodiment, where the select line electrode that will be primarily made from electrically conductive material <b>315</b> is copper, a copper alloy, or the like, first barrier layer <b>300</b> is preferably tantalum, a tantalum alloy, or the like. Second barrier layer <b>310</b> may be tantalum nitride Ta_xN_yand may be formed in either stoichiometric or other solid solution ratios. Second barrier layer <b>310</b> may be formed by PVD or CVD, or it may be thermally formed from a portion of first barrier layer <b>300</b>.

In another embodiment of the present invention, dielectric layer <b>270</b> is made of a first dielectric layer <b>272</b> and a second dielectric layer <b>274</b> as illustrated in FIG. <b>13</b>b. First dielectric layer <b>272</b> and second dielectric layer <b>274</b> are made of differing materials such that an etch to form recess <b>280</b> will leave a fist breach in first dielectric layer <b>272</b> with a first width <b>282</b> and a second breach in second dielectric layer <b>272</b> with a second width <b>284</b>. It is illustrated in FIG. 13b that first width <b>282</b> is greater than second width <b>284</b>. As the phase-change material <b>292</b> is formed in recess <b>280</b> of FIG. 13<i>c</i>, second width <b>284</b> acts to cause phase-change material <b>292</b> to have a width that may reflect the dimension thereof. By this method, phase-change material <b>292</b> has less likelihood of contact to the wall <b>276</b> of recess <b>280</b>.

Following the formation of phase-change material <b>292</b> first barrier layer <b>300</b> and second barrier layer <b>310</b> maybe formed as illustrated in FIG. 13<i>c</i>. Because first barrier layer <b>300</b> has better adhesion to the wall <b>276</b> of recess <b>280</b> than phase-change material <b>292</b> that is chalcogenide or the like, the use of second dielectric layer <b>274</b> therefore facilitates better retention of phase-change material <b>292</b> within recess <b>280</b> because of a deposition shadow that it casts in the direction of lower electrode <b>230</b>, either upon adhesion layer <b>260</b>, or if adhesion layer <b>260</b> is not present, upon second dielectric <b>250</b>. In any event, adhesion of first barrier layer <b>300</b> to wall <b>276</b> of recess <b>280</b> acts as a retainer or “clamp” to hold in, either phase-change material <b>290</b> as depicted in FIG. 13<i>a </i>or phase-hange material <b>292</b> as depicted in FIG. 13<i>c</i>. Because of the preference to avoid contact of phase-change material <b>292</b> with wall <b>276</b> of recess <b>280</b>, PVD is preferably used to thereby create a shadow deposition of phase-change material <b>292</b>, wherein the shadow is created by second width <b>284</b> of second dielectric layer <b>274</b>. In one embodiment, collimated deposition of phase-change material is used to resist deposition of the memory material upon wall <b>276</b>. Adhesion strength of first barrier layer <b>300</b> is preferably on the order of about 1 kpsi to about 10 kpsi, preferably above about 7 kpsi.

FIG. 14 shows the structure of FIG. 12 after the introduction of a volume of memory material <b>290</b> (represented as memory element <b>30</b> in FIG. 1) after deposition of conductive material <b>315</b>, and after a CMP process or the like to establish an upper electrode upper surface <b>317</b>. In one example, memory material <b>290</b> is a phase change material. In a more specific example, memory material <b>290</b> includes a chalcogenide element(s). Examples of phase change memory material <b>290</b> include, but are not limited to, compositions of the class of tellerium-germanium-antimony (Te_xGe_ySb_z) material. The volume of memory material <b>290</b>, in one example according to current technology, is introduced and patterned with a thickness in a range from about 100 Å to about 1,200 Å, preferably from about 300 A to about 900 Å, and most preferably on the order of about 600 Å.

Overlying the volume of memory material <b>290</b> in the structure of FIG. 13, are the barrier materials <b>300</b> and <b>310</b> of, for example, titanium (Ti) and titanium nitride (TiN), respectively. The barrier materials serve, in one aspect, to inhibit diffusion between the volume of memory material <b>290</b> and the second conductor or signal line material <b>315</b> overlying the volume of memory material <b>290</b> (e.g., second electrode <b>10</b> as depicted in FIG. <b>1</b>). Overlying barrier materials <b>300</b> and <b>310</b> is second conductor or signal line material <b>315</b>. In this example, second conductor or signal line material <b>315</b> serves as an address line, a column line (e.g., column line <b>10</b> of FIG. <b>1</b>). Second conductor or signal line material <b>315</b> is patterned to be, in one embodiment, generally orthogonal to first conductor or signal line material <b>140</b> (column lines are orthogonal to row lines). Second conductor or signal line material <b>315</b> is, for example, an aluminum material, such as an aluminum alloy, or a copper material such a copper alloy, or the like.

FIG. 15 shows the structure of FIG. 14 after the introduction of an upper dielectric layer <b>320</b> over upper surface <b>317</b> of second conductor or signal line material <b>315</b>. Upper dielectric layer <b>320</b> is, for example, SiO₂or other suitable material that overlies both the dielectric layer <b>270</b>, the second conductor or signal line material <b>315</b>, and the memory material <b>290</b> to electronically isolate such structure. Following introduction, upper dielectric layer <b>320</b> is planarized and a via <b>330</b> is formed in a portion of the structure through upper dielectric layer <b>320</b>, dielectric layer <b>270</b>, dielectric layer <b>210</b>, and masking material <b>180</b> to reducer material <b>170</b>. The via <b>330</b> may be etched in a two-etch process etch. The first etch process may be a fast oxide etch that stops on masking material <b>180</b>. The second etch process may be a slow nitride etch (if masking material <b>180</b> is a nitride) that stops on silicon or silicide. The via <b>330</b> is filled with conductive material <b>340</b> such as tungsten (W) and barrier material <b>350</b> such as a combination of titanium (Ti) and titanium nitride (TiN). Techniques for introducing upper dielectric layer <b>320</b>, forming and filling conductive vias, and planarizing are known to those skilled in the art.

The structure shown in FIG. 15 also shows additional conductor or signal line material <b>360</b> introduced and patterned to mirror that of first conductor or signal line material <b>140</b> (e.g., row line) formed on substrate <b>100</b>. Mirror conductor line material <b>360</b>, if present, mirrors first conductor or signal line material <b>140</b> and is coupled to first conductor or signal line material <b>140</b> through a conductive via By mirroring a doped semiconductor such as N-type silicon, mirror conductor line material <b>360</b> serves, in one aspect, to reduce the resistance of conductor or signal line material <b>140</b> in a memory array, such as memory array <b>5</b> illustrated in FIG. 1. A suitable material for mirror conductor line material <b>360</b> includes an aluminum material, such as an aluminum alloy, or a copper material such as a copper alloy.

In the above description of forming a memory element such as memory element <b>15</b> in FIG. 1, an electrode is described between a memory material and conductors or signal lines (e.g., row lines and column lines) that has improved electrical characteristics. In a first embodiment, the resistivity of the electrode is modified by fabricating an electrode of a first material (polycrystalliine silicon) having a first resistivity and a second material (e.g., SiC/poly or SiO₂/poly) of a second higher resistivity. The higher resistivity material is located adjacent, either proximally or directly, the volume of memory material. In this manner, a supplied voltage from second conductor or signal line material <b>320</b> or first conductor or signal line material <b>140</b> to the memory material may be near the volume of memory material and dissipation of energy to cause a phase change may be minimized. In a second embodiment, the resistivity of the electrode is established by formation a metal compound film such as a refractory metal. The device uses a lower electrode material that is a high resistivity metal compound. The high resistivity metal compound may be a refractory metal compound such as TaN, TIN, WN, TaSN, TiSIN, WSiN, TaSi, TiSi, and WSi.

The discussion detailed the formation of one memory element <b>30</b> of memory array <b>5</b>. Other memory elements of memory array <b>5</b> may be fabricated in the same manner. It is to be appreciated that many, and possibly all, memory elements of memory array <b>5</b>, along with other integrated circuit circuitry, may be fabricated simultaneously.

FIG. 16 presents a graphical representation of the setting and resetting of a volume of phase change memory material. Referring to FIG. 1, setting and resetting memory element <b>15</b> (addressed by column line <b>10</b><i>a </i>and row line <b>20</b><i>a</i>) involves, in one example, supplying a voltage to column line <b>10</b><i>a </i>to introduce a current into the volume of memory material <b>30</b>. The current causes a temperature increase at the volume of memory material <b>30</b>. Referring to FIG. 16, to amorphize a volume of memory material, the volume of memory material is heated to a temperature beyond the amorphisizing temperature, T_M. Once a temperature beyond TM is reached, the volume of memory material is quenched or cooled rapidly (by removing the current flow). The quenching is accomplished at a rate, t₁, that is faster than the rate at which the volume of memory material <b>30</b> can crystallize so that the volume of memory material <b>30</b> retains its amorphous state. To crystallize a volume of memory material <b>30</b>, the temperature is raised by current flow to the crystallization temperature for the material and retained at that temperature for a sufficient time to crystallize the material. After such time, the volume of memory material is quenched (by removing the current flow).

In each of these examples of resetting and setting a volume of memory material <b>30</b>, the importance of concentrating the temperature delivery at the volume of memory material <b>30</b> is illustrated. One way this is accomplished is modifying a portion of the electrode as described above. Another way is to use a metal compound film as described above. The inset of FIG. 16 shows memory cell IS having an electrode with modified portion <b>35</b> (illustrated as a resistor) to concentrate heat (current) at the volume of memory material <b>30</b>.

In the preceding example, the volume of memory material <b>30</b> was heated to a high temperature to amorphize the material and reset the memory element (e.g., program <b>0</b>). Heating the volume of memory material to a lower crystallization temperature crystallizes the material and sets the memory element (e.g., program <b>1</b>). It is to be appreciated that the association of reset and set with amorphous and crystalline material, respectively, is a convention and that at least an opposit&amp; convention may be adopted. It is also to be appreciated from this example that the volume of memory material <b>30</b> need not be partially set or reset by varying the current flow and duration through the volume of memory material.

In one embodiment of the present invention, better wall adhesion of first barrier layer <b>300</b> is achieved, in the place of phase-change material <b>292</b>. In other words, phase-change material <b>292</b> is clamped in place by the presence of first barrier layer <b>300</b>. In another embodiment, better wall adhesion of first barrier layer <b>300</b> is achieved, in the place of phase-change material <b>290</b>. In other words, phase-change material <b>290</b> is clamped in place by the presence of first barrier layer <b>300</b>.

Where phase-change material <b>290</b> is a chalcogenide material or the like, it is very sensitive to both wet and elevated temperature processing. Chalcogenide material is very reactive to standard wet chemistries that are used in semiconductor fabrication; they are difficult to protect during wet processing. Chalcogenide material is also relatively volatile during elevated temperature processing such as the formation of an ILD layer. During processing of the prior state of the art, the elevated thermal processing to form an ILD layer over the metal stack in a level that is the same or similar to the location of dielectric layer <b>270</b> would cause a significant portion of phase-change material to volatilize by sublimation. By the present invention, dielectric layer <b>270</b> is formed before the introduction of phase-change material <b>290</b>, and before the next elevated temperature process, phase-change material <b>290</b> has been substantially trapped beneath at least one sealing layer such as first barrier layer <b>300</b> or such as electrically conductive material <b>315</b>.

It will be-readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.