Reduced aspect ratio digit line contact process flow used during the formation of a semiconductor device

FIELD OF THE INVENTION

This invention relates to the field of semiconductor processing, and more particularly to a method for forming a contact and a container capacitor for a semiconductor device such as a dynamic random access memory.

BACKGROUND OF THE INVENTION

During the manufacture of a semiconductor device such as dynamic random access memories (DRAMs), static random access memories (SRAMs), microprocessors, and logic devices, several structures are commonly formed. For example, contact openings to a conductive layer such as doped monocrystalline silicon wafer, a polycrystalline silicon (polysilicon) layer, or a metal feature through a dielectric layer such as tetraethyl orthosilicate (TEOS) and/or borophosphosilicate glass (BPSG) can be formed. Further, openings are commonly formed within a dielectric layer as an early step in the formation of a container capacitor in a memory device.

FIGS. 1-6 depict a conventional process used during the formation of a semiconductor memory device such as a DRAM to form storage capacitors and digit line contacts. FIG. 1 depicts a semiconductor wafer substrate assembly comprising a semiconductor wafer <b>10</b>, field oxide <b>12</b>, doped wafer areas <b>13</b>, transistor control gates typically comprising a polysilicon gate <b>14</b>A and silicide <b>14</b>B, and surrounding dielectric typically comprising gate oxide <b>16</b>A, nitride spacers <b>16</b>B, and capping layer <b>16</b>C, for example TEOS. FIG. 1 further depicts polysilicon contact pads including pads <b>18</b> to which container capacitors will be electrically coupled and pads <b>20</b> which will form a portion of a digit line contact to the wafer <b>10</b>. The pads are separated by a dielectric layer <b>22</b>, for example BPSG. Also depicted is a second layer of dielectric <b>24</b> which can be one or more layers of TEOS and/or BPSG. A layer of photoresist <b>26</b> defines openings <b>28</b> which overlie pads <b>18</b> to which the container capacitors will be electrically coupled. The structure of FIG. 1 is exposed to a vertical anisotropic etch which removes the dielectric layer <b>24</b> selective to the polysilicon contact pads <b>18</b>.

FIG. 2 depicts openings <b>30</b> which result from the etch of the FIG. 1 structure. The etch exposes pads <b>18</b>, which in turn contact doped regions <b>13</b>. Pads <b>18</b>, therefore, decrease the amount of oxide which the etch of the FIG. 1 structure must remove. Without pads <b>18</b>, the etch would be required to remove the additional thickness of oxide layer <b>22</b> to expose doped regions <b>13</b>.

After forming the openings, a blanket layer of hemispherical silicon grain (HSG) <b>32</b> is formed over exposed surfaces including pads <b>18</b>. Subsequently, the openings are filled with a sacrificial protective material such as photoresist (not depicted) and the HSG and a portion of dielectric <b>24</b> are etched, for example using chemical mechanical polishing (CMP). This removes the HSG from the horizontal surface of dielectric <b>24</b>. Any protective material remaining within opening <b>30</b> is removed.

Next, blanket layers of cell nitride <b>34</b> and top plate polysilicon <b>36</b> are formed over the surface of the assembly as depicted in FIG. 3. A patterned photoresist layer <b>38</b> is provided which defines the storage nodes and capacitor top plate. After the etch, the photoresist <b>38</b> is removed.

As depicted in FIG. 4 another dielectric layer <b>40</b> such as BPSG is deposited and planarized and a patterned photoresist <b>42</b> is formed over dielectric <b>40</b>. Opening <b>44</b> within the photoresist layer overlies the digit line contact pad <b>20</b>. A vertical anisotropic etch is performed which etches through dielectric layers <b>40</b> and <b>24</b> to provide a contact opening <b>50</b> and to expose the digit line contact pad <b>20</b> as depicted in FIG. <b>5</b>. The etch exposes pad <b>20</b>, which in turn contacts doped region <b>13</b>. Pad <b>20</b>, therefore, decreases the amount of oxide which the etch of the FIG. 4 structure must remove. Without pad <b>22</b>, the etch would be required to remove the additional thickness of oxide layer <b>22</b> to expose doped region <b>13</b>. Finally, as depicted in FIG. 6, a conductive plug <b>60</b> typically comprising tungsten is formed within opening <b>50</b> and a metal digit line runner <b>62</b>, typically aluminum, is formed over dielectric layer <b>40</b> to electrically contact the plug <b>60</b> to provide a digit line.

One problem with a process such as that described above is that the etch of the digit line contact opening <b>50</b> to expose the digit line contact pad <b>20</b> requires etching through a very thick series of dielectric layers. With current processes the ratio of the contact opening height to the width (i.e. the “aspect ratio”) can be 10:1 or greater. For example, layer <b>24</b> depicted in FIG. 4 can have a thickness of 14,000 angstroms (Å) or more, and layer <b>40</b> can have a thickness of 4,000 Å for a total of 18,000 Å of dielectric to etch through to form a contact about 1,150 Å wide for an aspect ratio of about 15:1. As the aspect ratio of openings increases the opening becomes increasingly difficult to form reliably. Contact locations in a periphery of a semiconductor device (see <b>174</b> in FIG. 17, for example) often do not have pads <b>18</b>, <b>20</b> which further increases the aspect ratio. Problems forming high aspect ratio contacts include difficulty in etching the bottom portion of the dielectric layer, in maintaining the proper diameter of toward the top of the opening, and in filling the contact opening with conductive material subsequent to its formation.

A method for forming a contact opening which reduces or eliminates the problems described above would be desirable.

SUMMARY OF THE INVENTION

The present invention provides a new method that reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting from contact etches and fills requiring a high aspect ratio. In accordance with one embodiment of the invention a portion of a digit line contact opening is etched to expose a digit line contact pad, then the opening is filled with conductive material to form a digit line contact plug to the pad. A storage capacitor is subsequently formed and the remainder of the digit line plug and digit line runner are formed. This process decreases the aspect ratio of the contact openings which must be formed, and may provide increased capacitance of the storage capacitor by allowing an increased height of the capacitor as will be described in detail below.

Other advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section depicting an opening in a photoresist layer to define container capacitors within a dielectric layer;

FIG. 2 depicts the FIG. 1 structure after etching the dielectric layer and forming a blanket hemispherical silicon grain (HSG) layer;

FIG. 3 is a cross section of the FIG. 2 structure subsequent to a planarization step and after forming a cell dielectric layer, a cell top plate layer, and a patterned photoresist layer to define a storage capacitor;

FIG. 4 is a cross section of the FIG. 3 structure after etching the cell dielectric and top plate, after formation of a planarized dielectric layer and formation of a patterned photoresist layer to define digit line contacts;

FIG. 5 is a cross section of the FIG. 4 structure after etching the digit line contact opening;

FIG. 6 is a cross section of the FIG. 5 structure after forming a contact plug and a metal runner to form a digit line;

FIG. 7 is a cross section of a first embodiment of the invention having a patterned photoresist layer which defines a digit line contact opening in a dielectric layer;

FIG. 8 is a cross section of the FIG. 7 structure subsequent to etching the dielectric layer and forming a blanket conductive plug layer within the opening;

FIG. 9 is a cross section of the FIG. 8 structure after planarizing the blanket plug layer to form a first portion of a digit line contact plug and after forming a blanket dielectric layer over the first conductive plug portion and a patterned photoresist layer which defines the container capacitor in a dielectric layer;

FIG. 10 depicts the structure of FIG. 9 subsequent to etching the dielectric layer to define the container capacitor, and subsequent to forming a blanket HSG layer and a protective photoresist layer within recesses defined by the HSG;

FIG. 11 depicts the FIG. 10 structure after a planarization step, after removing the photoresist layer, and after forming a cell dielectric layer, a capacitor top plate layer, a dielectric layer, and a patterned photoresist layer which defines openings to the digit line contact plug previously formed;

FIG. 12 depicts the structure of FIG. 11 subsequent to an etch which exposes the digit line contact plug;

FIG. 13 depicts the structure of FIG. 12 subsequent to forming a spacer dielectric layer;

FIG. 14 depicts the FIG. 13 structure after an anisotropic etch of the spacer layer and the formation of a digit line runner layer which also forms a portion of the digit line contact plug;

FIG. 15 depicts a cross section for a second embodiment of the invention similar to that of FIG. 9 having a digit line contact opening aspect ratio similar to that of conventional devices;

FIG. 16 depicts a cross section of the FIG. 15 structure after completion of various steps of the inventive embodiment; and

FIG. 17 is a cross section depicting various additional exemplary structures which can be formed during the process of FIGS. 9-16.

It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A first embodiment of an inventive method used during the formation of a semiconductor device is depicted in FIGS. 7-14. FIG. 7 depicts a semiconductor substrate assembly comprising a semiconductor substrate such as a wafer <b>10</b>, field oxide <b>12</b>, a transistor control gate comprising a polysilicon gate <b>14</b>A and silicide <b>14</b>B, surrounding dielectric including gate oxide <b>16</b>A, nitride spacers <b>16</b>B, and capping dielectric <b>16</b>C, for example comprising tetraethyl orthosilicate (TEOS) and nitride. FIG. 7 further depicts capacitor storage node contact pads <b>18</b> comprising polysilicon, a digit line contact pad <b>20</b> comprising polysilicon, and an overlying dielectric <b>24</b> such as borophosphosilicate glass (BPSG) which has been chemically-mechanically planarized (CMP) to about 14,000 Å thick in this exemplary embodiment in accordance with the conventional device described above. A patterned photoresist layer <b>70</b> defines an opening <b>72</b> to the digit line contact pad <b>20</b>. The structure depicted in FIG. 7 can be manufactured by one of ordinary skill in the art from the description herein.

After forming the FIG. 7 structure, BPSG layer <b>24</b> is etched to expose the digit line contact pad <b>20</b>. An etch comprising an atmosphere of CHF₃at a flow rate of 50 standard cubic centimeters (sccm), a temperature of about 50° C., and a pressure of about 15 millitorr (mT) would remove about 40 Å of oxide/minute. Thus for a BPSG layer <b>24</b> between about 14,000 Å as described above, a duration of about 5.8 minutes would be sufficient. The contact opening at the bottom, in accordance with the conventional embodiment described above, should have a minimum width at the bottom of 1,150 Å.

Subsequently, a blanket metal layer <b>80</b>, for example tungsten, is formed within the opening in BPSG <b>24</b> and overlying the BPSG layer as depicted in FIG. 8. A tungsten layer having a thickness of at least half as thick as the maximum width of opening <b>72</b> which defines the opening in the BPSG <b>24</b> can be formed using tungsten hexafluoride, WF₆, and silane, SiH₄, to begin the tungsten deposition. The silane provides a silicon source to tie up free fluorine atoms which can damage the substrate. After the initial layer of tungsten is produced, the deposition process is enhanced by replacing the silane with hydrogen gas.

Next, the structure of FIG. 8 is planarized, for example using chemical mechanical polishing (CMP) with an ammonia-based slurry, to remove the metal overlying dielectric <b>24</b> and leaving a metal plug <b>90</b> within dielectric <b>24</b> as depicted in FIG. <b>9</b>.

Another blanket dielectric layer <b>92</b> such as a TEOS layer between about 150 Å and about 250 Å, preferably about 200 Å, is deposited over the plug <b>90</b> and the BPSG layer <b>24</b>. TEOS can be formed using a liquid source such as Si(OC₂H₅)₄introduced into a low pressure chemical vapor deposition (LPCVD) furnace between about 690° C. and about 720° C. Other materials may also function for dielectric layer <b>92</b> such as a nitride, an oxynitride, or other similar diffusion barriers which are sufficient to prevent lower metal layers such as silicide gate portions <b>14</b>B from oxidizing.

A patterned photoresist layer <b>94</b> is formed over the TEOS layer <b>92</b> to define openings <b>96</b> to container capacitor contact pads <b>18</b>. An anisotropic oxide etch is performed on the structure of FIG. 9 to etch TEOS <b>92</b> and BPSG <b>24</b> to expose container capacitor contact pads <b>18</b> and to define the container capacitor. The oxide etch described previously relative to BPSG would sufficiently remove the TEOS and BPSG layers. The photoresist is removed.

Subsequently, a capacitor storage node layer <b>100</b> is formed over exposed surfaces as depicted in FIG. <b>10</b> and makes electrical contact with container capacitor contact pads <b>18</b>. The storage node layer can be formed using any number of workable processes. For example, a texturized polysilicon layer having a nominal thickness of between about 300 Å and about 1,500 Å can be formed using an in situ polysilicon in an LPCVD furnace at about 535° C. using silane and phosphine (PH₃) as source gasses. The wafer is moved to an oxidation furnace to receive a phosphorous deposition to a conductivity of between about 1E18 atoms/cm³to about 5E21 atoms/cm³. A native oxide will form on the polysilicon surface. The wafer is subjected to a 60 second 100:1 hydrofluoric acid bath, which results in partial removal of the native oxide such that thin patches of oxide remain. Next, hemispherical silicon grain (HSG) is formed over the in situ polysilicon layer in an LPCVD furnace at 555° C. using silane gas. The small oxide patches on the in situ surface give the polysilicon layer a rough surface. A target polysilicon thickness of between about 500 Å and about 3,000 Å would be sufficient depending on the width of the opening, and other thicknesses may be sufficient. Contact pads <b>18</b> are electrically coupled by physical contact with storage node <b>100</b> layer and with doped regions <b>13</b>.

After forming HSG layer <b>100</b>, the recess defined by the layer is filled with a sacrificial layer <b>102</b> such as photoresist. The surface of the FIG. 10 structure is then planarized, for example using CMP, to remove the HSG from the horizontal surface of the dielectric <b>92</b>. The HSG within the opening remains to form the container capacitor storage plate. The thickness of material removed from the structure should be small enough so that a portion of dielectric layer <b>92</b>, for example at least about 100 Å remains subsequent to planarization. After this planarization step, the photoresist layer <b>102</b> is removed.

Next, a cell dielectric layer <b>110</b> such as cell nitride and a top plate layer <b>112</b> such as polysilicon are formed over the exposed surfaces. A cell nitride layer between about 85 Å and 105 Å can be deposited by processing the wafer in an LPCVD furnace using dichlorosilane (SiH₂Cl₂) and ammonia (NH₃) gasses. A 2,000 Å polysilicon top plate layer can be formed in an LPCVD furnace at about 620° C. using an atmosphere of silane gas (SiH₄), or by using another workable method. As the polysilicon forms at a rate of about 4,000 Å/hr, the process is performed for about 30 minutes to form the 2,000 Å polysilicon layer as described above.

A dielectric layer <b>114</b>, for example BPSG between about 4,000 Å thick is formed and planarized. BPSG can be formed by employing an atmospheric pressure chemical vapor deposition (APCVD) system and silane, oxygen, phosphine (PH₃) and diborine (B₂H₆), and can be planarized using a reflow in a nitrogen purged atmospheric furnace at about 907° C. for about 25 minutes followed by a three hour anneal at about 800° C. The dielectric <b>114</b>, in this exemplary embodiment 4,000 Å, is then patterned using a photoresist layer <b>116</b> formed over the BPSG layer <b>114</b> which defines an opening to the underlying digit line contact plug <b>90</b>. The structure of FIG. 11 is etched using a vertical anisotropic etch, such as that described previously relative to BPSG adjusted for the present layer, which also etches the 2,000 Å of polysilicon <b>112</b>, the 95 Å of cell nitride <b>110</b> and the 200 Å of dielectric <b>92</b> to expose the plug <b>90</b> as depicted in FIG. <b>12</b>.

After exposing the digit line plug <b>90</b>, a polysilicon etch is performed to recess the exposed polysilicon <b>112</b> between nitride <b>110</b> and BPSG layer <b>114</b> as depicted in FIG. <b>13</b>. To adequately recess a polysilicon layer 525 Å thick, an etch comprising Cl₂at a flow rate of about 7 sccm, SF₆at a flow rate of about 25 sccm, He at a flow rate of about 35 sccm, O₂at a flow rate of about 12 sccm, at a pressure of about 600 mTorr for about 18 seconds. After recessing the polysilicon <b>112</b>, a dielectric layer is formed over the ends of polysilicon <b>112</b> which are exposed at the opening to the digit line plug <b>90</b>. This can be accomplished by forming a dielectric layer <b>130</b> such as a conformal layer of nitride, or a planar layer such as TEOS, over exposed surfaces then performing a vertical spacer etch to result in the spacers <b>140</b> of FIG. <b>14</b>. Alternately, a facet etch of the BPSG <b>114</b>, for example using cations from an argon plasma to chip off protruding BPSG from the top corners of layer <b>114</b> and to redistribute or redeposit it to the sidewalls and to isolate polysilicon <b>112</b>, would be sufficient and would eliminate the need for forming a separate dielectric layer. Such a process may be sufficient for any oxide or glass film with some modification, for example to adjust for various dopants which may affect the etch. It will be appreciated by one of ordinary skill in the art that this self-aligned isolation of the cell polysilicon reduces the possibility of shorting between the digit line plug and the cell polysilicon over conventional processes.

After forming the dielectric layer <b>140</b> over the exposed ends of polysilicon layer <b>112</b>, a patterned metal layer <b>142</b> such as titanium and aluminum/copper is formed to contact the digit line plug <b>90</b> as depicted in FIG. <b>14</b>. In one exemplary metal deposition process, argon gas is changed into a plasma and the ions are used to bombard titanium and aluminum/copper targets. Atoms of metal material are sputtered from the metal target to the wafer surface to form layer <b>142</b>.

The inventive process disclosed above has the advantage over conventional processes that an excessive dielectric thickness does not need to be etched to form the digit line plug and the aspect ratio of the contact plug opening is reduced. The plug opening is, in effect, etched using two separate etches. In the embodiment of the invention described above the two etches which define the plug are separated in time by an etch which defines the capacitor storage plate. Using the conventional process described herein in the Background of the Invention above, 18,000 Å of dielectric was etched through using a single etch to form the plug opening. With the instant process, 14,000 Å of oxide dielectric were removed from a first BPSG layer in a first etch. In a second etch, 4,000 Å of dielectric, 2,000 Å of polysilicon, 95 Å of cell nitride, and 200 Å of TEOS were removed to form a structure analogous to the plug of conventional processes. As the opening in each case is about 1,150 Å, the aspect ratio of the first oxide etch is about 12:1, and in the second etch the aspect ratio is about 5.5:1.

In a second embodiment of the invention the aspect ratio of the conventional process is maintained for the etch of the FIG. 7 structure by forming a thicker layer <b>24</b>, then the process is continued according to the first embodiment. With this second embodiment, a storage capacitor having a greater height and therefore a greater capacitance is formed. FIG. 15 depicts a structure similar to FIG. 9, except that the opening which forms plug <b>150</b> has the aspect ratio of the opening <b>50</b> of the conventional structure of FIG. <b>5</b>. In this embodiment, dielectric layer <b>152</b> of FIG. 15 is about the same thickness as layers <b>24</b> and <b>40</b> (FIG. 5) combined. After forming the structure of FIG. 15, wafer processing continues as described above for the first inventive embodiment, adjusted for thicker layer <b>152</b>, to result in the structure of FIG. <b>16</b>. In comparing FIG. <b>16</b> and FIG. 14, the storage capacitor comprises a greater height and surface area, and therefore an increased capacitance, with no increase in horizontal spacing. Thus this embodiment has the advantage over the conventional process of FIGS. 1-6 that a larger storage capacitor is formed without increasing the aspect ratio of the digit line contact plug.

In a third embodiment of the invention, the digit line contact plug opening has an intermediate aspect ratio between that of the first and second inventive embodiments. This third embodiment reduces the digit line contact opening aspect ratio, and therefore the difficulty of the etch, but allows for a larger storage capacitor having a larger capacitance than is possible with conventional devices having a larger digit line contact opening aspect ratio.

It will be appreciated by one of ordinary skill in the art that various other features, such as silicide to improve polysilicon conductivity and various steps such as inspection and cleaning will be present depending on the design of the device which have been omitted from the FIGS. and description for simplicity of explanation.

In another embodiment layer <b>92</b> may not be required. Layer <b>92</b> protects underlying layers during high-temperature processing of the wafer subsequent to its formation. For example, the formation of layer <b>142</b> may require a high-temperature anneal depending on the material used. High-temperature steps such as the anneal can result in oxidation of various substructures such as silicide <b>14</b>B, some of which have contacts formed thereto, depicted as layer <b>170</b> in FIG. <b>17</b>. If the silicide oxidizes, the electrical properties of the contact can be degraded, and layer <b>92</b> reduces or eliminates oxidation of underlying layers. If high-temperature steps are not required, it may be possible to eliminate layer <b>92</b>. However, layer <b>92</b> requires no additional masking steps. FIG. 17 further depicts a contact plug <b>172</b> to a doped region <b>174</b> in the wafer <b>10</b> formed simultaneously with the other contact plugs <b>90</b>, <b>170</b>.

A semiconductor device formed in accordance with the invention may be attached along with other devices to a printed circuit board, for example to a computer motherboard or as a part of a memory module used in a personal computer, a minicomputer, or a mainframe. The inventive device can be useful in electronic devices related to telecommunications, the automobile industry, semiconductor test and manufacturing equipment, consumer electronics, or virtually any piece of consumer or industrial electronic equipment.

While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.