Method for fabricating semiconductor device

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for fabricating a semiconductor device and, in particular, to a method for forming a metal interconnection contact hole in a peripheral circuit region, without damaging the semiconductor substrate.

2. Description of the Background Art

In general, the metal interconnection contacts on a DRAM are formed to at least the substrate in active regions, the gate electrodes, the bit lines and the capacitor plate electrodes. In highly integrated devices, the aspect ratio of a metal interconnection contact hole is typically greater than 10. Therefore, the metal interconnection contact hole is formed when a selection ratio to a deep ultraviolet (DUV) photoresist film used to form the contact pattern is at least 8 in an oxide film etching process. An etching process for forming the contact hole is performed in a reactive ion etch (RIE) system having an intermediate plasma density using a perfluorocarbon containing gas mixture such as C₄F₈and Ar, C₄F₆and Ar, or C₅F₈and Ar.

In a high density plasma system, the selection ratio to the photoresist film is more typically 3 or 4. Accordingly, such systems are not suitable as the etch system for forming the metal interconnection contact holes.

In a conventional method for forming the metal interconnection contact hole, a mask insulating film of the gate electrode or bit line is an oxide film, and thus the etching process can be performed by using gas combinations and parameter that will generate a large amount of polymers, such as C₄F₈and Ar.

However, when the mask insulating film of the gate electrode or bit line consists of an SiN or SiON film, a multi-step etching process is required.

A first etching process is performed onto the upper portion of the gate electrode using an etching gas such as a mixture of C₄F₈and Ar, in order to obtain a high selection ratio to the photoresist film. A second etching process is then performed on the SiN or SiON film, by employing a mixed gas of CHF₃, Ar and O₂or a mixed gas of CF₄, Ar and O₂, both of which provide better selectivity to the photoresist film.

The semiconductor substrate may be damaged in the two-step etching process. Because the wells of highly integrated devices are shallow, damage to the semiconductor substrate tends to increase contact resistance remarkably. Therefore, the etching process for forming the metal interconnection contact must be generally carried out by using the mixed gas of CHF₃, Ar and O₂as the etching gas to obtain the high selection ratio with respect to the semiconductor substrate. In addition, when the mask insulating film is a SiN film, the etching process can be performed by using the mixed gas of CHF₃, Ar and O₂.

However, when that the mask insulating film is a SiON film, its etching properties vary according to film composition. The general SiON film consists of Si₃N₄film and SiO₃film, and thus can be etched by using the mixed gas of CHF₃, Ar and O₂. However, when the Si-rich SiON (SRON) film is used as an etch barrier film in the etching process according to a self aligned contact (SAC) method for a bit line contact and storage electrode contact, it is very difficult to etch the metal interconnection contact.

The SAC method employing the general SiN film has disadvantages in that transistor properties may be deteriorated due to the high stress within SiN film, tending to lift the gate electrode or bit line, increasing contact junction leakage current. Further, and additional reflection barrier film process is required in the formation of the photoresist film for the gate electrode or bit line.

In order to overcome such disadvantages, the SiN film is typically replaced by the SiO₂film or SiON film. However, when the SiO₂film or SiON film is used, the SAC process for forming the contacts to the bit line and storage electrode cannot be performed with acceptable margins.

Moreover, it is almost impossible to obtain a high selection ratio with respect to both the SiON film and the SiO₂film in the oxide film etching process. Accordingly, because silicon is affected by different etch chemistry than that used to etch the oxide film when Si is added to the SiON to form a Si-rich SiON film, it is possible to obtain an improved etching selection ratio in the oxide etching process.

Thus, the Si-rich SiON film has been utilized as an etch barrier film for the SAC process for forming the bit line contact and storage electrode contact. However, the Si-rich SiON film has the disadvantage when it is used in the metal interconnection contact etching process in that it is generally etched using the mixed gas of CHF₃, Ar and O₂or a mixed gas of CF₄, Ar and O₂. Here, the Si-rich SiON film is etched by using the mixed gas of CHF₃, Ar and O₂with a large amount of O₂included to maintain the selection ratio with respect to the photoresist film.

The semiconductor substrate will, however, be damaged by etch chemistry having large amounts of O₂. Especially, in the chemical mechanical polishing (CMP) process, the non-uniformity of the insulating films that must be opened to form the metal interconnection contact can be over 2000 Å. As a result, it is difficult to apply a three-step etching process including 1) a high selective etching process for the photoresist film, 2) an etching process for the Si-rich SiON film, and 3) a highly selective etching process for the semiconductor substrate, instead of the two-step etching process.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor device which can form a metal interconnection contact hole by performing a first etching process for removing an interlayer insulating film using a photoresist film pattern as an etch mask, a second etching process for removing an etch barrier film and a mask insulating film, and a third etching process for exposing the semiconductor substrate in the contact areas.

In order to achieve the above-described object of the present invention, in a method for fabricating a semiconductor device for forming a metal interconnection contact hole exposing a gate electrode in a peripheral circuit region of a semiconductor substrate and a presumed portion of a metal interconnection contact on the semiconductor substrate, a method for fabricating a semiconductor device includes the steps of: forming a MOSFET having the gate electrode and source/drain regions on the semiconductor substrate, a mask insulating film pattern being provided at the upper portion of the gate electrode, an insulating film spacer being provided at the side walls of the gate electrode; forming a first interlayer insulating film having a contact plug contacted with a presumed portion of a bit line contact and a storage electrode contact on the semiconductor substrate, and an etch barrier film over the entire structure; forming a bit line and a capacitor contacted with the contact plug, and a second interlayer insulating film; forming a photoresist film pattern exposing a presumed portion of the metal interconnection contact on the second interlayer insulating film over the entire structure; and forming the metal interconnection contact hole by etching the stacked structure of the second interlayer insulating film, the etch barrier film and the mask insulating film pattern, and the stacked structure of the etch barrier film and the first interlayer insulating film according to a three-step etching process, by employing the photoresist film pattern as an etching mask, and removing the photoresist film pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus should not be considered to unecessarily limit the present invention as defined by the claims.

FIGS. 1A through 1I are cross-sectional diagrams illustrating sequential steps of a method for fabricating a semiconductor device in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As illustrated in FIG. 1A, a device isolating film (not shown) is formed and etched to define active regions and device isolating regions on a semiconductor substrate <b>11</b>. A gate insulating film (not shown) is formed over the entire structure.

A stacked structure of a gate electrode conductive layer (not shown) and a first mask insulating film (not shown) is formed on the gate insulating film in the active regions.

Thereafter, a gate electrode <b>13</b> and a first mask insulating film pattern <b>15</b> are formed by patterning and etching the stacked structure using a gate electrode mask as an etching mask and a mixed gas of CF₄, Ar and O₂or a mixed gas of CHF₃, Ar and O₂as the etching gas. Here, the first mask insulating film pattern <b>15</b> consists of an Si-rich SiON film (SRON).

A nitride film is then formed over the entire structure.

A nitride film spacer <b>17</b> is formed at the sidewalls of the gate electrode <b>13</b> and the first mask insulting film pattern <b>15</b> by etching the nitride film.

Source/drain regions (not shown) are then formed by implanting an impurity in to the semiconductor substrate <b>11</b> at both sides of the nitride film spacer <b>17</b>. The source/drain regions may have a lightly doped drain (LDD) structure.

Referring to FIG. 1B, a first interlayer insulating film <b>19</b> is formed over the entire structure. Here, the first interlayer insulating film <b>19</b> consists of an oxide film having an etching selection ratio difference from the nitride film spacer <b>17</b> and the first mask insulating film pattern <b>15</b>.

Thereafter, a first photoresist film pattern <b>21</b> that exposes the insulating film <b>19</b> where the bit line contacts and storage electrode contacts are to be formed on the semiconductor substrate <b>11</b> is formed on the first interlayer insulating film <b>19</b>.

As depicted in FIG. 1C, the first interlayer insulating film <b>19</b> is removed according to an etching process employing the first photoresist film pattern <b>21</b> as an etching mask, thereby forming a first storage contact hole <b>23</b> exposing the intended portion of the bit line contact and the storage electrode contact.

In order to provide a highly selective etching process for the first mask insulating film pattern <b>15</b> and the nitride film spacer <b>17</b>, the etching process is performed using a perfluorocarbon containing gas that generates a large amount of polymers, such as C₂F₆, C₂F₄, C₃F₆, C₃F₈, C₄F₆, C₄F₈, C₅F₈, C₅F₁₀or C₂HF₅.

The etching process may be carried out by using a mixed gas comprising a perfluorocarbon containing gas and a hydrogen containing gas, such as CHF₃, CH₃F, CH₂F₂, CH₂, CH₄, C₂H₄or H₂.

In addition, the etching process may be performed by adding an inert gas such as He, Ne, Ar or Xe to the perfluorocarbon containing gas or to a mixed gas of the perfluorocarbon containing gas and the hydrogen containing gas, thereby overcoming an etch stop phenomenon by improving plasma stability and sputtering effects, and performing a reproducible etching process.

The etching process employs CxHyFz gas (x≧2, y≧2, z≧2) as an etching gas, and thus obtains a high etching selection ratio to the mask insulating film pattern and the insulating film spacer. On the other hand, the etching process may be performed by using a mixed gas of the CxHyFz gas (x≧2, y≧2, z≧2) and the inert gas as an etching gas.

The first photoresist film pattern <b>21</b> is then removed.

As shown in FIG. 1D, a conductive layer <b>25</b> for a first contact plug is then formed over the entire structure.

As illustrated in FIG. 1E, the first contact plug <b>27</b> is formed by removing the remainder of the conductive layer <b>25</b> with a chemical mechanical polishing (CMP) process. The CMP process employs the first mask insulating film pattern <b>15</b> as an end point indicator.

As depicted in FIG. 1F, an etch barrier film <b>28</b> is formed over the entire structure by using an SiN or SiON film. The intended location of the bit line contact is exposed in the first contact plug <b>27</b>.

Thereafter, a bit line <b>30</b> is formed in contact with the first contact plug <b>27</b>. Here, a second mask insulating film pattern <b>32</b> is provided at the upper portion of the bit line <b>30</b>, and a second insulating film spacer <b>34</b> is provided at the sidewalls of the stacked structure.

A second interlayer insulating film <b>29</b> is then formed over the entire structure.

The second interlayer insulating film <b>29</b> is etched by using a contact mask that exposing the intended location for the storage electrode contact in the first contact plug <b>27</b>, thereby forming a contact hole. When forming the contact hole, the etch barrier film <b>28</b> formed on the first contact plug <b>27</b> is removed.

A second contact plug <b>31</b> is formed in contact with the first contact plug through the contact hole.

A storage electrode <b>33</b> is then formed in contact with the second contact plug <b>31</b>.

Thereafter, a dielectric film (not shown) and a plate electrode <b>35</b> are formed over the entire structure, thereby forming a capacitor in a cell region of the semiconductor substrate <b>11</b>.

A third interlayer insulating film <b>37</b> is formed over the entire structure, and then planarized. A second photoresist film pattern <b>39</b> exposing a the intended location of a metal interconnection contact in a peripheral circuit region of the semiconductor substrate <b>11</b> is formed on the third interlayer insulating film <b>37</b>.

As illustrated in FIGS. 1G to <b>1</b>I, a metal interconnection contact hole is then formed according to a three-step etching process using the second photoresist film pattern <b>39</b> as an etching mask.

Referring to FIG. 1G, a first etching process etches the third interlayer insulating film <b>37</b> and the second interlayer insulating film <b>29</b> using the second photoresist film pattern <b>39</b> as an etching mask. In the first etching process, the etch barrier film <b>28</b> is used as an etch barrier, and the perfluorocarbon containing gas generating a large amount of polymers and having a high etching selection ratio to the second photoresist film pattern <b>39</b> is used as an etching gas. In addition, the first etching process may be performed by utilizing a mixed gas of the perfluorocarbon containing gas and an oxygen containing gas as the etching gas.

As shown in FIG. 1H, a second etching process forms the metal interconnection contact hole <b>41</b> exposing the gate electrode <b>13</b>, by removing the first mask insulating film pattern <b>15</b> on the gate electrode in the peripheral circuit region. Here, of a predetermined thickness the first interlayer insulating film <b>19</b> is removed in the region where the gate electrode <b>13</b> has not been formed.

The second etching process uses CF₄, CHF₃, NF₃or C₂F₆as a main etching gas. In addition, the second etching process may be performed by adding CH₃F, CH₂F₂or C₂HF₅, an inert gas such as He, Ne, Ar or Xe, or an oxygen containing gas such as CO, CO₂or O₂to the main etching gas. Here, a large amount of O₂gas is used. Since the etching selection ratio to the semiconductor substrate <b>11</b> is relatively low, the etch depth is controlled to avoid exposing the semiconductor substrate <b>11</b>.

As depicted in FIG. 1I, a third etching process is then performed with a high etching selection ratio to the semiconductor substrate <b>11</b>. In the third etching process, the mixed gas of the first etching process may again be used as the etching gas. The semiconductor substrate <b>11</b> is exposed by completely removing the remaining thickness the first interlayer insulating film <b>19</b> in the region where the gate electrode has not been formed, thereby forming a metal interconnection contact hole <b>42</b>.

Although not illustrated, a metal interconnection with the gate electrode <b>13</b> and the semiconductor substrate <b>11</b> made through the metal interconnection contact holes <b>41</b>, <b>42</b> is then formed by using a metal layer.

As discussed earlier, in accordance with the present invention, in the process for forming the metal interconnection contact hole on the gate electrode including the Si-rich SiON film as the mask insulating film in the peripheral circuit region and on the semiconductor substrate, the metal interconnection contact hole is formed according to the three-step etching process using the photoresist film pattern that exposes the intended locations of the metal interconnection contacts as an etching mask. Accordingly, contact properties are improved by preventing damage to the semiconductor substrate, leakage current is reduced, and device properties and yield are improved.

As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited to the specific details provided in the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims. Therefore, all changes and modifications to the process that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are therefore intended to be embraced by the appended claims.