Nova Patents
US6594753B2

Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units

Summary by NHIP

Dual Issue Control Unit

The instruction issue control unit issues undecoded program instructions to multiple symmetrical multifunctional processing logic units. Each unit contains identical sets of execution circuits, including floating point adders, dividers, ALUs, and integer multipliers.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.

US6594753B2, drawing sheet 1
Sheet 1 of 7

Term

Term ended

Expired 6 March 2020, 6.6 years ago.

  1. Priority
  2. Filed
  3. Granted
  4. Expired
  5. Today

37 claims: 4 independent, 33 dependent

  1. 1
    Broadest claimClaim Score 79, broad(NHIP)An instruction issue control unit comprising logic to issue an instruction that is not decoded to a first multifunctional processing logic unit of a plurality of multifunctional processing logic units that each contain a set of independent processing logic circuits capable of performing a matching set of functions.
  2. 13
    A microprocessor comprising:a plurality of registers to store operands;an instruction cache to store instructions;an instruction issue control unit coupled with the instruction cache to receive instructions from the cache and to issue instructions;a first multifunctional execution unit coupled with the instruction issue control unit and with the plurality of registers and containing a first plurality of different execution units that are capable of providing a first set of functions on operands received from the cache according to instructions received from the instruction issue control unit;a first multiplexer coupled between the plurality of registers and the first multifunctional execution unit to receive a first operand from the registers and provide the first operand to the first multifunctional execution unit, wherein the first multiplexer has a single input to receive a result of an executed instruction that has been executed by the first multifunctional execution unit;a second multifunctional execution unit coupled with the instruction issue control unit and with the plurality of registers and containing a second plurality of different execution units that are capable of providing a second set of functions on operands received from the cache according to instructions received from the instruction issue control unit, wherein the first set of functions and the second set of functions match;and a second multiplexer coupled between the plurality of registers and the second multifunctional execution unit to receive a second operand from the registers and provide the second operand to the second multifunctional execution unit, wherein the second multiplexer has only one input to receive a result of an executed instruction that has been executed by the second multifunctional execution unit.
  3. 16
    A microprocessor comprising:a plurality of registers to store at least one operand;an instruction cache to store at least one un-decoded instruction;an instruction issue control unit coupled with the instruction cache to receive the instruction and comprising logic to issue the un-decoded instruction;and a plurality of multifunctional processing pipelines that are each coupled with the plurality of registers to receive the operand, that are each coupled with the instruction issue control unit to receive the issued instruction, and that each comprise a set of independent processing logic circuits that are capable of providing a matching set of processing functions, wherein each set of independent processing logic circuits contains at least two different independent processing logic circuits including an independent processing logic circuit that is capable of processing the operand according to the issued instruction.
  4. 28
    An integrated circuit comprising:a plurality of registers to store at least one operand;an instruction cache to store at least one un-decoded instruction;instruction issue means coupled with the instruction cache for issuing the un-decoded instruction received from the instruction cache;and a plurality of multifunctional processing pipelines that are each coupled with the plurality of registers to receive the operand, that are each coupled with the instruction issue means to receive the issued un-decoded instruction, and that each comprise a set of independent processing logic circuits that are capable of providing a matching set of processing functions, wherein each set of independent processing logic circuits contains at least two different independent processing logic circuits including an independent processing logic circuit that is capable of processing the operand according to the issued instruction.
Independent claims4