Semiconductor device manufacturing method capable of reliable inspection for hole opening and semiconductor devices manufactured by the method

CROSS REFERENCE TO RELATED APPLICATION

This application is based on Japanese patent application 2001-313706, filed on Oct. 11, 2001, the whole contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

A) Field of the Invention

The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device manufacturing method with an inspection for hole opening for via holes to be formed through an insulating film on a wiring layer, and to semiconductor devices manufactured by such a method.

B) Description of the Related Art

Several inspection methods for hole opening are known for inspecting whether a via hole formed through an interlayer insulating film reaches the surface of the underlying layer of the interlayer insulating film.

FIG. 12A is a cross sectional view showing a peripheral area of a via hole to be inspected by the inspection method for hole opening disclosed in JP-A-60-109240. On an underlying interlayer insulating film <b>500</b>, a wiring line <b>501</b> is formed. An upper interlayer insulating film <b>502</b> formed on the interlayer insulating film <b>500</b> covers the wiring line <b>501</b>. A via hole <b>503</b> is formed through the interlayer insulating film <b>502</b>. The via hole <b>503</b> is disposed so that the edge of the wiring line <b>501</b> passes through the bottom area of the via hole <b>503</b>, as viewed along a line parallel to the normal to the substrate surface.

If the via hole <b>503</b> reaches the wiring line <b>501</b>, a step formed by the wiring line <b>501</b> can be observed when the bottom of the via hole is observed with a scanning electron microscope (SEM). If the via hole <b>503</b> does not reach the wiring line <b>501</b>, a step by the wiring line cannot be observed.

An inspection for opening of the via hole <b>503</b> can therefore be made relying upon whether the step by the wiring line <b>501</b> can be observed.

As shown in FIG. 12B, if the edge of a wiring line <b>507</b> to be formed on an interlayer insulating film <b>505</b> having a via hole <b>506</b> is disposed in the opening of the via hole, it is possible to detect an alignment shift between the layer formed with the via hole <b>506</b> and the layer disposed with the wiring line, by observing the step on the bottom of the via hole <b>506</b>.

FIGS. 13A and 13B are cross sectional views showing peripheral areas of via holes to be inspected by the inspection method for hole opening disclosed in JP-A4-12531.

As shown in FIG. 13A, a wiring line <b>511</b> is disposed on an underlying interlayer insulating film <b>510</b>. An upper interlayer insulating film <b>512</b> disposed on the interlayer insulating film <b>510</b> covers the wiring line <b>511</b>. The region of the interlayer insulating film <b>512</b> above the wiring line <b>511</b> is swelled, and the interlayer insulating film <b>512</b> becomes thicker near in the central area of the wiring line <b>511</b>. Therefore, as a via hole <b>513</b> is formed in an area corresponding to the wiring line <b>511</b>, residues <b>514</b> are likely to be left on the wiring line <b>511</b>. The left residues <b>514</b> make it difficult to detect a step of the wiring line <b>511</b>.

As shown in FIG. 13B, if two wiring lines <b>511</b> are juxtaposed, the upper surface of an interlayer insulating film <b>512</b> between the two wiring lines <b>511</b> can be made generally flat. If a via hole overriding at least one of the two wiring lines is formed in the interlayer insulating film <b>512</b>, residues are not left on the wiring lines <b>511</b> and a step of the wiring line or lines <b>511</b> can be detected easily.

FIG. 14 is a cross sectional view showing a peripheral area of via holes to be inspected by the inspection method for hole opening disclosed in JP-A-11-297777. On the surface of a semiconductor substrate <b>520</b>, an interlayer insulating film <b>521</b> is formed on which a wiring line <b>522</b> is formed. The wiring line <b>522</b> is electrically connected to the semiconductor substrate <b>520</b> via a via hole <b>523</b> formed through the interlayer insulating film <b>521</b>.

An upper interlayer insulating film <b>524</b> formed on the interlayer insulating film <b>521</b> covers the wiring line <b>522</b>. Via holes <b>525</b> are formed in the interlayer insulating film <b>524</b> to expose the partial upper surfaces of the wiring line <b>522</b>. The bottom of each via hole <b>525</b> observed with a SEM is bright if the wiring line <b>522</b> is exposed, and dark if the via hole <b>525</b> does not reach the wiring line <b>522</b>.

Even if the wiring line <b>522</b> is exposed on the bottom of the via hole <b>525</b>, the brightness of the bottom of the via hole lowers if electrons are accumulated in the wiring line <b>522</b>, and this case cannot be discriminated from the case that the via hole <b>525</b> does not reach the wiring line <b>522</b>. The structure that the wiring line <b>522</b> is connected to the semiconductor substrate <b>520</b> as shown in FIG. 14 can prevent accumulation of electrons in the wiring line <b>522</b>.

As compared to a conventional method of forming a wiring line by patterning a metal layer through reactive ion etching (RIE), a damascene method can satisfy more easily high integration requirements of semiconductor integrated circuit devices and can expect a reduction in the number of processes. The damascene method has therefore drawn attention and is suitable for forming a copper wiring with a lowered wiring resistance.

FIG. 15A is a cross sectional view showing a peripheral area of a via hole during a process of forming a copper wiring by a damascene method. In a wiring groove formed in a surface layer of an underlying interlayer insulating film <b>530</b>, a copper wiring line <b>532</b> is embedded. In order to prevent copper diffusion, the inner surface of the wiring groove is covered with a barrier metal layer <b>531</b> of tantalum (Ta) or the like.

On the interlayer insulating film <b>530</b>, a silicon nitride (SiN) film <b>533</b>, a silicon oxide (SiO₂) film <b>534</b>, a low dielectric constant insulating film <b>535</b>, an SiO₂film <b>536</b>, and an SiN film <b>537</b> are laminated in this order from the bottom. This lamination structure is formed with a via hole <b>538</b> which exposes a partial upper surface of the copper wiring line <b>532</b>. A wiring groove <b>539</b> is formed overlapping the via hole <b>538</b>, and reaches the bottom of the low dielectric constant insulating film <b>535</b>.

FIG. 15B shows a SEM photograph showing the peripheral area of the via hole <b>538</b>. Since the bottom of the via hole <b>538</b> is dark, it is not possible to judge whether the copper wiring line <b>532</b> is exposed.

FIG. 15C is a cross sectional view showing the peripheral area of a via hole <b>538</b>A wherein the via hole <b>538</b>A is slightly shifted from a copper wiring line <b>532</b> so that the edge of the copper wiring line <b>532</b> passes through the bottom area of the via hole <b>538</b>A. The via hole <b>538</b>A is formed by etching the lamination structure to the bottom of the SiO₂film <b>534</b> by using the SiN film <b>533</b> as an etching stopper film and thereafter removing the SiN film <b>533</b> exposed on the bottom of the via hole.

The etching conditions for the SiN film <b>533</b> are usually set so that the interlayer insulating film <b>530</b> and copper wiring line <b>532</b> are scarcely etched. Therefore, a step corresponding to the edge of the copper wiring line <b>532</b> is not formed.

FIG. 15D is a SEM photograph showing the peripheral area of the via hole <b>538</b>A. Almost the whole area of the bottom of the via hole <b>538</b>A is observed dark and the boundary between the copper wiring line <b>532</b> and interlayer insulating film <b>503</b> cannot be detected. This is because there is no step as opposed to the conventional example shown in FIG. <b>12</b>A.

The inspection for hole opening without utilizing a step is possible for the conventional case shown in FIG. <b>14</b>. However, as a diameter of the via hole <b>525</b> becomes small, a difference between darkness and brightness of the exposed and unexposed wiring lines <b>522</b> becomes small so that highly reliable inspection for hole opening is not possible.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor device manufacturing method capable of performing highly reliable inspection for hole opening even if a step is not formed on the bottom of a via hole and the diameter of the via hole is small.

It is another object of the present invention to provide a semiconductor device manufactured by the above-described semiconductor device manufacturing method.

According to one aspect of the present invention, there is provided a semiconductor device manufacturing method comprising steps of: (a) forming a first film of insulating material on a first surface defined on a substrate, the substrate having a surface layer portion made of insulating material and formed with a wiring groove filled with wiring line of conductive material, an upper surface of the wiring line being exposed on the first surface, the wiring line being electrically connected to a conductive member, and the conductive member occupying an area larger than an area of the wiring line as viewed along a line parallel to a normal to the first surface; (b) forming a via hole through the first film, the via hole being formed so that a boundary between the wiring line and the surface layer portion of insulating material passes through the inside of the via hole as viewed along a line parallel to the normal to the first surface; and (c) observing a bottom of the via hole with an apparatus for obtaining image information by utilizing secondary electrons and reflection electrons from a specimen, to judge whether a state of the bottom of the via hole is accepted or rejected.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate defining a first surface, the substrate having a surface layer portion made of insulating material and formed with a wiring groove filled with a wiring line of conductive material, an upper surface of the wiring line being exposed on the first surface, the wiring line being electrically connected to a first conductive member, and the first conductive member occupying an area larger than an area of the wiring line as viewed along a line parallel to a normal to the first surface; a first film made of insulating material and formed on the first surface of the substrate; a via hole formed in the first film, the via hole being disposed so that a boundary line between the wiring line and the surface layer portion of insulating material passes through the inside of the via hole as viewed along a line parallel to the normal to the first surface; and a second conductive member filled in the via hole and connected to the wiring line at a bottom of the via hole, wherein a bottom of said second conductive member has no step at a position corresponding to an edge of the wiring line.

Since the wiring lines are connected to a large conductive member, accumulation of charges in the wiring lines can be reduced and a clear image can be obtained by utilizing the intensity distribution of secondary electrons and reflection electrons. Since the boundary line between each wiring line and surface layer portion passes through the bottom area of the via hole, it can be judged whether the wiring line is exposed or not, by detecting a presence/absence of the boundary line on the bottom of the via hole.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are cross sectional views of a semiconductor device according to a first embodiment, and FIG. 1C is a plan view thereof.

FIGS. 2A and 2B are plan views of semiconductor devices according to modifications of the first embodiment.

FIG. 3A is a plan view of a semiconductor device according another modification of the first embodiment, FIG. 3B is a cross sectional view thereof, and FIG. 3C is a SEM photograph thereof.

FIG. 4 is a plan view of a semiconductor device according to a second embodiment.

FIG. 5A is a cross sectional view of a semiconductor device according to a third embodiment, and FIG. 5B is a plan view thereof.

FIG. 6A is a cross sectional view of a semiconductor device according to a fourth embodiment, and FIG. 6B is a plan view thereof.

FIG. 7 is a cross sectional view of a semiconductor device according to a fifth embodiment.

FIG. 8 is a cross sectional view of the peripheral area of a via hole for inspection for hole opening, explaining a problem of inspection for hole opening associated with the region where a wide wiring line is disposed.

FIG. 9A is a cross sectional view of a semiconductor device according to a sixth embodiment, and FIG. 9B is a plan view thereof.

FIGS. 10A to <b>10</b>H are cross sectional views illustrating a semiconductor device manufacturing method applicable to an inspection for hole opening used by the semiconductor devices of the embodiments.

FIG. 11 is a cross sectional view of a semiconductor device capable of incorporating the inspection for hole opening used by the semiconductor device of the embodiments.

FIGS. 12A and 12B are cross sectional views showing via holes and wiring lines to be subjected to conventional inspection for hole opening and inspection for alignment shift.

FIGS. 13A and 13B are cross sectional views showing via holes and wiring lines to be subjected to conventional inspection for hole opening.

FIG. 14 is a cross sectional view showing via holes and a wiring line to be subjected to conventional inspection for hole opening.

FIGS. 15A and 15C are cross sectional views of the peripheral areas of via holes wherein a conventional inspection method for hole opening is applied to wiring patterns of a damascene structure, and FIGS. 15B and 15D are SEM photographs of the devices shown in FIGS. <b>15</b>A and <b>15</b>C.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

With reference to FIGS. 1A to <b>1</b>C, a semiconductor device and its manufacturing method according to the first embodiment of the invention will be described.

FIGS. 1A and 1B are cross sectional views of the peripheral area of via holes of a semiconductor device of the first embodiment. FIG. 1C is a schematic plan view of an inspection pattern for hole opening. The cross sectional views taken along one-dot chain line A<b>1</b>—A<b>1</b> of FIG. 1C correspond to FIGS. 1A and 1B. Processes up to the state shown in FIG. 1A will be described.

On an interlayer insulating film <b>1</b> made Of SiO₂, an etching stopper film <b>2</b> of SiN having a thickness of 50 nm is formed by plasma CVD (plasma enhanced chemical vapor deposition). On the etching stopper film <b>2</b>, a wiring layer insulating film <b>3</b> of SiO₂having a thickness of 500 nm is formed by plasma CVD.

On the surface of the wiring layer insulating film <b>3</b>, a resist film is formed and openings corresponding to wiring grooves <b>4</b> are formed through the resist film. By using this resist film as a mask, the wiring layer insulating film <b>3</b> is dry-etched by using CF-containing etching gas, this etching being stopped at the etching stopper film <b>2</b>. Wiring grooves <b>4</b> are therefore formed through the wiring layer insulating film <b>3</b>. After the resist film is removed, the etching stopper film <b>2</b> exposed on the wiring grooves <b>4</b> is dry-etched by using CHF-containing etching gas.

A barrier metal layer <b>5</b>A of Ta having a thickness of 30 nm is formed by sputtering, covering the inner surfaces of the wiring grooves <b>4</b> and the upper surface of the wiring layer insulating film <b>3</b>. A seed layer of copper (Cu) having a thickness of 200 nm is formed on the upper surface of the barrier metal layer <b>5</b>A by sputtering. Cu is plated on the seed layer to a thickness of 1500 nm. The inside of each wiring groove <b>4</b> is therefore filled with main wiring material <b>5</b>B of copper. Chemical mechanical polishing (CMP) is performed until the upper surface of the wiring layer insulating film <b>3</b> is exposed. An inspection wiring pattern <b>5</b> for hole opening made of the barrier metal layer <b>5</b>A and main wiring material <b>5</b>B is therefore left in the wiring grooves <b>4</b>.

The wiring pattern <b>5</b> is constituted, for example as shown in FIG. 1C, of three wiring lines disposed in parallel. The three wiring lines are continuous with a pad <b>15</b> formed in the same wiring layer insulating film. The pad <b>15</b> is formed at the same time when the wiring pattern <b>5</b> is formed.

On the wiring layer insulating film <b>3</b>, an etching stopper film <b>10</b> of SiN having a thickness of 50 nm is formed by plasma CVD. On the etching stopper film <b>10</b>, an interlayer insulating film <b>11</b> of SiO₂having a thickness of 1200 nm is formed by plasma CVD. CMP is performed to planarize the surface of the interlayer insulating film <b>11</b>. The thickness of the interlayer insulating film <b>11</b> after planarization is set, for example, to about 800 nm.

A resist film is formed on the interlayer insulating film <b>11</b>, and openings corresponding to via holes <b>12</b> are formed through the resist film. By using this resist film as a mask, the interlayer insulating film <b>11</b> is dry-etched by using CF-containing gas, this etching being stopped at the etching stopper film <b>10</b>. Via holes <b>12</b> for inspection for hole opening are therefore formed through the interlayer insulating film <b>11</b>. The resist film is thereafter removed.

The etching stopper film <b>10</b> exposed on the bottoms of the via holes <b>12</b> is dry-etched by using CHF-containing gas to expose upper partial surfaces of the wiring layer insulating film <b>3</b> and wiring pattern <b>5</b> on the bottoms of the via holes <b>12</b>. As shown in FIG. 1C, the via holes <b>12</b> are disposed in a matrix shape of three rows and three columns. Three rows of the via holes <b>12</b> correspond to three wiring lines <b>12</b>.

In an ideal state without any alignment shift, the via holes <b>12</b> in the center row are disposed inside the center wiring line <b>5</b>, and the via holes in the uppermost and lower most rows are slightly shifted from the corresponding wiring lines <b>5</b> and the edges of the corresponding wiring lines <b>5</b> pass through the bottom areas of the via holes <b>12</b>. With this layout, even if there is an alignment shift between the wiring lines <b>5</b> and via holes <b>12</b>, the edge of the wiring line <b>5</b> passes through the bottom areas of the via holes in the corresponding row.

The bottom of the via hole <b>12</b> was observed with an SEM and the edge of the wiring line <b>5</b> was able to be detected clearly. This may be ascribed to that since the wiring pattern <b>5</b> is connected to the pad <b>15</b> having a large area, most of electrons radiated to the wiring pattern <b>5</b> during the observation with SEM are flowed into the pad <b>15</b> and charges can be suppressed from being accumulated in the wiring pattern <b>5</b>.

In order to suppress charges from being accumulated in the wiring pattern <b>5</b>, it is not necessarily required that the wiring pattern be connected to the pad <b>15</b> in the same wiring layer, but the wiring pattern <b>5</b> may be connected to a large conductive region in the same wiring layer or in the lower layer. In order to sufficiently suppress charges from being accumulated in the wiring pattern <b>5</b>, this conductive region has preferably an area larger than at least the wiring pattern <b>5</b>. In addition to the pad, the conductive region includes a semiconductor substrate itself, an antimoisture ring disposed in the chip peripheral area, a conductive region formed at the same time when the gate electrode is formed on the semiconductor substrate. Embodiments for these cases will be later described.

After it is confirmed through the inspection for hole opening that the wiring pattern <b>5</b> is exposed on the bottoms of the via holes <b>12</b>, the next process is executed. At the next process, as shown in FIG. 1B, conductive plugs <b>16</b> are filled in the via holes <b>12</b>. The conductive plug <b>16</b> is made of a barrier metal layer <b>16</b>A and main conductive material <b>16</b>B. The conductive plug <b>16</b> is formed by a method similar to the method of forming the wiring pattern <b>5</b>.

In the first embodiment, the bottom of the via hole <b>12</b> is observed with SEM. Instead, it may be observed with an apparatus for obtaining image information by utilizing an intensity distribution of secondary electrons or reflection electrons of a specimen.

FIGS. 2A and 2B are plan views of semiconductor devices according to modifications of the first embodiment. Cross sectional views taken along one-dot chain line A<b>1</b>—A<b>1</b> shown in FIGS. 2A and 2B are the same as the cross sectional view of the first embodiment shown in FIG. <b>1</b>A.

As shown in FIG. 2A, a plurality of via holes <b>30</b> are formed inside the pad <b>15</b>. Similar to the via holes <b>12</b> shown in FIG. 1A, the via holes <b>30</b> are formed through the interlayer insulating film <b>11</b> and etching stopper film <b>10</b> to expose the upper surface of the pad <b>15</b>. An upper layer pad is formed on the interlayer insulating film <b>11</b>. The upper layer pad is electrically connected to the lower layer pad <b>15</b> via conductive plugs embedded in the via holes <b>30</b>.

In the modification shown in FIG. 2B, via holes <b>31</b> are also formed in a via layer insulating film under the pad <b>15</b>. The pad <b>15</b> is electrically connected to a lower layer pad via conductive plugs embedded in the via holes <b>31</b>.

If the wiring pattern <b>5</b> is connected not only to the pad <b>15</b> formed in the wiring layer but also to a lower layer pad, accumulation of charges in the wiring pattern <b>5</b> can be reduced further.

With reference to FIGS. 3A to <b>3</b>C, another modification of the first embodiment will be described. FIG. 3A is a plan view showing the peripheral area of a via hole, and FIG. 3B is a cross sectional view taken along one-dot chain line B<b>3</b>—B<b>3</b> shown in FIG. 3B. A pad <b>15</b> is connected to a wiring pattern <b>5</b>. A via hole <b>12</b> is formed through an interlayer insulating film disposed on the wiring pattern <b>5</b>. A wiring groove <b>13</b> inclusive of the via hole <b>12</b> as viewed in plan is formed in the interlayer insulating film <b>11</b> to the intermediate depth thereof. In the plan view shown in FIG. 3A, the edge of the wiring pattern <b>5</b> passes through the bottom area of the via hole <b>12</b>.

FIG. 3C is a SEM photograph showing the bottom of the via hole <b>12</b>. It can be seen that the edge of the wiring pattern <b>5</b> can be detected clearly.

FIG. 4 is a plan view of an inspection pattern for hole opening of a semiconductor device according to the second embodiment. Three wiring lines <b>5</b>, a pad <b>15</b>, and via holes disposed in a matrix shape of three rows and three columns have the structure similar to the first embodiment shown in FIG. <b>1</b>A. In the second embodiment, a plurality of dummy wiring lines <b>5</b><i>a </i>are disposed on both sides of and in parallel to the three wiring lines <b>5</b>. The dummy wiring lines <b>5</b><i>a </i>are electrically isolated and are not connected to a conductive region.

The wiring lines <b>5</b> and dummy wiring lines <b>5</b><i>a </i>are uniformly distributed in an inspection wiring region <b>20</b>. Since a plurality of wiring lines are distributed at a high density, after CMP for forming the wiring lines <b>5</b>, a depression called erosion is formed on the upper surface layer of the wiring layer insulating film <b>3</b> shown in FIG. 1A in the inspection wiring region <b>20</b>. Since the interlayer insulating film <b>11</b> on the wiring layer insulating film <b>3</b> is planarized, the interlayer insulating film <b>11</b> on the wiring lines <b>5</b> is thicker corresponding in amount to a depth of the depression.

In the second embodiment, even if the thickness of the interlayer insulating film <b>11</b> becomes irregular because of erosion, highly reliable inspection for hole opening is possible. In order to positively utilize erosion in the inspection wiring region <b>20</b>, an area of the wiring lines in the inspection wiring region <b>20</b> is preferably set to 25% or higher of the area of the inspection wiring region <b>20</b>. For example, the width W<b>1</b> of each of the wring lines <b>5</b> and dummy wiring lines <b>5</b><i>a </i>is set to 0.2 μm and a distance between wiring lines is set to 0.6 μm.

If a depression to be formed by erosion is to be made deeper, for example, the wiring width W<b>1</b> and distance S<b>1</b> are both set to 1 μm, and the area of wiring lines in the inspection wiring region <b>20</b> is set to about 50% of the area of the inspection wiring region <b>20</b>. The ratio of the area of wiring lines in the inspection wiring region <b>20</b> is set generally equal to the ratio of the area where opening is most difficult to be formed in a chip, i.e., the area of wirings where the deepest depression is formed by erosion. With this setting, it is possible to judge the state of openings in the whole area of the chip through the inspection for hole opening in the inspection wiring region <b>20</b>.

FIGS. 5A and 5B are a cross sectional view and a plan view showing a semiconductor device according to the third embodiment FIG. 5A corresponds to the cross sectional view taken along one-dot chain line A<b>5</b>—A<b>5</b> shown in FIG. <b>5</b>B.

In the first embodiment, the wiring pattern <b>5</b> is connected to the pad <b>15</b> as shown in FIG. <b>1</b>C. In the third embodiment, a wiring pattern <b>5</b> is connected to an antimoisture ring <b>16</b>. The antimoisture ring <b>16</b> is formed by the same process as that of forming the wiring pattern <b>5</b>, and extends one turn along the outer peripheral area of the chip. The layout of the wiring pattern <b>5</b> and via holes <b>12</b> is similar to that of the semiconductor device of the first embodiment shown in FIGS. 1A and 1B.

An antimoisture ring groove <b>17</b> is formed through an interlayer insulating film <b>11</b> and an etching stopper film <b>10</b>. The antimoisture ring groove <b>17</b> is formed by the same process as that of forming the via holes <b>12</b>, and disposed on the underlying antimoisture ring <b>16</b>.

In the third embodiment, the antimoisture ring <b>16</b> suppresses accumulation of charges in the wiring pattern <b>5</b>, similar to the pad <b>15</b> of the first embodiment. It is therefore easy to perform inspection for hole opening.

FIGS. 6A and 6B are a cross sectional view and a plan view showing a semiconductor device according to the fourth embodiment. FIG. 6A corresponds to the cross sectional view taken along one-dot chain line A<b>6</b>—A<b>6</b> shown in FIG. <b>6</b>B.

As shown in FIG. 6A, on the surface of a silicon semiconductor substrate <b>25</b>, an element separation insulating region <b>26</b> is formed by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). An etching stopper film <b>27</b> of SiN covers the surface of the substrate <b>25</b>. An interlayer insulating film <b>1</b> of SiO₂is formed on the etching stopper film <b>27</b>. The layers above the interlayer insulating film <b>1</b> have the same structure as that of the semiconductor device of the third embodiment shown in FIG. <b>5</b>A.

An antimoisture ring <b>28</b> is embedded in a groove formed through the interlayer insulating film <b>1</b> and etching stopper film <b>27</b>. The antimoisture ring <b>28</b> is constituted of a barrier metal layer <b>28</b>A of TiN covering the inner surface of the groove and a main conductive member <b>28</b>B of tungsten filling the inside of the groove. The antimoisture ring <b>28</b> electrically connects the wiring pattern <b>5</b> to the substrate <b>25</b>. Since the wiring pattern <b>5</b> is connected to the substrate <b>25</b>, it is possible to prevent accumulation of charges in the wiring pattern <b>5</b>. Instead of connecting the wiring pattern <b>5</b> to the substrate via the antimoisture ring <b>28</b>, it may be connected to the substrate via a usual conductive plug.

FIG. 7 is a cross sectional view showing a semiconductor device according to the fifth embodiment. On the surface of a semiconductor substrate <b>25</b>, an element separation insulating region <b>35</b> is formed to define active regions. The active region is formed in a p-type or n-type well.

A lamination structure is formed on an upper partial surface of the active region, the lamination structure having three layers including an SiO₂film <b>36</b>, a polysilicon film <b>37</b> and a silicide film <b>38</b> of TiSi or CoSi. On the side walls of the lamination structure, side wall spacers <b>29</b> of SiO₂are formed. The SiO₂film <b>36</b> and polysilicon film <b>37</b> are formed at the same time when the gate insulating film and gate electrode of a MOSFET disposed in another area of the semiconductor substrate are formed. The silicide film <b>38</b> is formed by a well-known salicide (self aligned silicide) process.

In the surface layer of the semiconductor substrate <b>25</b> on both sides of the lamination structure, impurity doped regions <b>41</b> are formed. The impurity doped region <b>41</b> can be formed by the same process as that of implanting ions for the source and drain regions of MOSFET. The upper surface of the impurity doped region <b>41</b> is covered with a silicide film <b>42</b> of TiSi or CoSi. The silicide film <b>42</b> is formed at the same time when the silicide film <b>38</b> is formed.

An etching stopper film <b>27</b> of SiN is formed on the semiconductor substrate <b>25</b>, covering the lamination structure. On this etching stopper film <b>27</b>, an interlayer insulating film <b>1</b> of SiO₂is formed. The structure above the interlayer insulating film <b>1</b> is similar to that of the semiconductor device of the third embodiment shown in FIG. <b>5</b>A.

Via holes exposing partial surface areas of the silicide film <b>38</b> are formed through the interlayer insulating film <b>1</b>, and conductive plugs <b>40</b> are embedded in the via holes. The conductive plug <b>40</b> is constituted of a barrier metal layer <b>40</b>A of TiN covering the inner surface of the via hole and a main conductive member <b>40</b>B of tungsten filling the inside of the via hole. The conductive plugs <b>40</b> connect the wiring pattern <b>5</b> to the silicide film <b>38</b>. The wiring pattern <b>5</b> is therefore electrically connected to the polysilicon film <b>37</b>. The polysilicon film <b>37</b> and semiconductor substrate <b>25</b> sandwich the SiO₂film <b>36</b>, constituting a capacitor.

In the fourth embodiment shown in FIG. 6A, the wiring pattern <b>5</b> is electrically connected directly to the semiconductor substrate <b>25</b>. In the fifth embodiment, the wiring pattern <b>5</b> is connected to the semiconductor substrate <b>25</b> via the capacitor constituted of the polysilicon film <b>37</b> and semiconductor substrate <b>25</b>.

When the bottoms of via holes <b>12</b> are observed with SEM, most of electrons incident upon the wiring pattern are accumulated in the capacitor constituted of the polysilicon film <b>37</b> and semiconductor substrate <b>25</b>. It is therefore possible to reduce the amount of charges to be accumulated in the wiring pattern <b>5</b>.

In the first to fifth embodiments described above, the wiring line and via hole are disposed so that the edge of the wiring line passes through the bottom area of the via hole as viewed along a line parallel to the normal to the substrate. If a wiring line is wide, it is difficult to perform highly reliable inspection for hole opening in the manner described above. This difficulty will be explained in the following.

As shown in FIG. 8, in a wiring layer insulating film <b>50</b>, fine wiring lines <b>51</b><i>a </i>and a wide wiring line <b>51</b><i>b </i>are embedded. CMP for forming wiring lines forms a depression in the upper surface layer of the wide wiring line <b>51</b><i>b</i>. An etching stopper film <b>52</b> and a via layer insulating film <b>53</b> are formed in this order on the wiring lines <b>51</b><i>a </i>and <b>51</b><i>b </i>and wiring layer insulating film <b>50</b>.

The surface of the via layer insulating film <b>53</b> is planarized by CMP. Therefore, the via insulating film <b>53</b> is thicker above the central area of the wide wiring line <b>51</b><i>b</i>. Even if it is confirmed, by inspection for hole opening through a via hole <b>54</b><i>a </i>disposed overlapping the edge of the wide wiring line <b>51</b><i>b</i>, that the wiring line <b>51</b><i>b </i>is exposed, it is not possible to guarantee that a via hole <b>54</b><i>b </i>disposed in the central area of the wiring line <b>51</b><i>b </i>reaches the upper surface of the wiring line <b>51</b><i>b</i>. A chip may have the structure that a via hole is disposed in the central area of the wide wiring line. High reliability is not guaranteed for an inspection for hole opening using only the via hole <b>54</b><i>a </i>overlapping the edge of the wide wiring line <b>51</b><i>b</i>. In the sixth embodiment to be described in the following, highly reliable inspection for hole opening is possible even if a via hole is disposed in the central area of a wide wiring line.

FIG. 9A is a cross sectional view of a semiconductor device according to the sixth embodiment, and FIG. 9B is a plan view thereof. FIG. 9A corresponds to the cross sectional view taken along one-dot chain line A<b>9</b>—A<b>9</b> shown in FIG. <b>9</b>B. The cross sectional structure shown in FIG. 9A is almost similar to that of the semiconductor device of the first embodiment shown in FIG. <b>1</b>A. In the first embodiment, the wiring line has such a width as a depression is not formed on the upper surface thereof. In the sixth embodiment, since a wiring pattern <b>5</b> is wide, a depression is formed on the upper surface thereof.

Insulating regions <b>3</b><i>a </i>formed by partially leaving a wiring layer insulting film <b>3</b> are disposed in the wide wiring pattern <b>5</b>. The wiring pattern <b>5</b> surrounds the insulating region <b>3</b><i>a</i>. In the example shown in FIG. 9B, three insulating regions <b>3</b><i>a </i>are disposed along a longitudinal direction of the wiring pattern <b>5</b>. The insulating regions <b>3</b><i>a </i>are shifted from each other along a width direction of the wiring pattern <b>5</b>. It is preferable to form the insulating regions <b>3</b><i>a </i>in an area where the depression is deepest.

A via hole <b>12</b> is disposed in correspondence to each of the insulating regions <b>3</b><i>a</i>. The three via holes <b>12</b> are disposed at the same position along the width direction of the wiring pattern <b>5</b>. As viewed along a line parallel to the normal to the substrate surface, at least one of the via holes <b>3</b><i>a </i>overlaps the edge of the corresponding insulating region <b>3</b><i>a</i>. The wide wiring pattern <b>5</b> is connected to a pad <b>15</b>, similar to the first embodiment shown in FIGS. 1A to <b>1</b>C.

Since the via hole reaches the wiring pattern <b>5</b>, a boundary line between the wiring pattern <b>5</b> and insulating region <b>3</b><i>a </i>appears on the bottom of the via hole <b>12</b>. Inspection for hole opening is possible by observing the boundary line with SEM. The via hole <b>12</b> for inspection for hole opening passes through the thick region of the interlayer insulating film <b>11</b> on the wiring pattern <b>5</b>. Highly reliable inspect ion for hole opening is therefore possible.

The positional relations between the insulating regions <b>3</b><i>a </i>and via holes <b>12</b> of three pair s are different along the width direction of the wiring pattern <b>5</b>. Therefore, even if there is some alignment error, inspection for hole opening is possible by using one of the three pairs.

Next, with reference to FIGS. 10A to <b>10</b>H, a method of manufacturing a semiconductor device having an inspection pattern for hole opening of one of the embodiments will be described.

As shown in FIG. 10A, an etching stopper film <b>112</b> is formed on an underlying layer <b>111</b>, and a wiring layer insulating film <b>113</b> is formed on the etching stopper film <b>112</b>. For example, after MOSFET's are formed in active regions of a semiconductor wafer, an insulating film is formed on the wafer, and the underlying layer <b>111</b> has the structure that conductive plugs are embedded in the insulating film or the structure that conductive plugs are embedded in an upper via layer insulating film above the insulating film.

For example, the etching stopper film <b>112</b> is made of SiN having a thickness of 50 nm. The SiN film has an etching stopper function and a Cu diffusion prevention function. The wiring layer insulating film <b>113</b> is made of, for example, SiO₂having a thickness of 500 nm. On the surface of the wiring layer insulating film <b>113</b>, a resist film <b>114</b> is formed having an opening corresponding to a wiring pattern.

By using the resist film <b>114</b> as an etching mask, the wiring layer insulating film <b>113</b> is etched by reactive ion etching (RIE) using CF-containing etching gas. This etching is stopped at the etching stopper film <b>112</b>. Thereafter, the resist film <b>114</b> is removed by ashing using oxygen plasma. During this ashing, the underlying layer <b>111</b> is covered with the etching stopper film <b>112</b> so that the surface of conductive members in the underlying layer <b>111</b> can be prevented from being oxidized. The etching stopper film <b>112</b> exposed on the bottoms of grooves formed through the wiring layer insulating film <b>113</b> is removed by RIE using CHF-based etching gas. With the above processes, wiring grooves are formed.

Via holes for inspection for hole opening of one of the first to sixth embodiments are formed through the wiring layer insulating film <b>113</b> and etching stopper film <b>112</b>, to perform inspection for hole opening.

As shown in FIG. 10B, a barrier metal layer <b>115</b> and a main wiring layer <b>116</b> are formed on the structure with the wiring grooves. For example, the barrier metal layer <b>115</b> is made of Ta having a thickness of 30 nm, by sputtering, and the main wiring layer <b>116</b> is made of Cu by sputtering or plating. If the main wiring layer <b>116</b> is formed by plating, a Cu seed layer is first formed by sputtering and then Cu is plated on the Cu seed layer.

After the barrier metal layer <b>115</b> and main wiring layer <b>116</b> are formed, CMP is performed to remove the main wiring layer <b>116</b> and barrier metal layer <b>115</b> above the upper surface of the wiring layer insulating film <b>113</b>.

As shown in FIG. 10C, the wiring lines made of the barrier metal layer <b>115</b> and main wiring layer <b>116</b> are therefore left in the wiring grooves formed through the wiring layer insulating film <b>113</b>. At this time, a wiring pattern <b>5</b> for inspection for hole opening is also formed. The inspection wiring pattern <b>5</b> for hole opening may be disposed in the chip or on the scribe line. On the wiring layer insulating film <b>113</b>, an etching stopper film <b>117</b> of the second layer is formed. For example, the etching stopper film <b>117</b> is made of SiN having a thickness of 50 nm. On the etching stopper film <b>117</b>, a via layer insulating film <b>118</b> is formed. For example, the via layer insulating film <b>118</b> is made of SiO₂having a thickness of 1200 nm.

After the via layer insulating film <b>118</b> is formed, CMP is performed to planarize the upper surface of the via layer insulating film <b>118</b>. After planarization of the via layer insulating film <b>118</b>, an etching stopper layer <b>119</b> of the third layer and a wiring layer insulating film <b>120</b> are formed. For example, the etching stopper film <b>119</b> is made of SiN having a thickness of 50 nm, and the wiring layer insulating film <b>120</b> is made of SiO₂having a thickness of 500 nm. A resist film <b>121</b> having via hole openings is formed on the wiring layer insulating film <b>120</b>.

By using the resist film <b>121</b> as an etching mask, the wiring layer insulating film <b>120</b>, etching stopper film <b>119</b> and via layer insulating film <b>118</b> are etched by using CF-containing etching gas, CHF-containing etching gas or the like. By controlling the etching conditions, the etching is stopped on the surface of the etching stopper film <b>117</b>. The resist mask <b>121</b> is removed by ashing using oxygen plasma. Via holes reaching the etching stopper film <b>117</b> are therefore formed. At this time, via holes <b>12</b> for inspection for hole opening are also formed.

As shown in FIG. 10D, non-photosensitive resin is coated on the surface of the wiring layer insulating film <b>120</b>, and the resin is melted from its surface to leave fillers <b>122</b> only in the via holes. Thereafter, a resist film <b>123</b> having openings corresponding to wiring lines is formed on the surface of the wiring layer insulating film <b>120</b>.

By using the resist film <b>123</b> as an etching mask, the wiring layer insulating film <b>120</b> is etched by RIE using CF-containing gas. This etching stops on the surface of the etching stopper film <b>119</b>. Wiring grooves are therefore formed through the wiring layer insulating film <b>120</b>.

As shown in FIG. 10E, the resist film <b>122</b> is removed by ashing using oxygen plasma. At this time the fillers <b>122</b> of non-photosensitive resin are also removed. The etching stopper films <b>119</b> and <b>117</b> are exposed on the bottoms of the wiring grooves and via holes.

As shown in FIG. 10F, the exposed etching stopper films <b>119</b> and <b>117</b> are removed by RIE using CHF-containing etching gas. In this state, the bottom of the via hole <b>12</b> for inspection for hole opening is observed to perform inspection for hole opening.

As shown in FIG. 10G, a barrier metal layer <b>124</b> is formed covering the upper surface of the wiring layer insulating film <b>120</b> and the inner surfaces of the wiring grooves and via holes, and a main wiring layer <b>125</b> is formed on the barrier metal layer <b>124</b>. The barrier metal layer <b>124</b> and main wiring layer <b>125</b> are formed by the method similar to that of forming the lower barrier metal layer <b>115</b> and main wiring layer <b>116</b>. The barrier metal layer <b>124</b> and main wiring layer <b>125</b> deposited above the upper surface of the wiring layer insulating film <b>120</b> are removed by CMP.

As shown in FIG. 10H, the surface planarized by CMP is covered with an etching stopper film <b>126</b> of the fourth layer. The wiring <b>125</b> of a dual damascene structure is therefore formed.

In the embodiment method shown in FIGS. 10A to <b>10</b>H, the inspection pattern for hole opening of one of the embodiments is applied to the dual damascene structure. The inspection pattern for hole opening may be applied to a single damascene structure.

FIG. 11 is a cross sectional view showing an example of a semiconductor device having a damascene multi-layer wiring structure. An element separation trench is formed in a predetermined area of a semiconductor wafer <b>201</b> having wells, and insulating material such as silicon oxide is filled in the element separation trench to form an element separation insulating region <b>204</b> through shallow trench isolation (STI).

In the active region defined by the element separation insulating region <b>204</b>, an insulated gate electrode <b>205</b> and side wall spacers <b>206</b> are formed. Source/drain regions S/D are formed on both sides of the insulated gate electrode <b>205</b> through ion implantation. A first etching stopper film <b>210</b> is formed covering the insulated gate electrode <b>205</b>, and a first lower insulating film <b>211</b> is formed on the first etching stopper film. Conductive plugs made of a barrier metal layer <b>207</b> and wiring metal region <b>208</b> are formed through the first lower insulating film <b>211</b> and first etching stopper film <b>210</b>.

An organic insulating film <b>212</b> and a first upper insulating film <b>213</b> are formed on the first lower insulating film <b>211</b>. If the organic insulating film is a coating type, it has a planarization function so that a flat surface can be obtained without performing CMP. First wiring lines <b>209</b> are embedded in wiring grooves formed through the first upper insulating film <b>213</b> and organic insulating film <b>212</b>.

A second etching stopper film <b>220</b> and a second lower insulating film <b>221</b> are formed on the surface of the first wiring lines <b>209</b>, and CMP is performed for planarization. On the second lower insulating film <b>221</b>, a second organic film <b>222</b> and a second upper insulating film <b>223</b> are formed to form a dual damascene wiring structure <b>224</b>.

Similarly, a third etching stopper film <b>230</b> and a third lower insulating film <b>231</b> are formed on the surface of the second upper insulating film <b>223</b>, and CMP is performed for planarization. On the third lower insulating film <b>231</b>, a third organic film <b>232</b> and a third upper insulating film <b>233</b> are formed to form a second dual damascene wiring structure <b>234</b>.

A fourth etching stopper film <b>240</b> and a fourth lower insulating film <b>241</b> are formed on the surface of the third upper insulating film <b>233</b>, and CMP is performed for planarization. On the fourth lower insulating film <b>241</b>, a fourth organic film <b>242</b> and a fourth upper insulating film <b>243</b> are formed to form a third dual damascene wiring structure <b>244</b>. A surface protective film <b>250</b> is formed over the multi-layer wiring structure.

Inspection for hole opening of the embodiment is performed after the process of forming via holes through each layer of the multi-layer structure.

Although the multi-layer wiring structure of four layers has been described, the number of wring layers may be increased or decreased as desired. In place of the lamination of an organic insulating film and an upper insulating film, a lamination of an etching stopper film and an insulating film may also be used. A lamination structure having a low dielectric constant insulating film such as a silicon oxide film containing fluorine or carbon and a porous silicon oxide film may be used.

The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It is apparent that various modifications, improvements, combinations, and the like can be made by those skilled in the art.