Method of forming spacers in CMOS devices

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates a semiconductor fabrication technique, and in particular to a method of forming spacers in CMOS devices.

2. Description of the Prior Art

In the fabrication of CMOS devices, a polysilicon gate is typically deposited over a gate oxide grown on the silicon substrate. Ion implantation occurs through the field oxide located between the gates. In order to protect the gate region during the implantation step, the side walls of the gates are protected with vertical walls known as spacers. In the past, amorphous silicon was used for the spacers, but this created problems during subsequent etching in that it was difficult to avoid over-etching and the removal of part of the underlying layer. Over-etching occurs when etching extends into the underlying layer. Often when the spacers were removed, a polysilicon gate would be etched at the same time leaving a notch, known as a “mouse bite” in the polysilicon gate.

An object of the invention is to alleviate this problem.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, the side wall spacers are made of silicon nitride. Silicon nitride has the advantage of offering good selectivity, making it easy to avoid over-etching when the precursor conformal layer is removed.

In accordance with an important aspect of the invention, a conformal silicon nitride layer is etched using a chlorine-based plasma etch chemistry. Such etch chemistry consists of chlorine (Cl₂), hydrogen bromide (HB_r), and a mixture of helium and oxygen. This is in contrast to the conventional CHF₃chemistry, which is normally used for silicon nitride etching. The applicants have found that using conventional silicon nitride etch chemistry, it is very difficult to avoid over-etching into the gate oxide because of the high plasma power and the limited oxide/nitride selectivity of 1.8 to 1.

In accordance with the present invention, it has been found surprisingly that oxide/nitride selectivities in the order of 3 to 1 can be achieved, which completely protects the gate oxide. In the invention the etching is caused largely by chemical rather than the mechanical interaction associated with CHF₃plasmas. The Cl₋ radicals etch the silicon nitride chemically and the HBr component is responsible mainly for mechanical etching by the plasma. The reaction of HBr with silicon nitride also creates a protective polymer layer that protects the more vertical profiles of the etched films, resulting in a more anisoptropic etch. Some spacers are left along the polysilicon lines with a rounded shape.

While the etch rate using chlorine-based etch chemistry, typically around 2000 Angstroms per minute, is somewhat slower than CHF₃—based chemistry, typically around 5000 Angstroms per minute, this trade-off is more than offset by the improvement in selectivity obtainable.

The conformal nitride layer is preferably deposited onto a thin oxide layer, typically about 200 Angstroms thick.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings in which:

FIGS. 1 to <b>4</b> show successive steps in the manufacture of a CMOS device in accordance with the principles of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings, the CMOS device comprises a silicon substrate <b>10</b>. First, as shown in FIG. 1, a silicone nitride layer (not shown) is deposited on the substrate and then patterned to leave regions of exposed silicon. The wafer is then exposed to an oxidizing atmosphere to grow field oxide layer <b>12</b> in a conventional manner. After removal of the nitride layer, gate oxide <b>14</b> is grown between the field oxide regions <b>12</b>.

After growing the gate oxide <b>14</b>, a polysilicon layer is grown and subsequently patterned to form polysilicon gates <b>16</b> on gate oxide <b>14</b> (FIG. <b>2</b>).

Typically, after the patterning of the polysilicon gate <b>16</b>, a first ion implantation takes place to form source and drain active regions <b>15</b>.

Next, an oxidation step takes place (FIG. 3) to grow a thin silicon oxide layer <b>17</b>, which is typically about 200 Angstroms thick.

In the next step, a conformal silicon nitride layer <b>18</b> is deposited over the surface of the wafer using LPCDV (Low Pressure Chemical Vapor Deposition). The objective is to remove the silicon nitride layer <b>18</b> except for the vertical side wall portions <b>20</b> protecting the polysilicon gates <b>16</b> by etching down to the thin oxide layer <b>17</b>. The remaining side wall portions <b>20</b> forming the spacers slightly rounded as shown. The removal of the horizontal portions of the silicon nitride layer without effecting the underlying layers requires good nitride/oxide selectivity and also good anisotropy to avoid lateral etching into the side walls <b>20</b>.

In accordance with the principles of the invention, the anisotropic etch is performed using an etch recipe comprising chlorine (Cl₂), hydrogen bromide (HB_r) and a mixture of helium and oxygen. The etch is performed as an reactive ion etch using a magnetic field to ensure good uniformity on the wafer. The preferred etch variables are set out in the following table:

<tables><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="91pt" align="left" /><colspec colname="2" colwidth="56pt" align="left" /><colspec colname="3" colwidth="56pt" align="left" /><thead><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row><row><entry /><entry>Step</entry><entry>Main Etch</entry><entry>Over Etch</entry></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>Pressure</entry><entry> 150 mTorr</entry><entry>100 mTorr</entry></row><row><entry /><entry>Power</entry><entry> 325 Watts</entry><entry>150 Watts</entry></row><row><entry /><entry>Magnetic field</entry><entry> 75 Gauss</entry><entry> 75 Gauss</entry></row><row><entry /><entry>HBr flow</entry><entry> 10 Sccm</entry><entry> 10 Sccm</entry></row><row><entry /><entry>Cl₂flow</entry><entry> 30 Sccm</entry><entry> 15 Sccm</entry></row><row><entry /><entry>He/O₂flow</entry><entry>  0 Sccm</entry><entry> 10 Sccm</entry></row><row><entry /><entry>Nitride Etch rate</entry><entry>2063 Å/min.</entry><entry>480 Å/min.</entry></row><row><entry /><entry>Nitride Etch uniformity</entry><entry>0.96%</entry><entry>11.3%</entry></row><row><entry /><entry>Oxide Etch rate</entry><entry> 680 Å/min.</entry><entry> 30 Å/min.</entry></row><row><entry /><entry>Oxide Etch uniformity</entry><entry>3.7%</entry><entry>23.0%</entry></row><row><entry /><entry>Nitride to Oxide</entry><entry>3:1</entry><entry>16.5:1</entry></row><row><entry /><entry namest="OFFSET" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

The etch is formed in two steps: the main etch and the over-etch. It will be noted that in the main etch, nitride/oxide selectivities of 3 to 1 are achieved, and in the over-tech, to remove any remaining nitride layer, selectivities as high as 16.5 to 1 are achieved.

The etch endpoint is detected using optical methods by detecting the chlorine spectral line at 4705 Å. At this point, the chlorine stops being consumed, so by looking at the chlorine spectral line at 470.5 nm, it is possible to determine when the silicon nitride has been completely etched.

Finally, a second polysilicon layer is deposited over the wafer and selectively etched so that the second layer lies over the polysilicon gates <b>18</b>.

Next ion implantation is carried out through the thin oxide layer to form active components, such as transistors. Typically, N+ and P+ species are implanted, and in accordance with the principles of the invention, these are implanted directly through the thin oxide layer <b>17</b>, which is left in situ.

The use of silicon nitride spacers has several advantages. It gives more flexibility in the etching techniques that can be used for the adjacent films. It permits good control of conformability to the wafer surface, and the good selectivity permits the avoidance of over-etching of the underlying layer.

This is important because the silicon nitride layer is about 3,000-4,000 Å thick.

It is indeed surprising, but highly significant, that the use of an etch recipe typically applied to polysilicon improves the selectivity and anisotropy of a silicon nitride etch, a fact that leads to a major improvement in the fabrication of CMOS devices.