US6535385B2

High performance heat sink configurations for use in high density packaging applications

Summary by NHIP

Radial Fin Heat Dissipation Device

The device extracts heat from an integrated circuit using a thermally conductive core with concentric upper and lower outer surface areas. Radially extending fin arrays couple to these surfaces, where the lower array features a second outer diameter smaller than the first to allow component mounting below.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

An enhanced heat dissipation device to extract heat from an integrated circuit device includes a thermally conductive core having upper and lower outer surface areas. The device further includes a first array of radially extending pin fin structures. The first array is thermally coupled to the upper surface area such that a cooling medium introduced around the core and the first array creates an omni-directional flow around the first array and the core to enhance heat dissipation from the integrated circuit device. The core including the first array and the lower surface area are of sufficient size to allow components on a motherboard to encroach onto the integrated circuit device when the heat dissipation device is mounted onto the integrated circuit device.

US6535385B2, drawing sheet 1 — Sheet 1 of 13

Term

Term ended

Expired 20 November 2020, 5.8 years ago.

22 claims: 2 independent, 20 dependent

1
Broadest claimClaim Score 50, average(NHIP)A heat dissipation device comprising:a thermally conductive core, wherein the core has an axis, wherein the core has a base to mount upon an integrated circuit device, wherein the base is perpendicular to the axis, and wherein the core has upper and lower outer surface areas concentric to the axis and having first and second lengths, respectively;a first array of radially extending fin structures, the first array being thermally coupled to the upper outer surface area along the first length, wherein the first array has a first outer diameter, and a second array of radially extending fin structures, the second array being thermally coupled to the lower outer surface area along the second length, wherein the second array has a second outer diameter, the second outer diameter being less than the first outer diameter, and wherein the second length and the second outer diameter are sized to provide sufficient space below the first array to allow components to be mounted around and in close proximity to the lower outer surface area and below the first array when the base of the heat dissipation device is mounted on an integrated circuit device.
11
A heat dissipation system comprising:an integrated circuit device having a front side and a back side opposite the front side, wherein the front side is attached to a surface of a circuit board, the surface of the circuit board having components mounted thereon and projecting outwardly from the surface;and a heat dissipation device including a thermally conductive core having a base thermally coupled to the back side of the integrated circuit device, the core having an axis perpendicular to the base, and the core further having upper and lower outer surface areas concentric to the axis and having first and second lengths, respectively;a first array of radially extending fin structures, the first array being thermally coupled to the upper outer surface area along the first length, wherein the first array has a first outer diameter;and a second array of radially extending fin structures, the second array being thermally coupled to the lower outer surface area along the second length, wherein the second array has a second outer diameter, the second outer diameter being less than the first outer diameter, and wherein the second length and the second outer diameter are sized to provide sufficient space for the components around and in close proximity to the lower outer surface area and below the first array.

Independent claims2

62 paragraphs in 5 sections, as filed

This is a Continuation-in-Part of application Ser. No. 09/716,510, filed Nov. 20, 2000.

TECHNICAL FIELD

This invention relates generally to a heat dissipation system and method for an integrated circuit assembly, and more particularly to a system and method of dissipating heat from an integrated circuit device.

BACKGROUND

Integrated circuit devices, microprocessors and other related computer components are becoming more and more powerful with increasing capabilities, resulting in increasing packaging densities and amounts of heat generated from these components. Packaged units and integrated circuit device sizes of these components are decreasing or remaining the same, but the amount of heat energy given off by these components per unit volume, mass, surface area or any other such metric is increasing. In current packaging techniques, heat sinks typically consist of a flat base plate, which is mounted onto the integrated circuit device on one side. The heat sinks further include an array of fins running perpendicular to the flat base plate on the other side. Generally, the integrated circuit devices (which are the heat sources) have a significantly smaller footprint size than the flat base plate of the heat sink. The flat base plate of the heat sink has a large footprint. The large footprint requires more motherboard real estate than the integrated circuit device in contact therewith. The larger size of the base plate causes the outermost part of the base plate that is not directly in contact with the integrated circuit device to have a significantly lower temperature than the part of the base plate that is directly in contact with the integrated circuit device. This results in the outermost part of the heat sink that is not directly in contact with the integrated circuit being less efficient in dissipating heat into the cooling air.

Furthermore, as computer-related equipment becomes more powerful, more components are being placed inside the equipment and on the motherboard which further requires more motherboard real estate. In addition, the base plate of prior art heat sink designs is at the same level as the integrated circuit device to which it is attached. Consequently, the flat base plate configuration of the heat sink generally ends up consuming more motherboard real estate than the integrated circuit device on which it is mounted. As a result, the larger footprint size of the base plate prevents other motherboard components, such as low-cost capacitors, from encroaching around or on the microprocessor. Thus, the large amounts of heat produced by many of such integrated circuits, and the increasing demand for motherboard real estate need to be taken into consideration when designing the integrated circuit mounting and packaging devices.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an enhanced heat dissipation device and method that conserve motherboard real estate and allow electronic components to encroach on and around the microprocessor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an isometric view of a prior art heat sink attached to a microprocessor on an assembled motherboard.

FIG. 2 is an isometric view of one embodiment of an enhanced heat dissipation device according to the present invention.

FIG. 3 is an isometric view showing the enhanced heat dissipation device of FIG. 2 attached to a microprocessor on an assembled motherboard.

FIG. 4 is an isometric view of another embodiment of an enhanced heat dissipation device according to the present invention.

FIG. 5 is an isometric view showing the enhanced heat dissipation device of FIG. 4 attached to a microprocessor on an assembled motherboard.

FIG. 6 is an isometric view of another embodiment of an enhanced heat dissipation device according to the present invention.

FIG. 7 is an isometric view showing the enhanced heat dissipation device of FIG. 6 attached to a microprocessor on an assembled motherboard.

FIG. 8 is an isometric view of another embodiment of an enhanced heat dissipation device according to the present invention.

FIG. 9 is an isometric view of another embodiment of an enhanced heat dissipation device according to the present invention.

FIG. 10 is an isometric view of another embodiment of an enhanced heat dissipation device according to the present invention.

FIG. 11 is an isometric view of another embodiment of an enhanced heat dissipation device according to the present invention.

FIG. 12 is a diagrammatic view illustrating certain geometrical relationships among elements of an embodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description of the embodiments, reference is made to the accompanying drawings that illustrate embodiments of the present invention and its practice. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. Moreover, it is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described in one embodiment may be included in other embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the embodiments of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

This document describes, among other things, an enhanced heat dissipation device that allows electronic components to encroach around and on a microprocessor while maintaining high performance and cost effectiveness by leveraging currently enabled high-volume manufacturing techniques.

FIG. 1 shows an isometric view 100 of a prior art heat sink 110 mounted on a microprocessor 120 of an assembled motherboard 130. Also, shown in FIG. 1 are low-cost capacitors 140 mounted around the heat sink 110 and on the motherboard 130.

The prior art heat sink 100 has a flat base plate 150 including an array of fins 160 extending perpendicularly away from the flat base plate 150. This configuration of the heat sink 110 dictates the use of the flat base plate 110, with the array of fins 160 for dissipating heat from the microprocessor 120. Increasing the heat dissipation using the prior art heat sink 110 shown in FIG. 1, generally requires enlarging the surface area of the flat base plate 150 and/or the array of fins 160. This in turn results in consuming more motherboard real estate. Generally, the microprocessor 120 (which is the heat source) has a smaller footprint size than the flat base plate 150 configuration of the heat sink 110 shown in FIG. 1. A larger footprint size of the flat base plate 150 can cause the outermost part of the flat base plate 150 (the portion that is not directly in contact with the integrated circuit device) to have a significantly lower temperature than the part of the flat base plate 150 that is directly in contact with the integrated circuit device. Consequently, the prior art heat sink 110 with the larger flat base plate 150 is not effective in dissipating heat from the integrated circuit device. Furthermore, the packaged units and integrated circuit device sizes are decreasing, while the amount of heat generated by these components is increasing. The prior art heat sink 110 configuration dictates that the array of fins 160 extend to the edge of the flat base plate 150 to extract heat from the integrated circuit device. Also, the prior art heat sink 110 requires increasing the size of the array of fins 160 to increase the heat dissipation. In order to enlarge the fins 120 laterally, the flat base plate 150 has to increase in size. Enlarging the flat base plate 150 consumes more motherboard real estate. Consuming more motherboard real estate is generally not a viable option in an environment where system packaging densities are increasing with each successive, higher performance, integrated circuit device generation. Also, the prior art heat sink 110 is at the same level as the integrated circuit device on which it is mounted. It can be seen in FIG. 1, that the flat base plate 150 configuration of the prior art heat sink 110 mounted on the microprocessor 120 generally prevents other motherboard components, such as low-cost capacitors 140, from encroaching around the microprocessor 120.

FIG. 2 is an isometric view of one embodiment of the enhanced heat dissipation device 200 according to the present invention. Shown in FIG. 2 is the enhanced heat dissipation device 200 including a thermally conductive core 210, and a first array 220 of radially extending pin fin structures 222. The pin structures 222 can have cross-sectional shapes such as round, square, rectangle, elliptical, conical or any other suitable shape for dissipating heat. Also, shown in FIG. 2 is the core 210 having upper and lower outer surface areas 230 and 240. The first array 220 is thermally coupled to the upper surface area 230 of the core 210 such that a cooling medium such as air introduced around the upper and lower surface areas 230 and 240 of the core 210 and the first array 220 creates an omni-directional flow around the core 210 and the first array to enhance heat dissipation from the heat sink 200. FIG. 2 further shows an optional second array 290 of radially extending pin fin structures 292 thermally coupled to the lower surface area 240 of the core 210 such that the cooling medium introduced around the second array also creates an omni-directional flow around the second array 290. Each of the pin structures 222 and 292 can have a head to create a higher turbulent flow around the first and second arrays 220 and 290.

The core 210 has an axis 260. In some embodiments, the upper and lower surface areas 230 and 240 are parallel to the axis 260. The core 260 further has a base 270. In some embodiments, the base 270 is disposed in such a way that it is in close proximity to the lower surface area 240 and perpendicular to the axis 260. The upper and lower surface areas 230 and 240 can be concentric to the axis 260.

The first array 220 is thermally coupled to the upper surface area 230 such that components can be mounted around and in close proximity to the lower surface area 240 and below the first array 220 when the device 200 is mounted onto an integrated circuit device. In some embodiments, the components can encroach onto the integrated circuit device without mechanically interfering with the device 200.

The core 210 can be a solid body. The solid body can be cylindrical, conical, square, rectangular, or any other similar shape that facilitates in mounting onto the integrated circuit device and in attaching the first array 220 to the upper surface area 230. The core 210 can include heat transport mediums such as one or more heat pipes, a liquid, a thermo-siphon, or other such heat transport medium that enhance heat dissipation from the integrated circuit device.

In some embodiments, the first array 220 has a first outer diameter 250 (refer also to FIG. 12) and the second array 290 has a second outer diameter 255. The second outer diameter 255 is less than the first outer diameter 250. The first array 220 has a first depth (refer to FIG. 12) and the second array 290 has a second depth. The first and second outer diameters 250 and 255 including the first and second depths are of sufficient size to allow components to be mounted around and in close proximity to the integrated circuit device when the device is mounted on the integrated circuit device.

Referring again to FIG. 2, the second array 290 is thermally coupled to the lower core area 240 of the core 210 such that the cooling medium introduced around the first and second arrays 220 and 290 creates an omni-directional flow around the upper and lower surface areas 230 and 240 of the core 210 and the first and second arrays 220 and 290 to enhance heat dissipation from the heat sink 200. The device 200, including the core 210 and the first and second arrays 220 and 290, can be made from materials such as aluminum, copper, or any other materials that are capable of dissipating heat away from the integrated circuit device. The first and second arrays 220 and 290 can be formed to have outer shapes such as circular, square, rectangular, elliptical, conical or any other shape suitable for allowing components to encroach around and in close proximity to the first and second arrays 220 and 290.

FIG. 3 is an isometric view 300 showing the enhanced heat dissipation device 200 shown in FIG. 2, attached to the microprocessor 120 on an assembled motherboard 130. In the example embodiment shown in FIG. 3, the microprocessor 120 has a front side 340 and a back side 330. The front side 340 is disposed across from the back side 330. The front side 340 is attached to the assembled motherboard 130 that has components such as low-cost capacitors 140 and other such electrical components. The base 270 shown in FIG. 2, of the enhanced heat dissipation device 200, is attached to the back side 330 of the microprocessor 120. It can be seen from FIG. 3 that the first and second arrays 220 and 290 are of sufficient size so as to allow low-cost capacitors 140 mounted on the assembled board 130 to encroach around the microprocessor 120. It can also be seen that the low-cost capacitors 140 are below the first array 220 and around the second array 290.

Also, it can be seen in FIG. 3 that the first array 220 is larger than the second array 290, thereby increasing the heat dissipation rate without increasing a footprint size of the base 270 of the heat dissipation device 200 any more than the back side 330 of the microprocessor 120. The coinciding footprint sizes of the base 270 of the heat dissipation device 200 and the back side 330 of the microprocessor 120 enables the base 270 and the back side 330 of the microprocessor 120 to have the same heat transfer rates. This in turn increases the efficiency of heat transfer between the base 270 and the back side 330 of the microprocessor 120.

The core 210 further has a top surface 275 disposed across from the base 270. In some embodiments, the top surface 275 is perpendicular to the axis 260 and is in close proximity to the first array 220. A heat transport medium 350 such as a fan can be attached to the top surface 275 to introduce a heat transfer medium 297 such as air in a direction shown in FIG. 2. This creates an omni-directional flow around the core 210 and the first and second arrays 220 and 290 to enhance heat dissipation by the heat dissipation device 200. A heat transport medium 295 (refer to FIG. 2) such as a heat pipe or other such medium can be included in the core 210 to further enhance the heat transfer from the heat dissipation device 200.

In some embodiments, the enhanced heat dissipation device 200 is made of thermally conductive materials such as copper, aluminum, or any other such material capable of extracting heat away from the integrated circuit device. In some embodiments, the core 210 can include heat transport mediums such as one or more heat pipes, a liquid, a thermo-siphon, or other similar heat transport medium suitable for enhancing the extraction of heat from the integrated circuit device. In some embodiments, the first and second arrays 220 and 290 occupy a first and second volume of space, respectively, around the upper and lower surface areas 230 and 240 such that the second volume is less than the first volume to permit components to be mounted on the circuit board 130 and below the first array 220.

FIG. 4 is an isometric view of another embodiment of the enhanced heat dissipation device 400 according to the present invention. Shown in FIG. 4 is the enhanced heat dissipation device 400 including the thermally conductive core 210, and a first array 420 of radially extending substantially planar fin structures 422. Also, shown in FIG. 4 is the core 210 having the upper and lower outer surface areas 230 and 240. The first array 420 is thermally coupled to the upper surface area 230 of the core 210 such that a cooling medium such as air introduced around the upper and lower surface areas 230 and 240 of the core 210 and the first array 420, creates a flow that is substantially parallel to the upper and lower surface areas 230 and 240 and the first array 420 to enhance heat dissipation from the heat dissipation device 400. FIG. 4 further shows an optional second array 490 of radially extending substantially planar fin structures 492 thermally coupled to the lower surface area 240 of the core 210 such that the cooling medium introduced around the first and second arrays 420 and 490 creates a flow that is substantially parallel to the upper and lower surface areas 230 and 240 and the first and second arrays 420 and 490.

The core 210 has an axis 260. The substantially planar fin structures 422 and 492 of the first and second arrays 420 and 490, respectively, are thermally coupled to the upper and lower surface areas 230 and 240, respectively, such that they are substantially parallel to the axis 260 so that the cooling medium introduced around the core 210 and the first and second arrays 420 and 490, creates a flow substantially parallel to the axis 260 to enhance heat dissipation from the heat dissipation device 400. In some embodiments, the first and second arrays 420 and 490 including the substantially planar fin structures 422 and 492 are aligned and thermally coupled so that they form a single array as shown in FIG. 4. In some embodiments, the upper and lower surface areas 230 and 240 are parallel to the axis 260. The core 260 further has a base 270. In some embodiments, the base 270 is disposed in such a way that it is in close proximity to the lower surface area 240 and perpendicular to the axis 260. The upper and lower surface areas 230 and 240 can be concentric to the axis 260.

The first array 420 is thermally coupled to the upper surface area 230 such that components can be mounted around and in close proximity to the lower surface area 240 and below the first array 420 when the heat dissipation device 400 is mounted onto an integrated circuit device. In some embodiments, the components can encroach onto the integrated circuit device without mechanically interfering with the heat dissipation device 400.

The core 210 can be a solid body. The solid body can be cylindrical, conical, square, rectangular, or any other similar shape that facilitates in mounting onto the integrated circuit device and in attaching the first array 420 to the upper surface area 230. The core 210 can include heat transport mediums such as one or more heat pipes, a liquid, a thermo-siphon, or other such heat transport medium that enhances heat dissipation from the integrated circuit device.

The first array 420 has the first outer diameter 250 and the second array 490 has the second outer diameter 255. The second outer diameter 255 is less than the first outer diameter 250. The first array 420 has a first depth, and the second array 490 has a second depth. The first and second outer diameters 250 and 255, including the first and second depths, are of sufficient size to allow components to be mounted around and in close proximity to the integrated circuit device when the heat dissipation device 400 is mounted on the integrated circuit device.

The second array 490 is thermally coupled to the lower core area 240 of the core 210 such that the cooling medium introduced creates an omni-directional flow around the upper and lower surface areas 230 and 240 of the core 210 and the first and second arrays 420 and 490 to enhance heat dissipation from the heat dissipation device 400. The heat dissipation device 400, including the core 210 and the first and second arrays 420 and 490, can be made from materials such as aluminum, copper, or any other materials that are capable of dissipating heat away from the integrated circuit device. The first and second arrays 420 and 490 can be formed to have outer shapes such as circular, square, rectangular, elliptical, conical or any other shape suitable for allowing components to encroach around and in close proximity to the first and second arrays 420 and 490.

FIG. 5 is an isometric view 500 showing the enhanced heat dissipation device 400 shown in FIG. 4 attached to the microprocessor 120 on the assembled motherboard 130. In the example embodiment shown in FIG. 5, the microprocessor 120 has a front side 340 and a back side 330. The front side 340 is disposed across from the back side 330. The front side 340 is attached to the assembled motherboard 130 having components such as low-cost capacitors 140 and other such electrical components. The base 270, shown in FIG. 4, of the enhanced heat dissipation device 400 is attached to the back side 330 of the microprocessor 120. It can be seen from FIG. 5 that the first and second arrays 420 and 490 are of sufficient size so as to allow low-cost capacitors 140 mounted on the assembled board 130 to encroach around the microprocessor 120. It can also be seen that low-cost capacitors 140 are below the first array 420 and around the second array 490.

Also, it can be seen in FIG. 5 that the first array 420 is larger than the second array 490, thereby increasing the heat dissipation rate without increasing a footprint size of the base 270 (refer to FIG. 4) of the heat dissipation device 400 any more than the back side 330 of the microprocessor 120. The coinciding footprint sizes of the base 270 of the heat dissipation device 400 and the back side 330 of the microprocessor 120 enables the base 270 and the back side 330 of the microprocessor 120 to have the same heat transfer rates. This in turn increases the efficiency of heat transfer between the base 270 and the back side 330 of the microprocessor 120.

The core 210 further has the top surface 275 disposed across from the base 270 (refer to FIG. 4). In some embodiments, the top surface 275 is perpendicular to the axis 260 (refer to FIG. 4) and is in close proximity to the first array 420. A heat transport medium can be attached to the top surface 275 to introduce a heat transfer medium 297 such as air in a direction shown in FIG. 2, to create a flow around the core 210 and the first and second arrays 420 and 490 that is substantially parallel to the core 210 and the first and second arrays 420 and 490 to enhance the heat dissipation by the heat dissipation device 400. A heat transport medium 295 (refer to FIG. 2) such as a heat pipe or other such medium can be included in the core 210 to further enhance the heat transfer from the heat dissipation device 400.

In some embodiments, the enhanced heat dissipation device 400 is made of thermally conductive materials such as copper, aluminum, or any other such material capable of extracting heat away from the integrated circuit device. In some embodiments, the core 210 can include heat transport mediums such as one or more heat pipes, a liquid, a thermo-siphon, or other similar heat transport medium suitable for enhancing the extraction of heat from the integrated circuit device. In some embodiments, the first and second arrays 420 and 490 occupy a first and second volume of space around the upper and lower surface areas 230 and 240, respectively, such that the second volume is less than the first volume to permit components to be mounted on the circuit board 130 and below the first array 420.

FIG. 6 is an isometric view of another embodiment of the enhanced heat dissipation device 600 according to the present invention. Shown in FIG. 6 is the enhanced heat dissipation device 600 including the thermally conductive core 210, and a first array 620 of radially extending substantially planar fin structures 622. Also, shown in FIG. 6 is the core 210 having upper and lower outer surface areas 230 and 240. The first array 620 is thermally coupled to the upper core area 230 of the core 210 such that a cooling medium 297 such as air introduced around the upper and lower surface areas 230 and 240 of the core 210 and the first array 620 creates a flow that is substantially perpendicular to the core 210 to enhance heat dissipation from the heat dissipation device 600. FIG. 6 further shows an optional second array 690 of radially extending substantially planar fin structures 692 thermally coupled to the lower core area 240 of the core 210 such that the cooling medium 297 introduced around the first and second arrays 620 and 690 creates a flow that is substantially perpendicular to the core 210 to further enhance heat dissipation from the heat dissipation device 600.

The core 210 has an axis 260. In some embodiments, the upper and lower surface areas 230 and 240 are parallel to the axis 260. The core 210 further has a base 270. hi some embodiments, the base 270 is disposed in such a way that it is in close proximity to the lower surface area 240 and is perpendicular to the axis 260. The upper and lower surface areas 230 and 240 can be concentric to the axis 260.

The first array 620 is thermally coupled to the upper surface area 230 such that components can be mounted around and in close proximity to the lower surface area 240 and below the first array 620 when the heat dissipation device 600 is mounted onto the integrated circuit device. In some embodiments, the components can encroach onto the integrated circuit device without mechanically interfering with the heat dissipation device 600.

The core 210 can be a solid body. The solid body can be cylindrical, conical, square, rectangular, or any other similar shape that facilitates in mounting onto the integrated circuit device and in attaching the first array 620 to the upper surface area 230. The core 210 can include a heat transport medium 295 such as one or more heat pipes, a liquid, a thermo-siphon, or other such heat transport medium that enhance heat dissipation from the integrated circuit device.

The first array 620 has a first outer diameter 250, and the second array 690 has a second outer diameter 255. The second outer diameter 255 is less than the first outer diameter 250. The first array 620 has a first depth, and the second array 690 has a second depth. The first and second outer diameters 250 and 255, including the first and second depths, are of sufficient size to allow components to be mounted around and in close proximity to the integrated circuit device when the device is mounted on the integrated circuit device.

The second array 690 is thermally coupled to the lower core area 240 of the core 210 such that the cooling medium 297 introduced creates an omni-directional flow around the upper and lower surface areas 230 and 240 of the core 210 and the first and second arrays 620 and 690 to enhance heat dissipation from the device 600. The device 600, including the core 210 and the first and second arrays 620 and 690, can be made from materials such as aluminum, copper, or any other materials that are capable of dissipating heat away from the integrated circuit device. The first and second arrays 620 and 690 can be formed to have outer shapes such as circular, square, rectangular, elliptical, conical or any other shape suitable for allowing components to encroach around and in close proximity to the first and second arrays 620 and 690.

FIG. 7 is an isometric view 700 showing the enhanced heat dissipation device 600 shown in FIG. 6, attached to the microprocessor 120 on an assembled motherboard 130. In the example embodiment shown in FIG. 7, the microprocessor 120 has a front side 340 and a back side 330. The front side 340 is disposed across from the back side 330. The front side 340 is attached to the assembled motherboard 130 that has components such as low-cost capacitors 140 and other such electrical components. The base 270, shown in FIG. 6, of the enhanced heat dissipation device 600 is attached to the back side 330 of the microprocessor 120. It can be seen from FIG. 7 that the first and second arrays 620 and 690 are of sufficient size so as to allow low-cost capacitors 140 mounted on the assembled board 130 to encroach around the microprocessor 120. It can also be seen that low-cost capacitors 140 are below the first array 620 and around the second array 690.

Also, it can be seen in FIG. 7 that the first array 620 is larger than the second array 690, thereby increasing the heat dissipation rate without increasing the footprint size of the base 270 (refer to FIG. 6) of the heat dissipation device 600 any more than the back side 330 of the microprocessor 120. The coinciding footprint sizes of the base 270 of the heat dissipation device 600 and the back side 330 of the microprocessor 120 enables the base 270 and the back side 330 of the microprocessor 120 to have the same heat transfer rates. This in turn increases the efficiency of heat transfer between the base 270 and the back side 330 of the microprocessor 120.

A heat transport medium can be disposed around the heat dissipation device 600 to introduce a heat transfer medium 297 such as air in a direction shown in FIG. 6, to create a flow that is substantially perpendicular to the core 210. Further, the flow is substantially parallel to the first and second arrays 620 and 690 to enhance the heat dissipation by the heat dissipation device 600. A heat transport medium 295 such as a heat pipe, or other such medium can be included in the core 210 to further enhance the heat transfer from the heat dissipation device 600.

In some embodiments, the enhanced heat dissipation device 600 is made of thermally conductive materials such as copper, aluminum, or any other such material capable of extracting heat away from the integrated circuit device. In some embodiments, the core 210 can include a heat transport medium 295 such as one or more heat pipes, a liquid, a thermo-siphon, or other similar heat transport medium suitable for enhancing the extraction of heat from the integrated circuit device. In some embodiments, the first and second arrays 620 and 690 occupy a first and second volume of space around the upper and lower surface areas 230 and 240, respectively, such that the second volume is less than the first volume to permit components to be mounted on the circuit board 130 and below the first array 620.

FIG. 8 is an isometric view of another embodiment of an enhanced heat dissipation device 800 according to the present invention. Heat dissipation device 800 comprises a core 870 whose cross-section has the shape of a square. Heat dissipation device 800 further comprises a first array 820 of pin fin structures 822 and a second array 890 of pin fin structures 892. In the embodiment shown, the first array 820 and the second array 890 have an outer shape that is square. The volume occupied by the second array 890 is less than that occupied by the first array 820.

FIG. 9 is an isometric view of another embodiment of an enhanced heat dissipation device 900 according to the present invention. Heat dissipation device 900 comprises a core 970 whose cross-section has the shape of a rectangle. Heat dissipation device 900 further comprises a first array 920 of pin fin structures 922 and a second array 990 of pin fin structures 992. In the embodiment shown, the first array 920 and the second array 990 have an outer shape that is rectangular. The volume occupied by the second array 990 is less than that occupied by the first array 920.

FIG. 10 is an isometric view of another embodiment of an enhanced heat dissipation device 1000 according to the present invention. Heat dissipation device 1000 comprises a cylindrical core 1070. Heat dissipation device 1000 further comprises a first array 1020 of pin fin structures 1022 and a second array 1090 of pin fin structures 1092. In the embodiment shown, the first array 1020 and the second array 1090 have an outer shape that is elliptical. The volume occupied by the second array 1090 is less than that occupied by the first array 1020.

FIG. 11 is an isometric view of another embodiment of an enhanced heat dissipation device 1100 according to the present invention. Heat dissipation device 1100 comprises a conically-shaped core 1170. Heat dissipation device 1100 further comprises a first array 1120 of pin fin structures 1122 and a second array 1190 of pin fin structures 1192. In the embodiment shown, the first array 1120 and the second array 1190 have an outer shape that is conical. The volume occupied by the second array 1190 is less than that occupied by the first array 1120.

FIG. 12 is a diagrammatic view illustrating certain geometrical relationships among elements of an embodiment of the invention such as, for example, the embodiment illustrated in FIG. 2.

A core 210 has a base 270 and a top surface 275.

A first array whose general outline is represented by 220 has a first outer diameter 250 and a first depth 251.

A second array 290 whose general outline is represented by 290 has a second outer diameter 255 and a second depth 252.

Core 210 comprises an upper outer surface area 230 having a first length 271 extending from top surface 275 to the lower edge of the first array 220. The first array 220 is coupled to the upper outer surface area 230 of the core 210.

Core 210 also comprises a lower outer surface area 240 having a second length 272 extending from below the lower edge of the first array 220 to the lower edge of the second array 290. The second array 290 is coupled to the lower outer surface area 240 of the core 210.

CONCLUSION

The above-described device and method provide, among other things, enhanced heat dissipation by using an array of radially extending fin structures where possible. This allows electronic components to encroach around an integrated circuit device on which it is mounted, while maintaining high performance and cost effectiveness by leveraging currently enabled high volume manufacturing techniques.

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US8295046B2	Cited by	United States of America	Applicant
US7897420B2	Cited by	United States of America	Applicant
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US2006154393A1	Cited by	United States of America	Pre-grant
US2014334074A1	Cited by	United States of America	Pre-grant
US6681842B2	Cited by	United States of America	Search report
USD962879S	Cited by	United States of America	Search report
US2003189813A1	Cited by	United States of America	Pre-grant
US7563625B2	Cited by	United States of America	Applicant
US9137925B2	Cited by	United States of America	Search report
US2004080914A1	Cited by	United States of America	Pre-grant
US7629195B2	Cited by	United States of America	Applicant
US8466479B2	Cited by	United States of America	Applicant
US2011232885A1	Cited by	United States of America	Pre-grant
US2008142814A1	Cited by	United States of America	Pre-grant
US2008293171A1	Cited by	United States of America	Pre-grant
US7284596B2	Cited by	United States of America	Applicant
US2007166851A1	Cited by	United States of America	Pre-grant
US9130114B2	Cited by	United States of America	Applicant
US2005280992A1	Cited by	United States of America	Pre-grant
US7200934B2	Cited by	United States of America	Applicant
US6827130B2	Cited by	United States of America	Search report
US2007146995A1	Cited by	United States of America	Pre-grant
US7142422B2	Cited by	United States of America	Search report
US2008247874A1	Cited by	United States of America	Pre-grant
US2006113065A1	Cited by	United States of America	Pre-grant
US6691770B2	Cited by	United States of America	Search report
US2006154390A1	Cited by	United States of America	Pre-grant
US6653755B2	Cited by	United States of America	Search report
US7473936B2	Cited by	United States of America	Applicant
EP1081760A2	Cites	European Patent Office (EPO)	Applicant
US2337294A	Cites	United States of America	Search report
US3182114A	Cites	United States of America	Applicant
US3187082A	Cites	United States of America	Applicant
US3239003A	Cites	United States of America	Applicant
US4354729A	Cites	United States of America	Applicant
US4557225A	Cites	United States of America	Applicant
US4645279A	Cites	United States of America	Applicant
US4699593A	Cites	United States of America	Applicant
US4726739A	Cites	United States of America	Applicant
US4940432A	Cites	United States of America	Applicant
US4959029A	Cites	United States of America	Applicant
US4997034A	Cites	United States of America	Search report
US5035629A	Cites	United States of America	Applicant
US5132780A	Cites	United States of America	Search report
US5132875A	Cites	United States of America	Applicant
US5286208A	Cites	United States of America	Applicant
US5299090A	Cites	United States of America	Search report
US5375652A	Cites	United States of America	Applicant
US5437327A	Cites	United States of America	Applicant
US5545045A	Cites	United States of America	Applicant
US5567983A	Cites	United States of America	Applicant
US5597034A	Cites	United States of America	Applicant
US5661638A	Cites	United States of America	Applicant
US5704416A	Cites	United States of America	Applicant
US5777844A	Cites	United States of America	Applicant
US5785116A	Cites	United States of America	Applicant
US5794685A	Cites	United States of America	Applicant
US5800184A	Cites	United States of America	Applicant
US5920458A	Cites	United States of America	Applicant
US5975194A	Cites	United States of America	Applicant
US6075285A	Cites	United States of America	Applicant
US6075702A	Cites	United States of America	Applicant
US6129239A	Cites	United States of America	Applicant
US6152214A	Cites	United States of America	Applicant
US6176299B1	Cites	United States of America	Applicant
US6189601B1	Cites	United States of America	Applicant
US6208511B1	Cites	United States of America	Applicant
US6219239B1	Cites	United States of America	Applicant
US6244331B1	Cites	United States of America	Search report
US896107A	Cites	United States of America	Search report
JPH0677677A	Cites	Japan	Applicant
Cotton, M., "Microfeatures & Embedded Coaxial Technology", Electronic Circuits World Convention 8, 6 p., (Sep. 8, 1999).	Non-patent	–	Applicant

35 members in 13 offices

This recordMember, by publication datePriority claim3 more offices are in the list below

Priority claims1

Priority claims
Document	Office	Kind	Date
71651000	United States of America	A	2000-11-20

Members35

Family members, oldest first
Document	Office	Kind
US2002060902A1	United States of America	A1	2002-05-23
WO0241395A2	World Intellectual Property Organization (WIPO)	A2	2002-05-23
WO0241396A2	World Intellectual Property Organization (WIPO)	A2	2002-05-23
AU2584602A	Australia	A	2002-05-27
AU3655202A	Australia	A	2002-05-27
WO0241395A3	World Intellectual Property Organization (WIPO)	A3	2002-08-22
WO0241396A3	World Intellectual Property Organization (WIPO)	A3	2002-08-29
TW519742B	Taiwan Province of China	B	2003-02-01
US6535385B2This record	United States of America	B2	2003-03-18
GB0308872D0	United Kingdom	D0	2003-05-21
GB2384911A	United Kingdom	A	2003-08-06
EP1344251A2	European Patent Office (EPO)	A2	2003-09-17
US2003189813A1	United States of America	A1	2003-10-09
US6633484B1	United States of America	B1	2003-10-14
HK1055509A	Hong Kong, China	A	2004-01-09
HK1055509A1	Hong Kong, China	A1	2004-01-09
KR20040014415A	Republic of Korea	A	2004-02-14
KR20040014416A	Republic of Korea	A	2004-02-14
CN1486508A	China	A	2004-03-31
DE10196917T5	Germany	T5	2004-04-22
JP2004523883A	Japan	A	2004-08-05
JP2004523884A	Japan	A	2004-08-05
US6845010B2	United States of America	B2	2005-01-18
MXPA03004441A	Mexico	A	2005-01-25
GB2384911B	United Kingdom	B	2005-03-16
CN1708849A	China	A	2005-12-14
KR100566446B1	Republic of Korea	B1	2006-03-31
KR100566447B1	Republic of Korea	B1	2006-03-31
MY127105A	Malaysia	A	2006-11-30
CN1305131C	China	C	2007-03-14
CN100373602C	China	C	2008-03-05
JP4170756B2	Japan	B2	2008-10-22
MY138068A	Malaysia	A	2009-04-30
DE10196917B4	Germany	B4	2009-11-05
JP4801313B2	Japan	B2	2011-10-26

46 transactions on the USPTO file

Allowed after 1 non-final rejection.

Non-final rejections: 1
Final rejections: 0
RCEs: 0
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2005-03-07	Correspondence Address ChangeC.ADB	C.ADB
2003-03-18	Recordation of Patent Grant MailedPGM/	PGM/
2003-03-18	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2003-02-27	Issue Notification MailedAllowedWPIR	WPIR
2003-02-05	Receipt into Pubs	–
2003-02-05	Receipt into Pubs	–
2003-01-27	Receipt into PubsR1021	R1021
2003-01-14	Receipt into PubsR1021	R1021
2003-01-13	Mail Miscellaneous Communication to ApplicantMM327	MM327
2003-01-13	Miscellaneous Communication to Applicant - No Action CountM327	M327
2003-01-03	Application Is Considered Ready for IssuePILS	PILS
2002-12-12	Workflow - Drawings Matched with File at ContractorDRWM	DRWM
2002-12-02	Issue Fee Payment Verified	–
2002-12-02	Improper Request for Continued ExaminationIRCE	IRCE
2002-12-02	Workflow - Request for RCE - FinishFRCE	FRCE
2002-12-02	Issue Fee Payment Verified	–
2002-12-02	Issue Fee Payment ReceivedIFEE	IFEE
2002-12-02	Workflow - Request for RCE - BeginBRCE	BRCE
2002-10-08	Receipt into PubsR1021	R1021
2002-09-04	Workflow - File Sent to ContractorSENT	SENT
2002-09-04	Receipt into PubsR1021	R1021
2002-09-03	Dispatch to PublicationsD1220	D1220
2002-08-29	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2002-08-28	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2002-08-16	Date Forwarded to ExaminerFWDX	FWDX
2002-08-08	Workflow - Drawings Finished	–
2002-08-08	Workflow - Drawings Matched with File at ContractorDRWM	DRWM
2002-08-08	Workflow - Drawings Finished	–
2002-08-08	Information Disclosure Statement (IDS) Filed	–
2002-08-08	Information Disclosure Statement (IDS) Filed	–
2002-08-08	Response after Non-Final ActionA...	A...
2002-05-03	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2002-04-19	Non-Final RejectionNon-final rejectionCTNF	CTNF
2002-03-25	Information Disclosure Statement (IDS) Filed	–
2002-03-25	Information Disclosure Statement (IDS) Filed	–
2002-02-22	Date Forwarded to ExaminerFWDX	FWDX
2002-02-08	Response to Election / Restriction FiledELC.	ELC.
2002-01-31	Information Disclosure Statement (IDS) Filed	–
2002-01-31	Information Disclosure Statement (IDS) Filed	–
2001-12-04	Mail Restriction RequirementMCTRS	MCTRS
2001-11-08	Restriction/Election RequirementCTRS	CTRS
2001-04-30	Case Docketed to Examiner in GAUDOCK	DOCK
2001-03-12	Application Dispatched from OIPEOIPE	OIPE
2001-03-07	Correspondence Address ChangeC.AD	C.AD
2001-02-06	IFW Scan & PACR Auto Security Review	–
2001-01-22	Initial Exam Team nnIEXX	IEXX

6 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2014-08-20	Fee paymentFPAY	FPAY
2010-09-16	Fee paymentFPAY	FPAY
2006-09-15	Fee paymentFPAY	FPAY
2004-12-09	Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2003-02-27	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2001-01-22	AssignmentAS	AS