Transmitter and receiver

TECHNICAL FIELD

The present invention relates to an interleaving technique involved in digital modulation and demodulation, especially to a transmitter and a receiver capable of performing the unified interleave and deinterleave without employing an interleave method corresponding to a multiplexing scheme based on each transmission mode when implementing multiplex transmission combining a plurality of transmission modes with different error endurance.

BACKGROUND ART

FIG. 4 shows a multiplexed signal structure in which a frame structure is comprised of one frame including 48 slots and one super frame is structured by eight frames, for example. Here, a slot is a memory area for storing a packet consisting of 204 bytes adding a 16-byte RS(204, 188) error correction code to a 188-byte MPEG-2 TS packet. In digital transmission using a broadcasting satellite, it is assumed that the slots of the same number of each frame in a super frame, may use the same type transmission mode including the modulation scheme and error correction code, and four types of transmission modes can be used at maximum in one super frame. In addition, the transmission modes in the super frame are flexibly varied by reporting those modes from a transmitting side to a receiving side by using a control signal called a TMCC signal contained in the second previous super frame.

FIG. 5 shows the structure of a modulated signal generated from the multiplexed signal. In this case, the multiplexed data is subjected to interleaving in the transmitter side and deinterleaving in the receiving side in order to derive the full power of Reed-Solomon (RS) codes, typical external codes, by distributing burst errors which occur when the number of bit errors in the transmission channel are beyond the error correcting capability of a Viterbi decoder or a trellis decoder used for error correction in the receiver. For example, interleaving of depth eight is implemented by forming interleave frames at every eight slots using the same type transmission mode in a frame, and by reading out of the column the data of the interleave frames written into a row in a two dimensional memory. (When the number of the slots using the same type transmission mode is less than eight in a frame, or the number of the remaining slots is less than eight when the interleave frames are formed every eight slots in sequence, the interleave frame is structured in addition to slots of a frame which will be described later.

As structural examples, the implementing interleave process will now be described with reference to FIGS. 6 and 7. FIG. 6 shows an example in which 46 slots are transmitted by TC-8 PSK and one slot is transmitted by QPSK subjected to convolutional encoding with a coding rated of ½, and further, one slot is regarded as a dummy slot. FIG. 7 shows an example in which 44 slots are transmitted by TC-8 PSK and one slot is transmitted by BPSK subjected to convolutional encoding with a coding rate of ½, and further, three slots are regarded as dummy slots.

In either example, as for the one slot transmitted by QPSK or BPSK, one interleave frame is formed in one super frame. To match the timing of signals after the interleaving, a first-in-first-out (FIFO) memory for storing data with a length of the super frame {(data length of assigned slots)-(length of the interleave frame)} is necessary for the greater assigned slot number (in the above example, the 46 slots or 44 slots data transmitted by the TC-8 PSK).

Since the interleave frame is 204×8 bytes, a FIFO memory is comprised of 204×46×8−204×8=73440 bytes in the example of FIG. 6, and shows a FIFO memory is comprised of 204×44×8−204×8=70176 bytes in the example of FIG. 7, thus performing the interleave process by once storing the data amount close to one super frame every each transmission mode.

However, the capacity of the FIFO memory changes according to the assigned slot number for each of transmission modes in the frame, and a controller controlling the interleave process should be needed because address control is changed according to the change of the capacity of the FIFO memory, thereby complicating a circuit structure.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a transmitter and a receiver implementing an interleave process simply without changing the circuit configuration by changing the assigned slot number according to the transmission mode in each frame.

In the first aspect of the present invention, there is provided a transmitter applicable to a transmission system capable of transmitting digital data (called the transmission coded signal), which are encoded by using different types of error correction codes and modulated by different types of modulation with schemes, as packet units in the multiplexed data with a frame structure consisting of N packets, said transmitter performing interleaving of a super frame unit, and comprising:

means for forming an interleave frame by combining packets corresponding to the same slot number in each frame;

write means for sequentially writing data according to a frame number of the interleave frame into a two-dimensionally arrangeable memory along a row or a column direction; and

readout means for sequentially reading out the written data from the two-dimensionally arrangeable memory along a column or row direction different from the row or column direction of said write means.

In the second aspect of the present invention, there is provided a receiver applicable to a transmission system capable of transmitting digital data (called transmission coded signal), which are encoded by using different types of error correction codes and are modulated by different types of modulation techniques, as packet unit in the multiplexed data with a frame structure consisting of N packets, said receiver performing deinterleaving of a super frame unit, and comprising:

means for forming a deinterleave frame by combining packets corresponding to the same slot number in each frame;

write means for sequentially writing data according to a frame number of the deinterleave frame into a two-dimensionally arrangeable memory along the column or row direction corresponding to the readout direction of an interleave process during transmission; and

readout means for sequentially reading out the written data from the two-dimensionally arrangeable memory along the row or column direction different from the column or row direction of said write means corresponding to the writing direction of the interleave process during transmission.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic perspective view showing a frame structure as an embodiment according to the present invention;

FIG. 2 is a diagram showing a data arrangement in frames according to the present invention;

FIG. 3 is a diagram showing an example of an interleave process;

FIG. 4 is a schematic perspective view showing a conventional frame structure;

FIG. 5 is a diagram showing a data arrangement in conventional frames;

FIG. 6 is a block diagram showing a conventional transmission process; and

FIG. 7 is a block diagram showing another conventional transmission process.

BEST MODE FOR CARRYING OUT THE INVENTION

A preferred embodiment of the present invention will be described in detail with reference to the drawings.

The present invention relates to an interleave process applicable to digital transmission. In particular, in a transmission system that can transmit mixed data comprising of different types of transmission modes as packet units in the multiplexed data with a frame structure consisting of N packets, an interleave frame is formed by combining slots corresponding to the same slot number in each frame, and the interleave process is performed every interleave frame, thus simply performing the interleave process under the same memory control even though various types of transmission modes in mixed data may be transmitted.

This example refers to a reading and writing process of a transmission system in that interleave in the transmitter and deinterleave in the receiver, which is opposite to the interleave can be performed. A concrete example will be described as follows.

FIG. 1 shows the structure of a single super frame <b>10</b>. The super frame <b>10</b> is structured by eight frames <b>20</b>. Each frame <b>20</b> consists of 48 slots <b>30</b>. These slots <b>30</b> are structured by various types of signals, such as multiplexed signals including video, audio and associated informations, a frame synchronizer, TMCC and super frame synchronizer. One slot <b>30</b> consists of (1+187+16) bytes. FIG. 2 shows the frames <b>20</b> in the super frame <b>10</b> sequentially arranged.

The processings performed by the transmission and reception of the system will be described with reference to FIGS. <b>3</b>(<i>a</i>) to <b>3</b>(<i>e</i>).

FIG. <b>3</b>(<i>b</i>) shows a memory <b>40</b> capable of being arrayed in two dimensions. First, when FIG. 3 is assumed to be a process of the transmitter, FIG. <b>3</b>(<i>a</i>) shows the data arrangement in the super frame <b>10</b> before interleave. In contrast, FIG. <b>3</b>(<i>c</i>) shows the data arrangement after interleave. FIGS. <b>3</b>(<i>d</i>) to <b>3</b>(<i>e</i>) schematically shows the data read process from the memory <b>40</b>.

In the present example, using the memory <b>40</b>, the interleave process as to the data in the super frame <b>10</b> of FIG. 1 is performed. This is to say, the data is written into the memory <b>40</b> in the horizontal direction (along the row direction), and the data is read out from the memory <b>40</b> in the vertical direction (along the column direction). A more detailed example follows.

As an example, when slot number is <b>1</b>, the interleave is performed as to the slots #<b>1</b> of the first to eighth frames <b>20</b>, and the data is written into the two-dimensional memory <b>40</b> along the row direction sequentially from the first slot of the first frame <b>20</b>. In the present example, the ith data of each frame <b>20</b> (shaded area) is written every 203-byte data width.

After the data is written, the data is read out from the memory <b>40</b> along the column direction perpendicular to the row direction.

Table 1 shows a sequential arrangement of the actual read addresses and the data read addresses of the first slots according to each frame. Here, the numerals indicate frame-bytes.

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By doing the readout process, interleave can be performed independently of the assigned slot number every each frame.

Furthermore, by exchanging the readout direction and the write direction, deinterleave can be performed in the receiver (i.e. the deinterleave process can be performed by writing the data according to the readout direction of the interleave and can be performed by reading out the data according to the write direction of the interleave).

On the other hand, when FIG. 3 is assumed to be a process of the receiver, FIG. <b>3</b>(<i>c</i>) shows the data before the deinterleave process, and FIG. <b>3</b>(<i>a</i>) shows the data after the deinterleave process.

INDUSTRIAL APPLICABILITY

As described above, according to the present invention, an interleave frame is formed by combining slots corresponding to the same slot number in each frame when the interleave process is performed in a super frame, and the data are read out along the row or column direction (i.e. readout direction) and the data are written along the direction opposite to the readout direction in the same memory. This makes it possible to obviate complicated memory address controllers according to transmission mode structures in the interleave or deinterleave process, thereby enabling a uniform control in any case.