Method of forming a semiconductor device and an improved deposition system

This is a division of application Ser. No. 09/288,265, filed Apr. 8, 1999 now U.S. Pat. No. 6,372,114.

BACKGROUND OF THE INVENTION

The present invention relates to a method of forming a copper electrode buried in an insulating layer of a semiconductor device free from such a problem that a copper electrode plating layer is peeled thereby educing a yield of a semiconductor device, and more particularly to a method of forming a copper electrode on a copper seed layer on a TiN barrier layer formed in a trench groove and a through hole formed in an inter-layer insulator of a semiconductor device, buried in an insulating layer of a semiconductor device.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a novel a method of forming a copper electrode buried in an insulating layer of a semiconductor device free from such a problem that a copper electrode plating layer is peeled thereby educing a yield of a semiconductor device.

It is another object of the present invention to provide a method of forming a copper electrode on a copper seed layer on a TiN barrier layer formed in a trench groove and a through hole formed in an inter-layer insulator of a semiconductor device, buried in an insulating layer of a semiconductor device.

The first present invention provides a multi-layer structure comprising: a barrier layer on a predetermined region of an insulating layer; a metal seed layer made of a metal which is different in substance from the barrier layer, the metal seed layer extending not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and a metal plating layer made of the metal as the seed layer, and the metal layer being adhered on the metal seed layer so that the metal plating layer is separated from the barrier layer and also from the insulating layer.

The second present invention provides a method of forming a multi-layer structure over an insulating layer. The method comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the same metal as the seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.

The third present invention provides a deposition system for forming a multi-layer structure over an insulating layer. The deposition system comprises: a first deposition chamber having a first deposition mask for selectively depositing a barrier layer on a predetermined region of an insulating layer; and a second deposition chamber having a second deposition mask for selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer, wherein the first deposition mask has a first opening edge having a first diameter and the second mask has a second opening edge having a second diameter which is larger than the first diameter of the first deposition mask, whereby a metal plating layer made of the metal as the seed layer is formed on the metal seed layer, wherein the metal plating layer is separated from the barrier layer and also from the insulating layer.

The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 1A through 1E are fragmentary cross sectional elevation views illustrative of semiconductor devices in sequential steps involved in a novel fabrication method thereof by use of a novel deposition system in accordance with the present invention.

FIG. 2 is a plane view of a plane layout of a deposition system for depositing a barrier metal layer, a copper seed layer and a copper plating layer in accordance with the present invention.

FIG. 3A is a cross sectional elevation view illustrative of a TiN barrier chamber of a deposition system of FIG. 2 before clamping a wafer in accordance with the present invention.

FIG. 3B is a cross sectional elevation view illustrative of a TiN barrier chamber of a deposition system of FIG. 2 after having clamped a wafer for a sputtering process for deposition of a titanium nitride layer in accordance with the present invention.

FIG. 4A is a plane view illustrative of a clamp ring of the damper in the TiN barrier chamber in the deposition chamber of FIGS. 3A and 3B in accordance with the present invention.

FIG. 4B is a plane view illustrative of a clamp ring of the damper in the copper seed chamber in the deposition chamber of FIGS. 3A and 3B in accordance with the present invention.

FIG. 5A is a fragmentary cross sectional elevation view illustrative of a deposited TiN barrier layer not only on a wafer but also on a clamp ring after a sputtering process to a wafer in the TiN barrier chamber illustrated in FIG. 3B of the deposition system of FIG. 2 in accordance with the present invention.

FIG. 5B is a fragmentary cross sectional elevation view illustrative of a deposited copper seed layer not only on a wafer but also on a clamp ring after a sputtering process to a wafer in the copper seed chamber illustrated in FIG. 3B of the deposition system of FIG. 2 in accordance with the present invention.

FIG. 5C is a fragmentary cross sectional elevation view illustrative of the silicon wafer formed thereon with the copper plating layer in accordance with the present invention.

FIG. 6A is a cross sectional elevation view illustrative of another TiN barrier chamber of a deposition system of FIG. 2 before clamping a wafer in accordance with the present invention.

FIG. 6B is a cross sectional elevation view illustrative of another TiN barrier chamber of a deposition system of FIG. 2 after having clamped a wafer for a sputtering process for deposition of a titanium nitride layer in accordance with the present invention.

DISCLOSURE OF THE INVENTION

The first present invention provides a multi-layer structure comprising: a barrier layer on a predetermined region of an insulating layer; a metal seed layer made of a metal which is different in substance from the barrier layer, the metal seed layer extending not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and a metal plating layer made of the metal as the seed layer, and the metal layer being adhered on the metal seed layer so that the metal plating layer is separated from the barrier layer and also from the insulating layer.

It is preferable that the barrier layer comprises a TiN barrier layer, and the metal seed layer and the metal plating layer are made of copper.

It is also preferable that the multi-layer structure is formed in at least one of a trench groove in an inter-layer insulator as the insulating layer and a through hole also formed in the inter-layer insulator.

The second present invention provides a method of forming a multi-layer structure over an insulating layer. The method comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the same metal as the seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.

It is preferable that the first deposition mask has a first opening edge having a first diameter and the second mask has a second opening edge having a second diameter which is larger than the first diameter of the first deposition mask.

It is also preferable that the first deposition mask comprises a first clamping ring member with the first opening edge having the first diameter of a first damper for clamping a wafer for a deposition process for selectively depositing the barrier layer on the predetermined region of the insulating layer, and the second deposition mask comprises a second clamping ring member with the second opening edge having the second diameter of a second damper for clamping the wafer for a deposition process for selectively depositing the metal seed layer not only on an entire surface of the barrier layer but also the peripheral region positioned outside the predetermined region of the insulating layer.

It is also preferable that the first deposition mask comprises a first shielding plate extension member extending from a first shielding plate covering an inner wall of a first chamber, and the first shielding plate extension member having the first opening edge having the first diameter for selectively depositing the barrier layer on the predetermined region of the insulating layer, and the second deposition mask comprises a second shielding plate extension member extending from a second shielding plate covering an inner wall of a second chamber, and the second shielding plate extension member having the second opening edge having the second diameter for selectively depositing the metal seed layer not only on an entire surface of the barrier layer but also the peripheral region positioned outside the predetermined region of the insulating layer.

It is also preferable that the barrier layer comprises a TiN barrier layer, and the metal seed layer and the metal plating layer are made of copper.

It is also preferable that the multi-layer structure is formed in at least one of a trench groove in an inter-layer insulator as the insulating layer and a through hole also formed in the inter-layer insulator.

The third present invention provides a deposition system for forming a multi-layer structure over an insulating layer. The deposition system comprises: a first deposition chamber having a first deposition mask for selectively depositing a barrier layer on a predetermined region of an insulating layer; and a second deposition chamber having a second deposition mask for selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer, wherein the first deposition mask has a first opening edge having a first diameter and the second mask has a second opening edge having a second diameter which is larger than the first diameter of the first deposition mask, whereby a metal plating layer made of the metal as the seed layer is formed on the metal seed layer, wherein the metal plating layer is separated from the barrier layer and also from the insulating layer.

It is preferable that the first deposition mask comprises a first clamping ring member with the first opening edge having the first diameter of a first damper for clamping a wafer for a deposition process for selectively depositing the barrier layer on the predetermined region of the insulating layer, and the second deposition mask comprises a second clamping ring member with the second opening edge having the second diameter of a second damper for clamping the wafer for a deposition process for selectively depositing the metal seed layer not only on an entire surface of the barrier layer but also the peripheral region positioned outside the predetermined region of the insulating layer.

It is preferable that the first deposition mask comprises a first shielding plate extension member extending from a first shielding plate covering an inner wall of the first deposition chamber, and the first shielding plate extension member having the first opening edge having the first diameter for selectively depositing the barrier layer on the predetermined region of the insulating layer, and the second deposition mask comprises a second shielding plate extension member extending from a second shielding plate covering an inner wall of a second deposition chamber, and the second shielding plate extension member having the second opening edge having the second diameter for selectively depositing the metal seed layer not only on an entire surface of the barrier layer but also the peripheral region positioned outside the predetermined region of the insulating layer.

It is preferable that the barrier layer comprises a TiN barrier layer, and the metal seed layer is made of copper.

A first embodiment according to the present invention will be described in detail with reference to FIGS. 1A through 1E which are fragmentary cross sectional elevation views illustrative of semiconductor devices in sequential steps involved in a novel fabrication method thereof.

With reference to FIG. 1A, a first trench groove <b>102</b> is formed in an upper region of a first inter-layer insulator <b>101</b> which is formed over a silicon wafer which is not illustrated. A first barrier metal layer <b>103</b> is entirely deposited over the first inter-layer insulator <b>101</b> and on side walls and a bottom of the first trench groove <b>102</b>. The first barrier metal layer <b>103</b> may comprise a titanium nitride or titanium. A first level interconnection layer <b>104</b> of tungsten is further deposited on the first barrier metal layer <b>104</b>. Those first barrier metal layer <b>103</b> and the first level interconnection layer <b>104</b> are then subjected to a chemical mechanical polishing method to leave the first barrier metal layer <b>103</b> and the first level interconnection layer <b>104</b> only within the interconnection trench groove <b>102</b>.

With reference to FIG. 1B, a second inter-layer insulator <b>105</b> is formed on the surface of the first inter-layer insulator <b>101</b> and on the first level interconnection layer <b>104</b>. Second trench grooves <b>106</b> are formed in upper regions of the second inter-layer insulator <b>105</b>. A through hole <b>107</b> is then formed in the second inter-layer insulator <b>105</b>, so that the through hole <b>107</b> connects the bottom of the second trench groove and the top surface of the first level interconnection layer <b>104</b>, whereby a part of the top surface of the first level interconnection layer <b>104</b> is shown through the through hole <b>107</b>.

With reference to FIG. 1C, a second barrier metal layer <b>108</b> of titanium nitride is entirely deposited by a sputtering method on a top surface of the second inter-layer insulator <b>105</b> and side walls and bottoms of the second trench grooves <b>106</b> and on side walls of the through hole <b>107</b> as well as on the shown part of the top surface of the first level interconnection layer <b>104</b>. A copper seed layer <b>109</b> is then deposited on the second barrier metal layer <b>108</b> by a sputtering method.

With reference to FIG. 1D, a copper plating layer <b>110</b> is then formed on the copper seed layer <b>109</b>, so that the copper plating layer <b>110</b> is much thicker than the second trench grooves <b>106</b> and the through hole <b>107</b>, whereby the top surface of the copper seed layer <b>109</b> over the top surface of the second inter-layer insulator <b>105</b> is completely embedded within the copper plating layer <b>110</b>.

With reference to FIG. 1E, the copper plating layer <b>110</b> is then polished by a chemical mechanical polishing method so as to leave the copper plating layer <b>110</b> only within the second trench grooves <b>106</b> and the through hole <b>107</b> thereby forming copper electrodes as second level interconnection layers <b>111</b> within the second trench grooves <b>106</b> and the through hole <b>107</b>.

FIG. 2 is a plane view of a plane layout of a deposition system for depositing a barrier metal layer, a copper seed layer and a copper plating layer. The above fabrication processes of FIGS. 1C and 1D are carried out by use of this deposition system <b>200</b>. The deposition system <b>200</b> has a hexagonal shaped carrier chamber <b>201</b>, and first and second load lock chambers <b>202</b> and <b>203</b> and four vacuum chambers <b>204</b>, <b>205</b>, <b>206</b> and <b>207</b>. The first load lock chamber <b>202</b> serves as a loading chamber for setting a wafer <b>100</b> in a cartridge <b>210</b> accommodated in the first load lock chamber <b>202</b>. The second load lock chamber <b>203</b> also serves as an unloading chamber for setting the wafer <b>100</b> in another cartridge <b>211</b> accommodated in the first load lock chamber <b>203</b>. The first vacuum chamber <b>204</b> serves as a cleaning chamber. The second vacuum chamber <b>205</b> serves as a TiN barrier chamber. The third vacuum chamber <b>206</b> serves as a copper seed chamber. The fourth vacuum chamber <b>207</b> serves as a reserve chamber. The carrier chamber <b>201</b> is positioned in center of the deposition system. The two load lock chambers <b>202</b> and <b>203</b> and the four vacuum chambers <b>204</b>, <b>205</b>, <b>206</b> and <b>207</b> are positioned along six sides of the hexagonal shaped carrier chamber <b>201</b>. The carrier chamber <b>201</b> has a handler <b>208</b> for carrying the wafer in a clock wise direction. The two load lock chambers <b>202</b> and <b>203</b> and the four vacuum chambers <b>204</b>, <b>205</b>, <b>206</b> and <b>207</b> are connected through gates <b>202</b><i>a</i>, <b>203</b><i>a</i>, <b>204</b><i>a</i>, <b>205</b><i>a</i>, <b>206</b><i>a</i>, <b>206</b><i>a</i>, and <b>207</b><i>a </i>to the carrier chamber <b>201</b> so that the two load lock chambers <b>202</b> and <b>203</b> and the four vacuum chambers <b>204</b>, <b>205</b>, <b>206</b> and <b>207</b> are kept in vacuum states independently.

FIG. 3A is a cross sectional elevation view illustrative of a TiN barrier chamber of a deposition system of FIG. 2 before clamping a wafer. FIG. 3B is a cross sectional elevation view illustrative of a TiN barrier chamber of a deposition system of FIG. 2 after having clamped a wafer for a sputtering process for deposition of a titanium nitride layer. The wafer is mounted on a heat stage <b>221</b> accommodated in the TiN barrier chamber <b>205</b>. A damper <b>222</b> is provided around the heat stage for clamping the wafer <b>100</b> on the heat stage <b>221</b>. The damper <b>222</b> has a clamp ring <b>223</b> and a driver <b>224</b> for moving the clamp ring <b>223</b> in upward and downward directions for allowing the clamp ring <b>223</b> directly clamps or releases the wafer <b>100</b>. When the driver <b>224</b> moves the clamp ring <b>223</b> in downward direction so that the clamp ring <b>223</b> is made into contact with peripheral portions of the wafer <b>110</b> for clamping the wafer <b>110</b> on the heat stage <b>221</b>. A titanium nitride target <b>226</b> is provided over the heat stage <b>221</b>. A shield plate <b>225</b> is provided on an inner wall of the TiN barrier chamber <b>205</b> for preventing sputtered titanium nitride from being adhered onto the inner walls of the chamber. FIG. 4A is a plane view illustrative of a clamp ring of the damper in the TiN barrier chamber in the deposition chamber of FIGS. 3A and 3B. The clamp ring <b>223</b> of the damper <b>222</b> of the TiN barrier chamber <b>205</b> in the deposition chamber has an inner diameter φ W<b>1</b> which is smaller than an outer diameter φ W<b>0</b> of the wafer <b>100</b>.

The structure of the copper seed chamber <b>206</b> is essentially the same as the TiN barrier chamber <b>205</b>, for which reason illustrations thereof are omitted. The wafer is mounted on a heat stage accommodated in the copper seed chamber <b>206</b>. A damper is also provided around the heat stage for clamping the wafer on the heat stage. The damper has a clamp ring and a driver for moving the clamp ring in upward and downward directions for allowing the clamp ring directly clamps or releases the wafer. When the driver moves the clamp ring in downward direction so that the clamp ring is made into contact with peripheral portions of the wafer for clamping the wafer <b>110</b> on the heat stage. A copper target is provided over the heat stage. A shield plate is also provided on an inner wall of the copper seed chamber <b>206</b> for preventing sputtered copper from being adhered onto the inner walls of the chamber. FIG. 4B is a plane view illustrative of a clamp ring of the damper in the copper seed chamber in the deposition chamber of FIGS. 3A and 3B. The clamp ring of the damper of the copper seed chamber in the deposition chamber has an inner diameter φ W<b>2</b> which is smaller than an outer diameter φ W<b>0</b> of the wafer <b>100</b> but larger than the inner diameter φ W<b>1</b> of the clamp ring of the clamp chamber <b>205</b>.

Operations of the above deposition chamber <b>200</b> will be described. The wafer <b>100</b> having set in the first load clock chamber <b>202</b> is first carried by the handler <b>208</b> into the cleaning chamber <b>204</b> for cleaning a surface of the first level interconnection layer by use of a reversed sputtering process utilizing a radio frequency plasma. The wafer <b>100</b> is then carried by the handler <b>208</b> to the TiN barrier chamber <b>205</b>. In the TiN barrier chamber <b>205</b>, the wafer <b>100</b> is treated as illustrated in FIGS. 3A and 3B. Namely, the wafer <b>100</b> is mounted in the heat stage <b>221</b> to be heated up to a temperature of about 25-400° C., and also the clamp ring <b>223</b> is moved down to be made into contact with the peripheral portion of the wafer <b>100</b> for clamping the wafer <b>100</b> onto the heat stage <b>221</b>, whereby the sputtering process is carried out to deposit the TiN barrier layer <b>108</b> as illustrated in FIG. <b>1</b>C. FIG. 5A is a fragmentary cross sectional elevation view illustrative of a deposited TiN barrier layer not only on a wafer but also on a clamp ring after a sputtering process to a wafer in the TiN barrier chamber illustrated in FIG. 3B of the deposition system of FIG. <b>2</b>. Since the peripheral portion of the wafer <b>100</b> is covered by the clamping ring <b>223</b> of the damper <b>222</b>, the TiN barrier layer is deposited not only on the silicon wafer <b>100</b> but also on the clamping ring <b>223</b>. This means that no TiN barrier layer is deposited on the peripheral region of the wafer <b>100</b>, and the edge of the TiN barrier layer on the silicon wafer <b>100</b> is defined by the edge of the clamping ring <b>223</b>. The dimension of the peripheral region free of the deposition of the TiN barrier layer <b>108</b> is defined by a difference in the inner diameter φ W<b>1</b> of the clamping ring <b>223</b> of the damper <b>222</b> and the outer diameter φ W<b>0</b> of the silicon wafer <b>100</b>.

The wafer <b>100</b> formed thereon with the TiN barrier layer <b>108</b> is then carried by the handler <b>208</b> into the copper seed chamber <b>206</b>. In the copper seed chamber <b>206</b>, the wafer <b>100</b> is treated so that the wafer <b>100</b> is mounted in the heat stage to be heated up to a temperature of about 25° C., and also the clamp ring <b>223</b>B is moved down to be made into contact with the peripheral portion of the wafer <b>100</b> for clamping the wafer <b>100</b> onto the heat stage, whereby the copper sputtering process is carried out to deposit the copper seed layer <b>109</b> on the TiN barrier layer <b>108</b>. FIG. 5B is a fragmentary cross sectional elevation view illustrative of a deposited copper seed layer not only on a wafer but also on a clamp ring after a sputtering process to a wafer in the copper seed chamber illustrated in FIG. 3B of the deposition system of FIG. <b>2</b>. Since the peripheral portion of the wafer <b>100</b> is covered by the clamping ring <b>223</b>B of the damper <b>222</b>B, the copper seed layer <b>109</b> is deposited not only on the TiN barrier layer <b>108</b> over the silicon wafer <b>100</b> but also on the clamping ring <b>223</b>B. This means that no copper seed layer is deposited on the peripheral region of the wafer <b>100</b>, and the edge of the copper seed layer <b>109</b> on the silicon wafer <b>100</b> is defined by the edge of the clamping ring <b>223</b>B. The dimension of the peripheral region free of the deposition of the copper seed layer <b>109</b> is defined by a difference in the inner diameter φ W<b>2</b> of the clamping ring <b>223</b>B of the damper <b>222</b>B and the outer diameter φ W<b>0</b> of the silicon wafer <b>100</b>. Since the inner diameter φ W<b>2</b> of the clamping ring <b>223</b>B of the damper <b>222</b>B in the copper seed chamber <b>206</b> is larger than the inner diameter φ W<b>1</b> of the clamping ring <b>223</b> of the damper <b>222</b> in the TiN barrier chamber <b>205</b>, then the edge of the copper seed layer <b>109</b> is positioned outside the edge of the TiN barrier layer <b>108</b>, whereby the copper seed layer <b>109</b> is deposited not only on the TiN barrier layer <b>108</b> and the clamping ring <b>223</b>B of the damper <b>222</b>B in the copper seed chamber <b>206</b> but also on the silicon wafer <b>100</b> in an outside region defined between the inner diameter φ W<b>2</b> of the clamping ring <b>223</b>B of the copper seed chamber <b>206</b> and the inner diameter φ W<b>1</b> of the clamping ring <b>223</b> of the TiN barrier chamber <b>205</b>. Namely, the TiN barrier layer <b>108</b> is completely covered by the copper seed layer <b>109</b>. The dimension of the outside region of the silicon wafer <b>100</b> is defined by the difference in the inner diameter φ W<b>2</b> of the clamping ring <b>223</b>B of the copper seed layer <b>109</b> and the inner diameter φ W<b>1</b> of the clamping ring <b>223</b> of the TiN barrier layer <b>205</b>.

The wafer <b>100</b> is then carried by the handler <b>208</b> to the second load lock chamber <b>203</b> as the unloading chamber <b>203</b>. The wafer <b>100</b> is then picked out from the second load lock chamber <b>203</b>. Thereafter, the copper plating layer <b>110</b> is then formed on the copper seed layer <b>109</b>. FIG. 5C is a fragmentary cross sectional elevation view illustrative of the silicon wafer formed thereon with the copper plating layer. Since the TiN barrier layer <b>108</b> is completely covered by the copper seed layer <b>109</b>, then the copper plating layer <b>110</b> is completely separated by the copper seed layer <b>109</b> from the TiN barrier layer <b>108</b>.

The copper plating layer <b>110</b>, the copper seed layer <b>109</b> and the TiN barrier layer <b>108</b> are sequentially polished by a chemical and mechanical polishing method so as to leave the copper plating layer <b>110</b>, the copper seed layer <b>109</b> and the TiN barrier layer <b>108</b> only with in the second trench groove and the through hole, whereby the copper electrode <b>111</b> is then formed in the second trench groove formed in the second inter-layer insulator. The entire parts of the copper plating layer <b>110</b> is formed in contact with the surface of the copper seed layer <b>109</b>, for which reason the copper plating layer <b>110</b> is free from the problem with a possibility of peeling from the wafer <b>100</b>. This means that no problem is raised with drop of the yield due to the peeled part of the copper plating layer. Namely, the present invention allows the improvement in the yield of the semiconductor device.

FIG. 6A is a cross sectional elevation view illustrative of another TiN barrier chamber of a deposition system of FIG. 2 before clamping a wafer. FIG. 6B is a cross sectional elevation view illustrative of another TiN barrier chamber of a deposition system of FIG. 2 after having clamped a wafer for a sputtering process for deposition of a titanium nitride layer. The copper seed chamber may also be structured as of the TiN barrier chamber. The wafer <b>100</b> is mounted on a heat stage <b>221</b> accommodated in the TiN barrier chamber <b>205</b>. The wafer <b>100</b> is fixed by an electrostatic chuck <b>227</b> provided on the heat stage <b>221</b>. A titanium nitride target <b>226</b> is provided over the heat stage <b>221</b>. A shield plate <b>225</b> is provided on an inner wall of the TiN barrier chamber <b>205</b> for preventing sputtered titanium nitride from being adhered onto the inner walls of the chamber. No clamper is provided but a sputter mask <b>225</b><i>a </i>is provided which extends from the shield plate <b>225</b> so that the sputter mask <b>225</b><i>a </i>is positioned to cover the peripheral region of the wafer <b>100</b>, so that no deposition of the TiN barrier layer is made onto the peripheral region of the wafer <b>100</b>. The heat stage <b>221</b> is moved in upward and downward directions by a driver <b>224</b>. For the sputtering process, the driver <b>24</b> moves the heat stage <b>221</b> upwardly so that the peripheral region of the wafer <b>100</b> is covered by the sputter mask <b>225</b><i>a </i>extended from the shield plate <b>225</b> to prevent the deposition of the TiN barrier layer on the peripheral region of the wafer <b>110</b>. The sputter mask <b>225</b><i>a </i>is defined by an opening edge thereof which has an inner diameter φ W<b>1</b> smaller than the outer diameter φ W<b>0</b> of the wafer <b>100</b>.

The copper seed chamber <b>206</b> may also be structured as illustrated in FIGS. 6A and 6B. The wafer <b>100</b> is also mounted on a heat stage accommodated in the copper seed chamber <b>206</b>. The wafer <b>100</b> is fixed by an electrostatic chuck provided on the heat stage. A titanium nitride target is provided over the heat stage. A shield plate is provided on an inner wall of the copper seed chamber <b>206</b> for preventing sputtered copper from being adhered onto the inner walls of the chamber. No damper is provided but a sputter mask is provided which extends from the shield plate so that the sputter mask is positioned to cover the peripheral region of the wafer <b>100</b>, so that no deposition of the copper seed layer is made onto the peripheral region of the wafer <b>100</b>. The heat stage is moved in upward and downward directions by a driver. For the sputtering process, the driver moves the heat stage upwardly so that the peripheral region of the wafer <b>100</b> is covered by the sputter mask extended from the shield plate to prevent the deposition of the copper seed layer on the peripheral region of the wafer <b>110</b>. The sputter mask is defined by an opening edge thereof which has an inner diameter φ W<b>2</b> smaller than the outer diameter φ W<b>0</b> of the wafer <b>100</b> but larger than the inner diameter φ W<b>1</b> sputter mask <b>225</b><i>a </i>extended from the shield plate <b>225</b> in the TiN barrier chamber <b>205</b>.

Since the peripheral portion of the wafer <b>100</b> is covered by the sputter mask extended from the shield plate, the copper seed layer <b>109</b> is deposited not only on the TiN barrier layer <b>108</b> over the silicon wafer <b>100</b> but also on the sputter mask extended from the shield plate. This means that no copper seed layer is deposited on the peripheral region of the wafer <b>100</b>, and the edge of the copper seed layer <b>109</b> on the silicon wafer <b>100</b> is defined by the opening edge of the sputter mask extended from the shield plate. The dimension of the peripheral region free of the deposition of the copper seed layer <b>109</b> is defined by a difference in the inner diameter φ W<b>2</b> of the sputter mask extended from the shield plate and the outer diameter φ W<b>0</b> of the silicon wafer <b>100</b>. Since the inner diameter φ W<b>2</b> of the sputter mask extended from the shield plate in the copper seed chamber <b>206</b> is larger than the inner diameter φ W<b>1</b> of the sputter mask extended from the shield plate in the TiN barrier chamber <b>205</b>, then the edge of the copper seed layer <b>109</b> is positioned outside the edge of the TiN barrier layer <b>108</b>, whereby the copper seed layer <b>109</b> is deposited not only on the TiN barrier layer <b>108</b> and the sputter mask extended from the shield plate in the copper seed chamber <b>206</b> but also on the silicon wafer <b>100</b> in an outside region defined between the inner diameter φ W<b>2</b> of the sputter mask extended from the shield plate of the copper seed chamber <b>206</b> and the inner diameter φ W<b>1</b> of the sputter mask extended from the shield plate of the TiN barrier chamber <b>205</b>. Namely, the TiN barrier layer <b>108</b> is completely covered by the copper seed layer <b>109</b>. The dimension of the outside region of the silicon wafer <b>100</b> is defined by the difference in the inner diameter φ W<b>2</b> of the sputter mask extended from the shield plate of the copper seed chamber <b>206</b> and the inner diameter φ W<b>1</b> of the sputter mask extended from the shield plate of the TiN barrier chamber <b>205</b>.

The wafer <b>100</b> is then carried by the handler <b>208</b> to the second load lock chamber <b>203</b> as the unloading chamber <b>203</b>. The wafer <b>100</b> is then picked out from the second load lock chamber <b>203</b>. Thereafter, the copper plating layer <b>110</b> is then formed on the copper seed layer <b>109</b>. Since the TiN barrier layer <b>108</b> is completely covered by the copper seed layer <b>109</b>, then the copper plating layer <b>110</b> is completely separated by the copper seed layer <b>109</b> from the TiN barrier layer <b>108</b>.

The copper plating layer <b>110</b>, the copper seed layer <b>109</b> and the TiN barrier layer <b>108</b> are sequentially polished by a chemical and mechanical polishing method so as to leave the copper plating layer <b>110</b>, the copper seed layer <b>109</b> and the TiN barrier layer <b>108</b> only with in the second trench groove and the through hole, whereby the copper electrode <b>111</b> is then formed in the second trench groove formed in the second inter-layer insulator. The entire parts of the copper plating layer <b>110</b> is formed in contact with the surface of the copper seed layer <b>109</b>, for which reason the copper plating layer <b>110</b> is free from the problem with a possibility of peeling from the wafer <b>100</b>. This means that no problem is raised with drop of the yield due to the peeled part of the copper plating layer. Namely, the present invention allows the improvement in the yield of the semiconductor device.

In the above embodiment, the buried copper electrode is formed in the trench groove and the through hole which are formed in the second level inter-layer insulator. Notwithstanding, the above present invention is applicable to the other cases, where the copper electrode is formed in at least one of the groove and the through hole of the upper level inter-layer insulator than the second level inter-layer insulator.

The TiN barrier chamber and the copper seed chamber may be provided in separate or different deposition systems.

As a further modification, it is possible that the damper is fixed in position whilst the heat stage is movable in upward and downward directions by the driver so that the wafer is made into contact with the bottom surface of the clamp ring of the damper for masking the peripheral region of the wafer to prevent the deposition of the TiN barrier layer and the copper seed layer.

Whereas modifications of the present invention will be apparent to a person having ordinary skill in the art, to which the invention pertains, it is to be understood that embodiments as shown and described by way of illustrations are by no means intended to be considered in a limiting sense. Accordingly, it is to be intended to cover by claims all modifications which fall within the spirit and scope of the present invention.