Method of forming recessed thin film landing pad structure

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to interconnection between wiring in multilayer electrical and electronic devices and more particularly to via interconnections and methods of manufacture thereof.

2. Description of Related Art

U.S. Pat. No. 5,716,218 of Farnsworth et al. for “Process for Manufacturing an Interconnect for Testing a Semiconductor Die” shows a structure, and a process of manufacture of a compliant interconnect wherein a series of contacts are formed conformally over an undulating insulator layer with tapered side walls where the structure shape is optimized for the ability to connect to another electrical component.

U.S. Pat. No. 5,861,344 of Roberts et al. for “Facet Edge for Improved Step Coverage of Integrated Circuit Contacts” describes a structure and a method for providing a facet etch to improve step coverage where two conductive layers converge at and in a via hole; and over at least one layer of insulation to improve the structural integrity of a via having a fixed geometry. The contact area, and thus the maximum potential electrical performance are not increased.

U.S. Pat. No. 5,998,295 of Madurawe for “Method of Forming a Rough Region on a Substrate” describes a method of forming a rough region over a substrate, where a metal line converges into a contact over at least one layer of insulation. Methods are described for creating variations in topology of a semiconductor surface for the sole purpose of achieving optical reference points on an otherwise flat surface to enable visual alignment for process tooling. The patent does not relate to any electrical properties of the semiconductor.

U.S. Pat. No. 6,013,547 of Liaw for “Process for Creating a Butt Contact Opening for a Self-Aligned Contact Structure” describes a method of forming a metal connection (via a butt contact opening) between a gate structure and active semiconductor devices. The process of Liaw is employed primarily for manufacturing MOSFET SRAM (N type and P type) devices. After the devices and gates are constructed a step of etching by RIE with methyl trifluoride gas (CHF₃) is used to remove silicon oxide capping the gate structures to make openings for connection to the gates of FET devices. There is a process problem that the invention addresses, which is the undesired removal, during the silicon oxide RIE step, of portions of lightly doped source and drain regions in addition to removal of areas of device isolation insulators. The Liaw patent teaches applying an organic layer, polyimides or BARC (bottom anti-reflective coatings), over the layer before RIE etching the butt contact opening. The organic layer then protects the source and drain regions as well as the insulator areas during RIE of the silicon oxide. The organic and silicon oxide are removed at different rates in RIE, in addition various RIE chemistries can be used to control removal rates. The Liaw patent describes a method of protecting areas of the structure from removal during connection formation, but it does not describe a way to increase the bottom contact area. No patterning is done to layers below the layer being processed to enhance connection area, which one of the key features of the present invention. The Liaw patent describes a sequence of process steps that may be used on the layer being processed to control the area where material is removed. In summary, the Liaw patent describes a way to limit the regions where material is removed during device connection formation.

U.S. Pat. No. 5,834,365 of Ming-Tsung Liu et al. for a “Method of Forming a Bonding Pad” describes method of bonding, where, a plurality of metal layers converge over an undulating insulator layer and forms an additional bond area (pad) by creating metal features on the layer below. These features replicate up into the bond pad. The features used to increase bond area use real estate that could otherwise be used for active features. This technique would potentially reduce wireability. The Liu et al. patent builds features with some photolithography and metallization steps, to get features on a fine enough scale to affect the via areas we have would require semiconductor manufacturing processes. Features that fine would be totally planarized by polyimide insulators as thick as are used in Thin Film (TF) packaging. It appears that the bonding pad described applies to features in the 100's of microns, but does not apply to features in the 10's of microns. It probably cannot be used in internal wiring levels, there may not be “free” space to build the topography enhancement features in internal wiring levels.

See U.S. Pat. No. 5,494,853 of Lur for “Method to Solve Holes in Passivation by Metal Layout” and U.S. Pat. No. 5,956,615 of Nguyen et al. for “Method of Forming a Metal Contact to Landing Pad Structure in an Integrated Circuit.”

FIGS. 1A-1C are cross-sectional views of sequence of steps in the manufacture of a device <b>10</b> which illustrate a Prior Art method of forming a thin film via <b>27</b> (FIG. 1C) through a polyimide layer <b>24</b> which provides interconnection between a top conductor line <b>28</b> above an upper polyimide layer <b>24</b> and another conductor line <b>17</b> below the polyimide layer <b>24</b>.

In FIG. 1A, a Prior Art device <b>10</b> is shown in an intermediate stage of fabrication. Device <b>10</b> is formed on a planar substrate <b>12</b> composed of a non-conductive material such as undoped silicon semiconductor material or a dielectric material. Initially, a first conductor line <b>14</b>, which comprises a thin metal film is formed on the planar surface of the substrate <b>12</b>. Then a planar, first polyimide layer <b>16</b> was formed covering the first conductor line <b>14</b> as well as the exposed surface of the substrate <b>12</b>. However, subsequent to formation of planar, first polyimide layer <b>16</b>, a via hole <b>15</b> therethrough was filled with the metallization of a via <b>18</b> which was formed through the first polyimide layer <b>16</b>. The via hole <b>15</b> reached down to expose a portion of the conductor line <b>14</b>. Then, an intermediate, second, conductor line <b>17</b> was formed on the surface of the planarized, first polyimide layer <b>16</b> reaching down into the via hole <b>15</b> to form the via <b>18</b> with the intermediate, second, conductor line <b>17</b> in electrical and mechanical contact with first conductor line <b>14</b>. As will be well understood by those skilled in the art, a widened area of the line segment <b>17</b>, often referred to as a landing pad <b>19</b> is formed in a line segment where a second via <b>27</b> is to be formed. As shown the line <b>17</b> and the metal landing pad <b>19</b> are planar and are formed on the flat planar surface of the polyimide layer <b>16</b> so that from the cross-sectional view in FIGS. 1B and 1C no recognizable difference its configuration or thickness can be discerned. Then a planarized, second polyimide layer <b>24</b> was formed covering the intermediate, second, conductor line <b>17</b> and the exposed surface of the first polyimide layer <b>16</b>.

In FIG. 1B, the device of FIG. 1A is shown after a via hole <b>26</b> with sidewalls <b>26</b>W has been formed through the second polyimide layer <b>24</b> exposing a portion of the surface of the intermediate, second, conductor line <b>17</b>, which comprises a thin metal film. The via hole <b>26</b> with sidewalls <b>26</b>W has been formed by ablation with an excimer laser beam <b>29</b> passing through opening <b>25</b>′ in a laser mask <b>25</b> which blocks the laser beam <b>29</b> from reaching other portions of the device <b>10</b>. The etching of the second polyimide layer <b>24</b> by the laser beam <b>29</b> was stopped at the time at which the top surface of conductor line <b>17</b> was exposed. The via <b>26</b> hole and via <b>27</b> may be formed at the terminating end of line <b>17</b>.

In FIG. 1C, the device <b>10</b> of FIG. 1B is shown after a third conductor line <b>28</b> was formed on the surface of the planarized, second polyimide layer <b>24</b> reaching down to form a second via <b>27</b> with sidewalls <b>27</b>W over the sidewalls <b>26</b>W of the via hole <b>26</b>. The third conductor line <b>28</b> is in electrical and mechanical contact with the intermediate, second, conductor line <b>17</b>. The location of an ablated hole <b>26</b> in which the via <b>27</b> is formed is located over the widened area of the line segment <b>17</b> comprising the landing pad <b>19</b>.

SUMMARY OF THE INVENTION

While the Liaw patent, above, describes a method of protecting areas of the structure from removal during connection formation, it does not describe a way to increase bottom contact area as does the present invention. No patterning is done to layers below the layer being processed to enhance connection area, which one of the key features of the present invention. Unlike Liaw, the present invention describes a way to increase via connection area, without increasing via diameters or loosening ground rules.

The contact area, and the maximum potential electrical performance is increased by the present invention which increases the via contact area, providing a robust connection with increased contact area and thus enhanced electrical properties.

The present invention creates additional via area by ablating the polyimide under the via, without affecting features sizes, ground rules or free active area.

Current landing pads for thin film vias are flat. Increasing via contact area will result in a more reliable connection modifications to existing via ablation (widening the ablation) will increase via contact at the expense of capture criteria

In accordance with this invention, partially ablate the polyimide at subsequent via locations using the next via mask at the same level as the current vias are created masks are already available little added cycle time. Modifications to current ablation criteria fill the landing zone, without sacrificing the capture criteria with. That modification is required to account for deeper penetration depth due to the recess.

Further in accordance with this invention, a method of fabricating a via connection between two conductor lines formed above and below an insulating material comprises the following steps.

Form a recess in a top surface of a lower layer which is electrically relatively non-conductive or dielectric.

Form a first conductor line on the top surface of the lower layer reaching over at least a portion of the recess.

Form an upper layer composed of a dielectric material over the top surface of the lower layer and covering the first conductor line at least within the proximity of the recess.

Form a via hole reaching down toward the recess exposing the surface of the conductor line above the recess.

Form an intermediate, second, conductor line reaching down into the via hole into contact with the first conductor line above the recess.

Preferably, the lower layer and the upper layer comprise polymeric materials such as polyimide; the recess and the via are both formed by laser ablation of the lower layer and the same laser mask is employed for forming the recess and for forming the via; the recess has tapered walls and has a bottom within the lower layer; the via hole is formed by laser ablation of a hole through the upper layer having tapered walls and having a bottom exposing the intermediate, second, conductor line; the lower layer and the upper layer consist of polyimide material having a thickness of from about 7-10 micrometers.

Preferably, the laser ablation of the via hole is performed with a xenon/chlorine excimer laser in accordance with the parameters as follows:

<tables><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="77pt" align="left" /><colspec colname="2" colwidth="126pt" align="left" /><thead><row><entry /><entry namest="OFFSET" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>Wavelength:</entry><entry>308 nanometers</entry></row><row><entry /><entry>Hertz:</entry><entry>300 pulses per second</entry></row><row><entry /><entry>Pulse duration:</entry><entry>roughly 20 nanoseconds</entry></row><row><entry /><entry>Fluence:</entry><entry>190 millijoules per square centimeter</entry></row><row><entry /><entry>Number of pulses:</entry><entry>300</entry></row><row><entry /><entry namest="OFFSET" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

and the laser ablation of the recess is performed with a xenon/chlorine excimer laser in accordance with the parameters as follows:

<tables><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="77pt" align="left" /><colspec colname="2" colwidth="126pt" align="left" /><thead><row><entry /><entry namest="OFFSET" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>Wavelength:</entry><entry>308 nanometers</entry></row><row><entry /><entry>Hertz:</entry><entry>300 pulses per second</entry></row><row><entry /><entry>Pulse duration:</entry><entry>roughly 20 nanoseconds</entry></row><row><entry /><entry>Fluence:</entry><entry>190 millijoules per square centimeter</entry></row><row><entry /><entry>Number of pulses:</entry><entry>20</entry></row><row><entry /><entry namest="OFFSET" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which:

FIGS. 1A-1C are cross-sectional views of sequence of steps in the manufacture of a device which illustrate a Prior Art method of forming a thin film via through a polyimide layer to provide interconnection between two wiring lines.

FIGS. 2A-2G are a series of cross-sectional views of a sequence of steps in the manufacture of a thin film device producing an improved via in a device in accordance with this invention.

FIG. 3 is a sketch of the parameters of a cross section of landing pad in accordance with this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIGS. 2A-2G are a series of cross-sectional views of a process of forming a via in a thin film device in accordance with this invention. FIGS. 2A-2G show the process of manufacturing a device <b>40</b> which illustrates the sequence of steps of the method of this invention.

The product seen in FIG. 2G yields an improved thin film upper via <b>67</b> in accordance with this invention. The upper via <b>67</b> extends through a polymeric material layer <b>54</b> which provides interconnection between a top conductor line <b>58</b> above the upper polymeric layer <b>54</b> and intermediate conductor line <b>47</b> below the upper polymeric layer <b>54</b>. In this preferred embodiment, the polymeric layer <b>54</b> is polyimide, so hereinafter the polymeric layer <b>54</b> will be referred to as polyimide which is a superior material for supporting and encapsulating electrically conductive elements especially in semiconductor packages and semiconductor elements. An alternative to polyimide is epoxy.

FIGS. 2A-2G are a series of cross-sectional views of a device <b>40</b> which illustrate a sequence of steps employed in method of forming a thin film second, upper via <b>67</b> (FIG. 2G) through a planar, second, upper polyimide layer <b>54</b>. Upper via <b>67</b> provides interconnection between a top, third conductor line <b>58</b> above the planar, upper polyimide layer <b>54</b> and the intermediate (second) conductor line <b>47</b> below the upper polyimide layer <b>54</b>.

In FIG. 2A, the device <b>40</b> is shown in a relatively early intermediate stage of fabrication. Device <b>40</b> is formed on a planar substrate <b>42</b> composed of a non-conductive material such as undoped silicon semiconductor material or a dielectric material. Initially, a first conductor line <b>44</b>, which comprises a thin metal film is formed on the planar surface of the substrate <b>42</b>. Then a planar, first polyimide layer <b>46</b> was formed covering the first conductor line <b>44</b> as well as the exposed surface of the substrate <b>42</b>. While the first conductor line <b>44</b> is shown parallel to the plane of the drawing, it can be directed at any angle on the top surface of substrate <b>42</b>.

Referring to FIG. 2B, the device <b>40</b> of FIG. 2A is shown subsequent to formation, by a laser ablation step, of the planar, first polyimide layer <b>46</b> a first via hole <b>45</b> with sloping sidewalls <b>45</b>W. The first via hole <b>45</b> reaches down through to the bottom of first polyimide layer <b>46</b> thereby exposing a portion of the first conductor line <b>44</b> which at the bottom of the first via hole <b>45</b>. The first via hole <b>45</b> with sidewalls <b>45</b>W has been formed by ablation with an excimer laser beam <b>32</b> passing through opening <b>31</b> through a mask <b>30</b> which blocks the laser beam <b>32</b> from reaching other portions of the first polyimide layer <b>46</b>.

Referring to FIGS. 2C and 2F, this invention involves utilizing a laser ablation via mask <b>34</b> for forming a via hole <b>66</b> through an upper level polyimide layer <b>54</b> of device <b>40</b> to form a shallow recess <b>37</b>/<b>37</b>W comprising a landing pad depression in a first/lower polyimide layer <b>46</b> at the location that a subsequent via <b>67</b> will be placed as seen in FIG. <b>2</b>G.

Referring to FIG. 2C, the device <b>40</b> of FIG. 2B is shown subsequent to formation of the shallow recess <b>37</b> with sidewalls <b>37</b>W (i.e., a depression in the surface of the first polyimide layer <b>46</b>) by a second laser ablation step. The second laser ablation step is performed by an excimer laser beam <b>36</b> passing through opening <b>35</b> through a mask <b>34</b> which blocks the laser beam <b>36</b> from reaching other portions of the first polyimide layer <b>46</b>. The bottom of the shallow recess <b>37</b> is substantially above the bottom of layer <b>46</b> and conductor <b>44</b> leaving an adequate thickness to provide electrical insulation between the recess <b>37</b> and conductor <b>44</b>.

Referring to FIG. 2D, the device <b>40</b> of FIG. 2C is shown subsequent to formation of the intermediate (second) conductor line <b>47</b> composed of a thin film of metallization extending across the planarized, first polyimide layer <b>46</b> into the via hole <b>45</b>/<b>45</b>W reaching down to contact the exposed portion of the conductor line <b>44</b> and forming a metal via pad <b>39</b>/<b>39</b>W in the recess <b>37</b>/<b>37</b>W of FIG. <b>2</b>C . The intermediate (second) conductor line <b>47</b> reaches across sloping sidewalls <b>45</b>W and across the bottom of first via hole <b>45</b> into contact with the first conductor line <b>44</b> to form a lower via <b>48</b> with the intermediate (second) conductor line <b>47</b> in electrical and mechanical contact with first conductor line <b>44</b>. The intermediate (second) conductor line <b>47</b> also reaches across sloping sidewalls <b>37</b>W and the bottom surface of the shallow recess <b>37</b> to form a metal landing pad <b>39</b> for a upper via <b>67</b> which is to be formed in a subsequent step as shown in FIG. <b>2</b>G. The intermediate (second) conductor line <b>47</b> is shown parallel to the plane of the drawing which has been selected to be in the plane which reveals the connections of intermediate (second) conductor line <b>47</b> to vias <b>45</b> and <b>67</b>.

As will be well understood by those skilled in the art, metal landing pad <b>39</b> comprises a widened segment (area) of the intermediate (second) conductor line <b>47</b> where the upper via <b>67</b> is to be formed. As shown the intermediate (second) line <b>47</b> and the metal landing pad <b>39</b> are planar and are formed on the flat planar surface of the polyimide layer <b>46</b> so that no recognizable difference its configuration or thickness can be discerned in the cross-sectional views seen in FIGS. 2D-2G.

Referring to FIG. 2E, the device <b>40</b> of FIG. 2D is shown subsequent to formation of a planarized, second polyimide layer <b>54</b> covering the intermediate (second) conductor line <b>47</b> and the exposed surfaces of the first polyimide layer <b>46</b>.

In FIG. 2F, the device of FIG. 2E is shown after a via hole <b>66</b> with sidewalls <b>66</b>W has been formed through the second polyimide layer <b>54</b> exposing a portion of the surface of the intermediate (second) conductor line <b>47</b>, which comprises a thin metal film. The via hole <b>66</b> with sidewalls <b>66</b>W has been formed by ablation with virtually the same excimer laser beam <b>36</b>′ as in FIG. 2C passing through the same opening <b>35</b> through the same mask <b>34</b> as in FIG. <b>2</b>C. Mask <b>34</b> is reused in the step illustrated by FIG. 2F to assure correct alignment and to minimize mask preparation expense. As in FIG. 2C, mask <b>34</b> blocks the laser beam <b>36</b>′ from reaching other portions of the device <b>40</b>. The ablation of the second polyimide layer <b>54</b> by the laser beam <b>36</b>′ was stopped at the time at which the top surface of intermediate (second) conductor line <b>47</b> was exposed. The via <b>66</b> hole (and upper via <b>67</b> shown in FIG. 2G) may be formed at the terminating end of intermediate (second) conductor line <b>47</b>.

In FIG. 2G, the device <b>40</b> of FIG. 2F is shown after a third conductor line <b>68</b> was formed on the surface of the planarized, second polyimide layer <b>54</b> reaching down across sidewalls <b>66</b>W into via hole <b>66</b> to form a second upper via <b>67</b> with sidewalls <b>67</b>W extending over the sidewalls <b>66</b>W of the via hole <b>66</b>. The upper (third) conductor line <b>68</b> is in electrical and mechanical contact with the intermediate (second) conductor line <b>47</b>. The location of an ablated hole <b>66</b> in which the upper via <b>67</b> is formed is located over the widened area of the intermediate (second) conductor line segment <b>47</b> comprising the metal landing pad <b>39</b>. While the third conductor line <b>68</b> is shown parallel to the plane of the drawing it can be directed at any angle on the top surface of second polyimide layer <b>54</b> just so long as it traverses the via opening <b>66</b> thereby forming the upper via <b>67</b>.

Process Parameters for Laser Ablation to Form Vias and to Form Recessed Landing Pads

In practicing the above process/method of this invention, the preferred methods of forming via holes <b>66</b> through a polyimide layer <b>54</b> in FIGS. <b>2</b>B/<b>2</b>F and/or forming landing pad recesses <b>37</b> in FIG. 2C are described in Tables I and II below respectively.

<tables><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217pt" align="center" /><thead><row><entry namest="1" nameend="1" rowsep="1">TABLE I</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row><row><entry>Via hole ablation process: Laser- Xe/Cl (Xenon/Chlorine) pulsed</entry></row><row><entry>Excimer Laser</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="105pt" align="left" /><colspec colname="2" colwidth="112pt" align="left" /><tbody valign="top"><row><entry>Wavelength</entry><entry>308 nanometers</entry></row><row><entry>Hertz:</entry><entry>300 pulses per second</entry></row><row><entry>Pulse duration:</entry><entry>roughly 20 nanoseconds</entry></row><row><entry>Fluence:</entry><entry>190 millijoules per square centimeter</entry></row><row><entry>Number of pulses:</entry><entry>300</entry></row><row><entry>Typical thickness of the ablated</entry><entry>7-10 microns</entry></row><row><entry>polyimide polymer for via ablation</entry></row><row><entry>on a product</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

<tables><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217pt" align="center" /><thead><row><entry namest="1" nameend="1" rowsep="1">TABLE II</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row><row><entry>Ablation process for Recessed/Depressed Landing Pad for via interface</entry></row><row><entry>Laser: Xe/Cl (Xenon/Chlorine) pulsed Excimer Laser</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="77pt" align="left" /><colspec colname="2" colwidth="126pt" align="left" /><tbody valign="top"><row><entry /><entry>Wavelength</entry><entry>308 nanometers</entry></row><row><entry /><entry>Hertz:</entry><entry>300 pulses per second</entry></row><row><entry /><entry>Pulse duration:</entry><entry>roughly 20 nanoseconds</entry></row><row><entry /><entry>Fluence:</entry><entry>190 millijoules per square centimeter</entry></row><row><entry /><entry>Number of pulses:</entry><entry>20</entry></row><row><entry /><entry namest="OFFSET" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

As can be seen, the ratio of the number of pulses for formation of a recess to the number of pulses for forming a via hole is (300/20=15) which means that the ratio is greater than an order of magnitude.

To create a landing pad recess/depression <b>37</b> in FIG. 2C in the polyimide layer <b>46</b> to be located under an upper via <b>67</b> (which upper via <b>67</b> is to be formed thereabove subsequently), the number of pulses was limited to 20, all other parameters were the same as a normal ablation process.

Typical ablation etch rates of polyimides used on line at 308 nm are 0.06 to 0.08 microns per pulse. Twenty (20) pulses resulted in a recess/depression <b>37</b> in FIG. 2C approximately 1.5 microns deep.

Advantages of the Present Invention

This method and structure of this invention results in significantly more metal contact area in each via (e.g. a 30% increase in contact area). The structure also provides a much more stable interface, eliminating a sharp interface structure while also geometrically isolating the line to reduce thermal stress effects. Via defects are a consistent source of defects which either result in the loss of assets (scrap) or significant rework.

This invention results in better metal-to-metal contact between line <b>68</b> and intermediate (second) conductor line <b>47</b> at upper via <b>67</b> in FIG. 2G by increasing the area of contact because intermediate (second) conductor line of the increased surface area created by the formation of the recess/depression with its tapered sidewalls <b>66</b>W/<b>67</b>W. It also allows the metal line <b>68</b> to make contact to intermediate (second) conductor line <b>47</b> at a low angle of incidence, significantly reducing the stress effects which lead to subsequent via failure.

Since via defects are a main yield detractor in processing of thin film devices, this enhanced contact structure and method provide a significant advance in the state of the art.

FIG. 3 is a sketch of the parameters of a cross section of landing pad in accordance with this invention. The benefits of the present invention are increased yield/cycle time due to fewer via related Electric Module Tester (EMT) defects are better contact between levels due to greater contact area (approximately 25%) 25% based on comparing the contact area of a flat circular area (diameter=20 μm) to that obtained by calculating the area of a rotated trapezoid shown in FIG. 3 with a width of 20 μm and a height of 2 μm. The total via area results have been calculated to be: 40.75 mm²vs. 32.56 mm². The actual contact area approaches estimate as metal thickness becomes a thinner more stable structure due to anchoring of line at the via location in the recess.

While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e., that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.