Method and apparatus for isolating a computer system upon detection of viruses and similar data

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to computer systems. More particularly, this invention relates to a method and apparatus for isolating a computer system upon detection of a virus and similar data.

2. The Prior Art

Recently, transmission of data viruses over the Internet has become a serious concern for Internet users. To reduce the concern, several methods are used to isolate computers from the Internet while the users are in local mode. However, when users of such methods are in a connected mode, they become prey to any virus that they may unwittingly download.

Computer virus scanners are common and can be used to detect a virus once it is downloaded. However, such scanners cannot prevent the virus from being downloaded. They can only aid in the identification of a virus once it has already infected the user's computer.

Nowhere does the prior art disclose a method or apparatus for detecting a virus as it is being received from a network and isolating the user's computer from the Internet when an incoming virus is detected.

SUMMARY OF THE INVENTION

The above-noted disadvantages of the prior art are overcome by the present invention, which in one aspect is an apparatus for isolating a data receiving entity from a data sending entity. A first data channel is coupled to the data sending entity and a second data channel is coupled to the data receiving entity. A processor is operationally coupled to the first data channel and detects a data virus received from the first data channel. An isolation circuit that is responsive to the processor couples the first data channel to the second data channel when the processor does not detect a data virus and isolates the first data channel from the second data channel when the processor detects a data virus.

In another aspect, the invention includes a first data channel coupled to the data sending entity and a second data channel coupled to the data receiving entity. A processor that is programmed to compare a plurality of data words received from the first data channel to at least one data word characteristic of a data virus asserts a control signal when a data word received from the first data channel corresponds to a data word characteristic of a data virus. A memory, that is operationally coupled to the processor, stores at least one data word characteristic of a data virus. The memory presents to the processor at least one data word characteristic of a data virus and an input buffer stores data received by the processor from the first data channel. An optical isolator, coupled to the first data channel and the second data channel and having an enable signal input, is capable of isolating the first data channel from the second data channel when the enable signal input is not asserted and is also capable of placing the first data channel and the second data channel in optical communication with each other when the enable signal input is asserted. A controllable power supply that is responsive to the control signal from the processor is coupled to the enable signal input of the optical isolator. The power supply asserts the enable signal when the control signal is not asserted and does not assert the enable signal when the control signal is asserted, thereby causing the optical isolator to isolate the first data channel from the second data channel.

In yet another aspect, the invention is a method for isolating data receiving entity from a data sending entity. When a data virus received from the data sending entity is detected, the data sending entity is isolated from the data receiving entity.

An advantage of the invention is that it prevents a data receiving entity, such as a computer, from receiving a virus from a data sending entity, such as a computer network.

A further advantage of the invention is that it isolates the data sending entity from the data receiving entity without disrupting normal operation of either entity.

These and other advantages will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings, although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure.

BRIEF DESCRIPTION OF THE FIGURES OF THE DRAWINGS

FIG. 1 is a simplified schematic diagram of the invention.

FIG. 2 is a detailed schematic diagram of the invention.

DETAILED DESCRIPTION OF THE INVENTION

A preferred embodiment of the invention is now described in detail. Referring to the drawings, like numbers indicate like parts throughout the views. As used in the description herein and throughout the claims that follow, "a," "an," and "the" includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of "in" includes "in" and "on" unless the context clearly dictates otherwise.

As shown in FIG. 1, the apparatus 10 of the invention evaluates data received from a data sending entity 20, such as the Internet, by a data receiving entity 30, such as a personal computer or even a local area network. The data is received via a first data channel 22 coupled to the data sending entity 20 and a second data channel 32 coupled to the data receiving entity. A data comparitor 40 is operationally coupled to the first data channel 22 and is used to detect data viruses received from the first data channel 22. When a virus is detected, a data isolator 60, that is responsive to a control signal 42 from the data comparator 40, isolates the first data channel 22 from the second data channel 32. Thus, viruses are detected and prevented from being received by the data receiving entity 30.

As shown in FIG. 2, the apparatus 10 of one preferred embodiment of the invention interfaces with a peripheral control interface (PCI) 12 of a data receiving entity 30, such as a personal computer, to provide isolation from a data sending entity 20, such as the Internet. The data sending entity 20 is connected to an input interface 24, such as a standard PBX interface, via a first data channel 22. The data stream received by the input interface 24 is demodulated using a demodulator circuit 26 so as to conform to the data format of the data receiving entity 30.

The data stream is then fed into the data comparator 40. In the comparitor circuit 40, a UART chip 46 formats the incoming serial data into parallel data words and a processor 44, such as a PCI host controller, using an asynchronous transfer mode segmentation and reassembly, compares the parallel data with known virus signatures stored in a memory 48, such as an EEPROM. The processor 44, which is controlled by a control memory 50, buffers data from the UART chip 46 in a memory chip 52 as it awaits virus scanning analysis.

After the processor 44 has analyzed an incoming word, it is then sent to the data isolator 60 for eventual transfer to the data receiving entity 30. The data isolator 60 comprises an optical isolator 62 that is driven by a power enable signal 66 received from a power supply conditioning ISO drive 64. The power supply conditioning ISO drive 64 receives power from a power up control logic circuit 54 which receives power from a power line 74 in the PCI bus 12.

If no virus is found, the data stream is transferred through the optical isolator 62 to a modulation level shifting circuit 68, that conditions the data for receipt by the data receiving entity 30, to a modem interface 34. The modem interface 34 provides protocol matching to the input interface 24 and sends the data to the data receiving entity 30.

When a virus is detected in the incoming data stream, a control line 42 from the processor 44 causes the power up control logic circuit 54 to cause the power supply conditioning ISO drive 64 to cut off power to the optical isolator 62, thereby causing the optical isolator 62 to prevent passage of data therethrough. A modem standby circuit 36 then takes over and simulates protocol exchanges with the input interface 24, thereby preventing an abnormal disconnect.

During power-up, the processor 40 runs the system through a self checking routine. If any system abnormalities are detected, an interrupt line 70 is asserted. The interrupt line 70 passes through an optical isolator 14 to ensure unidirectional data transmission to the PCI bus 12.

The power up control logic circuit 54 also performs a self check. a battery reference 56 is compared to the value on the incoming power line 74 from the PCI bus 12, and if the system is improperly powered, an interrupt line 72 is asserted. The interrupt line 72 is also passed through an optical isolator 16 that ensures that the interrupt line 72 is unidirectional to the PCI bus 12.

The above described embodiment is given as an illustrative example only. It will be readily appreciated that many deviations may be made from the specific embodiment disclosed in this specification without departing from the invention. Accordingly, the scope of the invention is to be determined by the claims below rather than being limited to the specifically described embodiment above.