Digital bit synchronizer

[57] ABSTRACT

A system for deriving synchronizing pulses from a train of digital signals that is fed to in-phase and midphase gates each including an adder with a delay feedback. The output of the mid-phase gate is multiplied by a sign factor determined by a logic circuit connected to the in-phase gate. The output of the two gates are then mixed, filtered, and summed with a value dependent upon the clock rate and fed to a number controlled oscillator which includes a counter and a comparing circuit. The output of the number controlled oscillator is fed back to the in-phase and mid-phase gates.

Claims, 8 Drawing Figures

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PATENTED NOV 131973

3,772,600

SHEET 1 GF 4 ig.u

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PATENTED NOV 131973

3,772,600

SHEET 2 GF 4

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PATENTED HOY 131973

3,772.600

SHEET 3 CF 4

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PATENTED ml 3 B73

3,772,600

SHEET U OF 4

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ΣΕ^ΙΕ.6

3,772,600

DIGITAL BIT SYNCHRONIZER

BACKGROUND OF THE INVENTION

This invention relates to timing synchronizing and more particularly to a system deriving bit synchronization from digital samples.

In electronic systems using digital data detectors there is a need for obtaining bit synchronization usually derived from the received signal. The present invention presents a novel and improved system for obtaining the necessary bit synchronization from a sequence of digital samples taken from binary synchronization usually derived from the received signal. The present invention presents a novel and improved system for obtaining the necessary bit synchronization from a sequence of digi- 15 tai samples taken from binary waveforms.

SUMMARY OF THE INVENTION

In order to illustrate a means of obtaining a measure of the phase error, consider the set of samples S,, S₂,.

. . S₈ from one bit and S₉, S_lo,... S_I6 from the previous bit where S, is the most recent sample.

A means of generating the phase error signal is as follows. The phase error signal is generated by a midphase (MP) gate which performs the summation,

Smp = Si i=5 an in-phase (IP) gate forms the sums

S,_P(n) = f S.·

The digital bit synchronizer is basically a digital phase lock loop which is capable of tracking samples of 20 a binary waveform. Since transitions may or may not occur between adjacent bits, a nonlinear operation is required in the phase detector to insure the output has the proper sign.

It is an object of this invention to provide a novel and 25 improved system for synchronizing bits from a train of digital samples.

It is another object to provide a synchronizer in the form of a digital phase-locked loop which is capable of tracking samples of a binary data waveform. ³⁰

It is yet another object to provide a system for synchronizing bits of a binary waveform where transitions may occur between adjacent bits.

These and other objects, features and advantages of the invention will become more apparent from the fol- ³⁵lowing description taken in connection with the illustrative embodiments in the accompanying drawings.

DESCRIPTION OF THE DRAWINGS

FIGS, la through Ic are waveform diagrams showing ⁴θ the derivation of bit synchronizing pulses derived from a data impulse wave.

FIG. 2 is an input/output detector characteristic curve of the digital bit synchronizer.

FIG. 3 is a block diagram showing an embodiment of ⁴⁵the invention;

FIG. 4 is a block diagram of the loop filter used in the embodiment of FIG. 3;

FIG. 5 is a block diagram showing the details of the in-phase and mid-phase detectors and associated logic ⁵used in the embodiment of FIG. 3; and

FIG. 6 is a block diagram of the number controlled oscillator used in the embodiment of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED 55 EMBODIMENTS

Digital data detectors generally require some type of bit synchronization usually derived from the received signals. The present invention has the capability of de- ₆θ riving bits from a sequence of digital samples taken from a binary waveform such as that shown in FIG. la which is a basic data waveform having a pulsewidth of T. Samples are taken as shown in FIG. lb, the samples being represented by arrows with the time difference ₆₅between samples being shown as T,. The bit synchronization pulses are then derived and are shown in FIG. Ic as vertical lines.

and

Sip(n — 1) = i=9

The output of the mid-phase gate is then multiplied by +1, 0, or —1, based on the following logic rules:

S_IP(n— 1) &gt; 0, S_IP(n) &lt; 0; multiply by +1 (opposite signs)

S_rP(n— 1) &lt; 0, S,p(n) &gt; 0; multiply by —1 (opposite signs)

S_IP(n— 1) and S_IP(n) are the same sign; multiply by 0.

The resulting phase error detector characteristic is shown in FIG. 2 where A represents the signal amplitude, N the number of samples in the mid-phase gate, 2A the step height, and 1/N the step width.

A block diagram of the digital bit synchronizer employing the in-phase and mid-phase (IP/MP) detectors is shown in FIG. 3. The digital input signal is fed to inphase gate 11 together with the clock pulses. Gate 11 includes summing circuit 13 and feedback delay 15. The sign is determined by circuit 17 and then fed to logic circuit 19 where the logic previously explained is performed. The digital input data and clock pulses are also fed to mid-phase gate 21 including summing circuit 23 and feed-back delay 25. The output of midphase gate 21 is fed to delay circuit 27 and is then mixed in mixer 29 with the output of logic circuit 19. The output of mixer 29 is a phase error signal and is smoothed in loop filter 31. This filter is shown as FIG. 4 and includes amplifier 41 fed by the phase error signal and summer 43 having feedback loop 45. The output of filter 41 designated as N_o is fed to summing circuit 33 which is also fed by a value equal to N₍ = T/T_c, where T = time length of the sample and T_c = pulse period of the clock. The N„ value is such that the digital bit synchronizer operates at the data rate where there is no error number present. The N_o signal shrinks the gate size until the phase lock is achieved, i.e., the phase error is zero. The output of summer 33 is fed to number control oscillator (NCO) 35 which includes comparing circuit 39 and counter 37. This circuit is a divide-by-N circuit where N is a variable and programmable. Midphase gate timing is obtained by generating a pulse when the counter reaches half of its total count.

In practice, it may be desired to have the NCO to count a considerably higher rate than the sampling rate to achieve smaller increments between NCO frequen3,772,600 cies. It is assumed that this is the case and that the NCO counts some multiple of the sampling rate.

It can be shown that the noise power into the loop filter is directly proportional to the length of the midphase gate and that it is advantageous to use an integration time of one half bit or less. It is noted that the shorter gate allows a constant integration time to be used in the mid-phase channel.

One output from number control oscillator 35 is fed to comparing circuit 47 and is compared with the sum from summer 33 after division by divide-by-2 circuit 49. Comparing circuit 47 then controls in-phase gate 11 while comparing circuit 39 controls mid-phase gate 25.

As an example of the rate of operation, the bit synchronizer was designed and built for operation at a data rate of 19.2 kbps with 20 samples per bit, each sample quantized to a maximum of 5 bits. The synchronizer counts a basic frequency of 300 times the bit rate (5.76 MHz) thus allowing the small changes in phase required for narrow noise bandwidths. The mid-phase gate is eight samples wide (out of 20). The loop filter is a constant gain which results in a first order loop.

IP/MP gates and associated logic circuits are shown in FIG. 5 as parallel digital accumulators. The inputs to these gates consist of five bits samples coded in twos complement by register 51. The IP accumulator or adder 53 carries nine bits and is fed back through registers 55 and 57. The data output is the sign bit at the end of the integration period through flip-flop 59. midphase gate 21 uses eight bit adder 61 and is fed back through registers 63 and 65. It is dumped after the 16th sample and the output is stored after eight samples have been summed and stored in register 67. Multiplication by —1 consists of inverting the output and adding 1. This is done with inverting gates 69 and 71 through flip-flops 59 and 73 having complementary inputs and outputs and multiplying circuits 75 and 77.

The number controlled oscillator shown in FIG. 6 consists of fixed counters 79 and 81 and variable counter 83. Counter 81, a modulo 15 counter, counts pulses at a rate of 300/T pps. It receives clock pulses through amplifier 85 and gate 87. On the fifteenth count, counter 79, a modulo 20 counter, through gate 89 is advanced by one count. When counter 79 reaches the fifth state the clock line is switched via gate 91 to counter 83 which counts to 15 + N„, the error number out of the loop filter. This addition takes place in error adder 93. The clock line is switched back to counter 81. Lines 95, 96 and 97 are intermediate states of counter 79 used to control the in-phase and mid-phase gates.

The digital bit synchronizer can be built using standard TTL integrated circuits and other available hardware.