Pattern generator

Nov. 25, 1969

S. MANBER

3,480,943

PATTERN GENERATOR

Filed April 5, 1967

Sheets-Sheet 1

<img file="US3480943A_D0001.tif" />

FIG. 1

INVENTOR.

Solomon Manber

RY

<img file="US3480943A_D0002.tif" />

ATTORNEY

Nov. 25, 1969

3,480,943

S. MANBER

PATTERN GENERATOR

Filed April 3, 1967

Sheets-Sheet-

<img file="US3480943A_D0003.tif" />

S- MANBER

PATTERN GENERATOR

Nov. 25, 1969

Filed April 3, 1967

3,480,943

Sheets-rSheet. 3

FIG.2B

SVR

<img file="US3480943A_D0004.tif" />

United States Patent Office

3,480,943

Patented Nov. 25, 1969

3,480,943 PATTERN GENERATOR Solomon Manber, Sands Point, N.Y., assignor to Alphanumeric Incorporated, Hicksville, N.Y., a corporation of Delaware

Filed Apr. 3, 1967, Ser. No. 628,034 Int. Cl. G08b 23/00; Glib 13/00 U.S. CI. 340—324 14 Claims

ABSTRACT OF THE DISCLOSURE ¹⁰

Patterns are traced on the face of a cathode ray tube past which moves a photosensitive film. The patterns are generated in response to coded combinations of indicia which position the electron beam of the cathode ray 15 tube to specified points on the face of the tube. After the beam has been horizontally and vertically positioned as directed by some of the coded combinations of indicia, the electron beam is turned on and controlled to vertically scan for a given distance related to portions of some of 20 the coded combinations of indicia. In this way, the pattern is built up by generating contiguous linear regions.

This invention is related to pattern generators and more particularly to the generation at a very high speed of high-quality patterns such as characters on an electromagnetic radiation sensitive medium.

Pattern generators have many applications such as 30 display devices, computer output devices, etc. Of these applications the ones which produce the greates amount of end result output are character generators used in the graphic arts and printing fields. Although these fields are very old the best automated line casting machines avail- 35 able today are electromechanical devices which can produce fifteen to twenty characters per second.

In order to increase the rate of generating characters, there have been attempts to utilize light beams and photosensitive films. Some early approaches were to use the 40 controlled trace of a cathode ray tube which was driven by figure eight bar generators which produced intelligible symbols by appropriate combinations of barlike elements. However, such characters in no way approached the quality of the characters produced by conventional metal 45 type slugs. Vector generators were also employed to drive the cathode ray tube beams with a slight improvement in quality.

About fifteen years ago a cathode ray tube was introduced which included a stencil of a plurality of characters 50 equivalent to a degenerate type font. The electron beam was first aimed on the region of the stencil having the outline of the character selected for output and further deflection circuits deflected the beam to the desired position on the face of the tube. Although the quality of the out- 55 put characters greatly improved, only one type font was available per tube. In addition, the circuits and the stencils are relatively expensive.

Other approaches included a multicharacter stencil having controllably ignitible light sources behind each char- 60 acter outline with optical focusing to direct the image to a particular portion of the output media. However, the proposal suffered from all the defects of the cathode ray tube-stencil systems and was even more expensive.

A further approach included the video scanning of a 65 stencil and using the video signal to intensity modulate the beam of a cathode ray tube. Such a system demanded very precisely engraved stencils which are prohibitively expensive to initially fabricate and to reproduce.

The field has tried dispensing with mechanical stencils ⁷⁰and has tried using pre-wired control circuits and magnetic core matrices, one per character, to generate patterns of signals to intensity modulate a cathode ray tube beam. However, the pre-wired control circuits and core matrices are exorbitantly expensive when high-quality characters are required.

An improvement on these systems is disclosed in U.S. Patent No. 3,165,045, for a Data Processing System wherein each character is represented by a plurality twovalued (black or white) elements in a matrix array. A storage means stores the representations of the characters as bits, with one bit per element. The bits are fed serially to a light source which scans a photographic medium. The bits intensity modulate the light source. Since the bits are stored on an addressable magnetic drum, the disadvantages of the pre-wired matrix are not present. However, this system is merely an electromagnet version of a conventional dot printer. Such printers are notorious for their inability to produce graphic arts quality characters. Such quality requires a very finely divided matrix array, for example an array of 70 columns and 100 rows, or 7000 elements per character. Therefore, it is necessary to store 7000 bits per character.

In order to minimize the number of stored bits per character, there has been disclosed in U.S. Patent No. 3,305,841, for a Pattern Generator, assigned to the same assignee, a system utilizing coded combinations of indicia or bits. In particular, it discloses a system wherein each character is divided into linear regions. Within each region is a line segment. The stored indicia (bits) are in groups of coded combinations of indicia which indicate the starting and ending points of the line segments in each linear region. With such a system, in the worst case, the number of bits required to represent a character is compressed, vis-a-vis the system of U.S. Patent No. 3,165,045, by a factor of three, and in the average case the compression is fivefold. While such compressions are extremely valuable, they have created a demand for even greater compressions.

Apparatus for effecting these greater compressions has been disclosed in application, Ser. No. 572,609, filed Aug. 15, 1966, assigned to the same assignee, and now abandoned.

While the apparatus disclosed in the above-cited patent and application performed admirably, it created a demand for much simpler apparatus as well as apparatus which could internally operate at slower speeds and still produce result copy at the same or higher speeds. In addition the previously disclosed appartus was often used with partially free-running cathode ray tube systems. Consequently it was necessary to synchronize the operation of the apparatus to the speed of operation of the free-running cathode ray tube system.

It is accordingly a general object of the invention to provide slower operating and more simple apparatus of the class described without decreasing the rate of output copy.

It is a further object of the invention to provide apparatus wherein the operation of electromagnetic radiation source for recording on the record medium is controlled by the remainder of the apparatus so that the previously mentioned synchronizing problems are eliminated.

Briefly, the invention contemplates a system for presenting at least one character to a record medium which is sensitive to electromagnetic radiation. The character comprises a plurality of areas having a second visual state (“black”) on a background of a first visual state (“white”). Each of these areas is divisible into adjacent linear regions aligned parallel to a first reference line extending in a first direction (say, the vertical). Each of the linear regions is associated with a position on a second reference line extending in a second direction (say,

3,480,943 the horizontal). Means are provided for storing a coded representation of the character as a plurality of coded combination of indicia. At least one of the coded combinations of indicia is related to the position on the second reference line of one of the linear regions of at least one of the areas. Others of the coded combinations of indicia are associated with the linear regions and include first and second coded groups of indicia. Each first coded group of indicia indicates a position on the first reference line where the associated linear region begins. The indication can be to an absolute position or to a relative position. Each of the second coded groups of indicia indicates the linear extent of the associated region. The indication can be an absolute ending position, a relative ending position, an ending position specified with respect to a distance from the starting position or an incremental distance which modifies a previous distance from a starting position.

There is an electromagnetic radiation source which includes means, which, when energized, scans the record medium in the first direction. First positioning means position the electromagnetic radiation source means to points opposite the record medium related to positions on the first reference line. Second positioning means position the electromagnetic radiation source means to points opposite the record medium related to positions on the second reference line.

Means sequentially transmit the coded combinations of indicia from the storing means. The first positioning means receives the first groups of indicia of the other coded combinations of indicia to position the electromagnetic radiation source means in accordance with the received first coded groups of indicia. The second positioning means receives the one coded combination of indicia to position the electromagnetic radiation source means in accordance with the received coded combination of indicia. Means receive the other coded combinations of indicia for energizing the electromagnetic radiation source means to linearly scan the record medium from positions associated with the first groups of indicia to positions associated with the second groups of indicia.

Repositioning means cause the second positioning means to position the electromagnetic radiation source means to the position associated with the linear region region adjacent to the linear region whose associated other coded combination of indicia just energized the electromagnetic radiation source means at least whenever the one coded combination of indicia is not received by the second positioning means.

The features and other objects and the advantages of the invention will be apparent for the following detailed description when read with the accompanying drawings which show, by way of example and not limitation, representative apparatus for realizing the concepts of the invention.

In the drawings:

FIGURE 1 shows in detail a character superimposed on a coordinate system for explaining the invention; and

FIGURES 2a and 2b show a block diagram representation of a system for generating patterns or characters on an electromagnetic radiation sensitive medium.

In general, the system can generate a line of characters at a time wherein the characters are serially generated along the line. When one line is completely generated, the system can start generating the next line of characters. The lines of characters will, in being generated, energize a source of electromagnetic radiation such as a light source which creates visual representations of the characters for exposure onto an electromagnetic radiation or light sensitive medium such as a photographic film. The film thereafter can be used for creating printing plates. Therefore, each character will be recorded on an area of one visual state such as one color (for example, white) and the character itself will comprise line portions in a second visual state such as a contrasting color (for example, black).

Not only can the characters be generated serially along a line, but each of the actual characters is generated by a plurality of serially generated lines, such as columns of elements.

FIGURE 1 shows by way of example a greatly enlarged version of a 12 point upper case G on a grid of rows and columns. This character will now be analyzed. It is seen that it occupies the region between columns C8 and C63, and between rows R4 and R75. However, it should be noted that columns C5, C6, and C7 are blank. Similarly, columns C64, C65 and C66 are blank. These columns are space columns to the left and right of the pattern columns C8 and C63 inclusive. A pattern column is a column of the character slug which includes at least one “black” element. Accordingly, the columns defining the 12 point G include three blank columns followed by 56 pattern columns followed by three blank columns.

Now consider the pattern column portion of the character. This portion can be divided into areas having a second visual state, say “black,” superimposed on a region having a first visual state, say white. There are three such areas, Al, A2 and A3. Area Al extends from column C8 to column 060 across the top of the character. Area A2 extends from column C63 to column C42 across the crossbar region of the character and area A3 extends from column C48 to column C18 across the bottom of the character.

Now consider typical pattern columns. Column C8 scanned from top to bottom comprises an area of “white” extending from row R1 to row R30, i.e., background, an area of “black” extending from row R31 to row R45, and an area of “white” from row R46 to row R100, i.e., background. Thus column C8 has one area of black in area Al. Column C34 comprises a first area of white extending from row R1 to row R3, a first area of black extending from row R4 to row R9, a second area of white extending from row RIO to row R69, a second area of black extending from row R70 to row R75, and a third area of white extending from row R76 to row R100. Column C34 has one area of black in area Al and one area of black in area A3. Column C44 has three areas of black, an area in area Al, an area in area A2, and an area in area A3, interspersed between four areas of white. If any area of black within a pattern column is defined as a linear region, it is seen that each pattern column includes a linear region of at least one of the areas Al, A2 or A3. In fact, the black areas of each pattern column are made up of linear regions of the areas Al, A2 and A3 where there is no more than one linear region from any one of the areas. This property of having no more than one linear region per area is extremely important in generating characters since it simplifies the apparatus and speeds the rate of generation of the characters. For the given example, three specific areas are shown for the letter G. However, other characters are divided into different areas wherein there is no more than one linear region per area.

It is also possible to analyze the character by means of rows. In such a case each pattern row will have at least one row segment. The invention contemplates both types of analyses and the claims employ the generic word “line” to mean either “row” or “column.”

From the above analysis of the pattern columns it is possible to establish a method of defining the linear regions within the areas Al, A2 and A3. In particular, it is only necessary to indicate the starting row of an area of black or linear region and to indicate the ending row of the linear region. Accordingly, the pattern in column C8 can be defined as a linear region of area Al starting at row R31 and ending at row R45. The linear region of the next column, column C9, starts at row R28 and ends at row R52. Similarly, the pattern of column C34 can be defined as: a linear region of area Al starting at row R4

3,480,943 element addresses as well as the vertical length (L) of the linear regions, and also with respect to vertical or row starting element address increments (DS) and ending element address increments (DE) as well as increments in the vertical length (DL) of the linear regions.

and ending at row R9, and a linear region of area A3 starting at row R70 and ending at row R75. The pattern of column C44 would be similarly defined. Therefore, any linear region can be defined with two units of information, wherein the first unit indicates a starting element _ address (the row at which the linear region starts) and an ending element address (the row at which the linear regions ends).

With the starting and ending address method, it is also possible to define the starting and ending element a,d- jq dresses of the linear region of column C9 by incrementally moifying the starting and ending element addresses of the linear region of column C8. In particular, the starting element address R31 of column C8 can be changed by an incremental value of —3 to obtain R28, the starting ele- 15 ment address of column C9. Similarly, the ending element address R46 of column C8 can be changed by the incremental value +6 to obtain the ending element address R52 of column C9. Thus, the incremental values indirectly define the starting and ending element addresses 20 of the linear region of column C9.

It is also possible to define the linear region by a starting element address along with an element area (the length of the linear region). It should be noted that the element area indirectly defines an ending address element 25 as a displacement of the starting address element.

In such a case, it is also possible to define subsequent element areas by merely specifying the incremental difference between the subsequent element area and the previously specified element area. 30

Tables I, II and III are an analysis of the character of FIGURE 1 broken down in areas Al, A2 and A3 with respect to the vertical or row starting (S) and ending (E)

TABLE I.—FOR AREA Al

Endpoint Increment

Method Method

S E L DS DE DL

<td> 8__________________</td><td> _____________ 31</td><td> 46</td><td colspan="4"> 15 ..................</td>

<td> 9_________________-</td><td> _____________ 28</td><td> 52</td><td> 24</td><td> -3</td><td> +6</td><td> +9</td>

<td> 10_________________</td><td> _____________ 25</td><td> 55</td><td> 30</td><td> -3</td><td> +3</td><td> +6</td>

<td> 11_________________</td><td> _____________ 23</td><td> 57</td><td> 34</td><td> -2</td><td> +2</td><td> +4</td>

<td> 12_________________</td><td> _____________ 21</td><td> 59</td><td> 38</td><td> -2</td><td> +2</td><td> +4</td>

<td> 13_________________</td><td> _____________ 19</td><td> 61</td><td> 42</td><td> -2</td><td> +3</td><td> +4</td>

<td> 14_____________— -</td><td> ........ 17</td><td> 63</td><td> 46</td><td> —2</td><td> +2</td><td> +4</td>

<td> 15_________________</td><td> ............. 16</td><td> 65</td><td> 49</td><td> -1</td><td> +2</td><td> +3</td>

<td> 16_________________</td><td> _____________ 15</td><td> 66</td><td> 51</td><td> -1</td><td> +1</td><td> +2</td>

<td> 17_________________</td><td> _____________ 14</td><td> 67</td><td> 53</td><td> -1</td><td> +1</td><td> +2</td>

<td> 18_________________</td><td> ......... 13</td><td> 31</td><td> 18</td><td> -1</td><td> -36</td><td> -35</td>

<td> 19.........-.......-</td><td> _____________ 12</td><td> 26</td><td> 14</td><td> -1</td><td> -5</td><td> -4</td>

<td> 20_________________</td><td> _____________ 11</td><td> 22</td><td> 11</td><td> -1</td><td> -4</td><td> —3</td>

<td> 21 ________________</td><td> _____________ 10</td><td> 20</td><td> 10</td><td> -1</td><td> -2</td><td> -1</td>

<td> 22_________________</td><td> _____________ 9</td><td> 18</td><td> 9</td><td> -1</td><td> -2</td><td> -1</td>

<td> 23_________________</td><td> _____________ 8</td><td> 16</td><td> 8</td><td> -1</td><td> —2</td><td> -1</td>

<td> 24_________________</td><td> _____________ 8</td><td> 15</td><td> 7</td><td> 0</td><td> -1</td><td> -1</td>

<td> 25--_______________</td><td> ......... 7</td><td> 14</td><td> 7</td><td> -1</td><td> -1</td><td> 0</td>

<td> 26_________________</td><td> _____________ 7</td><td> 13</td><td> 6</td><td> 0</td><td> -1</td><td> -1</td>

<td> 27_________________</td><td> _____________ 6</td><td> 12</td><td> 6</td><td> -1</td><td> -1</td><td> 0</td>

<td> 28_________________</td><td> _____________ 6</td><td> 12</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 29-.______________</td><td> ........ 5</td><td> 11</td><td> 6</td><td> -1</td><td> -1</td><td> 0</td>

<td> 30_________________</td><td> ......... 5</td><td> 11</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 31_________________</td><td> _____________ 5</td><td> 11</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 32_________________</td><td> _____________ 4</td><td> 10</td><td> 6</td><td> -1</td><td> -1</td><td> 0</td>

<td> 33_________________</td><td> _____________ 4</td><td> 10</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 34_________________</td><td> _____________ 4</td><td> 10</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 35_________________</td><td> .......... 4</td><td> 10</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 36_________________</td><td> ........... 4</td><td> 10</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 37_________________</td><td> _____________ 4</td><td> 10</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 38_________________</td><td> _____________ 4</td><td> 10</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 39-..______________</td><td> _____________ 4</td><td> 10</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 40_________________</td><td> _____________ 4</td><td> 10</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 41....... -</td><td> _____________ 5</td><td> 11</td><td> 6</td><td> +1</td><td> +1</td><td> 0</td>

<td> 42_________________</td><td> _____________ 5</td><td> 11</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 42_________________</td><td> ........... 6</td><td> 12</td><td> 6</td><td> +1</td><td> +1</td><td> 0</td>

<td> 44_________________</td><td> _____________ 6</td><td> 12</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 45 ________________</td><td> _____________ 7</td><td> 13</td><td> 6</td><td> +1</td><td> +1</td><td> 0</td>

<td> 46_________________</td><td> _____________ 7</td><td> 13</td><td> 6</td><td> 0</td><td> 0</td><td> 0</td>

<td> 47_._______________</td><td> ______i______ 7</td><td> 14</td><td> 7</td><td> 0</td><td> +1</td><td> +1</td>

<td> 48______________—</td><td> _____________ 8</td><td> 14</td><td> 6</td><td> +1</td><td> 0</td><td> -1</td>

<td> 49_________________</td><td> _____________ 8</td><td> 15</td><td> 7</td><td> 0</td><td> +1</td><td> +1</td>

<td> 50_________________</td><td> _____________ 9</td><td> 16</td><td> 7</td><td> +1</td><td> +1</td><td> u</td>

<td> 51__________________</td><td> _____________ 9</td><td> 17</td><td> 8</td><td> 0</td><td> +1</td><td> +1</td>

<td> 52_________________</td><td> _____________ 10</td><td> 18</td><td> 8</td><td> +1</td><td> +1</td><td> 0</td>

<td> 53_________________</td><td> _____________ 10</td><td> 19</td><td> 9</td><td> 0</td><td> +1</td><td> +1</td>

<td> 54_________________</td><td> _____________ 10</td><td> 21</td><td> 11</td><td> 0</td><td> +2</td><td> +2</td>

<td> 55_________________</td><td> _____________ 10</td><td> 25</td><td> 15</td><td> + 0</td><td> +4</td><td> +4</td>

<td> 56_________________</td><td> _____________ 9</td><td> 26</td><td> 17</td><td> -1</td><td> +1</td><td> +2</td>

<td> 57_________________</td><td> _____________ 9</td><td> 26</td><td> 17</td><td> 0</td><td> 0</td><td> 0</td>

<td> 58_________________</td><td> ........... 9</td><td> 26</td><td> 17</td><td> 0</td><td> 0</td><td> 0</td>

<td> 59________________-</td><td> _____________ 9</td><td> 26</td><td> 17</td><td> 0</td><td> 0</td><td> 0</td>

<td> 60—________________</td><td> _____________ 10</td><td> 25</td><td> 15</td><td> +1</td><td> -1</td><td> -2</td>

TABLE Π.-FOR AREA A2

Endpoint Increment

Method Method

S E L DS DE DL

Col. No.:

63....

62-.-.

61____

60-.-.

59--..

58-.-.

57-.-.

56-.-.

55-...

54-...

53--..

52____

51_...

50____

49____

48--.. 47__..

46....

45____

44____

43_.„

42____

Col. No. . 48—

47-..

46-.. 45__. 44__. 43—, 42—.

41-.. 40-..

39-.. 38-.. 37-.. 36. .. 35-.. 34—.

33-.. 32...

31—. 30-..

29...

27__

26..

25_.

24—

23-.

22—

21-.

2019—

18..

3__________________

-1 +1+2

60+1+1

0 +24+24

0 +1+1

0 00

0 00

0 00

0 00

0 -1-1

0 -1-1 :29 0 00

0 00

0 00

0 +1+1

0 —24-24

50-1-1

0 00

0 00

0 00

0 00 +1 -1—2

TABLE III. —FOR AREA A3

Endpoint Increment

Method Method

S E L DS DE DL

73 7 __________________

74 7 +1 +10

74 6 +1 0-1

75 7 0 +1+1

75 6 +1 0-1

75 6 0 00

76 6 +1 +10

76 6 0 00

76 6 0 00

76 6 0 00

76 6 0 00

76 6 0 00

76 6 0 00

76 6 0 00

76 6 0 00

76 6 0 00

76 6 0 00

76 6 0 00

75 6 —1 —10

75 6 0 00

75 7 -1 0+1

74 6 0 -1-1

74 7 -1 0+1

73 6 0 -1-1

72 6 -1 -10

72 7 -1 0+1

71 8 —2 -1+1

71 10 —2 0+2

70 13 -4 -1+3

69 16 —4 -1+3

68 23 -8 -1+7

A study of FIGURE 1 and Tables I, II and III reveals the following interesting phenomena. Area Al starts at column C8 and steps forward column-by-column without a gap to column C60. The starting column can be specified by a column number address 8. In each column of area Al there is only one linear region. Column C8 has a starting element address 31 and an ending element address 46. Thus the linear region can be defined by these two addresses. However this linear region can just as well be specified by starting element address 31 and a displacement therefrom (a length) of 15. Once the starting element address of column C8 (the first column of the area Al), and the ending element address or the length are given, the information concerning the linear regions can be given relative to the information of column C8. For example,, the starting element address of column C9 is 28. However, it can be specified as a decrement of —3 (negative increment) of the starting element address 31 of column C8, i.e., 31-3--28. Similarly, the ending element address of col3,480,943 umn C9 which is 52 can be specified as an increment +6 of the ending element address 46 of column C8, i.e., 46+6=52. Furthermore, in using the length or displacement method the length 24 of the linear region of column C9 can be specified as an increment of +9 to the length of the linear region of column C8, i.e., 15+9=24.

Area A2 begins with column C63 and steps back column-by-column without a gap to column C42. Note there is a jump from the end of area Al (column C60) to the start of area A2 (column C63). It is possible to specify this jump as an increment of 3 in the column number address or a new starting column number address 63 can be specified. The specifying of the linear regions of area A2 follows the same scheme as that of area Al. The specifications for area A3 follow the same pattern and therefore will not be described.

Referring to FIGURE 2 there will now be described a system for executing the above described inventive concepts.

The system generates patterns by directing an electron beam to particular horizontal and vertical coordinates (a point) inside of the face of a cathode ray tube. The electron beam is then turned on and driven to scan vertically for an indicated period of time. The beam is generally incrementally displaced one element in a horizontal direction and vertically positioned to a new point before being turned on and driven to scan again. Of course, the horizontal and vertical directions can be interchanged. However, vertical scans are more desirable when the patterns are actually a line of characters.

In particular the electron beam is controllably turned on and driven to scan for an increment of time related to the linear region of column of the area then being generated.

As has been discussed above, each column of an area has a plurality of elements and has at least one distinct linear region of contiguous elements. The linear regions have start and end points or elements. The electron beam is positioned to a point related to the start point, a scan is initiated and the beam is turned off at a time thereafter related to the end point of each linear region in each column of each of the areas Al, A2 or A3.

By equating the elements on the face of the cathode ray tube with the elements in the pattern, the elements of the pattern are mapped onto the face of the cathode ray tube. Now, by storing in registers the “addresses” of the start elements, i.e., the number of elements along a reference line from a base point, of each linear region of a column of each of the areas Al, A2 and A3, it is possible to use the start addresses to position the electron beam to related elements on the face of the cathode ray tube.

In order to determine the electron beam turn-off time after the beam has been turned on and the scan start, each column is also divided into a plurality of equal time increments. Since the cathode ray tube scan can be made a linear function of time, each time increment is equal to an element in the column on the face of the cathode ray tube. After the beam has been positioned and the scan started there is a counting of the number of time increments (elements) elapsing during a vertical scan from the start of the vertical scan by the cathode ray tube. For example, when the number of counted time increments equals the difference between stored address of the start element (start element address) of the linear region in the column and the address of the end element (end element address) of the linear region, the electron beam is turned off and the scan terminated. After the linear region has been scanned, the beam is horizontally repositioned and the registers are updated for the next scan by any combination of the following methods:

(1) The start and end element addresses in the registers can be replaced by new start and end element addresses received from a memory; or (2) The start and end element addresses in the registers can be modified by combining them algebraically with incremental data obtained from a memory; or (3) A new start element address and a displacement quantity from a memory can be inserted in the registers;

or (4) The start element address and the displacement quantity in the registers can be modified with incremental data from a memory.

Several system parameters are worth noting before describing the system. All words, whether data or code (control), are transferred from the memory as 4-bit bytes in parallel. Every starting and ending element address is an 8-bit byte. Therefore two words are required to transfer an address from the memory. Every increment is a 4-bit byte with the most significant bit always being zero.

The following table indicates the types of words transferred from the memory.

TABLE IV

Decimal BinaryValue Code Mnemonic Comments

0—--------- 0000 MOD Modification data.

0001 MODDo.

0010 MODDo.

0011 MODDo.

............. 0100 MODDo.

5_____________ 0101 MODDo.

6........ 0110 MODDo;

7___....... 0111 MODDo.

8............. 1000 NOP No operation.

9_____________ 1001 NOPDo.

0.......... 1010 SUB Substitute new value.

1011 LCN Load column number.

1100 MCN Modify column number.

1101 RDIS Reverse data increment sign.

14..,......... 1110 RCIS Reverse column increment sign;

15............ 1111 EOP End of pattern.

Only memory data words assume values from zero to seven. In general they will be indicated by their decimal equivalents, while in fact they are transmitted through the system in binary notation. The operation codes or code words have values between eight and fifteen. The operation codes have the following meanings.

The codes NOP indicate no operation is to be performed. The SUB code indicates that the next two words from memory are data words which are to be combined to form a new start or end element address. The LCN code indicates that the next word from memory represents the column number. The MCN code indicates that the next word from memory represents an increment of the column number. The RDS code indicates that the direction of incrementing for one of the start or end element addresses or the length of one of the linear regions is to be changed. The RCS code indicates that the direction of incrementing column numbers is to be changed. The EOP code indicates the end of the data for the pattern. The data has one of the following meanings:

DS=Start element address increment DE=End element address increment DL=Length increment

SM=Most significant half of a start address SL=Least significant half of a start address EM=Most significant half of an end address EL=Least significant half of an end address LM=Most significant half of length LL=Least significant half of length DC=Column position increment

CM=Most significant half of a column position address CL=Least significant half of a column position address.

The various units of the system will now be described with reference to FIGURE 2.

It should be noted that signal names and the lines carrying the signal have the same reference designation. For example, the MM1 signal is transmitted on the MM1 signal line. Generally, the “positive” or “high” signals are shown or mentioned. However, many of the signals also have a complementary signal. For example, the start-end flip-flop SEF transmits, from its two outputs, two signals, respectively, in parallel, the SEF and SEF' signals. When the SEF signal js “high” the SEF' signal is low, and vice

3,480,943 versa. When specifically required, both the signal and its complement are shown and mentioned. In addition, many of the lines which carry data are shown as a single line, for example, the MM signal line. This line is actually a cable of four lines MM1 to MM4. For simplicity, only the single line cable is shown. However, when required the cable is fanned out and the specific lines therein are given their appropriate suffix numbers. Numerals shown in parentheses adjacent to lines indicate the actual number of lines or line pairs where appropriate in the cable.

The memory M can be a magnetic core memory with suitable address selection and control circuits. The memory delivers 4-bit parallel words to four output lines MM1 to MM4 (shown as line or cable MM) in response to step pulses received from the step pulse generator SPG. Each step pulse causes the memory to output one word.

There is a control unit comprising a function decoder FD, a step pulse generator SPG, the start-end flip-flop SEF circuitry, and the most-least counter MLK. The decoder FD is used to generate control signals in response to code words received from memory M. The decoder FD can comprise four paraphase amplifiers connected via four AND gates to the four MM signal lines, respectively. Each of the AND circuits has three inhibit control inputs to receive the IFD, LCN and MCN signals so that information can only enter the decoder during the absence of all three signals. The outputs of the amplifiers are connected to inputs of a binary-to-hexadecimal decoder. The outputs of this decoder are connected via gating logic, to the set inputs of flip-flops which generate the control signals, SUB, LCN, MCN, RDIS, RCIS and EOP. The positive output of the paraphase amplifier connected to the most significant bit line MM4 drives a flip-flop for the MOD signal. However, provision is made to insure that the MOD signal does not occur for the one data word following MCN code word and the two data words following the LCN and SUB code words. This can be done by feeding the MOD signal to an input of a gate having other inhibiting inputs connected to the MCN, LCN and SUB signals.

The flip-flops are cleared by using a circuit employing gating logic, a counter and a delay device which responds to the step pulses on line STEP. Each of the flip-flops, except those generating SUB, MCN and LCN, is cleared after the next step pulse. The flip-flop generating the MCN signal is cleared after the second next step pulse. The flipflops generating the LCN and SUB signals are cleared after the third next step pulse. An OR circuit buffers together the MOD, MCN, RDIS, RCIS and EOP signals to generate the OPL signal. Another OR circuit buffers together the SUB and LCN signals to generate the TPL signal.

The step pulse generator SPG which is used to call for words from the memory M is basically three channels of one-shot multivibrators. In the first channel, the OPL signal line is connected to the input of a first one-shot multivibrator which delivers a pulse from its output a given period of time after it receives a signal at its input. This output is connected to one input of an OR circuit. In the second channel, the MCN signal line is connected to the input of a second one-shot multivibrator which delivers a pulse from its output the given period of time after it receives a signal at its input. The output of the second one-shot multivibrator is connected to the input of a similar third one-shot multivibrator. The outputs of the second and third one-shot multivibrators are connected to two other inputs of the OR circuit. The third channel comprises fourth, fifth and sixth cascaded one-shot multivibrators. The input of the fourth multivibrator (the first in this channel) receives the LCN signal. The output of each of these one-shot multivibrators is connected to further inputs of the OR circuit. The output of the OR circuit is connected to the STEP signal line. In addition, the outputs of the fourth and fifth one-shot multivibrators are connected to another OR circuit whose output is the

OE signal line connected to the input of the most-least counter MLK.

The most-least counter MLK is a one-stage binary counter having an initial clear input (not shown) for setting it to the zero state at the start of an operation. The counter delivers outputs to the ML signal line and is used to keep track of the most and least significant halves of the addresses during the SUB and LCN operations.

The start-end flip-flop SEF determines whether an incrementing operation is to be with respect to the start element address or the end element address. Flip-flop SEF has a set input connected via OR circuit Bl which receives the SUB and MOD signals, and a clear input which receives the ICN signal. When the flip-flop SEF is cleared it indicates that a start element address is to be incremented; when the flip-flop is set it indicates that an end element address is to be incremented.

The adder-subtractor AS which is used to modify by incrementing start and end element addresses, or displacements or column numbers, can be an eight binary position parallel adder-subtractor. The adder-subtractor has eight augend inputs connected to the eight lines AUG1 to AUG8, respectively and has eight addend inputs. Each of the four least significant addend inputs are connected via one of the four ADDN1 to ADDN4 signal lines and one of four AND circuits GS1 to one of the four lines MM1 to MM4, respectively. The four most significant addend inputs are wired to permanently represent zeros. The AND circuits GS1 can be four AND circuits having control inputs connected, via OR circuits, to the MOD and MCN signal lines so that they operate during the presence of either one of the MOD or MCN signals. An adder-subtractor control is connected via the SIGN signal line to the sign logic SL. When the signal on the SIGN signal line represents zero the addersubtractor AS operates as an adder and when the signal represents one it operates as a subtractor. The eight result terminals of the adder-subtractor are connected via the eight RES signal lines to the substitute/increment switch SIS. Since incrementing can occur for a start element address, an end element address, or a column number, there are three possible addends. Accordingly, there are three one-stage binary counters for sign storage, each associated with one of the possible addends. The input of i the counter associated with the start element address addend is connected via an AND circuit to the RDIS signal line from the function decoder FD, the input of the counter associated with the end element address addend is connected via an AND circuit to the RDIS signal line from the function decoder FD, and the input of the counter associated with the column number addend is connected to the RCIS signal line from the function decoder FD. The control input of one of these AND circuits is connected to the SEF and the control input of the other of these AND circuits is connected to the SEF signal line. The counters generate the SSVI, SEVI, and SCNI signals respectively. These signals are transmitted to the logic network which satisfies the following Boolean equation:

SIGN=SCNI MCN+MOD SEF · SEVI +MOD-SEF'-SSVI

The (+) indicates an OR operation, the (·) an AND operation, and a (') the complement of a signal.

The substitute/increment switch SIS is basically a logic network that switches information from either the memory M, via the four MM signal lines, or the result from the added-subtractor AS, via the eight RES signal lines, to either the column number counter CNK, via the eight TCNK signal lines, or the start value register SVR, via the eight TSVR signal lines, or the end value register

3,480,943

EVR, via the eight TEVR signal lines. Typical Boolean equations for the logic network are as follows:

TCNKI=(MMI-LCN-ML)+BESI.MCN TO NK4= (MM4-LCN-ML) -/-RESt'-MCN TCNK5= (MM1.LCN-ML')+RES5-MCN

TCNK8= (MM4-LCN-ML')+RES8.MCN

Τ8νΒ1=(ΜΜ1·8υΒ·8ΕΕ'·ΜΒ)+(ΕΕ81·Μ0η·8ΕΕ'·)

TSVR4=(MM4.SUB.SEF'-ML)+(RES4-MOD.SEF') TSVR5=(MM1.SUB.SEF'.ML')+(RES5-MOD-SEF')

TSVE8=(MM4.SUB.SEF'-ML')+(RES8.M0D-SEF')

TEVR4=(MM4.SXJB-SEF-ML)+(RES4.M0D.SEF) TEVR5=(MM1.SUB.SEF-ML')-|-(ReS5.MOD.SEF

TEVR8=(MM4.SUB.SEF.ML')+(RES8.m6d-SEF)

The column number counter CNK which stores the instantaneous column number can be an eight-stage binary up-down counter which has a unit count input connected to the ICN signal line. In addition, each stage can be selectively preset by signals received in parallel, via the. TCNK1 to TCNK8 signal lines, from the substitute/increment switch SIS. The direction of counting is controlled by signals received from the sign logic SL via SCNI signal line. The stages of the counter CNK transmit the CNK1 to CNK8 signals.

The start value register SVR which stores the start element address can be an eight-stage flip-flop register wherein each stage is loaded via one of the TSVR1 to TSVR8 signal lines and transmits a signal via one of the SVR1 to SVR8 signal lines.

The end value register EVR which stores the end element address or a displacement value can be an eightstage flip-flop register wherein each stage is loaded via one of the TEVR1 to TEVR8 signal lines and transmits a signal via one of the EVR1 to EVR8 signal lines.

The adder-subtractor switch ASS is a logic network which selectively transfers the contents of the column number counter CNK, or the start value register SVR, or the end value register EVR, via the AUG1 to AUG8 signal lines, to the augend inputs of the adder-subtractor AS. The network satisfies the following Boolean equations:

AUG1=CNK1-MCN+SVR1.MOD.SEF4-EVR1.MOD.SEF^/AVG8=CNK8.MCN+SVR8-MOD.SEF+EVR8-M0D.SEF'

The inhibit FD flip-flop IFDF generates the IFD signal which prevents the operation of the function decoder FD by generating the IFD signal while the scan of the record medium actually occurs. The flip-flop is set when the _f_j . ...

any reason and is cleared by a signal (kfN)7nffiLating the end of the scan. In particular, the set input of flip-flop IFDF is connected to the output of AND circuit G1 whose inputs are connected to the SEE signal line and _{lcclvxlcu ω}to the output of OR circuit Bl. The clear input is con- 55 signal line, nected to the ICN signal line.

In FIGURE 2B there is shown generally the cathode ray tube control circuits. The column element counter CEK counts the time increments and therefore the eleThe column element counter CEK can be an eight-stage binary counter. The unit count input is connected to the output of AND circuit G2. The counter can be preset via signals received, via eight AND circuits GS2, from the SVR1 to SVR8 signal lines. Each of the AND cir- 65 cuits has a control input connected to the IFD signal line. The outputs of the stages are connected via the CEN signal lines to one side of column element comparator CEC. The other side of the comparator receives the EVR sigemits an ICN signal when an equality is detected. The counter CEK has an initial clear input (not shown) which clears it to zero. The step or unit count input is connected T?T^^e °^f ^^{ND CirCUit G2}· ^{The retrace C0Unter} — — — ^a moving mm rLM me

RTK establishes the retrace time period for the electron 75 scroll drive SDX past lens LENS. Thus i beam by counting time increments. The counter RTK is a five-stage binary counter. When it reaches its capacity it resets to zero and emits an overflow pulse on the SVS signal line. The step or count input is connected to the output of AND circuit G3. The counter RTK has an initial clear input (not shown) which sets the counter to a count of zero.

The flip-flop VS controls the scan and retrace times of the beam of the cathode ray tube CRT. When the flipflop VS is set by an SVS signal from counter RTK a signal is present on the VD signal line to permit a scan. When the flip-flop VS is cleared by an ICN signal from comparator CEC a signal is present on the VD' signal line to permit the initiation of a retrace period which insures that the beam has returned to the start position and settled down before another scan can begin.

The VD and VD' signals are connected to the control inputs of AND circuits G2 and G3 whose other inputs are connected to the output of free-running oscillator OSC which generates equitimed pulses. The outputs of AND circuits G2 and G3 are connected to the unit count inputs of counters CEK and RTK respectively.

The vertical deflection control VDFC can be a current generator which drives the vertical deflection yoke of the cathode ray tube CRT. The input to the current generator can be a summing circuit having inputs connected to the sawtooth generator STG and the vertical digital-to-analog converter VDAC. Converter VDAC receives, via the SVR1 to SVR8 signal lines, the contents of the start value register SVR to vertically position the electron beam for the start of a scan. Sawtooth generator STG can be a gated sawtooth generator which is turned when the VD signal goes high and is turned off when the VD signal goes low.

In general the scan cycle operates in the following manner. When the flip-flop VS is in the clear state, the VD signal is low and both of the AND circuits G2 and G3 are closed. Now when an IFD signal is received at the outer control input of AND circuits G3 indicating a scan should occur, this circuit opens. Pulses from the oscillator OSC start stepping the counter RTK. When the counter RTK exceeds its capacity (overflows), indicating the end of the retrace period, the SVS pulse is emitted setting the flip-flop VS which generates the VD signal to turn on the 45 sawtooth generator STG. AND circuit G2 opens and

AND circuit G3 closes. Pulses from oscillator OSC are now fed to the count input of counter CEK which may have been preset to start element address value. While counter CEK is counting it transfers signals (representing ------------------- _v„_u„_l), via the CEN lines, to the column element comparator CEC. The other side of the comparator is receiving an end address for a linear region via the lines EVR1 to EVR8. When equality is ^r®^acbeii ^{the com}P^arator CEC emits a pulse on the ICN

The ICN signal line is connected to the clear inputs of flip-flops VS, SEF and IFDF to end the scan cycle and permit the reading in of the next word from the memory M. In addition, the ICN signal line is connected to the .-- -------------------1 one to the count therein. It should be noted that the VD signal also drives the video drive circuits VDC (the usual Z-axis circuits) of the cathode ray tube CRT so that an electron beam is only present during the scan.

The cathode ray tube CRT has a horizontal deflection control HDC which drives the yoke of the horizontal deflection system. The horizontal deflection control is driven by the horizontal digital-to-analog decoder HDAC which L^eCeiAS^⁸”^aIs^^^{reSenting the horizonta}l position, via counter CNK. The cathode ray tube also receives electron beam accelerating voltages from source AVS.

The face of the cathode ray tube is focused by the lens LENS onto a moving film FLM. The film is driven bv

---------„„„ images generated anv relZ SdT^^ ⁵⁰ th“kXeou^ *=Λ ^{by th}* ^deCt™ «θ -put of counter CNKtoadd nals. The comparator is an equality comparator which 70 the CNK1 tc&gt; CNK31posffion via emits an ICN simal when ;&gt;n ennalitv _ie „^{K8 s} lines, from column number

3,480,943 on the face of the cathode ray tube are recorded on film FLM.

The system will now be cycled through the “writing” of several typical columns of the pattern of FIGURE 1. It is assumed that all registers, flip-flops and binary counters _ have been cleared to their initial states.

Table V summarizes the operation of “writing” the character shown in FIGURE 1 using starting and ending addresses for the linear regions.

table v ¹⁰

<td rowspan="2"> Memory Word Number(s)</td><td rowspan="2"> Memory Word(s) Contents</td><td rowspan="2"> Comments</td><td colspan="3"> Sign</td><td rowspan="2"> Col. No.</td>

<td> C</td><td> s</td><td> E</td>

<td> m+0____________</td><td> 11</td><td> LCN Code________</td><td> +</td><td> +</td><td> + .</td><td></td>

<td> m+1 and 2.......</td><td> 08</td><td> CM=0, CL=8.....</td><td> +</td><td> +</td><td> +</td><td> 8 ¹⁵</td>

<td> m+3............</td><td> 10</td><td> SUB Code........</td><td> +</td><td> +</td><td> +</td><td> 8</td>

<td> m-H and 5______</td><td> 31</td><td> SM=3, 8L=1_____</td><td> +</td><td> +</td><td> +</td><td> 8</td>

<td> m+6____________</td><td> 10</td><td> SUB Code........</td><td> +</td><td> +</td><td> +</td><td> 8</td>

<td> m+7 and 8______</td><td> 46</td><td> EM=4, EL=6—_</td><td> +</td><td> +</td><td> +</td><td> 8</td>

<td> m+9____________</td><td> 13</td><td> RDIS Code_______</td><td> +</td><td></td><td> +</td><td> 9</td>

<td> m+10...........</td><td> 03</td><td> DS—3—...........</td><td> +</td><td> —</td><td></td><td> 9</td>

<td> m+U___........</td><td> 06</td><td> DE=6____________</td><td> +</td><td> _</td><td> +</td><td> 9 20</td>

<td> m+12...........</td><td> 03</td><td> DS=3_____________</td><td> +</td><td> —</td><td> +</td><td> 10</td>

<td> m+13...........</td><td> 03</td><td> DE=3—-.........</td><td> +</td><td> —</td><td> +</td><td> 10</td>

<td> n+0.............</td><td> 13</td><td> RDIS Code_______</td><td> +</td><td> +</td><td> +</td><td> 60</td>

<td> n+1-------------</td><td> 01</td><td> DS=1..._.........</td><td> +</td><td> +</td><td> +</td><td></td>

<td> n+2.............</td><td> 13</td><td> RDS Code________</td><td> +</td><td> +</td><td></td><td> 60</td>

<td> n+3_____________</td><td> 01</td><td> DE=1____________</td><td> +</td><td> +</td><td> —</td><td> 60</td>

<td> n+4.............</td><td> 12</td><td> MCN Code_______</td><td> +</td><td> +</td><td> —</td><td> 61</td>

<td> 11+5_____________</td><td> 2</td><td> DC=2____________</td><td> +</td><td> +</td><td> —</td><td> 63</td>

<td> n+6_____________</td><td> 14</td><td> RCIS Code_______</td><td></td><td> +</td><td> —</td><td> 63</td>

<td> n+7.—..... —</td><td> 10</td><td> SUB Code________</td><td> —</td><td> +</td><td></td><td> 63</td>

<td> n+8 and 9.......</td><td> 44</td><td> SM=4, SL=4_____</td><td> —</td><td> +</td><td></td><td> 63</td>

<td> n+10____________</td><td> 10</td><td> SUB Code________</td><td> —</td><td> +</td><td> —</td><td> 63 30</td>

<td> n+ll and 12_____</td><td> 47</td><td> EM=4, EL=7_...</td><td> —</td><td> +</td><td></td><td> 63</td>

<td> n+13____________</td><td> 13</td><td> RDIS Code_______</td><td> —</td><td></td><td> —</td><td> 62</td>

<td> n+14._..........</td><td> 1</td><td> DS—1_____________</td><td></td><td> —-</td><td> —</td><td> 62</td>

<td> n+15____________</td><td> 13</td><td> RDIS Code_______</td><td> —</td><td> —</td><td> +</td><td> 62</td>

<td> n+16____________</td><td> 1</td><td> DE=1____________</td><td></td><td> —</td><td> +</td><td> 62</td>

<td> n+17............</td><td> 0</td><td> DS=0..._.........</td><td> —</td><td> —</td><td> +</td><td> 61</td>

<td> n+18-...........</td><td> 1</td><td> DE—1____________</td><td> —</td><td> —</td><td> +</td><td></td>

<td> n+19_...........</td><td> 0</td><td> DS=0.____________</td><td> —</td><td> —</td><td> +</td><td> 60 ⁰⁵</td>

<td> n+20.............</td><td> 10</td><td> SUB Code________</td><td></td><td> —</td><td> +</td><td> 60</td>

<td> n+21 and 22______</td><td> 24</td><td> EM=2, ELM_____</td><td> —</td><td></td><td> +</td><td> 60</td>

<td> n+23_____________</td><td> 0</td><td> DS=0.............</td><td></td><td> —</td><td> +</td><td> 59</td>

<td> n+24............</td><td> 1</td><td> DE=1____________</td><td> —</td><td> —</td><td> +</td><td> 59</td>

<td> . . .</td><td> . . .</td><td></td><td></td><td></td><td></td><td> ‘ · · 40</td>

<td> p+0-------------</td><td> 11</td><td> LCN Code________</td><td> —</td><td> +</td><td> —</td><td> 41</td>

<td> p+1 and 2_______</td><td> 48</td><td> CM=4, CL=8.—</td><td></td><td> +</td><td></td><td> 48</td>

<td> p+3-------------</td><td> 10</td><td> SUB Code________</td><td> —</td><td> +</td><td> —</td><td> 48</td>

<td> p+4 and 5________</td><td> 66</td><td> SM=6, SL—6_____</td><td> —</td><td> +</td><td> —</td><td> 48</td>

<td> p+6--------------</td><td> 10</td><td> SUB Code________</td><td> —</td><td></td><td></td><td> 48</td>

<td> p+7 and 8________</td><td> 73</td><td> EM=7, EL=3.__..</td><td> _</td><td> +</td><td></td><td> 48</td>

<td> p+9--------------</td><td> 01</td><td> DS = 1_____________</td><td> —</td><td> +</td><td> —</td><td> 47</td>

<td> P+10.............</td><td> 13</td><td> RDIS Code_______</td><td></td><td> +</td><td> +</td><td>⁴⁷ 45</td>

<td> p+11-------------</td><td> 01</td><td> DE=1............</td><td> —</td><td> +</td><td> +</td><td> 47 **</td>

<td> q+0--------------</td><td> 10</td><td> SUB Code........</td><td></td><td></td><td></td><td> 18</td>

<td> q+1 and 2........</td><td> 45</td><td> SM=4, SL=5_____</td><td> —</td><td> —</td><td></td><td> 18</td>

<td> q+3--------------</td><td> 1</td><td> DE=1____________</td><td> —</td><td> —</td><td> —</td><td>¹⁸ tn</td>

<td> q+4--------------</td><td> 15</td><td> End of Pattern....</td><td> —</td><td> —</td><td> —</td><td> 17 50</td>

Note all memory words or pairs of memory words where appropriate will be expressed as their demical equivalent for the sake of simplicity whereas their binary _ggequivalents are used within the system.

Columns C8, C9 and CIO of area Al will first be written. It will be assumed that a first STEP pulse causes the memory M to deliver the first memory word m+0 to the MM signal lines. The first memory word is a load θθ column number (LCN) code which enters the function decoder FD to generate the LCN signal. The LCN signal within the decoder FD blocks the entry AND circuits to the decoder FD. The LCN signal is fed to the substitute/increment switch SIS to establish paths between the MM signal lines and the TCNK signal lines under control of the ML signal. In addition, the LCN signal within the function decoder FD generates the TPL signal. The TPL signal causes step pulse generator SPG to generate three step pulses and two OE pulses. The first step pulse causes the memory word m+1 to pass from the memory M via the MM signal lines switch SIS, and lines TCNK1 to TCNK4 to the four more significant stages of column number counter CNK by virtue of the ML signal being present in switch SIS. The second step pulse causes the 75 memory word »z-|-2 to pass from the memory M via the MM signal lines, switch SIS, and lines TCNK5 to TCNK8 to the four less significant stages of counter CNK by virtue of the ML' signal being present in switch SIS. Note that the trailing edge of the first OE pulse signal coincident with the first step pulse shifted the state of the counter MLK. At the end of the transfer of the memory word m+2, the second OE pulse signal restored counter MLK to its original state and counter CNK has been preset to represent column C8. The CNK1 to CNK8 signals generated by counter CNK are fed to horizontal digital-toanalog converter HDAC which generates a current proportional to their numerical representation. The current is fed to the horizontal deflection control HDC which horizontally positions the electron beam (when present) to the position for column C8. The third of the step pulses causes the termination of the LCN signal, the opening of the entry AND circuits of the decoder FD (hereafter, merely referred to as decoder entry gates) and the availability of the word m+3 at memory M.

Memory word m+3 is decoded to a SUB code by the decoder FD indicating that the next two memory words comprise an element address. The SUB signal internal to the decoder FD blocks decoder entry gates. The SEF' signal (start-end flip SEF is in the cleared state) and the SUB signal cooperate in the substitute/increment switch SIS to connect paths from the MM signal lines to the TSVR signal lines. The SUB signal causes the decoder FD to transmit a TPL signal to the step pulse generator SPG which generates three step pulses and two OE pulses. The first step pulse causes the memory M to transmit memory word m+4, via the MM1 to MM4 signal lines, the switch SIS, and the TSVR1 to TSVR4 signal lines to four more significant stages of the start value register SVR. Note the ML signal is present. The second step pulse causes the memory M to transmit memory word m+5, via the MM1 to MM4 signal lines, the switch SIS, and the TSVR5 to TSVR8 signal lines to the four less significant stages of the start value register SVR. The ML' signal is present. Note most-least counter MLK operates in the same way as during the operation associated with memory words m+1 and m+2.

The start value register SVR now contains the representation for the start element address 31. The SVR1 to SVR8 signal lines transmit this digital representation to the vertical digital-to-analog converter VDAC which generates a current proportional to their numerical representation. The current is fed to the vertical deflection control VDFC which vertically positions the electron beam (when present) to the start element address position for the column C8 linear region in area Al. The third of the step pulses causes the termination of the SUB signal, the setting of the start-end flip-flop SEF (the trailing edge of the SUB signal triggers this flip-flop), the opening of the decoder entry gates, and the transfer of the word m+6 from the Memory M.

Memory word m+6 is another SUB code word and the system operates in a manner similar to the SUB code word of memory word m+3 to load memory words m+7 and m+8 in the end value register EVR except for the following: (1) the SEF signal is now present so that switch SIS connects lines MM to the input lines TEVR of end value register EVR to cause memory words m+7 and m+8 to enter the end value register EVR as they are transmitted by the memory in response to the usual first two step pulses; (2) the SEF signal cooperates with the SUB signal (passing through OR circuit Bl) at AND circuit G1 to set inhibit FD flip-flop IFDF which generates the IFD signal that is used to keep the decoder entry gates blocked even after the third step pulse; (3) the scan of the record medium is performed. In particular, the IFD signal opens AND circuits GS2 and the contents of the start value register SVR are entered into the column element counter CEK. The IFD signal opens AND circuit G3, starting the retrace period under control of retrace

3,480,943

IS counter RTK. When counter RTK overflows the SVS signal sets flip-flop VS which generates the VD signal. The VD signal is fed to video drive circuits VDC to turn on the electron beam of the cathode ray tube CRT and to trigger on the sawtooth generator STG. The sawtooth generator generates a sawtooth current waveform that is superimposed on the vertical position current in the vertical deflection control VDFC causing the electron beam to sweep vertically from the position represented by the start element address value. At the same time the VD signal opens AND circuit G2 causing equi-timed pulses to pass from oscillator OSC to column element counter CEK which starts counting up from the previously loaded start element address (31). Column element comparator CEC compares the running count in counter CEK with the end element address (46) which had been loaded in the end value register EVR. When the count in the counter CEK has been unit added 15 times, comparator CEC detects an equality and emits an ICN signal. The ICN signal clears flip-flop VS terminating the VD signal, the electron beam is turned off and the sawtooth generator STG triggered off. The vertical scan of the record medium associated with the linear region of column C8 in area Al is complete. Thus, the routine for writing a linear region is seen to comprise the steps of horizontally positioning the electron beam to a particular point, vertically positioning the electron beam to a particular point, turning on the electron beam and causing the electron beam to vertically scan through a particular distance, and turning off the electron beam and ending the scan. The ICN signal is also fed to the count input of column number counter CNK to increment its contents by one preparatory to scanning associated with the column C9 position of area Al. The ICN signal also clears start-end flip-flop SEF so that the next address to be modified will be a start element address. Finally the ICN signal clears the flip-flop IFDF terminating the IFD signal so that the decoder entry gates open, allowing memory word m+9 to enter the decoder FD.

Memory word m-i-9 calls for a reversal of the sign associated with an address. Decoder FD thu generates an RDIS signal that is fed to the sign logic SL where it cooperates with the SEF' signal to change the state of the one-stage binary counter associated with the start element address. Since this counter was initially set to represent plus it now represents minus. The decoder FD emits an OPL signal causing step pulse generator SPG to generate one step pulse and memory transmits the rn+10 memory word.

Memory word m+10 is a data word calling for a start element address change of 3 elements. Hence, the decoder FD generates the MOD signal. The MOD signal opens AND circuits GS1 connecting the MM signal lines to the ADDN signal lines (the element addend having the value 3 is fed to the adder-subtractor AS). The MOD and SEF' signals cooperate in the sign logic SL to transmit the output of the counter associated with the start element address (minus) via the SIGN signal line to the sign control input of the adder-subtractor which becomes a subtractor. The MOD and SEF' signals in the addersubtractor switch ASS cooperate to connect the SVR1 to SVR8 signal lines (the contents of the start value register SVR) to the AUG1 to AUG8 signal lines (the augend inputs of the adder-subtractor). Thus, three is subtracted from the start element address (31) to give a new start element address (28) on the RES1 to RES8 signal lines. The MOD and SEF' signals cooperate in substitute/increment switch SIS to connect the RES1 to RES8 signal lines to the TSVR1 to TSVR8 signal lines and the new start element address is loaded in the start value register SVR. Finally, the MOD signal causes the decoder FD to generate an OPL signal resulting in the memory M transmitting memory word The trailing edge of the

MOD signal, passing through OR circuit Bl, sets flip-flop

SEF which starts generating the SEF signal associated with end element addresses.

Memory m-f-11 is a data word indicating a change of 6 in an element address (in particular an end element address, the SEF signal is present). The MOD signal is generated and an operation similar to that for memory word /«-Ι-ΙΟ is performed with the following exceptions due to the presence of the SEF instead of the SEF' signal. The contents of the end value register EVR are modified. The modification is actually an addition (the counter storing the sign associated with the end element addresses in the sign logic SL has never been reversed and therefore indicates addition). In addition, the MOD signal cooperates with the SEF signal at AND circuit G1 sets flip-flop IFDF which generates the IFD signal. The IFD signal initiates a new scan cycle just as it did during operation on the memory word τη+6.

The generation of the linear regions column-by-column continues in the same way until area Al is completed by the operation associated with «+3 memory word.

It will be noted that after the initial horizontal positioning of the electron beam by memory words m-l-0, m+1 and m-f-2, the beam was repositioned by virtue of the ICN signal after each scan cycle. This technique was possible because the linear regions were contiguous. (This was the criterion in defining areas Al, A2 and A3.) However, in going from area Al to area A2 there is a jump from column C61 to column C63. To accommodate this jump, the column number counter CNK must be changed by the rise of memory words. Accordingly, memory word n+4 is an MCN code word.

The MCN code word is decoded by function decoder FD to generate the MCN signal Internal to the decoder FD, the MCN signal blocks the decoder entry gates. The MCN signal at AND circuits GS1 connects the MM signal lines to the ADDN signal lines. The MCN signal at the substitute/increment switch SIS connects the RES signal lines to the TCNK signal lines; and the MCN signal at the adder-subtractor switch ASS connects the CNK signal lines to the AUG signal lines. In addition, the MCN signal at the sign logic SL gates the output of the column number sign counter to the SIGN. Since the column number sign counter has never been reversed it still indicates plus. Finally, the MCN signal is fed to the step pulse generator SPG causing it to emit two step pulses. The first step pulse causes the memory M to transmit memory word n+5 (an increment value of 2) which is added to the column number (61) to give a result (63) that is stored in the column number counter CNK. The second step pulse terminates the MCN signal, opens the decoder entry gates and causes the transmission of the «+6 memory word from memory M. Memory word n+6 calls for a reversal of the sign counter associated with the column number and the SCN1 signal changes state causing the column number counter CNK to become a down counter. Memory words n-f-7, «+8 and n+9 call for replacing the stored start address element by the address (44). This operation is similar to that performed for memory words m-j-3, m-j-4 and m+5. Memory words 71+10, «+11 and «+12 call for the substitution of the end element address by the address (47). This operation is similar to that performed for memory words in+6, m+7 and m+8. However, note that when the ICN signal now occurs and is received by column number counter CNK, it unit subtracts from the count since the SCN1 signal indicates subtractions. Thus, the column numbers are unit decremented for each scan until otherwise indicated. The remainder of the “writing” of area A2 proceeds in the usual manner until the end of area A2 (column C41) is reached.

After the scan associated with column C41 of area A2, memory word p+0 is read out calling for a new column number for the start of area A3 since the next column to be written is not contiguous with the previous column.

Note in this case that instead of modifying the column

3,480.943 number by an increment (or a decrement) the actual value of the new column number is substituted for the value stored in column number counter CNK. The new column number (48) is specified by memory words p+1 and p+2. The operation is the same as the operation described for memory words m+0, m+1 and n?+2. Area A3 is then written in a straightforward manner until column C18 is written as directed by memory words ¢+0, ¢+1, ¢+2 and ¢+3. The memory word ¢+4 is transmitted from memory M to the function decoder FD to give the EOP signal. The pattern for the letter G of FIGURE 1 has been recorded on the record medium. The EOP signal can be used to halt the system or to initiate the start of a new line of characters, a new character, etc.

The writing of the character has been described wherein the limits of the linear regions have been specified by start element addresses and end element addresses. Now there will be indicated how the character can be written with the limits of the linear regions being specified by a start element address and a length or displacement value from the start element address. First, it should be realized that the length data is equivalent to an end element address; therefore, it can be directly substituted for end element address data. Accordingly, it will be stored in the end value register EVR. Furthermore, there is no need to preset the column element counter CEK with start element addresses, since column element comparator CEC will compare a number representing the number of elements in a length or displacement (now indicated by the EVR signals) with a running count from zero in counter CEK. Thus, counter,CEK need not receive the SVR signals via AND circuits GS2 and the connection therebetween can be removed. Furthermore, after each equality indicated by comparator CEC, counter CEK must be cleared to zero. Therefore, by feeding the ICN signal via a delay network to the clear input of counter CEK the required clearing to zero is obtained.

With these changes, the start element address-displacement method of writing the character will be outlined with respect to Table VI.

¹⁸

ICN signal which in addition to performing its usual functions clear the counter CEK to zero.

Memory word m'+9 is the same as memory word m+9 and results in a reversal of the sign for the start g element addresses. Memory word m'+10 is the same as memory word m+10 and results in a decrement of the start element address to (28). Memory words m'+ll, m'+12 and m'+13 are similar to memory words m'+6, m'+7 and m'+8 and result in the loading of the length j₀ value (24) in the end value register EVR and a linear region having a length of 24 column elements is scanned. The memory word m'+14 is the same as memory word m+14 and results in a decrementing of the start element address by 3 to a new value of 25. The memory word 15 m'+15 is similar to memory word m+15 and results in an incrementing of the length value by 6 to a value of 30 and a linear region having a length of 30 column elements is scanned.

The remainder of the writing of the character continues 20 in the same manner and will not be discussed for the sake of brevity.

Thus, there has been shown an improved system for recording patterns on a radiation sensitive record medium by positioning a source of radiation to specified points 25 and then causing the source to scan the record medium in a direction for a given period of time.

Since the various elements shown in the system are made up of standard components, and standard assemblies, reference may be had to “High Speed Computing 30 Devices,” by the staff of Engineering Research Associates, Inc. (McGraw-Hill Book Company, Inc., 1950); and appropriate chapters in “Computer Handbook” (McGraw-Hill, 1962) edited by Harvey D. Huskey and Granino A. Korn, and for detailed circuitry, to the exam35 pie “Principles of Transistor Circuits,” edited by Richard F. Shea, published by John Wiley and Sons, Inc., New York and Chapman and Hall, Ltd., London, 1953 and 1957. In addition, other references are: For system organization and components: “Logic Design of Digital 40 Computers,” by M. Phister, Jr., (John Wiley and Sons, New York); “Arithmetic Operations in Digital ComTABLE VI

Memory Sign

Memory Word Word(s) --------Number(s) Contents Comments C S E Col. No 45 m'+0„_..........

m'4-1 and 2__.....

____________ m'-Hkand 5_______ m'+6._...........

m'4-7 and 8.......

m'+9.............

m'-l-lO............

m'-Hl............

m'4-12 and 13.....

m'4-14____________ m'-H5............

31

03

3

LCN Code__.....

CM=0, CL=8_... SUB Code________

SM=3, SL=1_____

SUB Code........

LM==1, LL=5_____

RDIS.............

DS=3_____________

SUB Code________

LM=2, LL=4_____

DS=3.............

DL=6............

+ + + + + + q'+4..... 15 End of Pattern..-. — — — 17

Memory words m'+0, m'+l and m'+2 are the same as memory words m+0, m+1 and m+2 of Table V and 60 result in column number (8) being inserted in column number counter CNK. Memory words m'+3, m'+4 and m'+5 are the same as memory words m+3, m+4 and m+5 and result in start element address (31) being inserted in start value register SVR. Memory words m'+6, 65 m'+7 and m'+8 are similar to memory words m+6, m+7 and m+8, except that a length value (15) is inserted in end value register EVR instead of end element address (46). Now when the IFD signal is generated to start a scan cycle, the length value 15 is present on the 70 EVR signal lines feeding column element comparator CEC. After the retrace portion of the scan cycle, pulses are fed in the usual manner to column element counter CEK which had been cleared to zero. When counter CEK has accumulated 15 pulses comparator CEC emits an puters” by R. K. Richards (D. Van Nostrand Company, Inc., New York). For circuits and details: “Digital Computer Components and Circuits”, by R. K. Richards (D. Van Nostrand Company, Inc., New York).

An especially worthwhile book for finding the components mentioned in the specification, and the hardware for realizing the components as well as the techniques for mechanizing Boolean equations to actual logic networks is “The Digital Logic Handbook”, 1966-67 edition, copyrighted in 1966 by the Digital Equipment Corporation of Maynard, Mass.

While only a limited number of embodiments of the invention have been shown and described in detail, there will now be obvious to those skilled in the art, many modifications and variations satisfying many or all of the objects of the invention without departing from the spirit thereof as defined by the appended claims.