Signal phasing system

2,932,012

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April 5, 1960

O. A. JORGENSEN

SIGNAL PHASING SYSTEM

Filed April 15, 1959

Sheets-Sheet 1

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FIG.2α

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FIG.2b

INVENTOR.

OTTO A. JORGENSEN

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ATTORNEY

April 5, 1960 o. a. jorgensen 2,932,012

SIGNAL PHASING SYSTEM

Filed April 15, 1959 ₂ gheets-Sheet 2

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FIG. 4

United States Patent Office

2,932,012

Patented Apr. 5, 1960

2,932,012

SIGNAL PHASING SYSTEM

Otto A. Jorgensen, Pittsford, N.Y., assignor to General Dynamics Corporation, Rochester, N.Y., a corporation of Delaware

Application April 15, 1959, Serial No. 806,717

Claims. (Cl. 340—174) _ My invention relates generally to a system for phasing signals, i.e., for shifting signals into a definite relationship with respect to a particular time base.

In the past, apparatus has been provided for feeding signals occuring at random times into a system which requires that such input signals occur at regular intervals with respect to a time base. Such apparatus usually has employed a memory unit or units capable of accepting and storing each random-time input signal. The apparatus also has included means periodically operated from a clock, which defines the aforementioned time base, for applying readout signals to the memory units and thereby producing signals at the output of the apparatus which are in the required time position. Such output signals then may be applied to succeeding equipment for utilization.

The use of such apparatus presupposes that the memory units therein are capable of accepting input signals occurring at any time. However, some memory devices, such as parametrically-excited resonators, do not have such a capability, but accept signals only when separate excitation signals are applied thereto, the memory devices being unresponsive to input signals applied at other times. Because the last-named type of memory devices has other features which may make their use in a signal phasing or rephasing system particularly apt, it is therefore desirable to provide a system by which randomlyoccurring signals may be written into at least one of the memory units which are capable only when excited of accepting such signals.

Accordingly, it is an object of my invention to provide a new and improved system for phasing or rephasing electrical signals.

Another object of my invention is to provide new and improved apparatus for controlling the phasing of signals wherein the memory units accept signals only upon the regular reoccurrence of exciting signals.

Another object of my invention is to provide new and improved apparatus for controlling the phasing of signals wherein the memory units accept signals only upon the application of exciting signals thereto. .

Another object of my invention is to provide new and improved apparatus for phasing signals employing parametrically-excited resonators as storing units.

I accomplish these and other objects in a system having a source capable of producing signals of uniform duration which may occur at random times. A shift register is provided having a plurality of memory elements disposed in a series, each of the elements having a first signal input, an exciting input and an output, and each of the intermediate and last of the elements in the series having a second signal input. The elements of the series are arranged in such a manner that the output of each of the first and intermediate ones of the elements are coupled to the second signal input of the next succeeding one of the series elements. The output of the last series element also serves as an output for the register. The elements of the register are chosen to be responsive to the application of a signal to either of its signal inputs and to the exciting input for producing a signal on the output of that element only for the duration of the signal β applied to the exciting input. An example of such an element is a parametrically-excited resonator, which is understood by those skilled in the art.

In order to supply signals to the exciting inputs of the various elements, I provide driving means having 10 outputs coupled to aforementioned exciting inputs of individual ones of the register elements and effective for supplying thereover signals in regularly recurring sequence, starting at the first of the register elements and proceeding element by element through the register to 16 the last. Each such exciting signal produced by the driving means slightly overlaps in time the exciting signals occuring immediately before and thereafter and the lastoccurring exciting signal in each frame overlaps in time (he first-occurring signal in the next frame. Each excit20 ing signal is the same or greater duration as the signals supplied by the aforementioned random time signal source. With this arrangement, any signal occurring (i.e., an information bit stored) in one of the elements is _ advanced from that element through the succeeding ele25 ment in series and ultimately is produced at the register output as a useful signal in synchronism with the regularly occurring exciting signal applied to the last element of the series.

In order to provide an input signal for any one of the elements, I furnish a plurality of signal producing means which correspond in number to the number of elements in the register. Each signal producing means is operative for generating signals in coincidence with the signals applied to the exciting input of the element to which the ^d° individual signal producing means corresponds. A plurality of gates, each of which is individual to one of the signal producing means and register elements are provided, each gate being used for coupling the corresponding signal producing means to the first signal input of ^υ the next succeeding memory element in the aforementioned· series. Each gate has a control input and is operative only in response to the application of a signal thereto for passing signals from its signal producing means to its register element.

.^In. ^ord®^r (° control the gates, and therefore the admission of signals to the various register element inputs, I provide means for coupling the random time signal source to the control inputs of all the aforementioned gates. With this arrangement, a randomly-occuring signal 50 applied to the control input of any one of the gates must occur in a time position which corresponds to the time position of at least one of the signals applied to the exciting inputs of the register elements. Therefore, an information bit is inserted at that time within one of the ₆₅ register elements and subsequently is advanced toward and arrives at the register output in coincidence with the excitation of the last element within the register. This rephased signal, occurring only when the last register element is excited, can thereafter be utilized within other, g0 succeeding equipment.

In the description of the preferred embodiment of my invention which follows, reference is made to the drawings attached to and forming a part of the present specification in which :

Fig- 1 shows a schematic diagram of a parametricallyexcited resonator;

Figs. 2a and 2b show the symbols used to represent a parametrically-excited resonator;

Figs. 3a-3i show a series of signal vs. time curves havγθ ing a common time base; and

Fig. 4 shows a logic-schematic diagram of a signal ip. phasing system;

2,932,012 resonator. It is to be seen, at the left-hand end of the Fig. 3h signal curve, that the small resonant frequency signal cross the tank circuit and resonator output, which occurs when a resonant frequency signal is applied to ter5 minal 4, is built up within the tank circuit to a maximum upon and subsequent to the occurrence of the exciting signal on terminal 6. The output signal is thereafter main.- tained at the maximum level until the Fig. 3b exciting signal is removed from terminal 6, and, upon the disappear10 ance of the exciting signal, the output signal decays to zero.

Before leaving the consideration of the individual parametrically-excited resonator, it is pointed out that the resonator is bistable in the sense that it is capable of producing either first or second signals which are 180 degrees out-of-phase with each other when the phase of the input signal is regularly related to the phase of the exciting signal. The phase of the output signal appearing at terminal 7 (Fig. 3h) is the same phase as the input signal20 applied to terminal 4 (Fig. 3/). In Fig. 3f, the solid and broken signal curves represent first and second possible output signals at terminal 7. Thus, it is to be seen that by selectively applying to terminal 4 signals in “0” or π phase with reference to each other (represented by solid 25 and broken lines, respectively), “0” or π phase signals can be taken off at the output. It is this bistable characteristic which makes the parametrically-excited resonator particularly suited to my invention which is described below. In the description which follows, the “0” and π phase sig30 nals may be considered as “0” and “1” outputs, respectively, of each parametrically-excited resonator.

In order to simplify the Fig. 4 schematic drawing of the system representing my invention and the description thereof, each of the several parametrically-excited resona33 tors is represented by a circle, it being understood that all resonators function in substantially the same manner as the one described above. Referring to Figs. 2α and 26,. the circular symbols representing parametrically-excited resonators also have lines extending radially therefrom. ⁴⁰ Such radial lines have arrows pointing toward the circle and represent signal inputs, such as the one including terminal 4 in the above described Fig. 1 resonator. Similarly, a radial line having an arrow pointing away from the circle is used to represent an output, such as the one. ⁴⁸ including terminal 7 in the Fig. 1 resonator. A radial line running into the circle and bearing no arrow is used for representing the exciting input of the resonator.

Referring to the system shown in Fig. 4, I provide a source 40 capable of generating signals of substantially ⁵⁰ uniform duration at random times. Source 40 is coupled to the input of delay multivibrator 41 wherein the signals incoming from source 40 are shaped and reduced to signals of uniform width and which appear on output conductor 41α. The next described apparatus is directed ⁸⁵ to rephasing or shifting each such randomly-occurring signal into coincidence with one of regularly recurring reference signals.

In order to receive signals triggered by delay multivibrator 41,1 provide a shift register comprising first, sec⁸⁸ ond and third parametrically-excited esonators 42, 43 and 44, respectively, tuned to resonate at the same particular frequency. Each of resonators 42, 43 and 44 has a first signal input 42α, 43α and 44α, respectively, and an output 426, 43Z> and 44b, respectively. Resonators 42, 43 and ⁸⁸ 44 are arranged in a series, the outputs 42b and 43b of the first and intermediate parametric resonators being connected to the first signal inputs 43α and 44α, respectively, of the succeeding (or intermediate) and last of the parametric resonators 43 and 44 in the series. Each of ⁷⁰ resonators 42, 43 and.44 has a second input 42c, 43c and. 44c, respectively, the use of which is to be. explained presently. At this time, it is pointed out that output 44b of resonator 44 represents the output of the system, that 5 the, system: normally is to be effective for regularly, pro?

The memory units or elements used in the preferred embodiment of my invention are parametrically-excited resonators, which may be of the type described by Ei-ichi Goto in his paper entitled “On the Application of Parametrically-Excited Non-Linear Resonators” appearing in the Journal of Electrical Communications Engineering of June, 1955. In order to simplify the description of the preferred embodiment of my invention, which employs many such resonators, I next describe the operation of a single parametrically-excited resonator, it being understood that all resonators later referred to in this description function in substantially the same manner.

Fig. 1 shows a parametrically-excited resonator. A tank circuit in the resonator includes an inductance element consisting of series-connected, substantially elec- 15 trically-equal windings la and 2α of transformers 1 and 2, respectively, and capacitor 3 Coupled in parallel with the inductive element. Capacitor 3 and the inductance element are chosen to make the tank circuit resonate at a particular frequency.

In order to excite the tank circuit, means including continuously operating generator 13 coupled in series with a blocking capacitor 10 is connected through exciting signal input terminal 6 to the transformer 1 and 2 secondary windings lb and 2b, which are substantially equal to each other in the electrical sense and are connected in series opposition with respect to windings la and 2α. Generator 13 is selected so that its output signal is twice the resonant frequency of the above-described tank. The tank circuit exciting means also includes series-connected battery 12 and variable resistor 11 coupled in series with windings lb and 2b, the direct current flow from battery 12 being adjusted to the point where the flux density in the cores of transformers 1 and 2 is just less than saturation. With this arrangement, the small, periodic changes in current within windings lb and 2b of transformers 1 and 2 caused by generator 13 are effective for repeatedly driving the cores of transformers 1 and 2 between nonsaturated and saturated conditions, so that the inductance presented by windings la and 2α changes at frequency of the signals produced by generator 13. Since windings lb and 2b are connected in opposition to each other with respect to windings la and lb, no signal from generator 13 is detectable across the aforementioned tank and output terminal 7, which is connected across the tank. In the absence of an external signal applied across the aforementioned tank, the tank circuit does not resonate under the influence of signals applied to its excitation input from generator 13.

In order to start production of a signal in the parametrically-excited resonator, a plurality of signal inputs, such as terminal 4 and series-connected resistor 8, are provided. A momentary, ground-referenced signal of frequency substantially equal to the resonant frequency of the tank circuit from a source (not shown) applied to terminal 4 is coupled to the tank circuit by resistor 8. If no exciting signal is being applied to the tank circuit when a start signal is applied to terminal 8, the resonant frequency signal within the tank decays to zero subsequent to the removal of the start signal from terminal 4. However, application of a resonant frequency signal to terminal 4 when an exciting signal is present on terminal 6 causes a signal to be built up within the tank circuit by virtue of the above-described changes in the value of the tank circuit inductive element. This built-up signal directly coupled to the resonator output, which includes terminal 7, is continued subsequent to the removal of the start signal from terminal 4 and until the exciting signal is removed from terminal 4.

The relationship among input, exciting, and output signals is best demonstrated by comparing Figs. 3b, 3f and 3h which may be considered to represent the exciting and input signals applied to terminals 6 and 4 and the output signal measured at terminal 7, respectively, of the Fig. 1 ducing “0” signals, and that the system is to substitute a » phase or “1” signal for the one of the “0” signals in response to the appearance of a signal on conductor 41a.

Each resonator is further provided with an exciting input 42d, 43d and 44d. In order to excite each resonator 42, 43 and 44 sequentially and in the order named, I provide a clock 45 for producing a continuous sinusoidal signal at twice the resonant frequency of resonators 42, 43 and 44. The output of clock 45 is connected to the input of signal distributor 46. Distributor 46 has first, second and third outputs 47, 48 and 49 and is effective for admitting signals from clock 45 to those conductors in the order named and in the relationship indicated in Figs. 3a, 3b and 3c, respectively. The operation of distributor 46 is such that the signal appearing on any one of conductors 47, 48 or 49 slightly overlaps the signals present on the others of the conductors. Conductors 47, 48 and 49 are connected to the excitation inputs 44d, 42d, and 43d, respectively. In this manner, each of resonators 42, 43 and 44 is periodically fed an exciting signal which slightly overlaps the excitation signals applied to the next preceding and next succeeding one of the series of resonators.

In order to supply “0” signals to first resonator 42 within the shift register, I provide a frequency divider 50 having an input connected to clock 45. Frequency divider 50 is effective for intermittently producing signals, each of which is a first subharmonic of the signals produced by clock 45. In other words, divider 50 produces signals at half the frequency of clock 45 and in substantial coincidence with two consecutive complete signals produced by clock 45. The output signals of divider 50 are applied to the primary of transformer 51. The righthand, secondary winding of transformer 51 is tapped to ground, the signals appearing at its lower terminal being 180 degrees out-of-phase with the signals represented in Fig. 3e appearing at its upper terminal and conductor 60.

The lower winding terminal signals may be passed through other apparatus (not shown) which is effective for passing signals to conductor 59 during the times that exciting signals are present on conductor 48. Such signals are represented in Fig. 3d. It is to be understood that the signal chopping apparatus is not strictly necessary to the functioning of the apparatus used to practice my invention, but is included in order to make it easier for the reader to understand the operation of the apparatus.

From the above considerations, it is to be seen that divider 50 can be regarded as being equivalent to first and second signal generators which are operative for producing ir and intermittent 0” phase signals on conductors 60 and 59, respectively. Divider 50 is further arranged so that the “0” phase signal on conductor 59 are substantially equal to the amplitude of signals produced by resonators 42, 43 and 44.

The “0” signals from voltage divider 5® which are represented in Fig. 3d, are coupled directly to the first input 42α of resonator 42, so that the continuing “0” signals applied to resonator 42 are shifted through the various resonator stages and normally appear at output 44b of last resonator 44 in the register. Thus far, the operation described is basically similar to that described in the aforementioned Goto paper as a “normal” or “three-step” parametric excitation.

Upon the occurrence of a signal on conductor 41α, it is desired to cause the excited one of the register stages to transmit a π phase signal instead of the normal “0” signal. Accordingly, I provide means including parametrically-excited resonators 52, 53 and 54 for supplying π phase signals to second inputs 42c, 43c and 44c of resonators 42, 43 and 44, respectively. Each of resonators 52, 53 and 54 has a signal input, 52α, 53α and 54α coupled to the upper secondary winding terminal of transformer 51. Resonators 52, 53 and 54 also include exciting inputs 52b, 53b and 54b, respectively, connected to copductors 47_t 48 and 49, respectively. With this ar- ¹

4¾ ... o rangement,. each of resonators 52, 53 and 54 produces at its output 52c, 53c and 54c, respectively, a π phase signal represented in Fig. 3e, having an amplitude substantially twice that of the “0” signals on conductor 59 and normally appearing on first signal inputs 42α, 43α and 44α of resonators 42, 43 and 44, respectively.

In order to couple any of resonators 52, 53 and 54 of outputs 52c, 53c and 54c into the corresponding one of the aforementioned second inputs of resonators 42, 43 or 44,1 provide gates 55, 56 and 57. Each gate of gates 55, 56 and 57 has a control input, 55α, 56α and 57α, respectively, and is operative in response to the application of a signal thereto for making the gate pass signals from the corresponding one of resonators 52, 53 and 54 to the appropriate one of second signal input of gates 42, 43 and 44. The application of a “1” signal at double strength to the second input of any of stages 42, 43 or 44 m coincidence with the application of a normal strength “0” signal to the first input of any one of resonators 42, 43 or 44 at a time that an exciting signal is applied to the exciting input of the same resonator is effective for causing the resonator to produce a “1” output signal, rather than ₍the normal “0” signal. As in the case of 0” signals, a “1” signal produced and temporarily stored in any one 25 of resonators 42, 43 or 44 is shifted through the succeeding stages of the shift register and appears ultimately as a 1” signal on output 44b of resonator 44 for utilization in succeeding equipment (not shown).

In order to control gates 55, 56 and 57,1 provide means 30 for coupling the output conductor 41α of multivibrator 41 to each of control inputs 55α, 56α and 57α of gates 55, 56 and 57, respectively. With this arrangement, the appearance of a signal on conductor 41α at any instant in time must coincide at a time when at least one of resonators 35 52, 53 or 54 is excited. As a result, a π phase signal from the concurrently excited one of resonators 52, 53 and 54 passes into the one of shift register resonators 42, 43 or 44 which is to be next excited.

While the simultaneous enabling of gates 55 and 56 or 40 of gates 56 and 57 at a time when both resonators 52 and 53 or both resonators 53 and 54 are excited is without effect other than to admit a ir phase signal to the second inputs of resonators 42 and 43 or to the inputs of resonators 43 and 44. Such simultaneous input of π phase 45 signals to either of the aforementioned pairs of resonators must occur at a time when the one resonator of the pair closer to divider 50 in the series of shift register resonators has already been set to producing a “0” signal, the application of the 7Γ phase signal to the latter resonator is without effect, and the π phase signal is produced only in the one of the aforementioned resonator pairs remote from divider 5® in the series of shift register resonators. However, the simultaneous enabling of gates 57 and 55 by a pulse on conductor 41α which overlaps in time the excitation signals on conductors 47 and 49 could result in the transmission of two separate output signals, since it would be possible to set both resonators 44 and 42 to producing π phase signals at separate times. In order to prevent such a double output signal, I provide means including inverter 58 for coupling the output of gate 57 to a second input 52d of resonator 52. Inverter 58 is effective for supplying to input 52d a signal substantially the same, amplitude but 180 degrees out-of-phase with the input signal applied to input 52α of that same resonator. Consequently, the input signals applied to the inputs of resonator 52 cancel each other, and resonator 52 is made incapable of producing signals for application to resonator 42 during the interval that resonator 54 is supplying a signal to resonator 44 of the shift register.

While I have shown and described a specific embodiment of my invention, other modifications will readily occur to those skilled in the art. I do not therefore desire my invention to be limited to the specific arrange75 ment shown apd described, and I intend in the appended

2,932,012 each of said signal producing means being operative in response to the coincident application of signals to said signal and said exciting inputs thereof for producing signals on said output thereof; means for applying to 5 each of said signal producing means exciting signals in coincidence with signals applied to said exciting input of the corresponding one of said register elements; means for applying signals to each of said signal producing means; signal input in coincidence with signals applied to 10 said exciting input thereof; a plurality of gates, each of said gates being individual to a particular one of said signal producing means and having a control input; each of said gates being operative in response to the application of a signal applied to said control input thereof for 15 passing signals therethrough; means including said gates for coupling said outputs of the corresponding ones of said signal producing means to said first signal input of the next of said elements in said series; and means for coupling said random signal source to said control inputs 20 of said gates; whereby the production of signals by said random signal producing means allows the passage of signals from one of said signal producing means into the next succeeding one of said elements in said register, and the resulting signal stored in that one of said elements 25 is advanced to arrive at said register output in coincidence with the exciting signal applied to the last of said elements in said register.

3. In a system for phasing signals emanating from a source capable of producing signals of uniform duration 30 at random times; a shift register comprising a plurality of substantially identical memory elements disposed in a series; each of said elements having first and second signal inputs, an exciting input, and an output; said output of each of the first and intermediate of said elements 35 in said series being coupled to said second signal input of the next succeeding one of said elements in said series, said output of the last of said elements in said series constituting an output for said register; each of said elements being operative in response to the coincident ap40 plication of a signal to said exciting input and signals of particular characteristics to said signal inputs for producing for the duration of the signal applied to said exciting input on said output a signal having the same characteristics as the one of the signals applied to said inputs 45 having greater amplitude; driving means operative for repetitively applying signals of at least the same duration as signals produced by said random time signal source in sequence to said exciting input of each of said elements in the order of occurrence of said elements in said 50 series in order to advance a signal stored within any one of said elements to said register output; a first generator operative for applying to said second signal input of the first of said series elements signals of first characteristic substantially in coincidence with signals applied to said 55 exciting input of the first of said register elements and of amplitude substantially equal to signals produced at said outputs of said memory elements; a second generator operative for producing signals of a second characteristic in coincidence with each signal produced by 60 said driving means; a plurality of signal producing means; each of said signal producing means corresponding to one of said register elements and having an input coupled to said second generator, an exciting input coupled in parallel with said exciting input of the corre65 spending one of said register elements, and an output; each of said signal producing means being operative, in response to the application of a signal to said exciting input thereof and to the coincident application of a signal of a particular characteristic to said signal in70 put thereof for producing a signal of the same characteristic and of amplitude substantially greater than signals produced by said first generator and said register elements at said output thereof for the duration of the signal applied to said exciting input thereof; a plurality 75 of gates, each of said gates corresponding to a particu· claims to cover all such modifiactions falling within the spirit and scope of my invention.