Semiconductor package

CROSS-REFERENCE TO RELATED APPLICATION(S)

0001This application claims benefit of priority to Korean Patent Application No. 10-2018-0135128 filed on Nov. 6, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

0002The present disclosure relates to a semiconductor package.

2. Description of Related Art

0003A significant recent trend in the development of technology related to semiconductor chips has been reductions in the size of semiconductor chips. Therefore, in the field of package technology, in accordance with a rapid increase in demand for small-sized semiconductor chips, or the like, demand for semiconductor packages having a compact size while including a plurality of pins has increased.

0004One type of package technology suggested to satisfy the technical demand as described above may be a fan-out semiconductor package. Such a fan-out semiconductor package has a compact size and may allow a plurality of pins to be implemented by redistributing connection terminals up to a region that is out of a region overlapping a semiconductor chip. Meanwhile, a semiconductor package has been recently required to improve heat dissipation characteristics.

SUMMARY

0005An aspect of the present disclosure may provide a semiconductor package in which heat dissipation characteristics are improved.

0006According to an aspect of the present disclosure, a semiconductor package may include a connection structure having first and second surfaces opposing each other and including a redistribution layer. A semiconductor chip is disposed on the first surface of the connection structure and has connection pads connected to the redistribution layer. An encapsulant is disposed on the first surface of the connection structure and covers the semiconductor chip, and a support pattern is disposed on a partial region of an upper surface of the encapsulant. A heat dissipation bonding material has a portion embedded in the encapsulant in a region overlapping the semiconductor chip and extends to the upper surface of the encapsulant so as to cover the support pattern. A heat dissipation element is bonded to the upper surface of the encapsulant by the heat dissipation bonding material.

0007According to another aspect of the present disclosure, a semiconductor package may include a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. A connection structure is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads, and an encapsulant covers the inactive surface of the semiconductor chip and has a concave portion formed in a region overlapping the semiconductor chip. A support pattern is disposed on at least a region of an upper surface of the encapsulant positioned in the vicinity of the concave portion, and a heat dissipation bonding material is disposed in the concave portion and extends to the upper surface of the encapsulant so as to cover the support patter. A heat dissipation element is disposed on the upper surface of the encapsulant so as to cover the heat dissipation bonding material and is bonded to the encapsulant by the heat dissipation bonding material.

0008According to a further aspect of the present disclosure, a semiconductor package includes a semiconductor chip having an active surface with connection pads thereon and a second surface opposite to the active surface. An encapsulant contacts the semiconductor chip and has an opening overlapping with the semiconductor chip in a surface of the encapsulant facing away from the second surface of the semiconductor chip. A support pattern is disposed adjacent to the opening on the surface of the encapsulant facing away from the semiconductor chip, and a bonding material is disposed in the opening of the encapsulant and covers at least a portion of the support pattern adjacent to the opening. A heat dissipation element is disposed on the bonding material to overlap the opening.

BRIEF DESCRIPTION OF DRAWINGS

0009The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

0010<figref idref="DRAWINGS">FIG. 1</figref> is a schematic block diagram illustrating an example of an electronic device system;

0011<figref idref="DRAWINGS">FIG. 2</figref> is a schematic perspective view illustrating an example of an electronic device;

0012<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are schematic cross-sectional views illustrating a fan-in semiconductor package before and after being packaged;

0013<figref idref="DRAWINGS">FIG. 4</figref> is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package;

0014<figref idref="DRAWINGS">FIG. 5</figref> is a schematic cross-sectional view illustrating a fan-in semiconductor package mounted on an interposer substrate and ultimately mounted on a mainboard of an electronic device;

0015<figref idref="DRAWINGS">FIG. 6</figref> is a schematic cross-sectional view illustrating a fan-in semiconductor package embedded in an interposer substrate and ultimately mounted on a mainboard of an electronic device;

0016<figref idref="DRAWINGS">FIG. 7</figref> is a schematic cross-sectional view illustrating a fan-out semiconductor package;

0017<figref idref="DRAWINGS">FIG. 8</figref> is a schematic cross-sectional view illustrating a fan-out semiconductor package mounted on a mainboard of an electronic device;

0018<figref idref="DRAWINGS">FIG. 9</figref> is a schematic cross-sectional view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure;

0019<figref idref="DRAWINGS">FIG. 10</figref> is a plan view taken along line I-I′ of the semiconductor package of <figref idref="DRAWINGS">FIG. 9</figref>;

0020<figref idref="DRAWINGS">FIG. 11</figref> is a plan view illustrating the semiconductor package of <figref idref="DRAWINGS">FIG. 9</figref>;

0021<figref idref="DRAWINGS">FIG. 12</figref> is a schematic plan view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure; and

0022<figref idref="DRAWINGS">FIGS. 13 through 17</figref> are schematic cross-sectional views illustrating semiconductor packages according to various other exemplary embodiments in the present disclosure.

DETAILED DESCRIPTION

0023Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity.

0024Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a downward direction in relation to cross sections of the drawings for convenience, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the downward direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above, and concepts of upper and lower portions may be exchanged with each other.

0025The meaning of a “connection” of a component to another component in the description conceptually includes an indirect connection through an adhesive layer as well as a direct connection between two components. In addition, “electrically connected” conceptually includes a physical connection and a physical disconnection. It can be understood that when an element is referred to with terms such as “first” and “second”, the element is not limited thereby. They may be used only for a purpose of distinguishing the element from the other elements, and may not limit the sequence or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

0026The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

0027Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

0028<figref idref="DRAWINGS">FIG. 1</figref> is a schematic block diagram illustrating an example of an electronic device system.

0029Referring to <figref idref="DRAWINGS">FIG. 1</figref>, an electronic device <b>1000</b> may accommodate a mainboard <b>1010</b> therein. The mainboard <b>1010</b> may include chip related components <b>1020</b>, network related components <b>1030</b>, other components <b>1040</b>, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines <b>1090</b>.

0030The chip related components <b>1020</b> may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital (ADC) converter, an application-specific integrated circuit (ASIC), or the like. However, the chip related components <b>1020</b> are not limited thereto, but may also include other types of chip related components. In addition, the chip related components <b>1020</b> may be combined with each other.

0031The network related components <b>1030</b> may include protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical And

0032Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+ (HSPA+), high speed downlink packet access+ (HSDPA+), high speed uplink packet access+ (HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols, designated after the abovementioned protocols. However, the network related components <b>1030</b> are not limited thereto, but may also include a variety of other wireless or wired standards or protocols. In addition, the network related components <b>1030</b> may be combined with each other, together with the chip related components <b>1020</b> described above.

0033Other components <b>1040</b> may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-fired ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), or the like. However, other components <b>1040</b> are not limited thereto, but may also include passive components used for various other purposes, or the like. In addition, other components <b>1040</b> may be combined with each other, together with the chip related components <b>1020</b> or the network related components <b>1030</b> described above.

0034Depending on a type of the electronic device <b>1000</b>, the electronic device <b>1000</b> may include other components that may or may not be physically or electrically connected to the mainboard <b>1010</b>. These other components may include, for example, a camera <b>1050</b>, an antenna <b>1060</b>, a display <b>1070</b>, a battery <b>1080</b>, an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage unit (for example, a hard disk drive) (not illustrated), a compact disk (CD) drive (not illustrated), a digital versatile disk (DVD) drive (not illustrated), or the like. However, these other components are not limited thereto, but may also include other components used for various purposes depending on a type of electronic device <b>1000</b>, or the like.

0035The electronic device <b>1000</b> may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like. However, the electronic device <b>1000</b> is not limited thereto, but may be any other electronic device processing data.

0036<figref idref="DRAWINGS">FIG. 2</figref> is a schematic perspective view illustrating an example of an electronic device.

0037Referring to <figref idref="DRAWINGS">FIG. 2</figref>, a semiconductor package may be used for various purposes in the various electronic devices <b>1000</b> as described above. For example, a motherboard <b>1110</b> may be accommodated in a body <b>1101</b> of a smartphone <b>1100</b>, and various electronic components <b>1120</b> may be physically or electrically connected to the motherboard <b>1110</b>. In addition, other components that may or may not be physically or electrically connected to the mainboard <b>1010</b>, such as a camera module <b>1130</b>, may be accommodated in the body <b>1101</b>. Some of the electronic components <b>1120</b> may be the chip related components, and the semiconductor package <b>100</b> may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone <b>1100</b>, but may be other electronic devices as described above.

Semiconductor Package

0038Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in oneself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip is not used in oneself, and is packaged and is used in an electronic device, or the like, in a package state.

0039The reason why semiconductor packaging is used is that there is a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connection. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor and the mainboard is used.

0040A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

0041The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the accompanying drawings.

Fan-In Semiconductor Package

0042<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged, and <figref idref="DRAWINGS">FIG. 4</figref> is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

0043Referring to <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, a semiconductor chip <b>2220</b> may be, for example, an integrated circuit (IC) in a bare state, including a body <b>2221</b> including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads <b>2222</b> formed on one surface of the body <b>2221</b> and including a conductive material such as aluminum (Al), or the like, and a passivation layer <b>2223</b> such as an oxide layer, a nitride layer, or the like, formed on one surface of the body <b>2221</b> and covering at least portions of the connection pads <b>2222</b>. Since the connection pads <b>2222</b> may be significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

0044Therefore, a connection structure <b>2240</b> may be formed depending on a size of the semiconductor chip <b>2220</b> on the semiconductor chip <b>2220</b> in order to redistribute the connection pads <b>2222</b>. The connection structure <b>2240</b> may be formed by forming an insulating layer <b>2241</b> on the semiconductor chip <b>2220</b> using an insulating material such as a photoimageable dielectric (PID) resin, forming via holes <b>2243</b><i>h </i>opening the connection pads <b>2222</b>, and then forming wiring patterns <b>2242</b> and vias <b>2243</b>. Then, a passivation layer <b>2250</b> protecting the connection structure <b>2240</b> may be formed, an opening <b>2251</b> may be formed, and an underbump metal layer <b>2260</b>, or the like, maybe formed. That is, a fan-in semiconductor package <b>2200</b> including, for example, the semiconductor chip <b>2220</b>, the connection structure <b>2240</b>, the passivation layer <b>2250</b>, and the underbump metal layer <b>2260</b> may be manufactured through a series of processes.

0045As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost.

0046Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

0047However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in the case in which a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

0048<figref idref="DRAWINGS">FIG. 5</figref> is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device, and <figref idref="DRAWINGS">FIG. 6</figref> is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

0049Referring to <figref idref="DRAWINGS">FIGS. 5 and 6</figref>, in a fan-in semiconductor package <b>2200</b>, connection pads <b>2222</b>, that is, I/O terminals, of a semiconductor chip <b>2220</b> may be redistributed once more through an interposer substrate <b>2301</b>, and the fan-in semiconductor package <b>2200</b> may be ultimately mounted on a mainboard <b>2500</b> of an electronic device in a state in which it is mounted on the interposer substrate <b>2301</b>. In this case, low melting point metal or alloy balls <b>2270</b>, and the like, may be fixed by an underfill resin <b>2280</b>, or the like, and an outer side of the semiconductor chip <b>2220</b> may be covered with an encapsulant <b>2290</b>, or the like. Alternatively, a fan-in semiconductor package <b>2200</b> maybe embedded in a separate interposer substrate <b>2302</b>, connection pads <b>2222</b>, that is, I/O terminals, of a semiconductor chip <b>2220</b> may be redistributed once more by the interposer substrate <b>2302</b> in a state in which the fan-in semiconductor package <b>2200</b> is embedded in the interposer substrate <b>2302</b>, and the fan-in semiconductor package <b>2200</b> may be ultimately mounted on a mainboard <b>2500</b> of an electronic device.

0050As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-Out Semiconductor Package

0051<figref idref="DRAWINGS">FIG. 7</figref> is a schematic cross-sectional view illustrating a fan-out semiconductor package.

0052Referring to <figref idref="DRAWINGS">FIG. 7</figref>, in a fan-out semiconductor package <b>2100</b>, for example, an outer side of a semiconductor chip <b>2120</b> may be protected by an encapsulant <b>2130</b>, and connection pads <b>2122</b> of the semiconductor chip <b>2120</b> may be redistributed outwardly of the semiconductor chip <b>2120</b> by a connection structure <b>2140</b>. In this case, a passivation layer <b>2150</b> may further be formed on the connection structure <b>2140</b>, and an underbump metal layer <b>2160</b> may further be formed in openings of the passivation layer <b>2150</b>. Low melting point metal or alloy balls <b>2170</b> may be further formed on the underbump metal layer <b>2160</b>. The semiconductor chip <b>2120</b> may be an integrated circuit (IC) including a body <b>2121</b>, the connection pads <b>2122</b>, a passivation layer (not illustrated), and the like. The connection structure <b>2140</b> may include an insulating layer <b>2141</b>, redistribution layers <b>2142</b> formed on the insulating layer <b>2141</b>, and vias <b>2143</b> electrically connecting the connection pads <b>2122</b> and the redistribution layers <b>2142</b> to each other.

0053In the present manufacturing process, the connection structure <b>2140</b> may be formed after the encapsulant <b>2130</b> is formed outside the semiconductor chip <b>2120</b>. In this case, the connection structure <b>2140</b> may be formed after the semiconductor chip <b>2120</b> is encapsulated, and the vias <b>2143</b> connected to the redistribution layers may thus have a width that becomes small as they become close to the semiconductor chip (see an enlarged region).

0054As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection structure formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection structure formed on the semiconductor chip as described above. Therefore, even in the case in which a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

0055<figref idref="DRAWINGS">FIG. 8</figref> is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device.

0056Referring to <figref idref="DRAWINGS">FIG. 8</figref>, a fan-out semiconductor package <b>2100</b> may be mounted on a mainboard <b>2500</b> of an electronic device through low melting point metal or alloy balls <b>2170</b>, or the like. That is, as described above, the fan-out semiconductor package <b>2100</b> includes the connection structure <b>2140</b> formed on the semiconductor chip <b>2120</b> and capable of redistributing the connection pads <b>2122</b> to a fan-out region that is outside of a size of the semiconductor chip <b>2120</b>, such that the standardized ball layout may be used in the fan-out semiconductor package <b>2100</b> as it is. As a result, the fan-out semiconductor package <b>2100</b> may be mounted on the mainboard <b>2500</b> of the electronic device without using a separate interposer substrate, or the like.

0057As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out electronic component package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

0058Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

0059<figref idref="DRAWINGS">FIG. 9</figref> is a schematic cross-sectional view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure, and <figref idref="DRAWINGS">FIG. 10</figref> is a plan view taken along line I-I′ of the semiconductor package of <figref idref="DRAWINGS">FIG. 9</figref>.

0060Referring to <figref idref="DRAWINGS">FIGS. 9 and 10</figref>, a semiconductor package <b>100</b> according to the present exemplary embodiment may include a connection structure <b>140</b> having a first surface <b>140</b>A and a second surface <b>140</b>B opposing each other, a semiconductor chip <b>120</b> disposed on the first surface <b>140</b>A of the connection structure <b>140</b>, and an encapsulant <b>130</b> disposed on the first surface <b>140</b>A of the connection structure <b>140</b> and encapsulating the semiconductor chip <b>120</b>.

0061The semiconductor package <b>100</b> may further include a frame <b>110</b>, a wiring pattern <b>132</b>, wiring vias <b>133</b>, first and second passivation layers <b>150</b>A and <b>150</b>B, underbump metals <b>160</b>, electrical connection metals <b>170</b>, a heat dissipation bonding material <b>182</b>, and a heat dissipation element <b>185</b>.

0062The connection structure <b>140</b> may include three-layered redistribution layers <b>142</b> implemented on a plurality of (for example, three) insulating layers <b>141</b>, and connection pads <b>122</b> of the semiconductor chip <b>120</b> disposed on the first surface <b>140</b>A of the connection structure <b>140</b> may be connected to the redistribution layers <b>142</b>.

0063The frame <b>110</b> may be disposed on the first surface <b>140</b>A of the connection structure <b>140</b>, and may include a cavity <b>110</b>H in which the semiconductor chip <b>120</b> is accommodated. The frame <b>110</b> may include a wiring structure connecting an upper surface and a lower surface of the frame <b>110</b> with each other. The wiring structure used in the present exemplary embodiment may include three-layered wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>and first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>connecting the three-layered wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>to each other, but is not limited thereto. In some exemplary embodiments, the wiring structure may be formed to have layers of which the number is different from that in the present exemplary embodiment and a structure different from that described in the present exemplary embodiment (see, e.g., <figref idref="DRAWINGS">FIG. 16</figref>). The wiring structure (particularly, a first wiring layer <b>112</b><i>a</i>) of the frame <b>110</b> may be connected to (e.g., in contact with) the redistribution layer <b>142</b> of the connection structure <b>140</b>.

0064In the present exemplary embodiment, the encapsulant <b>130</b> may extend to cover the upper surface of the frame <b>110</b>. The semiconductor package <b>100</b> may further include a wiring pattern <b>132</b> disposed on the encapsulant <b>130</b> and electrically connected to the wiring structure. The wiring pattern <b>132</b> and the wiring structure (particularly, a third wiring layer <b>112</b><i>c</i>) may be connected to each other through the wiring vias <b>133</b> penetrating through the encapsulant <b>130</b>.

0065A heat dissipation system used in the present exemplary embodiment may include the heat dissipation bonding material <b>182</b> partially embedded in the encapsulant <b>130</b> and the heat dissipation element <b>185</b> bonded to the encapsulant <b>130</b> using the heat dissipation bonding material <b>182</b>.

0066As illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, the heat dissipation bonding material <b>182</b> may include a portion <b>182</b><i>b </i>embedded in a region of the encapsulant <b>130</b> overlapping the semiconductor chip <b>120</b> and a portion <b>182</b><i>a </i>extending from the embedded portion <b>182</b><i>b </i>and disposed on an upper surface of the encapsulant <b>130</b>. The heat dissipation element <b>185</b> may be disposed on the upper surface of the encapsulant <b>130</b> so as to cover the heat dissipation bonding material <b>182</b>.

0067In such an arrangement, the heat dissipation bonding material <b>182</b> may be provided as a heat dissipation path between the heat dissipation element <b>185</b> and the semiconductor chip <b>120</b>. In order to provide the embedded portion <b>182</b><i>b, </i>a concave portion CP or opening may be formed in the region of the encapsulant <b>130</b> overlapping the semiconductor chip <b>120</b>. The concave portion CP used in the present exemplary embodiment may extend up to and contact an inactive surface of the semiconductor chip <b>120</b>. That is, a bottom surface of the concave portion CP may be provided by the inactive surface of the semiconductor chip <b>120</b> (e.g., a surface of the semiconductor chip <b>120</b> opposing a surface of the semiconductor chip <b>120</b> on which the connection pads <b>122</b> are disposed).

0068A case in which the concave portion CP used in the present exemplary embodiment has a single structure is exemplified, but the concave portion CP may be modified to have various structures (for example, a plurality of through-holes or openings), which will be described in detail below (see, e.g., <figref idref="DRAWINGS">FIGS. 13 through 15</figref>).

0069In the present exemplary embodiment, the heat dissipation bonding material <b>182</b> may be connected to (e.g., in contact with) the inactive surface of the semiconductor chip <b>120</b> through the concave portion CP, and thus, may more effectively dissipate heat from the semiconductor chip <b>120</b>.

0070As described above, the heat dissipation bonding material <b>182</b> used in the present exemplary embodiment may be used as a unit bonding the heat dissipation element <b>185</b> and the encapsulant <b>130</b> to each other as well as the heat dissipation path between the heat dissipation element <b>185</b> and the semiconductor chip <b>120</b>.

0071The heat dissipation element <b>185</b> may include, for example, a heat sink, a heat spreader, a heat pipe, or a liquid cooled cool plate. The heat dissipation bonding material <b>182</b> may include a low melting point metal, for example, a low melting point metal such as tin (Sn)-aluminum (Al)-copper (Cu) alloy/mixture. However, the heat dissipation bonding material <b>182</b> is not limited thereto, and may include any material having heat dissipation characteristics and a bonding function. For example, the heat dissipation bonding material <b>182</b> may include a thermal interface material (TIM).

0072In the present exemplary embodiment, a support pattern <b>132</b>S disposed on a partial region of the upper surface of the encapsulant <b>130</b> may be additionally provided. The support pattern <b>132</b>S may be used as a unit enhancing bonding strength between the heat dissipation bonding material <b>182</b> and the encapsulant <b>130</b>.

0073As illustrated in <figref idref="DRAWINGS">FIG. 11</figref>, the support pattern <b>132</b>S may be formed in a ring structure along the surrounding of the concave portion CP on the upper surface of the encapsulant <b>130</b>. Since the extending portion <b>182</b><i>a </i>of the heat dissipation bonding material <b>182</b> is formed to cover the support pattern <b>132</b>S, the heat dissipation bonding material <b>182</b> may be firmly bonded to the support pattern <b>132</b>S with a sufficient contact area. The heat dissipation bonding material <b>182</b> may be maintained in a state in which it is more stably bonded to the encapsulant <b>130</b> by the support pattern <b>132</b>S.

0074In some exemplary embodiments, when the heat dissipation bonding material <b>182</b> and the encapsulant <b>130</b> are formed of heterogeneous materials, for example, when the heat dissipation bonding material <b>182</b> is formed of a low melting point metal and the encapsulant <b>130</b> is formed of a resin such as ABF, the support pattern <b>132</b>S, which is a metal pattern, may be formed on the upper surface of the encapsulant <b>130</b> in advance, and the heat dissipation bonding material <b>182</b> may be formed to cover the support pattern <b>132</b>S to ensure the stable bonding between the encapsulant <b>130</b> and the heat dissipation bonding material <b>182</b>. As a result, the heat dissipation element <b>185</b> bonded to the heat dissipation bonding material <b>182</b> may be stably bonded to the surface of the encapsulant <b>130</b>.

0075In some exemplary embodiments, the support pattern <b>132</b>S may include the same metal as that of the wiring pattern <b>132</b>. In detail, the support pattern <b>132</b>S may be formed together with the wiring pattern <b>132</b> and the wiring vias <b>133</b> in a process of forming the wiring pattern <b>132</b> and the wiring vias <b>133</b> (for example, seed layer forming/dry film resist (DFR) patterning/plating process). For example, the support pattern <b>132</b> may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or combinations thereof.

0076A case in which the support pattern <b>132</b>S is a continuous pattern having the ring structure is illustrated in <figref idref="DRAWINGS">FIG. 11</figref>. However, the support pattern <b>132</b>S is not limited thereto, and may have discontinuous patterns, as illustrated in <figref idref="DRAWINGS">FIG. 12</figref>. Referring to <figref idref="DRAWINGS">FIG. 12</figref>, the support pattern <b>132</b>S may include a plurality of patterns disposed at four corners of a rectangle, respectively, and having a ‘<img file="US2020144192A1_D0001.tif" />’ shape, as an example of the discontinuous patterns.

0077Main components of the semiconductor package <b>100</b> according to the present exemplary embodiment will hereinafter be described in more detail.

0078The frame <b>110</b> may improve rigidity of the semiconductor package <b>100</b> depending on certain materials, and serve to secure uniformity of a thickness of the encapsulant <b>130</b>. Since the frame <b>110</b> has the wiring structure connecting the upper and lower surfaces of the frame <b>110</b> with each other, the semiconductor package <b>100</b> may be utilized as a package-on-package (POP)-type package. The semiconductor chip <b>120</b> disposed in the cavity <b>110</b>H of the frame <b>110</b> may be disposed to be spaced apart from inner sidewalls of the frame <b>110</b> by a predetermined distance. Side surfaces of the semiconductor chip <b>120</b> may be surrounded by the frame <b>110</b>. However, such a form is only an example and may be variously modified to have other forms, and the frame <b>110</b> may perform another function depending on such a form.

0079As described above, the frame <b>110</b> may include a first insulating layer <b>111</b><i>a </i>in contact with the connection structure <b>140</b>, a first wiring layer <b>112</b><i>a </i>in contact with the connection structure <b>140</b> and embedded in the first insulating layer <b>111</b><i>a, </i>a second wiring layer <b>112</b><i>b </i>disposed on the other surface of the first insulating layer <b>111</b><i>a </i>opposing one surface of the first insulating layer <b>111</b><i>a </i>in which the first wiring layer <b>112</b><i>a </i>is embedded, a second insulating layer <b>111</b><i>b </i>disposed on the first insulating layer <b>111</b><i>a </i>and covering the second wiring layer <b>112</b><i>b, </i>and a third wiring layer <b>112</b><i>c </i>disposed on the second insulating layer <b>111</b><i>b. </i>The first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>may be electrically connected to connection pads <b>122</b>. The first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>may be electrically connected to each other through first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>each penetrating through the first to second insulating layers <b>111</b><i>a </i>and <b>111</b><i>b. </i>

0080When the first wiring layer <b>112</b><i>a </i>is embedded in the first insulating layer <b>111</b><i>a </i>as in the present exemplary embodiment, a step generated due to a thickness of the first wiring layer <b>112</b><i>a </i>may be significantly reduced, and an insulating distance of the connection structure <b>140</b> may thus become constant. The first wiring layer <b>112</b><i>a </i>may be recessed in the first insulating layer <b>111</b><i>a, </i>such that a lower surface of the first insulating layer <b>111</b><i>a </i>and a lower surface of the first wiring layer <b>112</b><i>a </i>may have a step therebetween. In this case, a phenomenon in which a material of an encapsulant <b>130</b> bleeds to pollute the first wiring layer <b>112</b><i>a </i>may be prevented. The frame <b>110</b> may be manufactured at a sufficient thickness by a substrate process, or the like, while the connection structure <b>140</b> may be manufactured by a semiconductor process, or the like so as to have a small thickness. Therefore, a thickness of each of the first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>of the frame <b>110</b> may be greater than that of each of the redistribution layers <b>142</b> of the connection structure <b>140</b>.

0081A material of each of the first and second insulating layers <b>111</b><i>a </i>and <b>111</b><i>b </i>may be, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. In some exemplary embodiments, a photoimageable dielectric (PID) resin may also be used as the insulating material. In terms of maintenance of rigidity, the prepreg may be used as the material of each of the first and second insulating layers <b>111</b><i>a </i>and <b>111</b><i>b. </i>

0082The first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>may serve to redistribute the connection pads <b>122</b> of the semiconductor chip <b>120</b>. Each of the first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>may perform various functions depending on designs of corresponding layers. For example, the first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>may include via pads, wire pads, ball pads, and the like.

0083The first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>may electrically connect the first to third wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i>and <b>112</b><i>c </i>formed on different insulating layers <b>111</b><i>a </i>and <b>111</b><i>b </i>to each other to form a wiring structure having an interlayer connection path within the frame <b>110</b>. A material of each of the first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>may be the conductive material described above. Each of the first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>may be a filled-type via filled with the conductive material, or be a conformal-type via in which the conductive material may be formed along a wall of each of via holes. Meanwhile, depending on a process, the first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>may have tapered shapes of which directions are the same as each other, that is, tapered shapes of which widths of upper portions are greater than those of lower portions, in relation to a cross section. When the first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>are formed by the same plating process, the first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>may be integrated with the second and third wiring layers <b>112</b><i>b </i>and <b>112</b><i>c. </i>

0084The semiconductor chip <b>120</b> may be an integrated circuit (IC) provided in an amount of several hundred to several million or more elements integrated in a single chip. In this case, the IC may be, for example, a processor chip (more specifically, an application processor (AP)) such as a central processor (for example, a CPU), a graphic processor (for example, a GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, or the like, but is not limited thereto. For example, the IC may be a memory chip such as a volatile memory (for example, a DRAM), a non-volatile memory (for example, a ROM), a flash memory, or the like, a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), or the like, or another kind of chip such as a power management IC (PMIC), or a combination of some thereof.

0085The semiconductor chip <b>120</b> may be formed on the basis of an active wafer. In this case, a base material of a body <b>121</b> may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body <b>121</b>. The connection pads <b>122</b> may electrically connect the semiconductor chip <b>120</b> to other components. A material of each of the connection pads <b>122</b> may be a conductive material such as aluminum (Al), copper (Cu), or the like. A passivation layer <b>123</b> opening the connection pads <b>122</b> may be formed on an active surface of the body <b>121</b>, and may be an oxide layer, a nitride layer, or the like, or a double layer of an oxide layer and a nitride layer. A lower surface of the connection pad <b>122</b> may have a step with respect to a lower surface of the encapsulant <b>130</b> through the passivation layer <b>123</b>. Therefore, the encapsulant <b>130</b> may fill at least portions of a space between the passivation layer <b>123</b> and the connection structure <b>140</b>.

0086In this case, a phenomenon in which the encapsulant <b>130</b> bleeds into the lower surface of the connection pad <b>122</b> may be prevented to some degree. An insulating layer (not illustrated), and the like, may also be further disposed in other appropriate positions. The semiconductor chip <b>120</b> may be a bare die, and the connection pads <b>122</b> may thus be in physical contact with connection vias <b>143</b> of the connection structure <b>140</b>. However, depending on a kind of semiconductor chip <b>120</b>, a separate redistribution layer (not illustrated) may further be formed on an active surface of the semiconductor chip <b>120</b>, and bumps (not illustrated), or the like, may be connected to the connection pads <b>122</b>.

0087The encapsulant <b>130</b> may protect the frame <b>110</b>, the semiconductor chip <b>120</b>, and the like. An encapsulation form of the encapsulant <b>130</b> is not particularly limited, but may be a form in which the encapsulant <b>130</b> surrounds at least portions of each of the frame <b>110</b> and the semiconductor chip <b>120</b>. For example, the encapsulant <b>130</b> may cover the frame <b>110</b> and an inactive surface (e.g., a surface opposite to the active surface on which the connection pads <b>122</b> are formed, or a surface on which the connection pads <b>122</b> are not formed) of the semiconductor chip <b>120</b>, and fill at least portions of the cavity <b>110</b>H. The encapsulant <b>130</b> may fill the cavity <b>110</b>H to thus serve as an adhesive and reduce buckling of the semiconductor chip <b>120</b> depending on certain materials.

0088A material of the encapsulant <b>130</b> may be, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber, or the like, but is not limited thereto. In some exemplary embodiments, a material of the encapsulant <b>130</b> may be a thermosetting resin such as prepreg, ABF, FR-<b>4</b>, or BT or a photoimageable encapsulant (PIE) resin.

0089The wiring pattern <b>132</b> may be formed on the encapsulant <b>130</b> and be connected to the wiring structure (particularly, the third wiring layer <b>112</b><i>c</i>), as described above. The wiring vias <b>133</b> may penetrate through at least portions of the encapsulant <b>130</b>, and may electrically connect the third wiring layer <b>112</b><i>c, </i>which is the uppermost wiring layer of the frame <b>110</b>, and the wiring pattern <b>132</b> to each other. A material of each of the wiring pattern <b>132</b> and the wiring via <b>133</b> may be the conductive material described above, and be a metal such as copper (Cu) in some exemplary embodiments. In addition, each of the wiring pattern <b>132</b> and the wiring via <b>133</b> may be a plurality of conductor layers including a seed layer and a plating layer. The wiring pattern <b>132</b> may perform various functions depending on a design. For example, the wiring pattern <b>132</b> may include ground patterns, power patterns, signal patterns, and the like. The wiring via <b>133</b> may also have a tapered shape of which a width of an upper surface is greater than that of a lower surface, in relation to a cross section.

0090The connection structure <b>140</b> may redistribute the connection pads <b>122</b> of the semiconductor chip <b>120</b>. Several tens to several hundreds of connection pads <b>122</b> of the semiconductor chip <b>120</b> having various functions may be redistributed by the connection structure <b>140</b>, and may be physically and/or electrically externally connected through the electrical connection metals <b>170</b> depending on the functions.

0091The connection structure <b>140</b> may include insulating layers <b>141</b> in contact with the frame <b>110</b> and the semiconductor chip <b>120</b>, the redistribution layers <b>142</b> disposed on the insulating layers <b>141</b>, and the vias <b>143</b> penetrating through the insulating layers <b>141</b> and connecting the connection pads <b>122</b> and the redistribution layers <b>142</b> to each other. A case in which the connection structures <b>140</b> include three insulating layers <b>141</b> and three-layered redistribution layers <b>142</b> and vias <b>143</b> is exemplified in <figref idref="DRAWINGS">FIG. 9</figref>, but the connection structure <b>140</b> may be implemented as a single layer or two layers or as a larger number of layers than three layers in another exemplary embodiment.

0092A material of each of the insulating layers <b>141</b> may be a photosensitive insulating material such as a PID resin, in addition to the insulating material described above. When the insulating layer <b>141</b> has photosensitive properties, the insulating layer <b>141</b> may be formed to have a smaller thickness, and a fine pitch of the connection via <b>143</b> maybe achieved more easily by a photolithography process. In some exemplary embodiments, each of the insulating layers <b>141</b> may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layers <b>141</b> are multiple layers, materials of the insulating layers <b>141</b> may be the same as each other, and may also be different from each other. Even though the insulating layers <b>141</b> are the multiple layers, a boundary between the insulating layers <b>141</b> may also not be apparent.

0093The redistribution layers <b>142</b> may serve to substantially redistribute the connection pads <b>122</b>, and may be formed of the conductive material described above. The redistribution layers <b>142</b> may perform various functions depending on designs of corresponding layers. For example, the redistribution layers <b>142</b> may include ground patterns, power patterns, signal patterns, and the like. Here, the signal patterns may include various signals except for the ground patterns, the power patterns, and the like, such as data signals, and the like, and may include pad patterns having various shapes.

0094The vias <b>143</b> may electrically connect the redistribution layers <b>142</b> formed on different layers, the connection pads <b>122</b>, and the like, to each other, and form an electrical path in a vertical direction (interlayer electrical path) within the semiconductor package <b>100</b>. A material of each of the vias <b>143</b> may be the conductive material described above. Each of the vias <b>143</b> may be completely filled with the conductive material or the conductive material may be formed along a wall of each of the via holes. Meanwhile, each of the vias <b>143</b> of the connection structure <b>140</b> may have a tapered shape of which a direction is opposite to the tapered shapes of each of the first and second wiring vias <b>113</b><i>a </i>and <b>113</b><i>b </i>of the frame <b>110</b>. That is, each of the vias <b>143</b> of the connection structure <b>140</b> may have a tapered shape of which a width of an upper surface is smaller than that of a lower surface, in relation to a cross section.

0095The first and second passivation layers <b>150</b>A and <b>150</b>B may protect the connection structure <b>140</b> and the wiring pattern <b>132</b> from external physical or chemical damage. The first and second passivation layers <b>150</b>A and <b>150</b>B may include the insulating material described above. In some exemplary embodiments, the first and second passivation layers <b>150</b>A and <b>150</b>B may include prepreg, ABF, FR-4, BT, a solder resist, or a PID. The first and second passivation layers <b>150</b>A and <b>150</b>B may have openings H opening partial regions of the redistribution layer <b>142</b> and the wiring pattern <b>132</b>.

0096A surface treatment layer <b>132</b>P may be formed in the opened regions of the wiring pattern <b>132</b> by plating such as noble metal plating. The surface treatment layer <b>132</b>P may be formed by, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/substituted gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like, but is not limited thereto.

0097The underbump metals <b>160</b> may be formed in openings of the outermost insulating layer <b>141</b> or the passivation layer <b>150</b>A by a metallization method using a conductive material such as a metal, but are not limited thereto. The number, an interval, a disposition form, and the like, of electrical connection metals <b>170</b> are not particularly limited, but may be sufficiently modified depending on design particulars. For example, the electrical connection metals <b>170</b> may be provided in an amount of several tens to several thousands according to the number of connection pads <b>122</b>, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less.

0098The electrical connection metals <b>170</b> may serve to physically and/or electrically connect the semiconductor package <b>100</b> to an external apparatus such as a mainboard of an electronic device. The electrical connection metal <b>170</b> may include a low melting point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu), or the like. The electrical connection metal <b>170</b> may be a single layer or multiple layers. For example, the multiple layers may include a copper pillar and a solder, and the single layer may include a tin-silver solder or copper.

0099A case in which the electrical connection metal <b>170</b> has a ball shape is exemplified, but the electrical connection metal <b>170</b> may have another structure or shape having a predetermined height, such as a land or a pin. Therefore, a predetermined mounting space may be secured on a lower surface of the insulating layer <b>141</b> by a height of the electrical connection metal <b>170</b>.

0100At least one of the electrical connection metals <b>170</b> may be disposed in a fan-out region. The fan-out region refers to a region except for (or outside of) a region overlapping the semiconductor chip <b>120</b> (e.g., a region outside of an area of overlap with the semiconductor chip <b>120</b> along a stacking direction of the semiconductor chip <b>120</b> on the connection structure <b>140</b>). The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness.

0101Although not illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, a plurality of semiconductor chips <b>120</b> performing functions that are the same as or different from each other may be disposed in the cavity <b>110</b>H. In some exemplary embodiments, a separate passive component such as an inductor, a capacitor, or the like, may be disposed in the cavity <b>110</b>H. In addition, in some exemplary embodiment, a plurality of cavities <b>110</b>H may be formed, and semiconductor chips <b>120</b> and/or passive components may be disposed in the cavities <b>110</b>H, respectively. A metal layer may be formed on walls of the cavity <b>110</b>H, optionally, in order to dissipate heat and block electromagnetic waves.

0102The heat dissipation system used in the present exemplary embodiment may be variously modified. For example, regions and forms of the support pattern and/or the heat dissipation bonding materials may be variously modified.

0103<figref idref="DRAWINGS">FIG. 13</figref> is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

0104Referring to <figref idref="DRAWINGS">FIG. 13</figref>, it may be understood that a semiconductor package <b>100</b>A according to the present exemplary embodiment has a structure similar to that illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> except that a concave portion CP does not completely penetrate through an encapsulant <b>130</b> and a support pattern <b>132</b>S extends up to an inner surface of the concave portion CP. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package <b>100</b> illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> unless explicitly described otherwise.

0105The concave portion CP used in the present exemplary embodiment may be positioned in a region overlapping a semiconductor chip <b>120</b>, but may not completely penetrate through the encapsulant <b>130</b> unlike the previous exemplary embodiment. A bottom surface of the concave portion CP may be provided by the encapsulant <b>130</b> and may be spaced apart from an upper surface of the semiconductor chip <b>120</b> by the encapsulant <b>130</b>.

0106The support pattern <b>132</b>S used in the present exemplary embodiment may have a portion <b>132</b>S<b>1</b> positioned on an upper surface of the encapsulant <b>130</b> and a portion <b>132</b>S<b>2</b> extending from the portion <b>132</b>S<b>1</b> to the inner surface of the concave portion CP. As described above, the support pattern <b>132</b>S may be formed over a relatively wide area. Therefore, a heat dissipation bonding material <b>182</b> and the support pattern <b>132</b>S may have a relatively wide connection area therebetween, and the heat dissipation bonding material <b>182</b> may thus be more stably coupled to the encapsulant <b>130</b> by the support pattern <b>132</b>S.

0107In the present exemplary embodiment, even though the heat dissipation bonding material <b>182</b> is not directly connected or contacted to the semiconductor chip <b>120</b> due to the presence of encapsulant <b>130</b> (and, optionally, of the support pattern portion <b>132</b>S<b>2</b>), an encapsulant portion (denoted by a dotted line) provided along the bottom surface of the concave portion CP may have a small thickness, and the heat dissipation bonding material <b>182</b> may thus effectively receive heat generated from the semiconductor chip <b>120</b>.

0108In addition, the support pattern <b>132</b>S may be formed of a metal (for example, Cu) having heat dissipation characteristics more excellent than (e.g., exceeding) those of the heat dissipation bonding material <b>182</b>, and may be provided over a wide area to be thus used as an adhesion improving unit or an effective heat dissipation unit.

0109<figref idref="DRAWINGS">FIG. 14</figref> is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

0110Referring to <figref idref="DRAWINGS">FIG. 14</figref>, it may be understood that a semiconductor package <b>100</b>B according to the present exemplary embodiment has a structure similar to that illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> except that a plurality of through-holes THs are formed in an encapsulant <b>130</b>. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package <b>100</b> illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> unless explicitly described otherwise.

0111A semiconductor package <b>100</b>B according to the present exemplary embodiment may have a plurality of concave portions, that is, a plurality of through-holes THs, instead of one concave portion CP, unlike the previous exemplary embodiment. The plurality of through-holes THs may be arranged in a region of the encapsulant <b>130</b> overlapping a semiconductor chip <b>120</b>. It may be understood that a plurality of through-holes THs are arranged in each of row and column directions when viewed in a plane.

0112The plurality of through-holes THs used in the present exemplary embodiment may be formed to be connected to or to extend to an inactive surface of the semiconductor chip <b>120</b> (e.g., a surface opposite to the active surface of the semiconductor chip <b>120</b>), and a heat dissipation bonding material <b>182</b> may have a portion <b>182</b><i>a </i>covering a support pattern <b>132</b>S disposed on an upper surface of the encapsulant <b>130</b> and a portion <b>182</b><i>b </i>connected to or contacting the inactive surface of the semiconductor chip <b>120</b> through the plurality of through-holes THs.

0113In the present exemplary embodiment, the heat dissipation bonding material <b>182</b> may be stably bonded to the encapsulant <b>130</b> by the support pattern <b>132</b>S, as in the exemplary embodiment illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, and additionally, may have a wide bonding area with the encapsulant <b>130</b> by the plurality of through-holes

0114THs and may thus be more stably bonded to the encapsulant <b>130</b>. Resultantly, a heat dissipation element <b>185</b> may be more firmly bonded to the semiconductor package <b>100</b>B by the heat dissipation bonding materials <b>182</b>.

0115<figref idref="DRAWINGS">FIG. 15</figref> is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

0116Referring to <figref idref="DRAWINGS">FIG. 15</figref>, it may be understood that a semiconductor package <b>100</b>C according to the present exemplary embodiment has a structure similar to that illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> except that an encapsulant <b>130</b> has a plurality of through-holes THs instead of a single concave portion, but the plurality of through-holes THs do not completely penetrate through the encapsulant <b>130</b>, and that a support pattern <b>132</b>S extends up to inner surfaces of the respective through-holes THs. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package <b>100</b> illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> unless explicitly described otherwise.

0117The plurality of through-holes THs used in the present exemplary embodiment may be disposed in a region overlapping a semiconductor chip <b>120</b>, similar to the through-holes illustrated in <figref idref="DRAWINGS">FIG. 14</figref>, but do not completely penetrate through the encapsulant <b>130</b> unlike the through-holes illustrated in <figref idref="DRAWINGS">FIG. 14</figref>. The support pattern <b>132</b>S may have a portion <b>132</b>S<b>1</b> positioned on an upper surface of the encapsulant <b>130</b> and a portion <b>132</b>S<b>2</b> extending from the portion <b>132</b>S<b>1</b> to the inner surfaces of the respective through-holes THs.

0118As described above, a heat dissipation bonding material <b>182</b> and the support pattern <b>132</b>S may have a relatively wide connection area therebetween, and the heat dissipation bonding material <b>182</b> may thus be more stably coupled to the encapsulant <b>130</b> by the support pattern <b>132</b>S.

0119In addition, as in the exemplary embodiment illustrated in <figref idref="DRAWINGS">FIG. 13</figref>, even though the heat dissipation bonding material <b>182</b> is not directly connected to or contacting the semiconductor chip <b>120</b> due to presence of the encapsulant <b>130</b>, an encapsulant portion (denoted by a dotted line) provided to a bottom surface of the through-holes THs may have a small thickness, and the support pattern <b>132</b>S is formed of a metal (for example, Cu) having heat dissipation characteristics more excellent than those of the heat dissipation bonding material <b>182</b>, and the heat dissipation bonding material <b>182</b> may thus effectively dissipate heat generated from the semiconductor chip <b>120</b>.

0120<figref idref="DRAWINGS">FIGS. 16 and 17</figref> are schematic cross-sectional views illustrating semiconductor packages according to various exemplary embodiments in the present disclosure.

0121Referring to <figref idref="DRAWINGS">FIG. 16</figref>, it may be understood that a semiconductor package <b>100</b>D according to the present exemplary embodiment has a structure similar to that illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> except for a form of a wiring structure of a frame <b>110</b>. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package <b>100</b> illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> unless explicitly described otherwise.

0122A frame <b>110</b> used in the present exemplary embodiment may have a structure different from that of the frame <b>110</b> described above, and a wiring structure of the frame <b>110</b> may thus be modified. In detail, the frame <b>110</b> may include a first insulating layer <b>111</b><i>a, </i>a first wiring layer <b>112</b><i>a </i>disposed on one surface of the first insulating layer <b>111</b><i>a, </i>a second wiring layer <b>112</b><i>b </i>disposed on another surface of the first insulating layer <b>111</b><i>a, </i>a second insulating layer <b>111</b><i>b </i>disposed on the one surface of the first insulating layer <b>111</b><i>a </i>and covering at least portions of the first wiring layer <b>112</b><i>a, </i>a third wiring layer <b>112</b><i>c </i>disposed on the other surface of the second insulating layer <b>111</b><i>b </i>opposing one surface of the second insulating layer <b>111</b><i>b </i>in which the first wiring layer <b>112</b><i>a </i>is embedded, a third insulating layer <b>111</b><i>c </i>disposed on the other surface of the first insulating layer <b>111</b><i>a </i>and covering at least portions of the second wiring layer <b>112</b><i>b, </i>and a fourth wiring layer <b>112</b><i>d </i>disposed on the other surface of the third insulating layer <b>111</b><i>c </i>opposing one surface of the third insulating layer <b>111</b><i>c </i>in which the second wiring layer <b>112</b><i>b </i>is embedded. First wiring vias <b>113</b><i>a </i>penetrate through the first insulating layer <b>111</b><i>a </i>and electrically connect the first and second wiring layers <b>112</b><i>a </i>and <b>112</b><i>b </i>to each other, second wiring vias <b>113</b><i>b </i>penetrate through the second insulating layer <b>111</b><i>b </i>and electrically connect the first and third wiring layers <b>112</b><i>a </i>and <b>112</b><i>c </i>to each other, and third wiring vias <b>113</b><i>c </i>penetrate through the third insulating layer <b>111</b><i>c </i>and electrically connect the second and fourth wiring layers <b>112</b><i>b </i>and <b>112</b><i>d </i>to each other. Since the frame <b>110</b> used in the present exemplary embodiment has a larger number of wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i><b>112</b><i>c, </i>and <b>112</b><i>d, </i>redistribution layers <b>142</b> of a connection structure <b>140</b> may further be simplified.

0123The first insulating layer <b>111</b><i>a </i>may have a thickness greater than those of the second insulating layer <b>111</b><i>b </i>and the third insulating layer <b>111</b><i>c. </i>The first insulating layer <b>111</b><i>a </i>may be basically relatively thick in order to maintain rigidity, and the second insulating layer <b>111</b><i>b </i>and the third insulating layer <b>111</b><i>c </i>may be introduced in order to form a larger number of wiring layers <b>112</b><i>c </i>and <b>112</b><i>d. </i>The first insulating layer <b>111</b><i>a </i>may include an insulating material different from those of the second insulating layer <b>111</b><i>b </i>and the third insulating layer <b>111</b><i>c. </i>For example, the first insulating layer <b>111</b><i>a </i>may be, for example, prepreg including a core material such as a glass fiber, an inorganic filler, and an insulating resin, and the second insulating layer <b>111</b><i>b </i>and the third insulating layer <b>111</b><i>c </i>may be an ABF or a PID including an inorganic filler and an insulating resin. However, the materials of the first insulating layer <b>111</b><i>a </i>and the second and third insulating layers <b>111</b><i>b </i>and <b>111</b><i>c </i>are not limited thereto. Similarly, the first wiring vias <b>113</b><i>a </i>penetrating through the first insulating layer <b>111</b><i>a </i>may have a diameter greater than those of the second and third wiring vias <b>113</b><i>b </i>and <b>113</b><i>c </i>each penetrating through the second and third insulating layers <b>111</b><i>b </i>and <b>111</b><i>c. </i>In addition, the first wiring via <b>113</b><i>a </i>may have an hourglass shape or a cylindrical shape, while the second and third wiring vias <b>113</b><i>b </i>and <b>113</b><i>c </i>may have tapered shapes of which directions are opposite to each other. Thicknesses of the first to fourth wiring layers <b>112</b><i>a, </i><b>112</b><i>b, </i><b>112</b><i>c, </i>and <b>112</b><i>d </i>may be greater than those of the redistribution layers <b>142</b> of the connection structure <b>140</b>.

0124Referring to <figref idref="DRAWINGS">FIG. 17</figref>, it may be understood that a semiconductor package <b>100</b>E according to the present exemplary embodiment has a structure similar to that illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> except that it does not include components (a wiring structure, a wiring pattern, and the like) associated with a frame.

0125Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package <b>100</b> illustrated in <figref idref="DRAWINGS">FIGS. 9 through 11</figref> unless explicitly described otherwise.

0126The semiconductor package <b>100</b>E according to the present exemplary embodiment does not use the frame, and an encapsulant <b>130</b> may be disposed on a first surface <b>140</b>A of a connection structure <b>140</b> to encapsulate a semiconductor chip <b>120</b>. In some exemplary embodiments, the semiconductor package <b>100</b>E may be configured to include electrical paths (for example, metal posts, or the like) connected to redistribution layers of the connection structure <b>140</b> and penetrating through the encapsulant in a vertical direction.

0127A heat dissipation system used in the present exemplary embodiment may include a heat dissipation bonding material <b>182</b> partially embedded in the encapsulant <b>130</b> and a heat dissipation element <b>185</b> bonded to the encapsulant <b>130</b> using the heat dissipation bonding material <b>182</b>, similar to the exemplary embodiment illustrated in <figref idref="DRAWINGS">FIG. 9</figref>. In addition, a support pattern <b>132</b>S disposed on a partial region of an upper surface of the encapsulant <b>130</b> may further be included.

0128The heat dissipation bonding material <b>182</b> may include a portion <b>182</b><i>b </i>embedded in a region of the encapsulant <b>130</b> overlapping the semiconductor chip <b>120</b> and a portion <b>182</b><i>a </i>extending from the embedded portion <b>182</b> and disposed on the upper surface of the encapsulant <b>130</b>. The heat dissipation element <b>185</b> may be disposed on the upper surface of the encapsulant <b>130</b> so as to cover the heat dissipation bonding material <b>182</b>.

0129In this arrangement, the heat dissipation bonding material <b>182</b> used in the present exemplary embodiment may be used as a unit bonding the heat dissipation element <b>185</b> and the encapsulant <b>130</b> to each other as well as to provide a heat dissipation path between the heat dissipation element <b>185</b> and the semiconductor chip <b>120</b>. In addition, the support pattern <b>132</b>S may be used as a unit enhancing bonding strength between the heat dissipation bonding material <b>182</b> and the encapsulant <b>130</b>.

0130As set forth above, according to an exemplary embodiment in the present disclosure, a semiconductor package may be provided in which heat dissipation characteristics are excellent and a heat dissipation element may be firmly maintained to improve reliability.

0131While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.