Method of manufacturing a semiconductor device and a semiconductor device
Claim Score by NHIP
Abstract
In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.
Term
10.8 yearsto projected expiry
Projected expiry 18 July 2037, counted from filing; an application has no term until it is granted.
- Priority
- Filed
- Published
- Today
- Projected expiry
20 claims: 3 independent, 17 dependent
- 1A semiconductor device comprising:a first structure disposed over a semiconductor substrate;a second structure disposed over the semiconductor substrate;and an isolation insulating layer disposed between the first structure and the second structure, wherein the first structure comprises: a stacked plurality of semiconductor wires;a first source/drain epitaxial layer in contact with ends of the semiconductor wires;a first gate dielectric layer disposed on and wrapping around a channel region of each of the semiconductor wires;a first gate electrode layer disposed on the first gate dielectric layer and wrapping around the channel region of each of the semiconductor wires;and insulating spacers disposed between adjacent semiconductor wires, the first gate electrode layer, and the first source/drain epitaxial layer, and the second structure comprises: a fin structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked;a second source/drain epitaxial layer disposed over a source/drain region of the fin structure;a second gate dielectric layer disposed over a channel region of the fin structure;and a second gate electrode layer disposed on the second gate dielectric layer.
- 12Broadest claimClaim Score 41, average(NHIP)A semiconductor device, comprising:a first field effect transistor (FET) and a second FET, wherein the first FET comprises: a plurality of silicon semiconductor wires stacked over a substrate;a first source/drain epitaxial layer in contact with ends of the silicon semiconductor wires;a first gate dielectric layer disposed on and wrapping around a channel region of each of the semiconductor wires;a first gate electrode layer disposed on the first gate dielectric layer and wrapping around the channel region of each of the semiconductor wires;and insulating spacers comprising a spacer material in direct contact with the first source/drain epitaxial layer and the semiconductor wire, wherein a periphery of the insulating spacers form substantial right angles where the first source/drain epitaxial layers and the semiconductor wires meet, and the second FET comprises: a fin-like structure;and a second gate electrode layer disposed over a channel region of the fin-like structure.
- 18A semiconductor device, comprising:an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET), wherein the NFET comprises: a plurality of semiconductor wires stacked over a substrate;a first source/drain epitaxial layer in contact with ends of the silicon semiconductor wires: a first gate dielectric layer disposed on and wrapping around a channel region of each of the semiconductor wires;a first gate electrode layer disposed on the first gate dielectric layer and wrapping around the channel region of each of the semiconductor wires;a cover layer disposed over a sidewall of a portion of the first gate electrode layer above the channel region;and insulating spacers comprising a spacer material filling a space between the first source/drain epitaxial layer, the first gate dielectric layer, and the semiconductor wire, wherein the space has right angle boundaries where the first source/drain epitaxial layer and the semiconductor wires meet, wherein the spacer material is disposed over the cover layer, and wherein the PFET comprises: a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;and a second gate electrode layer disposed over a channel region of the fin structure.
Independent claims3
168 paragraphs in 5 sections, as filed
CROSS-REFERENCE TO RELATED APPLICATIONS
0001This application is a continuation of U.S. patent application Ser. No. 16/206,730, filed on Nov. 30, 2018, which is a divisional patent application of U.S. patent application Ser. No. 15/653,068, filed on Jul. 18, 2017, now U.S. Pat. No. 10,211,307, the entire disclosures of each of which are incorporated herein by reference.
TECHNICAL FIELD
0002The disclosure relates to method of manufacturing semiconductor integrated circuits, and more particularly to method of manufacturing semiconductor devices including fin field effect transistors (FinFETs) and/or gate-all-around FETs, and semiconductor devices.
BACKGROUND
0003As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a multi-gate field effect transistor (FET), including a fin FET (Fin FET) and a gate-all-around (GAA) FET. In a Fin FET, a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer interposed therebetween. Because the gate structure surrounds (wraps) the fin on three surfaces, the transistor essentially has three gates controlling the current through the fin or channel region. Unfortunately, the fourth side, the bottom part of the channel is far away from the gate electrode and thus is not under close gate control. In contrast, in a GAA FET, all side surfaces of the channel region are surrounded by the gate electrode, which allows for fuller depletion in the channel region and results in less short-channel effects due to steeper sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL). As transistor dimensions are continually scaled down to sub 10-15 nm technology nodes, further improvements of the GAA FET are required.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
<figref idref="DRAWINGS">FIGS. 1A-1D</figref> show various views of a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 1A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 1B</figref> is a cross sectional view corresponding to Y<b>1</b>-Y<b>1</b> of <figref idref="DRAWINGS">FIG. 1A</figref>, <figref idref="DRAWINGS">FIG. 1C</figref> is a cross sectional view corresponding to Y<b>2</b>-Y<b>2</b> of <figref idref="DRAWINGS">FIG. 1A</figref>, <figref idref="DRAWINGS">FIG. 1D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 1C</figref>.
<figref idref="DRAWINGS">FIG. 2</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 3</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 4</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 5</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 6</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 7</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 8</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 9</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIGS. 10A-10D</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 10A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 10B</figref> is a cross sectional view along the X direction, <figref idref="DRAWINGS">FIG. 10C</figref> is a cross sectional view along the Y direction, and <figref idref="DRAWINGS">FIG. 10D</figref> shows another perspective view.
<figref idref="DRAWINGS">FIGS. 11A-11D</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 11A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 11B</figref> is a cross sectional view along the X direction, <figref idref="DRAWINGS">FIG. 11C</figref> is a cross sectional view along the Y direction, and <figref idref="DRAWINGS">FIG. 11D</figref> shows another perspective view.
<figref idref="DRAWINGS">FIGS. 12A-12C</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 12A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 12B</figref> is a cross sectional view along the X direction, and <figref idref="DRAWINGS">FIG. 12C</figref> is a cross sectional view along the Y direction.
<figref idref="DRAWINGS">FIG. 13</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 14</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 15</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 16</figref> shows one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure.
<figref idref="DRAWINGS">FIGS. 17A-17D</figref> show various views of a semiconductor FET device according to other embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 17A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 17B</figref> is a cross sectional view corresponding to Y<b>1</b>-Y<b>1</b> of <figref idref="DRAWINGS">FIG. 17A</figref>, <figref idref="DRAWINGS">FIG. 17C</figref> is a cross sectional view corresponding to Y<b>2</b>-Y<b>2</b> of <figref idref="DRAWINGS">FIG. 17A</figref>, <figref idref="DRAWINGS">FIG. 17D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 17C</figref>.
<figref idref="DRAWINGS">FIG. 18</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 19</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 20</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 21</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 22</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 23</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 24</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 25</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIGS. 26A-26D</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 26A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 26B</figref> is a cross sectional view along the X direction, <figref idref="DRAWINGS">FIG. 26C</figref> is a cross sectional view along the Y direction, and <figref idref="DRAWINGS">FIG. 26D</figref> shows another perspective view.
<figref idref="DRAWINGS">FIGS. 27A-27D</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 27A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 27B</figref> is a cross sectional view along the X direction, <figref idref="DRAWINGS">FIG. 27C</figref> is a cross sectional view along the Y direction, and <figref idref="DRAWINGS">FIG. 27D</figref> shows another perspective view.
<figref idref="DRAWINGS">FIGS. 28A-28C</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 28A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 28B</figref> is a cross sectional view along the X direction, and <figref idref="DRAWINGS">FIG. 28C</figref> is a cross sectional view along the Y direction.
<figref idref="DRAWINGS">FIG. 29</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 30</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 31</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 32</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIGS. 33A-33D</figref> show various views of a semiconductor FET device according to other embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 33A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 33B</figref> is a cross sectional view corresponding to Y<b>1</b>-Y<b>1</b> of <figref idref="DRAWINGS">FIG. 33A</figref>, <figref idref="DRAWINGS">FIG. 33C</figref> is a cross sectional view corresponding to Y<b>2</b>-Y<b>2</b> of <figref idref="DRAWINGS">FIG. 33A</figref>, <figref idref="DRAWINGS">FIG. 33D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 33C</figref>.
<figref idref="DRAWINGS">FIGS. 34A-34D</figref> show various views of a semiconductor FET device according to other embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 34A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 34B</figref> is a cross sectional view corresponding to Y<b>1</b>-Y<b>1</b> of <figref idref="DRAWINGS">FIG. 34A</figref>, <figref idref="DRAWINGS">FIG. 34C</figref> is a cross sectional view corresponding to Y<b>2</b>-Y<b>2</b> of <figref idref="DRAWINGS">FIG. 34A</figref>, and <figref idref="DRAWINGS">FIG. 34D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 34C</figref>.
<figref idref="DRAWINGS">FIG. 35</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIG. 36</figref> shows one of the various stages of manufacturing a semiconductor FET device according to other embodiments of the present disclosure.
<figref idref="DRAWINGS">FIGS. 37A-37C</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 37A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 37B</figref> is a cross sectional view along the X direction, and <figref idref="DRAWINGS">FIG. 37C</figref> is a cross sectional view along the Y direction.
<figref idref="DRAWINGS">FIGS. 38A-38C</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 38A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 38B</figref> is a cross sectional view along the X direction, and <figref idref="DRAWINGS">FIG. 38C</figref> is a cross sectional view along the Y direction.
<figref idref="DRAWINGS">FIGS. 39A-39C</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 39A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 39B</figref> is a cross sectional view along the X direction, and <figref idref="DRAWINGS">FIG. 39C</figref> is a cross sectional view along the Y direction.
<figref idref="DRAWINGS">FIGS. 40A-40C</figref> show one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 40A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 40B</figref> is a cross sectional view along the X direction, and <figref idref="DRAWINGS">FIG. 40C</figref> is a cross sectional view along the Y direction.
DETAILED DESCRIPTION
0045It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.
0046Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “being made of” may mean either “comprising” or “consisting of.”
0047In the present disclosure, a method for fabricating an inner spacer between a metal gate electrode and a source/drain epitaxial layer for a GAA FET and a stacked channel FET are provided. In this disclosure, a source/drain refers to a source and/or a drain. The inner spacer can be formed by the following process. After a dummy gate structure is formed over a stacked fin structure, in which two different semiconductor wires are alternately stacked, a source/drain region of the stacked fin structure is recessed. Then, an insulating (dielectric) layer is formed in the recess and then the formed insulating layer is etched to form inner spacers on ends of the semiconductor wires. Subsequently a source/drain epitaxial layer is formed over the inner spacers. It is noted that in the present disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same.
0048In the foregoing process, however, it is difficult to precisely control the etching of the insulating layer and thus it is difficult to precisely control the thickness and the location of the inner spacers. In view of this, the present disclosure provides a method for fabricating inner spacers between a metal gate electrode and a source/drain epitaxial layer, which can control the thickness, the shape and/or the location of the inner spacer more precisely.
0049<figref idref="DRAWINGS">FIGS. 1A-1D</figref> show various views of a semiconductor FET device according to embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 1A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 1B</figref> is a cross sectional view corresponding to Y<b>1</b>-Y<b>1</b> of <figref idref="DRAWINGS">FIG. 1A</figref>, <figref idref="DRAWINGS">FIG. 1C</figref> is a cross sectional view corresponding to Y<b>2</b>-Y<b>2</b> of <figref idref="DRAWINGS">FIG. 1A</figref>, <figref idref="DRAWINGS">FIG. 1D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 1C</figref>.
0050As shown in <figref idref="DRAWINGS">FIGS. 1A-1D</figref>, two semiconductor fin structures <b>11</b> are provided over a semiconductor substrate <b>10</b>. In some embodiments, the substrate <b>10</b> includes a single crystalline semiconductor layer on at least it surface portion. The substrate <b>10</b> may comprise a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In certain embodiments, the substrate <b>10</b> is made of crystalline Si.
0051The substrate <b>10</b> may include in its surface region, one or more buffer layers (not shown). The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate <b>10</b> comprises silicon germanium (SiGe) buffer layers epitaxially grown on the silicon substrate <b>10</b>. The germanium concentration of the SiGe buffer layers may increase from 30 atomic % germanium for the bottom-most buffer layer to 70 atomic % germanium for the top-most buffer layer.
0052The bottom part of the fin structures <b>11</b> are covered by an insulating layer <b>35</b> (a fin liner layer). The fin liner layer <b>35</b> includes one or more layers of insulating material.
0053An isolation insulating layer <b>40</b>, such as shallow trench isolations (STI), is disposed in the trenches over the substrate <b>10</b>. The isolation insulating layer <b>40</b> may be made of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. In some embodiments, the isolation insulating layer <b>40</b> is formed through a process such as CVD, flowable CVD (FCVD), or a spin-on-glass process, although any acceptable process may be utilized.
0054As shown in <figref idref="DRAWINGS">FIG. 1B</figref>, channel layers <b>25</b>, which are semiconductor wires, are disposed over the fin structure <b>11</b>. Each of the channel layers <b>25</b> is wrapped around by a gate dielectric layer <b>102</b> and a gate electrode layer <b>104</b>. In some embodiments, the gate dielectric layer <b>102</b> includes an interfacial layer <b>102</b>A and a high-k dielectric layer <b>102</b>B. Further, a gate cap insulating layer <b>106</b> is disposed over the gate electrode layer <b>104</b>.
0055As shown in <figref idref="DRAWINGS">FIGS. 1A, 1C and 1D</figref>, a source/drain epitaxial layer <b>80</b> is disposed over a source/drain region of the fin structure <b>11</b>. The source/drain epitaxial layer <b>80</b> is covered by an interlayer dielectric (ILD) layer <b>95</b>. In addition, a first cover layer <b>51</b> and/or an insulating layer <b>85</b> are formed between the source/drain epitaxial layer <b>80</b> and the ILD layer <b>95</b> and between the gate electrode <b>104</b> and the ILD layer <b>95</b>. Further, a source/drain contact <b>130</b> is disposed in contact with the source/drain epitaxial layer <b>80</b>. In some embodiment, the source/drain epitaxial layer <b>80</b> has a hexagonal shape, a diamond shape, other polygonal shapes or a semi-circular shape in the cross section.
0056<figref idref="DRAWINGS">FIG. 1C</figref> is a cross sectional view in the Y direction cutting the vertical portion of the insulating layer <b>85</b> at an area between the gate electrode <b>104</b> and the source/drain epitaxial layer <b>80</b>. In this area, the semiconductor wires <b>25</b> are at least partially covered by the insulating layer <b>85</b>. In some embodiments, one or more voids <b>70</b> are formed in the insulating layer <b>85</b> between the semiconductor wires <b>25</b>. The cross sectional shape of the voids <b>70</b> includes a circular shape, an oval shape (vertically and/or horizontally), a teardrop shape or a rectangular or a polygonal shape with rounded corners. In other embodiments, no void is formed.
0057<figref idref="DRAWINGS">FIG. 1D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 1C</figref>. As shown in <figref idref="DRAWINGS">FIG. 1D</figref>, the insulating layer <b>85</b> is disposed between end faces of the gate electrode layer <b>104</b> and the source/drain epitaxial layer <b>80</b>, as inner spacers. In some embodiments, the gate dielectric layer <b>102</b> is disposed between the insulating layer <b>85</b> and the gate electrode layer <b>104</b>. As shown in <figref idref="DRAWINGS">FIG. 1D</figref>, end faces of the inner spacers <b>85</b> in contact with the source/drain epitaxial layer <b>80</b> are vertically aligned (disposed on the same vertical plane). Further, the end faces of the inner spacers <b>85</b> in contact with the source/drain epitaxial layer <b>80</b> and interfaces between the end faces of the semiconductor wires and the source/drain epitaxial layer <b>80</b> are also vertically aligned. The interface between the gate electrode <b>104</b> and the inner spacers <b>85</b> has a curved surface protruding toward the gate electrode <b>104</b>, while the interface between the inner spacers <b>85</b> and the source/drain epitaxial layer <b>80</b> is substantially flat. In some embodiments, the inner spacers <b>85</b> are made of a low-k dielectric material, such as SiOC and/or SiOCN or any other suitable dielectric material. The low-k dielectric material has a dielectric constant smaller than silicon dioxide.
0058The thickness and widths of each of the semiconductor wires <b>25</b> is in a range from about 5 nm to about 15 nm in some embodiments, and is in a range from about 6 nm to about 12 nm in other embodiments. The space between adjacent semiconductor wires in the Z direction is in a range from about 2 nm to about 6 nm in some embodiments. The thickness W<b>1</b> of the inner spacer <b>85</b> is in a range from about 2 nm to about 6 nm in some embodiments. The cross sectional shape of the semiconductor wires <b>25</b> in the channel region can be any polygonal shape (square, rectangular, triangular, etc.), polygonal shape with rounded corners, circular, or oval (vertically or horizontally).
0059In <figref idref="DRAWINGS">FIGS. 1A-1D</figref>, two fin structures <b>11</b> and four semiconductor wires <b>25</b> are illustrated. However, the numbers are not limited thereto. The number of the fin structures can be one, three, four or more per gate, and the number of the semiconductor wires <b>25</b> can be one, two, three and more, up to ten.
0060In certain embodiments, the semiconductor device of <figref idref="DRAWINGS">FIGS. 1A-1D</figref> is an n-type GAA FET. In other embodiments, the semiconductor device of <figref idref="DRAWINGS">FIGS. 1A-1D</figref> is a p-type GAA FET. In some embodiments, one or more n-type GAA FETs and one or more p-type GAA FETs are provided on the same substrate <b>10</b>.
0061<figref idref="DRAWINGS">FIGS. 2-16</figref> show exemplary sequential processes for manufacturing the GAA FET shown in <figref idref="DRAWINGS">FIGS. 1A-1D</figref> according to one embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown by <figref idref="DRAWINGS">FIGS. 2-16</figref>, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.
0062As shown in <figref idref="DRAWINGS">FIG. 2</figref>, impurity ions (dopants) <b>12</b> are implanted into a silicon substrate <b>10</b> to form a well region. The ion implantation is performed to prevent a punch-through effect. The substrate <b>10</b> may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants <b>12</b> are, for example boron (BF<sub>2</sub>) for an n-type Fin FET and phosphorus for a p-type Fin FET.
0063Then, as shown in <figref idref="DRAWINGS">FIG. 3</figref>, stacked semiconductor layers are formed over the substrate <b>10</b>. The stacked semiconductor layers include first semiconductor layers <b>20</b> and second semiconductor layers <b>25</b>. Further, a mask layer <b>15</b> is formed over the stacked layers.
0064The first semiconductor layers <b>20</b> and the second semiconductor layers <b>25</b> are made of materials having different lattice constants, and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP.
0065In some embodiments, the first semiconductor layers <b>20</b> and the second semiconductor layers <b>25</b> are made of Si, a Si compound, SiGe, Ge or a Ge compound. In one embodiment, the first semiconductor layers <b>20</b> are Si<sub>1-x</sub>Ge<sub>x</sub>, where x is more than about 0.3, or Ge (x=1.0) and the second semiconductor layers <b>25</b> are Si or Si<sub>1-y</sub>Ge<sub>y</sub>, where y is less than about 0.4, and x>y. In this disclosure, an “M” compound” or an “M based compound” means the majority of the compound is M.
0066In another embodiment, the second semiconductor layers <b>25</b> are Si<sub>1-y</sub>Ge<sub>y</sub>, where y is more than about 0.3, or Ge, and the first semiconductor layers <b>20</b> are Si or Si<sub>1-x</sub>Ge<sub>x</sub>, where x is less than about 0.4, and x<y. In yet other embodiments, the first semiconductor layer <b>20</b> is made of Si<sub>1-x</sub>Ge<sub>x</sub>, where x is in a range from about 0.3 to about 0.8, and the second semiconductor layer <b>25</b> is made of Si<sub>1-y</sub>Ge<sub>y</sub>, where y is in a range from about 0.1 to about 0.4.
0067In <figref idref="DRAWINGS">FIG. 3</figref>, four layers of the first semiconductor layer <b>20</b> and four layers of the second semiconductor layer <b>25</b> are disposed. However, the number of the layers are not limited to four, and may be as small as 1 (each layer) and in some embodiments, 2-10 layers of each of the first and second semiconductor layers are formed. By adjusting the numbers of the stacked layers, a driving current of the GAA FET device can be adjusted.
0068The first semiconductor layers <b>20</b> and the second semiconductor layers <b>25</b> are epitaxially formed over the substrate <b>10</b>. The thickness of the first semiconductor layers <b>20</b> may be equal to or greater than that of the second semiconductor layers <b>25</b>, and is in a range from about 2 nm to about 20 nm in some embodiments, and is in a range from about 5 nm to about 15 nm in other embodiments. The thickness of the second semiconductor layers <b>25</b> is in a range from about 2 nm to about 20 nm in some embodiments, and is in a range from about 5 nm to about 15 nm in other embodiments. The thickness of each of the first semiconductor layers <b>20</b> may be the same, or may vary.
0069In some embodiments, the bottom first semiconductor layer (the closest layer to the substrate <b>10</b>) is thicker than the remaining first semiconductor layers. The thickness of the bottom first semiconductor layer is in a range from about 10 nm to about 50 nm in some embodiments, or is in a range from 20 nm to 40 nm in other embodiments.
0070In some embodiments, the mask layer <b>15</b> includes a first mask layer <b>15</b>A and a second mask layer <b>15</b>B. The first mask layer <b>15</b>A is a pad oxide layer made of a silicon oxide, which can be formed by a thermal oxidation. The second mask layer <b>15</b>B is made of a silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. The mask layer <b>15</b> is patterned into a mask pattern by using patterning operations including photo-lithography and etching.
0071Next, as shown in <figref idref="DRAWINGS">FIG. 4</figref>, the stacked layers of the first and second semiconductor layers <b>20</b>, <b>25</b> are patterned by using the patterned mask layer, thereby the stacked layers are formed into fin structures <b>30</b> extending in the X direction. In <figref idref="DRAWINGS">FIG. 4</figref>, two fin structures <b>30</b> are arranged in the Y direction. But the number of the fin structures is not limited to two, and may be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures <b>30</b> to improve pattern fidelity in the patterning operations. As shown in <figref idref="DRAWINGS">FIG. 4</figref>, the fin structures <b>30</b> have upper portions constituted by the stacked semiconductor layers <b>20</b>, <b>25</b> and well portions <b>11</b>.
0072The width W<b>1</b> of the upper portion of the fin structure along the Y direction is in a range from about 10 nm to about 40 nm in some embodiments, and is in a range from about 20 nm to about 30 nm in other embodiments. The height H<b>1</b> along the Z direction of the fin structure is in a range from about 100 nm to about 200 nm.
0073The stacked fin structure <b>30</b> may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the stacked fin structure <b>30</b>.
0074After the fin structures <b>30</b> are formed, an insulating material layer including one or more layers of insulating material is formed over the substrate so that the fin structures are fully embedded in the insulating layer. The insulating material for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. An anneal operation may be performed after the formation of the insulating layer. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, is performed such that the upper surface of the uppermost second semiconductor layer <b>25</b> is exposed from the insulating material layer. In some embodiments, a fin liner layer <b>35</b> is formed over the fin structures before forming the insulating material layer. The fin liner layer <b>35</b> is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN or SiOCN).
0075In some embodiments, the fin liner layers <b>35</b> include a first fin liner layer formed over the substrate <b>10</b> and sidewalls of the bottom part of the fin structures <b>11</b>, and a second fin liner layer formed on the first fin liner layer. Each of the liner layers has a thickness between about 1 nm and about 20 nm in some embodiments. In some embodiments, the first fin liner layer includes silicon oxide and has a thickness between about 0.5 nm and about 5 nm, and the second fin liner layer includes silicon nitride and has a thickness between about 0.5 nm and about 5 nm. The liner layers may be deposited through one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process may be utilized.
0076Then, as shown in <figref idref="DRAWINGS">FIG. 5</figref>, the insulating material layer is recessed to form an isolation insulating layer <b>40</b> so that the upper portions of the fin structures <b>30</b> are exposed. With this operation, the fin structures <b>30</b> are electrically separated from each other by the isolation insulating layer <b>40</b>, which is also called a shallow trench isolation (STI).
0077In the embodiment shown in <figref idref="DRAWINGS">FIG. 5</figref>, the insulating material layer <b>40</b> is recessed until the upper portion of the fin structure (well layer) <b>11</b> is exposed. In other embodiments, the upper portion of the fin structure <b>11</b> is not exposed. The first semiconductor layers <b>20</b> are sacrificial layers which are subsequently partially removed, and the second semiconductor layers <b>25</b> are subsequently formed into semiconductor wires as channel layers of a GAA FET.
0078After the isolation insulating layer <b>40</b> is formed, a sacrificial (dummy) gate structure <b>50</b> is formed, as shown in <figref idref="DRAWINGS">FIG. 6</figref>. <figref idref="DRAWINGS">FIG. 6</figref> illustrates a structure after a sacrificial gate structure <b>50</b> is formed over the exposed fin structures <b>30</b>. The sacrificial gate structure <b>50</b> is formed over a portion of the fin structures which is to be a channel region. The sacrificial gate structure defines the channel region of the GAA FET. The sacrificial gate structure <b>50</b> includes a sacrificial gate dielectric layer <b>52</b> and a sacrificial gate electrode layer <b>54</b>. The sacrificial gate dielectric layer <b>52</b> includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. The thickness of the sacrificial gate dielectric layer <b>52</b> is in a range from about 1 nm to about 5 nm in some embodiments.
0079The sacrificial gate structure <b>50</b> is formed by first blanket depositing the sacrificial gate dielectric layer <b>52</b> over the fin structures. A sacrificial gate electrode layer is then blanket deposited on the sacrificial gate dielectric layer and over the fin structures, such that the fin structures are fully embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range from about 100 nm to about 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process. Subsequently, a mask layer is formed over the sacrificial gate electrode layer. The mask layer includes a pad SiN layer <b>56</b> and a silicon oxide mask layer <b>58</b>.
0080Next, a patterning operation is performed on the mask layer and sacrificial gate electrode layer is patterned into the sacrificial gate structure <b>50</b>, as shown in <figref idref="DRAWINGS">FIG. 6</figref>. The sacrificial gate structure includes the sacrificial gate dielectric layer <b>52</b>, the sacrificial gate electrode layer <b>54</b> (e.g., poly silicon), the pad SiN layer <b>56</b> and the silicon oxide mask layer <b>58</b>. By patterning the sacrificial gate structure, the stacked layers of the first and second semiconductor layers are partially exposed on opposite sides of the sacrificial gate structure, thereby defining source/drain (S/D) regions, as shown in <figref idref="DRAWINGS">FIG. 6</figref>. In this disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same. In <figref idref="DRAWINGS">FIG. 6</figref>, one sacrificial gate structure is formed, but the number of the sacrificial gate structures is not limited to one. Two or more sacrificial gate structures are arranged in the X direction in some embodiments. In certain embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structures to improve pattern fidelity.
0081After the sacrificial gate structure is formed, a first cover layer <b>51</b> made of an insulating material is conformally formed over the exposed fin structures and the sacrificial gate structure <b>50</b>. Further, a second cover layer <b>53</b> is formed over the first cover layer <b>51</b>, as shown in <figref idref="DRAWINGS">FIG. 7</figref>. The first and second cover layers are deposited in a conformal manner so that they are formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the sacrificial gate structure, respectively. In some embodiments, the first cover layer <b>51</b> has a thickness in a range from about 2 nm to about 10 nm, and the second cover layer <b>53</b> has a thickness greater than the first cover layer and has the thickness in a range from about 5 nm to about 20 nm.
0082In one embodiment, the first cover layer <b>51</b> includes a low-k dielectric material, such as SiOC and/or SiOCN or any other suitable dielectric material. The second cover layer <b>53</b> includes one or more of SiN, SiON and SiCN or any other suitable dielectric material. The first cover layer and the second cover layer are made of different materials so that one of them can be selectively etched. The first cover layer <b>51</b> and the second cover layer <b>53</b> can be formed by ALD or CVD, or any other suitable method.
0083Then, as shown in <figref idref="DRAWINGS">FIG. 8</figref>, the fin structures of the source/drain regions are recessed down to about the upper surface of the isolation insulating layer <b>40</b>.
0084Subsequently, a source/drain epitaxial layer <b>80</b> is formed, as shown in <figref idref="DRAWINGS">FIG. 9</figref>. The source/drain epitaxial layer <b>80</b> includes one or more layers of Si, SiP, SiC and SiCP for an n-channel FET or Si, SiGe, Ge for a p-channel FET. For the P-channel FET, boron (B) may also be contained in the source/drain. The source/drain epitaxial layers <b>80</b> are formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). As shown in <figref idref="DRAWINGS">FIG. 9</figref>, the source/drain epitaxial layers grow from the recessed two fin structures, and the grown epitaxial layers merge above the isolation insulating layer and form a void <b>89</b> in some embodiments. The source/drain epitaxial layer <b>80</b> is formed in contact with the second cover layer <b>53</b> disposed over side faces of the sacrificial gate structure <b>50</b>.
0085Subsequently, as shown in <figref idref="DRAWINGS">FIGS. 10A-10D</figref>, the second cover layer <b>53</b> is removed, by wet and/or dry etching. <figref idref="DRAWINGS">FIG. 10A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 10B</figref> is a cross sectional view along the X direction cutting one fin structure, <figref idref="DRAWINGS">FIG. 10C</figref> is a cross sectional view along the Y direction cutting a gap <b>83</b> of <figref idref="DRAWINGS">FIG. 10D</figref>, and <figref idref="DRAWINGS">FIG. 10D</figref> shows another perspective view.
0086When the second cover layer <b>53</b> is made of SiN, the second cover layer <b>53</b> can be selectively removed by using H<sub>3</sub>PO<sub>4</sub>. By removing the second cover layer <b>53</b>, a gap <b>83</b> is formed between the source/drain epitaxial layer <b>80</b> and the first cover layer <b>51</b> disposed over the side faces of the sacrificial gate structure, as shown in <figref idref="DRAWINGS">FIG. 10D</figref>. As shown in <figref idref="DRAWINGS">FIG. 10D</figref>, a part of the structure is exposed from the gap. The space of the gap <b>83</b> is substantially the same as the thickness of the second cover layer <b>53</b>.
0087Then, as shown in <figref idref="DRAWINGS">FIGS. 11A-11D</figref>, part of the first semiconductor layers <b>20</b> is removed in the gap <b>83</b> from the fin structure, and spaces <b>21</b> are formed between the second semiconductor layers <b>25</b>. The first semiconductor layers <b>20</b> can be removed or etched using an etchant that can selectively etch the first semiconductor layers <b>20</b> against the second semiconductor layers <b>25</b>.
0088When the first semiconductor layers <b>20</b> are Ge or SiGe and the second semiconductor layers <b>25</b> are Si, the first semiconductor layers <b>20</b> can be selectively removed using a wet etchant such as, but not limited to, ammonium hydroxide (NH<sub>4</sub>OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. Likewise, when the first semiconductor layers <b>20</b> are Si and the second semiconductor layers <b>25</b> are Ge or SiGe, the first semiconductor layers <b>20</b> can be selectively removed using a wet etchant such as, but not limited to, ammonium hydroxide (NH<sub>4</sub>OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. As shown in <figref idref="DRAWINGS">FIG. 11C</figref>, the remaining second semiconductor layers <b>25</b> have a rounded corner shape in some embodiments. Due to wet etching properties, the end face of the first semiconductor layers <b>20</b> has a convex shape, as shown in <figref idref="DRAWINGS">FIG. 11B</figref>, in some embodiments. By adjusting the etching time, it is possible to control the locations of the end faces of the first semiconductor layers <b>20</b>.
0089Next, as shown in <figref idref="DRAWINGS">FIGS. 12A-12C</figref>, an insulating layer <b>85</b> is formed over the structure shown in <figref idref="DRAWINGS">FIGS. 11A-11D</figref>. The insulating layer <b>85</b> can be formed by ALD or CVD or any other suitable method. By depositing the insulating layer <b>85</b>, the spaces <b>21</b> are filled by the insulating material of the insulating layer <b>85</b>, thereby forming inner spacers <b>85</b>, as shown in <figref idref="DRAWINGS">FIG. 12B</figref>. In some embodiments, the insulating layer <b>85</b> includes a low-k dielectric material, such as SiOC and/or SiOCN or any other suitable dielectric material.
0090In some embodiments, as shown in <figref idref="DRAWINGS">FIG. 12C</figref>, one or more voids <b>70</b> are formed in the inner spacers <b>85</b>. In certain embodiments, a part of the second semiconductor layer <b>25</b> is exposed to the void. In other embodiments, no part of the second semiconductor layer <b>25</b> is exposed to the void. In some embodiments, no void is formed.
0091Subsequently, an interlayer dielectric (ILD) layer <b>95</b> is formed, as shown in <figref idref="DRAWINGS">FIG. 13</figref>. The materials for the ILD layer <b>95</b> include compounds comprising Si, O, C and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used for the ILD layer <b>95</b>. After the ILD layer <b>95</b> is formed, a planarization operation, such as CMP, is performed, so that the top portion of the sacrificial gate electrode layer is exposed. Then, the sacrificial gate electrode layer <b>54</b> and sacrificial gate dielectric layer <b>52</b> are removed, thereby forming a gate space <b>75</b>, in which the channel regions of the fin structures are exposed, as shown in <figref idref="DRAWINGS">FIG. 14</figref>.
0092The ILD layer <b>95</b> protects the S/D structures <b>80</b> during the removal of the sacrificial gate structures. The sacrificial gate structures can be removed using plasma dry etching and/or wet etching. When the sacrificial gate electrode layer <b>54</b> is polysilicon and the ILD layer <b>95</b> is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer <b>54</b>. The sacrificial gate dielectric layer <b>52</b> is thereafter removed using plasma dry etching and/or wet etching.
0093After the sacrificial gate structures are removed, the first semiconductor layers <b>20</b> in the fin structures are removed, thereby forming wires of the second semiconductor layers <b>25</b>, as shown in <figref idref="DRAWINGS">FIG. 15</figref>. The first semiconductor layers <b>20</b> can be removed or etched using an etchant that can selectively etch the first semiconductor layers <b>20</b> against the second semiconductor layers <b>25</b>, as set forth above.
0094After the semiconductor wires of the second semiconductor layers <b>25</b> are formed, a gate dielectric layer <b>102</b> is formed around each channel layers (wires of the second semiconductor layers <b>25</b>), and a gate electrode layer <b>104</b> is formed on the gate dielectric layer <b>102</b>, as shown in <figref idref="DRAWINGS">FIG. 16</figref>.
0095In certain embodiments, the gate dielectric layer <b>102</b> includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO<sub>2</sub>, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO<sub>2</sub>—Al<sub>2</sub>O<sub>3</sub>) alloy, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer <b>102</b> includes an interfacial layer <b>102</b>A formed between the channel layers and the dielectric material.
0096The gate dielectric layer <b>102</b> may be formed by CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer <b>102</b> is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each channel layers. The thickness of the gate dielectric layer <b>102</b> is in a range from about 1 nm to about 6 nm in one embodiment.
0097The gate electrode layer <b>104</b> is formed on the gate dielectric layer <b>102</b> to surround each channel layer. The gate electrode <b>104</b> includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof.
0098The gate electrode layer <b>104</b> may be formed by CVD, ALD, electro-plating, or other suitable method. The gate electrode layer is also deposited over the upper surface of the ILD layer <b>95</b>. The gate dielectric layer and the gate electrode layer formed over the ILD layer <b>95</b> are then planarized by using, for example, CMP, until the top surface of the ILD layer <b>95</b> is revealed. After the planarization operation, the gate electrode layer <b>104</b> is recessed and a cap insulating layer <b>106</b> is formed over the recessed gate electrode <b>104</b>, as shown in <figref idref="DRAWINGS">FIG. 1A</figref>. The cap insulating layer includes one or more layers of a silicon nitride-based material, such as SiN. The cap insulating layer <b>106</b> can be formed by depositing an insulating material followed by a planarization operation.
0099In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer <b>102</b> and the gate electrode <b>104</b>. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer. The work function adjustment layer may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the work function adjustment layer may be formed separately for the n-channel FET and the p-channel FET which may use different metal layers.
0100Subsequently, contact holes are formed in the ILD layer <b>95</b> by using dry etching. In some embodiments, the upper portion of the S/D epitaxial layer <b>80</b> is etched. In some embodiments, a silicide layer is formed over the S/D epitaxial layer <b>80</b>. The silicide layer includes one or more of WSi, CoSi, NiSi, TiSi, MoSi and TaSi. Then, a conductive material <b>130</b> is formed in the contact holes as shown in <figref idref="DRAWINGS">FIG. 1A</figref>. The conductive material <b>130</b> includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. It is understood that the GAA FETs undergoes further CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc.
0101<figref idref="DRAWINGS">FIGS. 17-17D</figref> show various views of a semiconductor FET device according to other embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 17A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 17B</figref> is a cross sectional view corresponding to Y<b>1</b>-Y<b>1</b> of <figref idref="DRAWINGS">FIG. 17A</figref>, <figref idref="DRAWINGS">FIG. 17C</figref> is a cross sectional view corresponding to Y<b>2</b>-Y<b>2</b> of <figref idref="DRAWINGS">FIG. 17A</figref>, <figref idref="DRAWINGS">FIG. 17D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 17C</figref>. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with respect to <figref idref="DRAWINGS">FIGS. 1A-16</figref> may be employed in the following embodiments, and detailed explanation thereof may be omitted.
0102In the GAA FET of <figref idref="DRAWINGS">FIGS. 17A-17D</figref>, the semiconductor FET is a p-type GAA FET and the semiconductor wires for the channel region are configured by the first semiconductor layer <b>20</b>. In some embodiments, the first semiconductor layers <b>20</b> are Si1-xGex, where x is more than about 0.3, or Ge (x=1.0) and the second semiconductor layers <b>25</b> are Si or Si1-yGey, where y is less than about 0.4, and x>y. Further, the structure of the source/drain region is different from that of the structure shown in <figref idref="DRAWINGS">FIGS. 1A-1D</figref>. In <figref idref="DRAWINGS">FIGS. 17A-17D</figref>, the semiconductor wires of the first semiconductor layer <b>20</b> extend into the source/drain region, and are wrapped around by a source/drain epitaxial layer <b>81</b>.
0103As shown in <figref idref="DRAWINGS">FIGS. 17A-17D</figref>, two semiconductor fin structures <b>11</b> are provided over a semiconductor substrate <b>10</b>. In certain embodiments, the substrate <b>10</b> is made of crystalline Si. The bottom part of the fin structures <b>11</b> are covered by an insulating layer <b>35</b> (a fin liner layer). The fin liner layer <b>35</b> includes one or more layers of insulating material. An isolation insulating layer <b>40</b>, such as shallow trench isolations (STI), is disposed in the trenches over the substrate <b>11</b>. The isolation insulating layer <b>40</b> may be made of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like.
0104As shown in <figref idref="DRAWINGS">FIG. 17B</figref>, channel layers <b>20</b>, which are semiconductor wires, are disposed over the fin structure <b>11</b>. Each of the channel layers <b>20</b> is wrapped around by a gate dielectric layer <b>102</b> and a gate electrode layer <b>104</b>. In some embodiments, the gate dielectric layer <b>102</b> includes an interfacial layer <b>102</b>A and a high-k dielectric layer <b>102</b>B. Further, a gate cap insulating layer <b>106</b> is disposed over the gate electrode layer <b>104</b>.
0105As shown in <figref idref="DRAWINGS">FIGS. 17A, 17C and 17D</figref>, a source/drain epitaxial layer <b>81</b> is disposed over a source/drain region of the fin structure <b>11</b>. The source/drain epitaxial layer <b>81</b> is covered by an interlayer dielectric (ILD) layer <b>95</b>. In addition, a first cover layer <b>51</b> and/or an insulating layer <b>85</b> are formed between the source/drain epitaxial layer <b>81</b> and the ILD layer <b>95</b> and between the gate electrode <b>104</b> and the ILD layer <b>95</b>. Further, a source/drain contact <b>130</b> is disposed in contact with the source/drain epitaxial layer <b>81</b>.
0106<figref idref="DRAWINGS">FIG. 17C</figref> is a cross sectional view in the Y direction cutting the vertical portion of the insulating layer <b>85</b> at an area between the gate electrode <b>104</b> and the source/drain epitaxial layer <b>80</b>. In this area, the semiconductor wires <b>20</b> are at least partially covered by the insulating layer <b>85</b>. In some embodiments, one or more voids <b>70</b> are formed in the insulating layer <b>85</b> between the semiconductor wires <b>20</b>. In other embodiments, no void is formed.
0107<figref idref="DRAWINGS">FIG. 17D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 17C</figref> and <figref idref="DRAWINGS">FIG. 17E</figref> shows a cross sectional view corresponding to X<b>2</b>-X<b>2</b> of <figref idref="DRAWINGS">FIG. 17C</figref>. As shown in <figref idref="DRAWINGS">FIG. 17D</figref>, the insulating layer <b>85</b> is disposed between end faces of the gate electrode layer <b>104</b> and the source/drain epitaxial layer <b>81</b>, as inner spacers. In some embodiments, the gate dielectric layer <b>102</b> is disposed between the insulating layer <b>85</b> and the gate electrode layer <b>104</b>. As shown in <figref idref="DRAWINGS">FIG. 17D</figref>, end faces of the inner spacers <b>85</b> in contact with the source/drain epitaxial layer <b>81</b> are vertically aligned (disposed on the same vertical plane).
0108The interface between the gate electrode <b>104</b> and the inner spacers <b>85</b> has a curved surface protruding toward the gate electrode <b>104</b>, while the interface between the inner spacers <b>85</b> and the source/drain epitaxial layer <b>81</b> is substantially flat. In some embodiments, the inner spacers <b>85</b> are made of a low-k dielectric material, such as SiOC and/or SiOCN or any other suitable dielectric material.
0109The thickness and widths of each of the semiconductor wires <b>20</b> is in a range from about 5 nm to about 15 nm in some embodiments, and is in a range from about 6 nm to about 12 nm in other embodiments. The space between adjacent semiconductor wires in the Z direction is in a range from about 2 nm to about 6 nm in some embodiments. The thickness W<b>1</b> of the inner spacer <b>85</b> is in a range from about 2 nm to about 6 nm in some embodiments. The cross sectional shape of the semiconductor wires <b>20</b> in the channel region can be any polygonal shape (square, rectangular, triangular, etc.), polygonal shape with rounded corners, circular, or oval (vertically or horizontally).
0110In <figref idref="DRAWINGS">FIGS. 17A-17D</figref>, two fin structures <b>11</b> and four semiconductor wires <b>20</b> are illustrated. However, the numbers are not limited thereto. The number of the fin structures can be one, three, four or more per gate electrode, and the number of the semiconductor wires <b>20</b> can be one, two, three and more, up to ten.
0111In certain embodiments, one or more semiconductor devices of <figref idref="DRAWINGS">FIGS. 1A-1D</figref> (an n-type and/or a p-type GAA FET) and one or more p-type GAA FETs of <figref idref="DRAWINGS">FIGS. 17A-17D</figref> are provided on the same substrate <b>10</b>.
0112<figref idref="DRAWINGS">FIGS. 18-32</figref> show exemplary sequential processes for manufacturing the GAA FET shown in <figref idref="DRAWINGS">FIGS. 17A-17D</figref> according to one embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown by <figref idref="DRAWINGS">FIGS. 18-32</figref>, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with respect to <figref idref="DRAWINGS">FIGS. 1A-16</figref> may be employed in the following embodiments, and detailed explanation thereof may be omitted. The GAA FET of <figref idref="DRAWINGS">FIGS. 1A-1D</figref> can be manufactured together with the GAA FET shown in <figref idref="DRAWINGS">FIGS. 17A-17D</figref>.
0113As shown in <figref idref="DRAWINGS">FIG. 18</figref>, impurity ions (dopants) <b>12</b> are implanted into a silicon substrate <b>10</b> to form a well region. The ion implantation is performed to prevent a punch-through effect. The substrate <b>10</b> may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants <b>12</b> are, for example, phosphorus for a p-type Fin FET.
0114Then, as shown in <figref idref="DRAWINGS">FIG. 19</figref>, stacked semiconductor layers are formed over the substrate <b>10</b>. The stacked semiconductor layers include first semiconductor layers <b>20</b> and second semiconductor layers <b>25</b>. Further, a mask layer <b>15</b> is formed over the stacked layers.
0115The first semiconductor layers <b>20</b> and the second semiconductor layers <b>25</b> are made of materials having different lattice constants, and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some embodiments, the first semiconductor layers <b>20</b> and the second semiconductor layers <b>25</b> are made of Si, a Si compound, SiGe, Ge or a Ge compound. In one embodiment, the first semiconductor layers <b>20</b> are Si<sub>1-x</sub>Ge<sub>x</sub>, where x is more than about 0.3, or Ge (x=1.0) and the second semiconductor layers <b>25</b> are Si or Si<sub>1-y</sub>Ge<sub>y</sub>, where y is less than about 0.4, and x>y.
0116In <figref idref="DRAWINGS">FIG. 20</figref>, four layers of the first semiconductor layer <b>20</b> and four layers of the second semiconductor layer <b>25</b> are disposed. However, the number of the layers are not limited to five, and may be as small as 1 (each layer) and in some embodiments, 2-10 layers of each of the first and second semiconductor layers are formed. By adjusting the numbers of the stacked layers, a driving current of the GAA FET device can be adjusted.
0117The first semiconductor layers <b>20</b> and the second semiconductor layers <b>25</b> are epitaxially formed over the substrate <b>10</b>. The thickness of the first semiconductor layers <b>20</b> may be equal to or greater than that of the second semiconductor layers <b>25</b>, and is in a range from about 2 nm to about 20 nm in some embodiments, and is in a range from about 5 nm to about 15 nm in other embodiments. The thickness of the second semiconductor layers <b>25</b> is in a range from about 2 nm to about 20 nm in some embodiments, and is in a range from about 5 nm to about 15 nm in other embodiments. The thickness of each of the first semiconductor layers <b>20</b> may be the same, or may vary.
0118In some embodiments, the bottom first semiconductor layer <b>20</b> (the closest layer to the substrate <b>10</b>) is thicker than the remaining first semiconductor layers. The thickness of the bottom first semiconductor layer is in a range from about 10 nm to about 50 nm in some embodiments, or is in a range from 20 nm to 40 nm in other embodiments.
0119In some embodiments, the mask layer <b>15</b> includes a first mask layer <b>15</b>A and a second mask layer <b>15</b>B. The first mask layer <b>15</b>A is a pad oxide layer made of a silicon oxide, which can be formed by a thermal oxidation. The second mask layer <b>15</b>B is made of a silicon nitride (SiN). The mask layer <b>15</b> is patterned into a mask pattern by using patterning operations including photo-lithography and etching.
0120Next, as shown in <figref idref="DRAWINGS">FIG. 20</figref>, the stacked layers of the first and second semiconductor layers <b>20</b>, <b>25</b> are patterned by using the patterned mask layer, thereby the stacked layers are formed into fin structures <b>30</b> extending in the X direction. In <figref idref="DRAWINGS">FIG. 20</figref>, two fin structures <b>30</b> are arranged in the Y direction. But the number of the fin structures is not limited to, and may be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures <b>30</b> to improve pattern fidelity in the patterning operations. As shown in <figref idref="DRAWINGS">FIG. 20</figref>, the fin structures <b>30</b> have upper portions constituted by the stacked semiconductor layers <b>20</b>, <b>25</b> and well portions <b>11</b>.
0121The width W<b>1</b> of the upper portion of the fin structure along the Y direction is in a range from about 10 nm to about 40 nm in some embodiments, and is in a range from about 20 nm to about 30 nm in other embodiments. The height H<b>1</b> along the Z direction of the fin structure is in a range from about 100 nm to about 200 nm.
0122The stacked fin structure <b>30</b> may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the stacked fin structure <b>30</b>.
0123After the fin structures <b>30</b> are formed, an insulating material layer including one or more layers of insulating material is formed over the substrate so that the fin structures are fully embedded in the insulating layer. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, is performed such that the upper surface of the uppermost second semiconductor layer <b>25</b> is exposed from the insulating material layer. In some embodiments, a fin liner layer <b>35</b> is formed over the fin structures before forming the insulating material layer. The fin liner layer <b>35</b> is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN or SiOCN).
0124Then, as shown in <figref idref="DRAWINGS">FIG. 21</figref>, the insulating material layer is recessed to form an isolation insulating layer <b>40</b> so that the upper portions of the fin structures <b>30</b> are exposed. With this operation, the fin structures <b>30</b> are electrically separated from each other by the isolation insulating layer <b>40</b> (STI).
0125In the embodiment shown in <figref idref="DRAWINGS">FIG. 21</figref>, the insulating material layer <b>40</b> is recessed until the upper portion of the fin structure (well layer) <b>11</b> is exposed. In other embodiments, the upper portion of the fin structure <b>11</b> is not exposed. The second semiconductor layers <b>25</b> are sacrificial layers which are subsequently partially removed, and the first semiconductor layers <b>20</b> are subsequently formed into semiconductor wires as channel layers of a GAA FET.
0126After the isolation insulating layer <b>40</b> is formed, a sacrificial (dummy) gate structure <b>50</b> is formed, as shown in <figref idref="DRAWINGS">FIG. 22</figref>. <figref idref="DRAWINGS">FIG. 22</figref> illustrates a structure after a sacrificial gate structure <b>50</b> is formed over the exposed fin structures <b>30</b>. The sacrificial gate structure <b>50</b> is formed over a portion of the fin structures which is to be a channel region. The sacrificial gate structure defines the channel region of the GAA FET. The sacrificial gate structure <b>50</b> includes a sacrificial gate dielectric layer <b>52</b> and a sacrificial gate electrode layer <b>54</b>. The sacrificial gate dielectric layer <b>52</b> includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. The thickness of the sacrificial gate dielectric layer <b>52</b> is in a range from about 1 nm to about 5 nm in some embodiments.
0127The sacrificial gate structure <b>50</b> is formed by first blanket depositing the sacrificial gate dielectric layer <b>52</b> over the fin structures. A sacrificial gate electrode layer is then blanket deposited on the sacrificial gate dielectric layer and over the fin structures, such that the fin structures are fully embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range from about 100 nm to about 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process. Subsequently, a mask layer is formed over the sacrificial gate electrode layer <b>54</b>. The mask layer includes a pad SiN layer <b>56</b> and a silicon oxide mask layer <b>58</b>.
0128Next, a patterning operation is performed on the mask layer and sacrificial gate electrode layer is patterned into the sacrificial gate structure <b>50</b>, as shown in <figref idref="DRAWINGS">FIG. 22</figref>. The sacrificial gate structure includes the sacrificial gate dielectric layer <b>52</b>, the sacrificial gate electrode layer <b>54</b> (e.g., poly silicon), the pad SiN layer <b>56</b> and the silicon oxide mask layer <b>58</b>. By patterning the sacrificial gate structure, the stacked layers of the first and second semiconductor layers are partially exposed on opposite sides of the sacrificial gate structure, thereby defining source/drain (S/D) regions, as shown in <figref idref="DRAWINGS">FIG. 22</figref>. In this disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same. In <figref idref="DRAWINGS">FIG. 22</figref>, one sacrificial gate structure is formed, but the number of the sacrificial gate structures is not limited to one. Two or more sacrificial gate structures are arranged in the X direction in some embodiments. In certain embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structures to improve pattern fidelity.
0129After the sacrificial gate structure is formed, a first cover layer <b>51</b> made of an insulating material is conformally formed over the exposed fin structures <b>11</b> and the sacrificial gate structure <b>50</b>. Further, a second cover layer <b>53</b> is formed over the first cover layer <b>51</b>, as shown in <figref idref="DRAWINGS">FIG. 23</figref>. The first and second cover layers are deposited in a conformal manner so that they are formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the sacrificial gate structure, respectively. In some embodiments, the first cover layer <b>51</b> has a thickness in a range from about 2 nm to about 10 nm, and the second cover layer <b>53</b> has a thickness greater than the first cover layer and has a thickness in a range from about 5 nm to about 20 nm.
0130In one embodiment, the first cover layer <b>51</b> includes a low-k dielectric material, such as SiOC and/or SiOCN or any other suitable dielectric material. The second cover layer <b>53</b> includes one or more of SiN, SiON and SiCN or any other suitable dielectric material. The first cover layer and the second cover layer are made of different materials so that one of them can be selectively etched. The first cover layer <b>51</b> and the second cover layer <b>53</b> can be formed by ALD or CVD, or any other suitable method.
0131Then, as shown in <figref idref="DRAWINGS">FIG. 24</figref>, the second semiconductor layers <b>25</b> of the fin structures of the source/drain regions are removed, thereby leaving the first semiconductor layer <b>20</b> as semiconductor wires. When the second semiconductor layers <b>25</b> are Ge or SiGe and the first semiconductor layers <b>20</b> are Si, the second semiconductor layers <b>25</b> can be selectively removed using a wet etchant such as, but not limited to, ammonium hydroxide (NH<sub>4</sub>OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions.
0132Subsequently, a source/drain epitaxial layer <b>81</b> is formed, as shown in <figref idref="DRAWINGS">FIG. 25</figref>. The source/drain epitaxial layer <b>81</b> includes one or more layers of Si, SiGe, Ge or any other suitable crystalline semiconductor material. The source/drain epitaxial layer <b>81</b> may contain boron. The source/drain epitaxial layers <b>81</b> are formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). As shown in <figref idref="DRAWINGS">FIG. 25</figref>, the source/drain epitaxial layers grow from the recessed two fin structures. The source/drain epitaxial layer <b>81</b> wraps around each of the first semiconductor layers (wires) <b>20</b>. In some embodiments, adjacent source/drain epitaxial layers <b>81</b> merge above the isolation insulating layer <b>40</b>, and in other embodiments, source/drain epitaxial layer <b>81</b> are independently formed over the respective fin structures. The source/drain epitaxial layer <b>81</b> is formed in contact with the second cover layer <b>53</b> disposed over side faces of the sacrificial gate structure <b>50</b>.
0133Subsequently, as shown in <figref idref="DRAWINGS">FIGS. 26A-26D</figref>, the second cover layer <b>53</b> is removed, by wet and/or dry etching. <figref idref="DRAWINGS">FIG. 26A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 26B</figref> is a cross sectional view along the X direction cutting one fin structure, <figref idref="DRAWINGS">FIG. 26C</figref> is a cross sectional view along the Y direction cutting a gap <b>83</b> of <figref idref="DRAWINGS">FIG. 26D</figref>, and <figref idref="DRAWINGS">FIG. 26D</figref> shows another perspective view.
0134When the second cover layer <b>53</b> is made of SiN, the second cover layer <b>53</b> can be selectively removed by using H<sub>3</sub>PO<sub>4</sub>. By removing the second cover layer <b>53</b>, a gap <b>83</b> is formed between the source/drain epitaxial layer <b>81</b> and the first cover layer <b>51</b> disposed over the side faces of the sacrificial gate structure, as shown in <figref idref="DRAWINGS">FIG. 26D</figref>. As shown in <figref idref="DRAWINGS">FIG. 26D</figref>, a part of the structure is exposed from the gap <b>83</b>. The space of the gap <b>83</b> is substantially the same as the thickness of the second cover layer <b>53</b>.
0135Then, as shown in <figref idref="DRAWINGS">FIGS. 27A-27D</figref>, part of the second semiconductor layers <b>25</b> is removed in the gap <b>83</b> from the fin structure, and spaces <b>21</b> are formed between the first semiconductor layers <b>20</b>. The second semiconductor layers <b>25</b> can be removed or etched using an etchant that can selectively etch the second semiconductor layers <b>25</b> against the first semiconductor layers <b>20</b>.
0136As shown in <figref idref="DRAWINGS">FIG. 27C</figref>, the remaining first semiconductor layers <b>20</b> have a rounded corner shape in some embodiments. Due to wet etching properties, the end face of the second semiconductor layers <b>25</b> has a convex shape, as shown in <figref idref="DRAWINGS">FIG. 27B</figref>, in some embodiments. By adjusting the etching time, it is possible to control the locations of the end faces of the second semiconductor layers <b>25</b>.
0137Next, as shown in <figref idref="DRAWINGS">FIGS. 28A-28C</figref>, an insulating layer <b>85</b> is formed over the structure shown in <figref idref="DRAWINGS">FIGS. 27A-27D</figref>. The insulating layer <b>85</b> can be formed by ALD or CVD or any other suitable method. By depositing the insulating layer <b>85</b>, the spaces <b>21</b> are filled by the insulating material of the insulating layer <b>85</b>, thereby forming inner spacers <b>85</b>, as shown in <figref idref="DRAWINGS">FIG. 28B</figref>. In some embodiments, the insulating layer <b>85</b> includes a low-k dielectric material, such as SiOC and/or SiOCN or any other suitable dielectric material.
0138In some embodiments, as shown in <figref idref="DRAWINGS">FIG. 28C</figref>, one or more voids <b>70</b> are formed in the inner spacers <b>85</b>. In certain embodiments, a part of the first semiconductor layer <b>20</b> is exposed to the void. In other embodiments, no part of the first semiconductor layer <b>20</b> is exposed to the void. In some embodiments, no voids are formed.
0139Subsequently, an interlayer dielectric (ILD) layer <b>95</b> is formed, as shown in <figref idref="DRAWINGS">FIG. 29</figref>. The materials for the ILD layer <b>95</b> include compounds comprising Si, O, C and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used for the ILD layer <b>95</b>. After the ILD layer <b>95</b> is formed, a planarization operation, such as CMP, is performed, so that the top portion of the sacrificial gate electrode layer is exposed. Then, the sacrificial gate electrode layer <b>54</b> and sacrificial gate dielectric layer <b>52</b> are removed, thereby forming a gate space <b>76</b>, in which the channel regions of the fin structures are exposed, as shown in <figref idref="DRAWINGS">FIG. 30</figref>.
0140The ILD layer <b>95</b> protects the S/D structures <b>81</b> during the removal of the sacrificial gate structures. The sacrificial gate structures can be removed using plasma dry etching and/or wet etching. When the sacrificial gate electrode layer <b>54</b> is polysilicon and the ILD layer <b>95</b> is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer <b>54</b>. The sacrificial gate dielectric layer <b>52</b> is thereafter removed using plasma dry etching and/or wet etching.
0141After the sacrificial gate structures are removed, the second semiconductor layers <b>25</b> in the fin structures are removed, thereby forming wires of the first semiconductor layers <b>20</b>, as shown in <figref idref="DRAWINGS">FIG. 31</figref>. The second semiconductor layers <b>25</b> can be removed or etched using an etchant that can selectively etch the second semiconductor layers <b>25</b> against the first semiconductor layers <b>20</b>, as set forth above.
0142After the semiconductor wires of the first semiconductor layers <b>20</b> are formed, a gate dielectric layer <b>102</b> is formed around each channel layers (wires of the second semiconductor layers <b>25</b>), and a gate electrode layer <b>104</b> is formed on the gate dielectric layer <b>102</b>, as shown in <figref idref="DRAWINGS">FIG. 32</figref>.
0143Subsequently, contact holes are formed in the ILD layer <b>95</b> by using dry etching. In some embodiments, the upper portion of the S/D epitaxial layer <b>81</b> is etched. In some embodiments, a silicide layer is formed over the S/D epitaxial layer <b>81</b>. Then, a conductive material <b>130</b> is formed in the contact holes as shown in <figref idref="DRAWINGS">FIG. 17A</figref>. The conductive material <b>130</b> includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. It is understood that the GAA FETs undergoes further CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc.
0144<figref idref="DRAWINGS">FIGS. 33A-33D</figref> show various views of a semiconductor FET device and <figref idref="DRAWINGS">FIGS. 34A-34D</figref> show various views of a semiconductor FET device according to other embodiments of the present disclosure. <figref idref="DRAWINGS">FIG. 33A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 33B</figref> is a cross sectional view corresponding to Y<b>1</b>-Y<b>1</b> of <figref idref="DRAWINGS">FIG. 33A</figref>, <figref idref="DRAWINGS">FIG. 33C</figref> is a cross sectional view corresponding to Y<b>2</b>-Y<b>2</b> of <figref idref="DRAWINGS">FIG. 33A</figref>, <figref idref="DRAWINGS">FIG. 33D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 33C</figref>. <figref idref="DRAWINGS">FIG. 34A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 34B</figref> is a cross sectional view corresponding to Y<b>1</b>-Y<b>1</b> of <figref idref="DRAWINGS">FIG. 34A</figref>, <figref idref="DRAWINGS">FIG. 34C</figref> is a cross sectional view corresponding to Y<b>2</b>-Y<b>2</b> of <figref idref="DRAWINGS">FIG. 34A</figref>, and <figref idref="DRAWINGS">FIG. 34D</figref> shows a cross sectional view corresponding to X<b>1</b>-X<b>1</b> of <figref idref="DRAWINGS">FIG. 34C</figref>. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with respect to <figref idref="DRAWINGS">FIGS. 1A-32</figref> may be employed in the following embodiments, and detailed explanation thereof may be omitted. The GAA FET shown in <figref idref="DRAWINGS">FIGS. 33A-33D</figref> and the FinFET shown in <figref idref="DRAWINGS">FIGS. 34A-34D</figref> are provided on the same substrate in some embodiments.
0145The GAA FET shown in <figref idref="DRAWINGS">FIGS. 33A-33D</figref> is substantially the same as the GAA FET shown in <figref idref="DRAWINGS">FIGS. 1A-1D</figref>, except that an etch-stop layer (ESL) <b>87</b> is further formed between the insulating layer <b>85</b> and the ILD layer <b>95</b>. The ESL <b>87</b> includes one or more layers of insulating material, such as SiN and SiON, or any other suitable material, formed by ALD, CVD or any other suitable method. The GAA FET shown in <figref idref="DRAWINGS">FIGS. 33A-33D</figref> can be an n-type FET or a p-type FET.
0146In the GAA FET shown in <figref idref="DRAWINGS">FIGS. 33A-33D</figref>, the semiconductor wires of the channel region are made of the second semiconductor layers <b>25</b>. In some embodiments, the cross sectional view of the second semiconductor layers <b>25</b> is a rectangular shape with rounded corners. In some embodiments, the width W<b>11</b> of the second semiconductor layers <b>25</b> is in a range from about 5 nm to about 15 nm and the thickness T<b>11</b> is in a range from about 1.5 nm to about 10 nm. The width W<b>11</b> of the second semiconductor layers <b>25</b> is in a range from about 6 nm to about 10 nm and the thickness T<b>11</b> is in a range from about 2 nm to about 6 nm, in other embodiments. The pitch P<b>11</b> is in a range from about 5 nm to about 15 nm in some embodiments, and is in a range from about 8 nm to about 12 nm in other embodiments.
0147In the FinFET of <figref idref="DRAWINGS">FIGS. 34A-35E</figref>, the semiconductor FET is a p-type FinFET and the channel region includes the first semiconductor layers <b>20</b> and the second semiconductor layers <b>25</b>. In some embodiments, the first semiconductor layers <b>20</b> are Si1-xGex, where x is more than about 0.3, or Ge (x=1.0) and the second semiconductor layers <b>25</b> are Si or Si1-yGey, where y is less than about 0.4, and x>y. Further, the structure of the source/drain region is different from that of the structures shown in <figref idref="DRAWINGS">FIGS. 1A-1D</figref>, <figref idref="DRAWINGS">FIGS. 17A-17D</figref>, or <figref idref="DRAWINGS">FIGS. 33A-33D</figref>. In the FinFET of <figref idref="DRAWINGS">FIGS. 34A-34D</figref>, the source/drain region includes the first semiconductor layers <b>20</b> and the second semiconductor layer <b>25</b> alternately stacked, and a source/drain epitaxial layer <b>81</b> wraps around the stacked source/drain structure.
0148As shown in <figref idref="DRAWINGS">FIGS. 34B and 34D</figref>, the channel region includes the first semiconductor layers <b>20</b> and the second semiconductor layer <b>25</b>. The width of the second semiconductor layers <b>25</b> is smaller than the width of the first semiconductor layers <b>20</b>. In some embodiments, the width in the Y direction of the first semiconductor layers <b>20</b> is in a range from about 3 nm to about 10 nm and the width in the Y direction of the second semiconductor layers <b>25</b> is in a range from about 1 nm to about 5 nm. In other embodiments, the width in the Y direction of the first semiconductor layers <b>20</b> is in a range from about 4 nm to about 6 nm and the width in the Y direction of the second semiconductor layers <b>25</b> is in a range from about 2 nm to about 4 nm. The difference in width between the first semiconductor layer <b>20</b> and the second semiconductor layers <b>25</b> is in a range from about 1 nm to about 3 nm in some embodiments.
0149<figref idref="DRAWINGS">FIGS. 35-40C</figref> show exemplary sequential processes for manufacturing the FinFET shown in <figref idref="DRAWINGS">FIGS. 34A-34D</figref> according to one embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown by <figref idref="DRAWINGS">FIGS. 35-40C</figref>, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with respect to <figref idref="DRAWINGS">FIGS. 1A-34D</figref> may be employed in the following embodiments, and detailed explanation thereof may be omitted. The GAA FET of <figref idref="DRAWINGS">FIGS. 1A-1D</figref>, GAA FET of <figref idref="DRAWINGS">FIGS. 17A-17D</figref> and/or the GAA FET of <figref idref="DRAWINGS">FIGS. 33A-33D</figref> can be manufactured together with the FinFET shown in <figref idref="DRAWINGS">FIGS. 34A-34D</figref>.
0150After the structure shown in <figref idref="DRAWINGS">FIG. 23</figref> is formed, the second cover layer <b>53</b> and the first cover <b>51</b> disposed over the source/drain region of the fin structure are removed, as show in <figref idref="DRAWINGS">FIG. 35</figref>.
0151Subsequently, a source/drain epitaxial layer <b>81</b> is formed, as shown in <figref idref="DRAWINGS">FIG. 36</figref>. The source/drain epitaxial layer <b>81</b> includes one or more layers of Si, SiGe, Ge or any other suitable crystalline semiconductor material. The source/drain epitaxial layer <b>81</b> may contain boron (B). The source/drain epitaxial layers <b>81</b> are formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). As shown in <figref idref="DRAWINGS">FIG. 36</figref>, the source/drain epitaxial layers grow from the recessed two fin structure of two fin structures. The source/drain epitaxial layer <b>81</b> wraps around each of the upper portions of the fin structures. In some embodiments, adjacent source/drain epitaxial layers <b>81</b> merge above the isolation insulating layer <b>40</b>, and in other embodiments, source/drain epitaxial layer <b>81</b> are independently formed over the respective fin structures. The source/drain epitaxial layer <b>81</b> is formed in contact with the second cover layer disposed over side faces of the sacrificial gate structure.
0152Then, as shown in <figref idref="DRAWINGS">FIGS. 37A-37C</figref>, the second cover layer <b>53</b> is removed, by wet and/or dry etching. <figref idref="DRAWINGS">FIG. 37A</figref> is a perspective view, <figref idref="DRAWINGS">FIG. 37B</figref> is a cross sectional view along the X direction cutting one fin structure, and <figref idref="DRAWINGS">FIG. 37C</figref> is a cross sectional view along the Y direction cutting a gap <b>83</b> of <figref idref="DRAWINGS">FIG. 26D</figref>.
0153When the second cover layer <b>53</b> is made of SiN, the second cover layer <b>53</b> can be selectively removed by using H<sub>3</sub>PO<sub>4</sub>. By removing the second cover layer <b>53</b>, a gap <b>83</b> is formed between the source/drain epitaxial layer <b>83</b> and the first cover layer <b>51</b> disposed over the side faces of the sacrificial gate structure, as shown in <figref idref="DRAWINGS">FIG. 37B</figref>. As shown in <figref idref="DRAWINGS">FIG. 37B</figref>, a part of the fin structure is exposed from the gap <b>83</b>.
0154Next, as shown in <figref idref="DRAWINGS">FIGS. 38A-38C</figref>, an insulating layer <b>85</b> is formed over the structure shown in <figref idref="DRAWINGS">FIGS. 37A-37D</figref>. The insulating layer <b>85</b> can be formed by ALD or CVD or any other suitable method. In some embodiments, the insulating layer <b>85</b> includes a low-k dielectric material, such as SiOC and/or SiOCN or any other suitable dielectric material.
0155Subsequently, an interlayer dielectric (ILD) layer <b>95</b> is formed, as shown in <figref idref="DRAWINGS">FIGS. 39A-39C</figref>. In some embodiments, before forming the ILD layer <b>95</b>, an etch-stop layer (ESL) <b>87</b> is formed over the insulating layer <b>85</b>. The ESL <b>87</b> includes one or more layers of insulating material, such as SiN and SiON, or any other suitable material, formed by ALD, CVD or any other suitable method.
0156The materials for the ILD layer <b>95</b> include compounds comprising Si, O, C and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used for the ILD layer <b>95</b>. After the ILD layer <b>95</b> is formed, a planarization operation, such as CMP, is performed, so that the top portion of the sacrificial gate electrode layer <b>54</b> is exposed. Then, the sacrificial gate electrode layer <b>54</b> and sacrificial gate dielectric layer <b>52</b> are removed, thereby forming a gate space <b>76</b>, in which the channel regions of the fin structures are exposed, as shown in <figref idref="DRAWINGS">FIGS. 39A-39C</figref>.
0157After the sacrificial gate structures are removed, the second semiconductor layers <b>25</b> in the fin structures are partially removed, as shown in <figref idref="DRAWINGS">FIG. 39C</figref>. The second semiconductor layers <b>25</b> can be etched using an etchant that can selectively etch the second semiconductor layers <b>25</b> against the first semiconductor layers <b>20</b>, as set forth above.
0158After the semiconductor wires of the first semiconductor layers <b>20</b> are formed, a gate dielectric layer <b>102</b> is formed over the channel layer including the first semiconductor layers <b>20</b> and the second semiconductor layers <b>25</b>, and a gate electrode layer <b>104</b> is formed on the gate dielectric layer <b>102</b>, as shown in <figref idref="DRAWINGS">FIGS. 40A-40C</figref>.
0159Subsequently, contact holes are formed in the ILD layer <b>95</b> by using dry etching. In some embodiments, the upper portion of the S/D epitaxial layer <b>81</b> is etched. In some embodiments, a silicide layer is formed over the S/D epitaxial layer <b>81</b>. Then, a conductive material <b>130</b> is formed in the contact holes as shown in <figref idref="DRAWINGS">FIGS. 34A-34D</figref>. The conductive material <b>130</b> includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. It is understood that the FETs undergoes further CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc.
0160The various embodiments or examples described herein offer several advantages over the existing art. For example, in the present disclosure, since the inner spacers <b>85</b> are formed after the source/drain epitaxial layer is formed, the inner spacers can be formed in a self-align manner. With the foregoing embodiments, it is possible to more precisely control the thickness, the shape and/or the location of the inner spacers and thus to control capacitances around the source/drain and the gate.
0161It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages.
0162In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed on opposing sides of the sacrificial gate structure. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material. In one or more of the foregoing and following embodiments, one or more voids are formed in the first insulating material between the second semiconductor layers. In one or more of the foregoing and following embodiments, the first insulating material is a low-k dielectric material. In one or more of the foregoing and following embodiments, the first insulating material is further formed on the source/drain epitaxial layer and the first cover layer. In one or more of the foregoing and following embodiments, the first cover layer is made of a first dielectric material and the second cover layer is made of a second dielectric material different from the first dielectric material. In one or more of the foregoing and following embodiments, the first dielectric material is a low-k dielectric material. In one or more of the foregoing and following embodiments, the forming the source/drain epitaxial layer includes recessing a part of the fin structure not covered by the sacrificial gate structure, and forming a third semiconductor layer over the recessed fin structure as the source/drain epitaxial layer. The third semiconductor layer is made of a different semiconductor material than the second semiconductor layers. In one or more of the foregoing and following embodiments, after the first insulating material is formed, the sacrificial gate structure is removed, thereby exposing a part of the fin structure. The first semiconductor layers are removed from the exposed fin structure, thereby forming channel layers including the second semiconductor layers. A gate dielectric layer and a gate electrode layer are formed around the channel layers. In one or more of the foregoing and following embodiments, the gate electrode layer is in contact with the first insulating material and isolated from the source/drain epitaxial layer by the first insulating material. In one or more of the foregoing and following embodiments, the first semiconductor layer is made of SiGe, and the second semiconductor layer is made of Si.
0163In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. The second semiconductor layers are removed from a part of the fin structure not covered by the sacrificial gate structure, thereby forming source/drain layers made by the first semiconductor layers. A source/drain epitaxial layer is formed over the source/drain layers. After the source/drain epitaxial layers are formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the second semiconductor layers in the gap is removed, thereby forming spaces between the first semiconductor layers. The spaces are filled with a first insulating material. In one or more of the foregoing and following embodiments, one or more voids are formed in the first insulating material between the first semiconductor layers. In one or more of the foregoing and following embodiments, the first insulating material is further formed on the source/drain epitaxial layer and the first cover layer. In one or more of the foregoing and following embodiments, the first cover layer is made of a first dielectric material and the second cover layer is made of a second dielectric material different from the first dielectric material. In one or more of the foregoing and following embodiments, after the first insulating material is formed, the sacrificial gate structure is removed, thereby exposing a part of the fin structure. The second semiconductor layers are removed from the exposed fin structure, thereby forming channel layers made by the first semiconductor layers. A gate dielectric layer and a gate electrode layer are formed around the channel layers. In one or more of the foregoing and following embodiments, the gate electrode layer is in contact with the first insulating material and isolated from the source/drain epitaxial layer by the first insulating material. In one or more of the foregoing and following embodiments, the first semiconductor layer is made of SiGe, and the second semiconductor layer is made of Si.
0164In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. The first and second cover layers are removed from a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby exposing the source/drain region of the fin structure. A source/drain epitaxial layer is formed over the source/drain region. A first insulating layer is formed over the source/drain epitaxial layer and the first cover layer. An etch-stop layer is formed over the first insulating layer. An interlayer dielectric layer is formed over the etch-stop layer. In one or more of the foregoing and following embodiments, after the interlayer dielectric layer is formed, the sacrificial gate structure is removed, thereby exposing a part of the fin structure. The second semiconductor layers are partially removed from the exposed fin structure, thereby forming channel layers including the first semiconductor layers and the second semiconductor layers having thinner widths than the first semiconductor layers. A gate dielectric layer and a gate electrode layer are formed around the channel layers. In one or more of the foregoing and following embodiments, the first insulating layer is made of a low-k dielectric material.
0165In accordance with one aspect of the present disclosure, a semiconductor device includes first semiconductor wires disposed over a substrate, a first source/drain region in contact with ends of the first semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the first semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and first insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region. End faces of the first insulating spacers in contact with the first source/drain region are vertically aligned. In one or more of the foregoing and following embodiments, the end faces of the first insulating spacers in contact with the first source/drain region and interface between the ends of the first semiconductor wires and the first source/drain region are vertically aligned. In one or more of the foregoing and following embodiments, one or more voids are formed in the first insulating spaces between the first semiconductor wires. In one or more of the foregoing and following embodiments, the first insulating spacers are made of a low-k dielectric material. In one or more of the foregoing and following embodiments, the low-k dielectric material includes at least one selected from the group consisting of SiOC and SiOCN. In one or more of the foregoing and following embodiments, a first insulating layer is formed over the source/drain region and over side faces of the gate electrode layer, and the first insulating layer is made of a same material as and formed at a same time as the first insulating spacers. In one or more of the foregoing and following embodiments, the semiconductor device further includes a cover layer disposed between the side faces of the gate electrode layer and the first insulating layer. In one or more of the foregoing and following embodiments, the source/drain region and the first cover layer are separated by the first insulating layer.
0166In accordance with another aspect of the present disclosure, a semiconductor device includes first semiconductor wires disposed over a substrate, a first source/drain epitaxial layer wrapping around source/drain regions of the first semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the first semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and first insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region. End faces of the first insulating spacers in contact with the first source/drain region are vertically aligned. In one or more of the foregoing and following embodiments, the first semiconductor wires are made of SiGe or Ge. In one or more of the foregoing and following embodiments, one or more voids are formed in the first insulating spaces between the first semiconductor wires. In one or more of the foregoing and following embodiments, the first insulating spacers include at least one selected from the group consisting of SiOC and SiOCN. In one or more of the foregoing and following embodiments, a first insulating layer is formed over the source/drain epitaxial layer and over side faces of the gate electrode layer, and the first insulating layer is made of a same material as and formed at a same time as the first insulating spacers. In one or more of the foregoing and following embodiments, the semiconductor device further includes a cover layer disposed between the side faces of the gate electrode layer and the first insulating layer. In one or more of the foregoing and following embodiments, the source/drain region and the first cover layer are separated by the first insulating layer. In one or more of the foregoing and following embodiments.
0167In accordance with another aspect of the present disclosure, a semiconductor device includes a first field effect transistor (FET) and a second FET. The first FET includes first semiconductor wires disposed over a substrate, a first source/drain epitaxial layer in contact with ends of the first semiconductor wires, a first gate dielectric layer disposed on and wrapping around each channel region of the first semiconductor wires, a first gate electrode layer disposed on the first gate dielectric layer and wrapping around the each channel region, and first insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent first semiconductor wires, the first gate electrode layer and the first source/drain epitaxial layer. The second FET includes a fin structure in which first semiconductor layer and second semiconductor layer are alternately stacked, a second source/drain epitaxial layer disposed over a source/drain region of the fin structure, a second gate dielectric layer disposed over a channel region of the fin structure, and a second gate electrode layer disposed on the second gate dielectric layer. In one or more of the foregoing and following embodiments, the first FET is an n-type FET and the second FET is a p-type FET. In one or more of the foregoing and following embodiments, end faces of the first insulating spacers in contact with the first source/drain epitaxial layer are vertically aligned. In one or more of the foregoing and following embodiments, one or more voids are formed in the first insulating spaces between the first semiconductor wires. In one or more of the foregoing and following embodiments, widths of the first semiconductor layers in the channel region are smaller than width of the second semiconductor layers in the channel region.
0168The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Contents5
38 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35 Sheet 36 Sheet 37 Sheet 38
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US12349334B2 | Cited by | United States of America | Applicant |
| US11038044B2 | Cited by | United States of America | Search report |
| US11038043B2 | Cited by | United States of America | Applicant |
| US11557655B2 | Cited by | United States of America | Applicant |
| US12376283B2 | Cited by | United States of America | Applicant |
| US11581426B2 | Cited by | United States of America | Applicant |
| US12408322B2 | Cited by | United States of America | Applicant |
| US12426232B2 | Cited by | United States of America | Applicant |
| US12419034B2 | Cited by | United States of America | Applicant |
| EP4184586A1 | Cited by | European Patent Office (EPO) | Search report |
16 members in 5 offices
Priority claims10
| Document | Office | Kind | Date |
|---|---|---|---|
| 201715653068 | United States of America | A | |
| 201715653068 | United States of America | A | |
| 201816206730 | United States of America | A | |
| 201816206730 | United States of America | A | |
| 201916655079 | United States of America | A | |
| 15653068 | – | – | – |
| 16206730 | – | – | – |
| US201715653068 | – | – | – |
| US201816206730 | – | – | – |
| US201916655079 | – | – | – |
Members16
| Document | Office | Kind | |
|---|---|---|---|
| DE102017119141A1 | Germany | A1 | |
| US2019027570A1 | United States of America | A1 | |
| CN109273362A | China | A | |
| KR20190009227A | Republic of Korea | A | |
| US10211307B2 | United States of America | B2 | |
| TW201909283A | Taiwan Province of China | A | |
| US2019115438A1 | United States of America | A1 | |
| TWI661490B | Taiwan Province of China | B | |
| KR102045356B1 | Republic of Korea | B1 | |
| US2020052084A1 | United States of America | A1 | |
| US10861952B2 | United States of America | B2 | |
| DE102017119141B4 | Germany | B4 | |
| US11139381B2 | United States of America | B2 | |
| CN109273362B | China | B | |
| CN114464535A | China | A | |
| CN114464535B | China | B |
67 transactions on the USPTO file
Allowed after 1 non-final rejection and 1 final rejection.
- Non-final rejections
- 1
- Final rejections
- 1
- RCEs
- 0
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Payment of Maintenance Fee, 4th Year, Large EntityM1551 | M1551 | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Email NotificationEML_NTR | EML_NTR | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Email NotificationEML_NTR | EML_NTR | |
| Printer Rush- No mailingTCPB | TCPB | |
| Mailing Corrected Notice of AllowabilityMCNOA | MCNOA | |
| Corrected Notice of AllowabilityCNOA | CNOA | |
| Pubs Case Remand to TCPUBTC | PUBTC | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| After Final Consideration Program Additional Consideration and/or updated searchAFAC | AFAC | |
| Examiner's Amendment CommunicationEX.A | EX.A | |
| Reasons for AllowanceEX.R | EX.R | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| PILOT- Request for After Final Consideration ProgramRAFC | RAFC | |
| Response after Final ActionA.NE | A.NE | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Email NotificationEML_NTR | EML_NTR | |
| Application ready for PDX access by participating foreign officesCCRDY | CCRDY | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Email NotificationEML_NTR | EML_NTR | |
| Application Is Now CompleteCOMP | COMP | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Application Dispatched from OIPEOIPE | OIPE | |
| FITF set to YES - revise initial settingFTFS | FTFS | |
| Cleared by L&R (LARS)L128 | L128 | |
| Referred to Level 2 (LARS) by OIPE CSRL198 | L198 | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Patent Term Adjustment - Ready for ExaminationPTA.RFE | PTA.RFE | |
| PTO/SB/69-Authorize EPO Access to Search ResultsSREXR141 | SREXR141 | |
| Applicants have given acceptable permission for participating foreignAPPERMS | APPERMS | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Entity Status Set To Undiscounted (Initial Default Setting or Status Change)BIG. | BIG. | |
| Initial Exam Team nnIEXX | IEXX |
13 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| Information on status: patent application and granting procedure in generalPUBLICATIONS -- ISSUE FEE PAYMENT VERIFIEDSTPP | STPP | |
| AssignmentAS | AS | |
| Information on status: patent application and granting procedure in generalNOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONSSTPP | STPP | |
| Information on status: patent application and granting procedure in generalNOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONSSTPP | STPP | |
| Information on status: patent application and granting procedure in generalRESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINERSTPP | STPP | |
| Information on status: application discontinuationFINAL REJECTION MAILEDSTCB | STCB | |
| Information on status: patent application and granting procedure in generalFINAL REJECTION MAILEDSTPP | STPP | |
| Information on status: patent application and granting procedure in generalNON FINAL ACTION MAILEDSTPP | STPP | |
| Information on status: patent application and granting procedure in generalDOCKETED NEW CASE - READY FOR EXAMINATIONSTPP | STPP | |
| Information on status: patent application and granting procedure in generalAPPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETEDSTPP | STPP | |
| AssignmentAS | AS | |
| Fee payment procedureENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP |
Numbers
- Publication
- 20200052084
- Publication, DOCDB
- 2020052084
- Publication, EPODOC
- US2020052084
- Application
- 16655079
- Application, DOCDB
- 201916655079
- Application, EPODOC
- US201916655079
Titles
- English
- METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
Patent term adjustment
- Net adjustment
- 0 days
Classification
- CPC, 30
- H01L29/42392
- H10D30/024
- H10D30/6735
- H10D30/014
- H10D62/235
- H01L29/04
- H10D30/023
- H01L29/0649
- H01L29/165
- H10D30/611
- H01L29/66545
- H10D30/62
- H01L29/78696
- H01L29/66795
- H01L29/7848
- H10D64/017
- H01L29/785
- H10D30/6757
- H01L29/66439
- H01L29/6656
- H10D30/6215
- H10D30/797
- H10D62/40
- H10D62/115
- H10D62/121
- H10D62/822
- H10D64/015
- H10D64/018
- H10D64/021
- H10D84/853
- IPC, 6
- H01L29 423
- H01L29 04
- H01L29 06
- H01L29 165
- H01L29 66
- H01L29 78
- USPC, 1
- 001001000