Forming structure and method for integrated circuit memory

BACKGROUND

Field

0001The present technology relates to integrated circuit memory based on programmable resistance memory, like phase change memory, and other memory technologies in which forming operations are utilized.

Description of Related Art

0002Some types of programmable resistance memory, including phase change memory (PCM), for example, comprise memory material that may not perform optimally until after a forming operation that involves exposure to a forming current. The forming operation can result in stabilized switching characteristics, for example, or better sensing margins.

0003Some of these materials may require forming current of relatively high magnitude. In some configurations, relatively high voltages may be required in the forming operation.

0004Various programmable resistance memory devices that utilize forming pulses include high density arrays of cells organized in a cross-point architecture, such as described in U.S. Pat. No. 6,579,760, entitled SELF-ALIGNED, PROGRAMMABLE PHASE CHANGE MEMORY, issued 17 Jun. 2003, by Lung. Cross-point architectures with memory cells that include a phase change memory element in series with an ovonic threshold switch have been developed as well. Other architectures are utilized, including a variety of 2-dimensional and 3-dimensional array structures.

0005In typical memory architectures, access to the memory cells in the array is made using access lines, such as bit lines and word lines, that are controlled using peripheral circuits implemented with low voltage CMOS transistors, or other technologies designed for high density and low power consumption. The high current or high voltage requirements of a forming operation may damage these peripheral circuits.

0006To avoid such damage, high voltage devices can be incorporated into the peripheral circuits. The high voltage devices, however, can have different device or circuit structures than are required in the peripheral circuits for normal operation of the memory. For example, CMOS transistors which can endure high voltage can be made using thicker gate insulators than are used in the other transistors on the memory. But this complicates the manufacturing process by introducing added steps for high voltage devices.

0007It is desirable to provide a high density memory array configured for forming operations, which can solve the high voltage damage problem and which can be compatible with the manufacturing processes used for the memory array and peripheral circuits.

SUMMARY

0008An integrated circuit technology is described that supports applying forming pulses to memory cells without damage to low-voltage circuitry on the integrated circuit.

0009In examples described herein, an integrated circuit comprises a set of pads that are configured for connection to external circuits, including a pad designated herein a “forming voltage pad.” A memory array on the integrated circuit includes a plurality of memory cells and a plurality of access lines connected in current flow communication to memory cells in the array. A forming voltage rail is coupled to the forming voltage pad. A diode is disposed in current flow communication with the forming voltage rail and with an access line in the plurality of access lines of the memory array. The diode is configured to be forward biased during application of the forming voltage to the forming voltage pad to induce a forming current in the memory cells on the access line. Also, the diode is configured to be reverse biased during application of the reference voltage, such as ground, to the forming voltage pad during utilization of the memory array for memory operations.

0010A set of one or more diodes, including the just mentioned diode, can be included, in which each diode in the set is in current flow communication with the forming voltage rail and a particular access line or group of access lines. In this manner, the forming current can be delivered to sets of memory cells in the array with a number of diodes in parallel.

0011The integrated circuit in some embodiments can include peripheral circuits coupled to pads in the set of pads that are configured to receive signals, such as address signals, clock signals, data signals and control signals. The peripheral circuits can include a control circuit configured to execute memory operations. A power rail is provided on the integrated circuit that is coupled to at least one pad in a power supply subset of the set of pads on the integrated circuit. Power for the integrated circuit memory and the peripheral circuits is distributed using the power rail for the memory operations.

0012In some embodiments, the control circuit is also configured to execute a forming operation in which current through the forming voltage rail is applied to the memory cells via the plurality of access lines, and to execute memory operations in which current through the power rail is applied to memory cells via the plurality of access lines.

0013In one configuration, the control circuit is configured to forward bias the set of one or more diodes when a forming voltage is applied to the forming voltage pad during a forming operation. Conversely, in the memory operations, the control circuit is configured to reverse bias the set of one or more diodes when a reference voltage, such as ground, is applied to the forming voltage pad.

0014For example, the memory array can include a plurality of second access lines coupled in current flow communication with the memory cells. In the forming operation, the control circuit can apply a bias voltage to the plurality of second access lines which results in a forward bias on the set of one or more diodes when a forming voltage is applied to the forming voltage pad. Also, the control circuit can be configured to apply voltages during memory operations that reverse bias the set of one or more diodes when a reference voltage, such as ground, is applied to the forming voltage pad.

0015The technology described herein is applicable to arrays of memory cells that comprise any type of memory cell, such as a programmable resistance memory cell, in which a forming pulse is utilized. In one example, the memory array comprises phase change memory cells. In another example, the memory array comprises memory cells including phase change memory elements in series with ovonic threshold switches.

0016In some embodiments, the memory array on the integrated circuit can include a plurality of banks of memory cells. The integrated circuit can include separate forming voltage pads and separate forming voltage rails for each of the banks, configured as discussed above.

0017In some embodiments, the memory array on the integrated circuit can include a plurality of banks of memory cells. Each bank includes a set of N access lines connected to a set of N diodes. The integrated circuit can include a single forming voltage pad coupled to a set of N forming voltage rails through a selection circuit. The selection circuit has a set of N switches and is used to select access lines, including in some embodiments, one access line at a time in each bank of memory cells during a forming operation.

0018A method utilizing this technology is described. The method includes providing an integrated circuit having a memory array including a plurality of memory cells, a plurality of access lines connected in current flow communication to memory cells in the array, and a forming voltage pad in current flow communication via a diode with access lines in the plurality of access lines. The method includes applying a forming pulse to the forming voltage pad using an external power source, where the forming pulse has a voltage magnitude to forward bias the diode.

0019The method can include connecting the integrated circuit to a forming pulse system, which can be implemented using a test platform utilized in integrated circuit manufacturing and testing. The power supply of the forming pulse system can be used as an external power supply applying the forming pulse to the forming voltage pad on the integrated circuit. In this way, the forming pulse is applied prior to mounting the integrated circuit as a component of an operational device. Also, the method can include mounting the integrated circuit as a component of an operational device after applying the forming pulse, and connecting the forming pulse pad to a constant reference, such as ground, whereby the diode is reverse biased during operation of the device.

0020Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description and the claims, which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

0021<figref idref="DRAWINGS">FIG. 1</figref> is a simplified block diagram of an integrated circuit which includes a memory array and a forming voltage pad, according to one embodiment.

0022<figref idref="DRAWINGS">FIG. 2</figref> is a perspective view of a 3D cross-point array including forming voltage pads and diodes according to one embodiment.

0023<figref idref="DRAWINGS">FIG. 3</figref> is a close-up view of a memory cell <b>120</b> in <figref idref="DRAWINGS">FIG. 2</figref>.

0024<figref idref="DRAWINGS">FIG. 4</figref> illustrates an arrangement of diodes and a forming voltage pad in a level of a 3D memory array embedded in an integrated circuit according to another embodiment.

0025<figref idref="DRAWINGS">FIG. 5</figref> illustrates an embodiment of a diode that can be used in an arrangement like that of <figref idref="DRAWINGS">FIG. 4</figref>.

0026<figref idref="DRAWINGS">FIG. 6</figref> illustrates an arrangement of diodes and a forming voltage pad in a level of a 3D memory array according to yet another embodiment.

0027<figref idref="DRAWINGS">FIG. 7</figref> illustrates connection among a plurality of banks in a memory array according to one embodiment.

0028<figref idref="DRAWINGS">FIG. 8</figref> illustrates connection among a plurality of banks in a memory array according to another embodiment.

0029<figref idref="DRAWINGS">FIG. 9</figref> is a simplified schematic diagram of yet another embodiment, including multiple banks of memory cells.

0030<figref idref="DRAWINGS">FIGS. 10A and 10B</figref> illustrate connection of an integrated circuit with a forming voltage system for executing a forming operation, and an integrated circuit mounted on an operational device, including grounding the forming voltage pad.

0031<figref idref="DRAWINGS">FIG. 11</figref> is a flow chart of a method including a forming operation as described herein.

DETAILED DESCRIPTION

0032A detailed description of embodiments of the present invention is provided with reference to the <figref idref="DRAWINGS">FIGS. 1-11</figref>.

0033<figref idref="DRAWINGS">FIG. 1</figref> shows an integrated circuit <b>1150</b> including a memory array <b>1100</b> comprising memory cells to be subject to a forming operation. The integrated circuit <b>1150</b> includes a set of pads <b>1210</b>-<b>1215</b> in this figure. The pads are structures on the integrated circuit that are configured for connection to external wiring. The set of pads includes signal pads (e.g. <b>1211</b>, <b>1212</b>, <b>1215</b>) configured to carry signals such as addresses, control signals like chip select signals, clock signals, data signals and so on. The set of pads includes a power supply pad <b>1213</b> and a ground pad <b>1214</b> by which power is applied to the integrated circuit for use during normal operation. In some embodiments, there may be a plurality of power supply pads and ground pads.

0034Also, a forming voltage pad <b>1210</b> is included in the set of pads. In some embodiments, there may be a plurality of forming voltage pads as discussed below.

0035The signal pads are coupled to circuitry on the integrated circuit via wiring layers on the device. The power supply pad <b>1213</b> and the ground pad <b>1214</b> are connected to power rails (Vdd rail <b>1223</b>, ground or Vss rail <b>1224</b>) which distribute the supply voltages to the memory array <b>1100</b> and peripheral circuitry, where the “peripheral circuitry” includes the circuits on the device other than the memory array. The power rails are typically patterned metal layers at the top of the plurality of metal layers, or close to the top. Of course, other conductive structures can be used for the power supply rails for distribution of the supply voltages. The peripheral circuitry can include CMOS transistors having breakdown voltages that are less than a forming voltage Vf applied to the forming voltage pad during a forming operation. According to one preferred embodiment of the technology described herein, the forming voltage and forming current are applied to the memory cells without utilization of high-voltage CMOS transistors or other special circuitry is designed to handle the high-voltage or high current required during forming operations. In an advantageous embodiment, the peripheral circuits comprise CMOS transistors, and all of the CMOS transistors in the peripheral circuits have a breakdown voltage that is less than a forming voltage Vf applied to the forming voltage pad and, as a result, manufacturing processes can be simplified. Other embodiments may use high-voltage CMOS transistors in the peripheral circuits, while taking advantage of the improved processes and structures herein.

0036A forming voltage rail <b>1201</b> is connected to the forming voltage pad <b>1210</b> and to the set of diodes <b>1205</b>. The forming voltage rail can be separate from and electrically isolated from the power rails. The forming voltage rail <b>1201</b> provides current flow connection between the forming voltage pad <b>1210</b> and the set of diodes <b>1205</b>. The forming voltage rail <b>1201</b> can comprise a patterned metal line on the same patterned metal layer as the power supply rails in some embodiments. In other embodiments, the forming voltage rail <b>1201</b> can be other types of conductive structures. The forming voltage rail <b>1201</b> in preferred embodiments is connected directly, without intervening active devices, such as high-voltage transistors, between the forming voltage pad <b>1210</b> and the diode or diodes in the set of diodes <b>1205</b>. In the illustrated example, a voltage level detector <b>1202</b> may be coupled to the forming voltage rail or forming voltage pad, which can generate a signal used by the controller <b>1109</b> to initiate a forming operation. Other embodiments do not include a voltage detector coupled to the forming voltage rail or pad.

0037The memory array includes a plurality of access lines <b>1112</b>, <b>1113</b>. In some embodiments, the memory array includes first access lines <b>1113</b>, such as bit lines, and second access lines <b>1112</b>, such as word lines or source lines. In some embodiments, in which the second access lines <b>1112</b> are source lines, the array may include word lines, in addition, for controlling the switch elements in the memory cells.

0038The set of diodes (represented by symbol <b>1205</b>) has one or more members, and includes diodes connected in series with access lines in the plurality of access lines. In this manner, the forming voltage pad <b>1210</b> is connected in current flow communication via the forming voltage rail <b>1201</b>, the set of diodes <b>1205</b>, and the first access lines (e.g. <b>1113</b>) directly to memory cells in the memory array <b>1100</b>, and through the memory cells to the second access lines (e.g. <b>1112</b>). In some embodiments, the set of diodes may be coupled to the second access lines <b>1112</b>, rather than the first access lines <b>1113</b>.

0039In the memory array <b>1100</b>, in one aspect of the technology described here, each memory cell has a switch element such as an ovonic threshold switch, and a memory element such as a phase change memory element connected in current flow communication with the first and second access lines, such as a bit line and a word line. A first access line decoder <b>1103</b> is coupled to and in electrical communication with the plurality of first access lines <b>1113</b>, which are arranged as columns in the memory array <b>1100</b> for reading data from, and writing data to, the memory cells in the memory array <b>1100</b>. The first access line decoder <b>1103</b> can comprise first access line drivers. A second access line decoder <b>1102</b> is coupled to, and in electrical communication with, the plurality of second access lines <b>1112</b>, which are arranged as rows in the memory array <b>1100</b>. The second access line decoder <b>1102</b> can comprise second access line drivers that apply bias voltages to the second access lines <b>1112</b> under control of the controller and of address decoding. Addresses are supplied on bus <b>1105</b> to the first access line decoder <b>1103</b>, and second access line decoder <b>1102</b>. Sense amplifiers and other supporting circuitry such as pre-charge circuits, and so on, along with data-in structures in block <b>1106</b>, are coupled to the first access line decoder <b>1103</b> via the bus <b>1107</b> in this embodiment. These circuit structures can apply bias voltages to the first access lines <b>1113</b> under control of the controller and of address decoding. Data is supplied via the data-in line <b>1121</b> from input/output drivers <b>1123</b> coupled to pads (<b>1215</b>) on the integrated circuit <b>1150</b> or other data sources, to the data-in structures in block <b>1106</b>. Data is supplied via the data-out line <b>1122</b> from the sense amplifiers in block <b>1106</b> to input/output drivers <b>1123</b> on the integrated circuit <b>1150</b>, or to other data destinations internal or external to the integrated circuit <b>1150</b>.

0040A state machine, or other logic in controller <b>1109</b>, controls a biasing arrangement supply circuit <b>1108</b> to execute memory operations, such as write (set and reset) and read operations. The biasing arrangement supply circuit <b>1108</b> is coupled to a Vdd rail <b>1223</b> which is connected to the power supply pad <b>1213</b>, and is coupled to a Vss rail <b>1224</b> which is connected to the ground pad <b>1214</b>. The biasing arrangement supply circuit <b>1108</b> can comprise level shifters or charge pumps to provide bias arrangements with different voltage levels other than Vdd, and deliver the required bias arrangement for the write and read operations to the first access line decoder <b>1103</b> and second access line decoder <b>1102</b>. Also, control circuitry in the controller <b>1109</b> coordinates operation of sense circuitry and the data-in structures in block <b>1106</b>, for read and write operations. The circuitry can be implemented using special purpose logic, a general purpose processor or a combination thereof.

0041The controller <b>1109</b> is configured to execute a forming operation in response to command decoding, voltage level detector signals, or other types of signals, in which current through the forming voltage rail is applied to the memory cells via the plurality of access lines, and to execute memory operations in which current through the power rail is applied to memory cells via the plurality of access lines. During the forming operation, the first access lines <b>1113</b> and the second access lines <b>1112</b> can be biased with a voltage that results in forward biasing of the diodes in the set of diodes <b>1205</b> when the forming voltage pad <b>1210</b> is coupled to a forming voltage Vf, so that the forming pulse causes flow of a forming current pulse through the memory cells. The controller <b>1109</b> can selectively activate separate banks of memory cells in the array, in some embodiments, in order to manage peak current flow through the forming voltage rail.

0042During normal operation of the memory integrated circuit, the controller <b>1109</b> is configured to apply bias voltages to the access lines which reverse biases the diode or diodes in the set of diodes <b>1205</b> when the forming voltage pad <b>1210</b> is coupled to a reference voltage such as ground.

0043<figref idref="DRAWINGS">FIG. 2</figref> is a perspective view of a 3D cross-point array. The 3D cross-point array comprises a plurality of memory cells, including memory cell <b>120</b>, disposed at respective cross-points of a plurality of first access lines, such as bit lines, (e.g. <b>111</b>, <b>112</b>, <b>113</b>, <b>114</b>, <b>115</b>, and <b>116</b>), and a plurality of second access lines, such as word lines (e.g. <b>101</b>, <b>102</b>, <b>103</b>, <b>104</b>, <b>105</b>, and <b>106</b>). Each memory cell has a cell structure that provides a switch function and a data storage function. In this example, the cell has a cell structure including a switch element (e.g. <b>121</b>) and a memory element (e.g. <b>122</b>).

0044In the illustration, a first level in the 3D cross-point array is interposed between a first patterned conductor layer of second access lines, including second access lines (word lines) <b>101</b>, <b>102</b>, and <b>103</b>, and a second patterned conductor layer of first access lines, including first access lines (bit lines) <b>111</b>, <b>112</b>, and <b>113</b>. A second level in the 3D cross-point array is interposed between the second patterned conductor layer of first access lines, including first access lines (bit lines) <b>111</b>, <b>112</b>, and <b>113</b>, and a third patterned conductor layer of second access lines, including second access lines (word lines) <b>104</b>, <b>105</b>, and <b>106</b>. A third level in the 3D cross-point array is interposed between the third patterned conductor layer of second access lines, including second access lines (word lines) <b>104</b>, <b>105</b>, and <b>106</b>, and a fourth patterned conductor layer of first access lines, including first access lines (bit lines) <b>114</b>, <b>115</b>, and <b>116</b>. In this embodiment, the consecutive levels share a patterned conductor layer of first or second access lines, and the memory cells are inverted such that the memory elements can be in contact with or proximal to a second access line and the switch element can be in contact with or proximal to a first access line. In some embodiments, each level can have its own conductive layers of first and second access lines. In some embodiments, the memory cells are not inverted such that the switch elements can be in contact with the first access lines or second access lines. An array implemented in the configuration of <figref idref="DRAWINGS">FIG. 1</figref> can have many levels, and many first access lines and second access lines in each level for formation of very high density memory devices. Other 3D configurations can be implemented.

0045The 3D cross-point array includes access lines coupled to and in electrical communication with a first access line decoder <b>131</b> and a second access line decoder <b>133</b>, where the first and second access line decoders can include drivers and bias voltage selectors to apply bias voltages to selected and unselected first access lines and second access lines in the write or read operation. In this embodiment, the plurality of first access lines is coupled to a first access line decoder <b>131</b> and the plurality of second access lines is coupled to a second access line decoder <b>133</b>. A plurality of diodes (e.g. <b>135</b>, <b>137</b>) is disposed on the circuit between a forming voltage rail and corresponding access lines. As illustrated, each diode has a first terminal and a second terminal. The first terminal of diode <b>135</b> is connected to an access line (bit line) in a first level (e.g., <b>114</b>, <b>115</b>, <b>116</b>). Likewise, the first terminal of diode <b>137</b> is connected to an access line (bit line) in a second level (e.g., <b>111</b>, <b>112</b>, <b>113</b>). The forming voltage pad <b>141</b> is connected to a forming voltage Vf rail <b>142</b>, which connects to second terminals of the diodes (e.g. <b>135</b>, <b>137</b>). The Vf rail <b>142</b> receives a forming voltage Vf during a forming operation. The forming voltage pad is configured to connect to an external power source, and can be independent of on-chip sources.

0046<figref idref="DRAWINGS">FIG. 3</figref> is a close-up view of an example memory cell <b>120</b> in <figref idref="DRAWINGS">FIG. 2</figref>. Memory cell <b>120</b> is in contact with the first access line (bit line) <b>111</b>, and in contact with the second access line (word line) <b>101</b>. Memory cell <b>120</b> includes a switch element <b>121</b> proximal to the first access line (bit line) <b>111</b> at surface <b>151</b>, and a memory element <b>122</b> proximal to the second access line (word line) <b>101</b> at surface <b>152</b>. A first barrier layer <b>123</b> is disposed between the switch element <b>121</b> and the memory element <b>122</b>. A second barrier layer <b>125</b> is disposed between the switch element <b>121</b> and the surface <b>151</b> of the first access line (bit line) <b>111</b>. The switch element <b>121</b>, for example, can be a two-terminal, bi-directional ovonic threshold switch (OTS), which comprises a chalcogenide material.

0047In one example, the switch element <b>121</b> can comprise a layer of chalcogenide selected for use as an ovonic threshold switch, such as As₂Se₃, ZnTe, and GeSe, and has for example a thickness of about 5 nm to about 25 nm, preferably about 15 nm. In some embodiments, the switch element <b>121</b> can comprise a chalcogenide in combination with one or more elements from the group consisting of tellurium (Te), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S) and antimony (Sb).

0048The first barrier layer <b>123</b> can provide adhesion and diffusion barrier functions between the switch element <b>121</b> and the memory element <b>122</b>. The first barrier layer <b>123</b> may have a layer of conductive material with a thickness of about 5 to about 50 nm, preferably about 20 nm. Example materials for the first barrier layer <b>123</b> can be a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiS iN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (WAIN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN). In addition to metal nitrides, first barrier layer <b>123</b> can comprise doped polysilicon, tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), and tantalum oxynitride (TaON).

0049The second barrier layer <b>125</b> can provide adhesion and diffusion barrier functions between the switch element <b>121</b> and the first access line (bit line) <b>111</b>. The second barrier layer <b>125</b> can have the same material as the first barrier layer <b>123</b>, such as TiN. In some embodiments, the second barrier layer <b>125</b> can have a different material than the first barrier layer <b>123</b>. In some embodiments, the second barrier layer <b>125</b> can be eliminated such that the switch element <b>121</b> is in contact with the first access line (bit line) <b>111</b>.

0050The memory element <b>122</b> can comprise a layer of programmable resistance material, for example, a layer of phase change material having a thickness of about 10 nm to about 50 nm, preferably about 30 nm. The thickness of the phase change memory element can be greater than the thickness of switch element <b>121</b> in some embodiments. The memory element <b>122</b> can comprise, for example, Ge₂Sb₂Te₅, in a pure stoichiometric form or in a form with additives or dopants, such as dielectric additives. Phase change materials are capable of being switched between a relatively low resistance state, amorphous phase, and a relatively high resistance state, crystalline phase, by application of energy such as heat or electrical current. In some embodiments, multilevel cells having multiple resistance states can be used.

0051Embodiments of materials for the memory element <b>122</b> can include chalcogenide-based materials and other materials. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IVA of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be for example dielectric doped Ge₂Sb₂Te₅, GeSb₂Te₄and GeSb₄Te₇. In some embodiments, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te or Ga/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are disclosed in Ovshinsky, U.S. Pat. No. 5,687,112 at columns 11-13, which examples are incorporated by reference.

0052The memory element <b>122</b> can comprise a layer of chalcogenide and other phase change materials with additives to modify conductivity, transition temperature, melting temperature, and other properties. Representative additives can include nitrogen (N), silicon (Si), oxygen (O), silicon dioxide (SiOx), silicon nitride (SiN), copper (Cu), silver (Ag), gold (Au), aluminum (Al), aluminum oxide (Al₂O₃), tantalum (Ta), tantalum oxide (TaOx), tantalum nitride (TaN), titanium (Ti), and titanium oxide (TiOx).

0053In some embodiments, other resistive memory structures can be implemented, such as metal-oxide resistive memories, magnetic resistive memories and conducting-bridge resistive memories.

0054The first access lines (bit lines) and the second access lines (word lines) can comprise a variety of metals, metal-like materials and doped semiconductors, or combinations thereof. Embodiments of the first and second access lines can be implemented using one or more layers of materials like tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polysilicon, cobalt silicide (CoSi), Tungsten silicide (WSi), TiN/W/TiN, and other materials. For example, the thicknesses of the first access lines and the second access lines can range from 10 to 100 nm. In other embodiments, the first access lines and the second access lines can be very thin, or much thicker. The material selected for the second access lines is preferably selected for compatibility with the memory element <b>122</b>. Likewise, the material selected for the first access lines is preferably selected for compatibility with the second barrier layer <b>125</b>.

0055In another embodiment, a bottom electrode (not shown) having a smaller contact surface than the surface of the memory element is interposed between the memory element <b>122</b> and the switch element <b>121</b> or between the memory element <b>122</b> and the second access line (word line) <b>101</b>. As such, an increased current density at the contact in the memory element can be achieved. Such bottom electrode may comprise titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), and tungsten nitride (WN). The bottom electrode in contact with the active region of the phase change material is sometimes referred to as a “heater,” reflecting embodiments in which the electrode can have relatively high resistance, and contributes to the Joule heating in the active region of the phase change material.

0056<figref idref="DRAWINGS">FIG. 4</figref> is a schematic illustration of a structure configured as a diode that can be used in circuits as described herein. The illustrated structure can be characterized as a diode-connected NMOS transistor. The diode has an anode <b>450</b> and a cathode <b>451</b>. The drain <b>452</b> and the gate <b>453</b> of the transistor are connected together to act as the anode <b>450</b>. The body <b>454</b> and the source <b>455</b> of the transistor are connected together to act as a cathode <b>451</b>. The sizes of the source <b>455</b>, drain <b>452</b>, a channel within the body <b>454</b>, and the gate <b>453</b>, and the thickness of the gate dielectric, can be configured as suits a particular embodiment, along with other characteristics of the structure. The diodes utilized can also comprise diode-connected PMOS transistors, P+/Nwell diodes which comprise a highly doped p-type contact formed within a n-type well on the substrate, Psub/N+ diodes which comprise a highly doped n-type contact formed in a p-type substrate, and other diode structures.

0057<figref idref="DRAWINGS">FIG. 5</figref> illustrates an arrangement of diodes D<b>1</b>, D<b>2</b>, D<b>3</b> and a forming voltage pad <b>405</b> connected in current flow communication with first access lines <b>411</b>, <b>412</b>, <b>413</b> in a level of a 3D memory array embedded in an integrated circuit according to an embodiment. In the illustration, a plurality of memory cells (e.g. M<b>1</b>˜M<b>9</b>) is disposed between and in current flow communication with a plurality of first access lines (e.g. <b>411</b>, <b>412</b>, <b>413</b>) and a plurality of second access lines (e.g. <b>421</b>, <b>422</b>, <b>423</b>). Each memory cell includes a switch element and a memory element. The plurality of first access lines is coupled to a first access line decoder <b>401</b> through selectors S<b>1</b>, S<b>2</b>, S<b>3</b>, and the plurality of second access lines is coupled to a second access line decoder <b>402</b>. Each of diodes D<b>1</b>, D<b>2</b>, D<b>3</b> has a first terminal and a second terminal, and each first terminal is connected to respective first access lines. A forming voltage pad <b>405</b> is connected via a forming voltage rail to the second terminal of the diode (e.g. D<b>1</b>˜D<b>3</b>). In this embodiment, the first terminal of the diode is a cathode, and the second terminal is an anode.

0058During the forming operation, the gates of the selectors S<b>1</b>, S<b>2</b>, S<b>3</b> are applied a voltage that can be for example about half of the forming voltage. In one example, the forming voltage may be 5 Volts, and the gates of the selectors S<b>1</b>, S<b>2</b>, S<b>3</b> are biased at about 2.5 Volts, well below a breakdown voltage for the selectors. This sets a gate to access line voltage below the VGS breakdown threshold for the transistors. Meanwhile, the second access lines <b>421</b>, <b>422</b>, <b>423</b> are coupled to ground Vss through the second access line decoder <b>402</b>. The voltage on the second access line decoder <b>402</b> will be lower than the forming voltage as a result of the resistive voltage drop across the memory cells. As a result, a forming current flows from the pad <b>405</b> through the diodes D<b>1</b>, D<b>2</b>, D<b>3</b>, to the first access lines <b>411</b>-<b>412</b>, to the memory cells M<b>1</b>-M<b>9</b>, and to the second access lines <b>421</b>-<b>423</b> to ground without flowing through switching devices and without causing breakdown voltage stress on any switching devices.

0059During the write and read operation, the forming voltage pad <b>405</b> receives a reference voltage, such a ground Vss, so that the diodes D<b>1</b>, D<b>2</b>, D<b>3</b> are reverse biased.

0060<figref idref="DRAWINGS">FIG. 6</figref> illustrates an arrangement of diodes D<b>4</b>, D<b>5</b>, D<b>6</b> and a forming voltage pad in a level of a 3D memory array according to yet another embodiment. The arrangement of <figref idref="DRAWINGS">FIG. 6</figref> differs from that of <figref idref="DRAWINGS">FIG. 4</figref> in that the diodes D<b>4</b>, D<b>5</b>, D<b>6</b> are reversely connected. In this embodiment, the first terminal of the diode is an anode, and the second terminal is a cathode.

0061During the forming operation, the forming voltage pad <b>405</b> is supplied with a negative forming voltage Vf. Even though the diodes D<b>4</b>, D<b>5</b>, D<b>6</b> are reverse connected, the diodes D<b>4</b>, D<b>5</b>, D<b>6</b> remain forward biased because the forming voltage has a lower potential energy relative to a voltage applied through the second access lines <b>421</b>, <b>422</b>, <b>423</b>, which can be set at a reference voltage Vss through the second access line decoder <b>402</b>.

0062During the write and read operations, the forming voltage pad <b>405</b> receives a reference voltage such as Vdd outputted from the pad power supply circuit such that the diodes D<b>1</b>, D<b>2</b>, D<b>3</b> are reverse biased.

0063<figref idref="DRAWINGS">FIG. 7</figref> illustrates connection among a plurality of banks in a memory array according to one embodiment. The plurality of memory cells in the memory array is divided into a plurality of banks. The plurality of banks comprise their own first access line decoders (e.g. <b>401</b>-<b>1</b>, <b>401</b>-<b>2</b>, <b>401</b>-<b>3</b>, <b>401</b>-<b>4</b>) and second access line decoders (e.g. <b>402</b>-<b>1</b>, <b>402</b>-<b>2</b>, <b>402</b>-<b>3</b>, <b>402</b>-<b>4</b>). In this illustrated configuration, each of the diodes is connected to the respective first access lines, and connected together to a forming voltage pad <b>405</b>. The forming voltage pad <b>405</b> is supplied to the forming voltage Vf to forward bias the diodes (e.g. D<b>01</b>˜D<b>12</b>) in the forming operation, and is supplied to the reference voltage Vss to reverse bias the diodes (e.g. D<b>01</b>˜D<b>12</b>) in the write and read operations.

0064<figref idref="DRAWINGS">FIG. 8</figref> illustrates connection among a plurality of banks in a memory array according to another embodiment. Compared to <figref idref="DRAWINGS">FIG. 7</figref>, <figref idref="DRAWINGS">FIG. 8</figref> differs in that each bank has a separate forming voltage pad (e.g. <b>405</b>-<b>1</b>, <b>405</b>-<b>2</b>, <b>405</b>-<b>3</b>, <b>405</b>-<b>4</b>) and separate forming voltage rail. The forming voltage pads can have their respective pad power supply circuits coupled to an external power source through the Vf rail. In some embodiments, the forming voltage pads can share a common pad power supply circuit.

0065<figref idref="DRAWINGS">FIG. 9</figref> is a simplified schematic of a memory array that includes a plurality of banks of memory cells, including banks B<b>0</b>, B<b>1</b> and B<b>2</b>, in this example. A memory array as shown in <figref idref="DRAWINGS">FIG. 9</figref> can be part of an integrated circuit as shown in <figref idref="DRAWINGS">FIG. 1</figref>, for example. The banks can be configured to lie on different levels of a 3D memory array, or distributed in different configurations as suits a particular implementation.

0066Each bank includes a plurality of word lines and a plurality of bit lines both of which are connected in current flow communication with memory cells in the bank, in this example. In this simplified schematic, each bank includes three word lines and the three bit lines. Thus, each bank includes a set of N access lines, configured as one of bit lines and word lines, where N is equal to three in this example. Of course, N can be any practical number.

0067In the illustration, bank B<b>0</b> includes bit lines BL<b>0</b>-<b>0</b>, BL<b>0</b>-<b>1</b> and BL<b>0</b>-<b>2</b>, and word lines WL<b>0</b>-<b>0</b>, WL<b>0</b>-<b>1</b> and WL<b>0</b>-<b>2</b>. Bank B<b>1</b> includes bit lines BL<b>1</b>-<b>0</b>, BL<b>1</b>-<b>1</b> and BL<b>1</b>-<b>2</b>, and word lines WL<b>1</b>-<b>0</b>, WL<b>1</b>-<b>1</b> and WL<b>1</b>-<b>2</b>. Bank B<b>2</b> includes bit lines BL<b>2</b>-<b>0</b>, BL<b>2</b>-<b>1</b> and BL<b>2</b>-<b>2</b>, and word lines WL<b>2</b>-<b>0</b>, WL<b>2</b>-<b>1</b> and WL<b>2</b>-<b>2</b>. The bit lines are connected to read and write circuits <b>910</b>-<b>0</b>, <b>910</b>-<b>1</b> and <b>910</b>-<b>2</b> in each bank. The word lines are connected to word line drivers <b>912</b>-<b>0</b>, <b>912</b>-<b>1</b> and <b>912</b>-<b>2</b> in each bank. Column select switches <b>900</b>, <b>901</b> and <b>902</b> in each bank are configured to connect selected bit lines to the read and write circuits <b>910</b>-<b>0</b>, <b>910</b>-<b>1</b> and <b>910</b>-<b>2</b>.

0068As illustrated, there is a plurality of sets of diodes. Each set of diodes in the plurality of sets is coupled to a corresponding bank in the plurality of banks. A set of diodes D<b>0</b>-<b>0</b>, D<b>0</b>-<b>1</b> and D<b>0</b>-<b>2</b> is coupled to bank B<b>0</b>. A set of diodes D<b>1</b>-<b>0</b>, D<b>1</b>-<b>1</b> and D<b>1</b>-<b>2</b> is coupled to bank B<b>1</b>. A set of diodes D<b>2</b>-<b>0</b>, D<b>2</b>-<b>1</b> and D<b>2</b>-<b>2</b> is coupled to bank B<b>2</b>. Each set of diodes has N members, which in this example is three members. The members in each of the set of diodes are connected in current flow communication with corresponding ones of the N access lines in its corresponding bank. Thus, for bank B<b>0</b>, diode D<b>0</b>-<b>0</b> is connected in current flow communication with its corresponding bit line BL<b>0</b>-<b>0</b>; diode D<b>0</b>-<b>1</b> is connected in current flow communication with its corresponding bit line BL<b>0</b>-<b>1</b>; and diode D<b>0</b>-<b>2</b> is connected in current flow communication with its corresponding bit line BL<b>0</b>-<b>2</b>.

0069In this embodiment, there is a set of forming voltage rails having N members, which in this example includes forming voltage rails FR-<b>0</b>, FR-<b>1</b> and FR-<b>2</b>. As shown, the N members of each set of diodes are connected in current flow communication with corresponding ones of the N members of the set of forming voltage rails. Thus, forming voltage rail FR-<b>0</b> is connected in current flow communication with (and corresponds to) diode D<b>0</b>-<b>0</b> which is coupled with bit line BL<b>0</b>-<b>0</b> in bank B<b>0</b>, with diode D<b>1</b>-<b>0</b> which is coupled with bit line BL<b>1</b>-<b>0</b> in bank B<b>1</b> and with diode D<b>2</b>-<b>0</b> which is coupled with bit line BL<b>2</b>-<b>0</b> in bank B<b>2</b>. Forming voltage rail FR-<b>1</b> is connected in current flow communication with diode D<b>0</b>-<b>1</b> which is coupled with bit line BL<b>0</b>-<b>1</b> in bank B<b>0</b>, with diode D<b>1</b>-<b>1</b> which is coupled with bit line BL<b>1</b>-<b>1</b> in bank B<b>1</b> and with diode D<b>2</b>-<b>1</b> which is coupled with bit line BL<b>2</b>-<b>1</b> in bank B<b>2</b>. Forming voltage rail FR-<b>2</b> is connected in current flow communication with diode D<b>0</b>-<b>2</b> which is coupled with bit line BL<b>0</b>-<b>2</b> in bank B<b>0</b>, with diode D<b>1</b>-<b>2</b> which is coupled with bit line BL<b>1</b>-<b>2</b> in bank B<b>1</b> and with diode D<b>2</b>-<b>2</b> which is coupled with bit line BL<b>2</b>-<b>2</b> in bank B<b>2</b>.

0070In this embodiment, there is a single forming voltage pad <b>405</b>. The forming voltage pad <b>405</b> is coupled to a selection circuit including a set of switches having N members, where switches in the set have a first terminal in current flow communication with the forming voltage pad <b>405</b>, and a second terminal in current flow communication with a corresponding forming voltage rail in the set of forming voltage rails. Thus, switch S<b>0</b> is coupled between the forming voltage pad <b>405</b>, and forming voltage rail FR-<b>0</b>. Switch S<b>1</b> is coupled between the forming voltage pad <b>405</b>, and forming voltage rail FR-<b>1</b>. Switch S<b>2</b> is coupled between the forming voltage pad <b>405</b>, and forming voltage rail FR-<b>2</b>. Control signals CNTL generated by control circuitry on the integrated circuit, or by off-chip test platforms for example, cause the switches in the selection circuit to electrically connect and disconnect the forming voltage pad <b>405</b> from their corresponding forming voltage rails in response to a control sequence. The control circuit on the integrated circuit, in some embodiments, is configured to execute a forming operation including the control sequence, including providing the control signal CNTL. The control sequence can include connecting in sequence each of the forming voltage rails in the set of forming voltage rails to memory cells via the corresponding ones of the N access lines. This enables a sequence for example, which applies a forming voltage in coordination with the word line drivers and the read and write circuitry to one cell in each bank at a time. Of course other configurations can be implemented.

0071In one example, during a forming operation, a high voltage such as 5 V is applied to the forming pad <b>405</b>. A control voltage is applied to the column select switches (<b>900</b>, <b>901</b>, <b>902</b>) on each of the bit lines that is less than the breakdown voltage of the device, such as 2.5 V, thereby avoiding device stress. A ground voltage is applied to a selected word line in each bank as determined by the word line drivers <b>912</b>-<b>0</b>, <b>912</b>-<b>1</b>, <b>912</b>-<b>2</b>. Unselected word lines receive an intermediate voltage, such as 2.5 V to improve current distribution uniformity. The plurality of switches S<b>0</b>-S<b>2</b> act as a selection circuit that is used for column decoding on the bit lines, thereby selecting a single bit line at a time in each bank. Thus, one of the switches S<b>0</b>-S<b>2</b> is turned on at a time, while the other two are turned off for each step of the control sequence.

0072Of course other embodiments may select more than one cell at a time in each bank.

0073During normal operation of the memory device, the forming voltage pad is connected to ground and the switches are enabled to pass ground voltage to the forming voltage rails.

0074In advantageous embodiments, the column select transistors in the column decoder circuit on the bit lines are implemented using transistors having characteristics manufacturable along with the peripheral circuits, which comprise devices that have a breakdown voltage less than the forming voltage. Likewise, the switches S<b>0</b>-S<b>2</b> in the selector circuit are implemented in advantageous embodiments using transistors having characteristics manufacturable along with the peripheral circuits, which comprise devices that have low breakdown voltages less than the forming voltage.

0075<figref idref="DRAWINGS">FIG. 10A</figref> illustrates a configuration in which an integrated circuit memory <b>500</b>, such as that shown in <figref idref="DRAWINGS">FIG. 1</figref>, is coupled to a test platform <b>501</b> that is used as a forming pulse system to apply forming pulses as described above. The test platform <b>501</b> can include a jig <b>502</b> or other structure designed for connection to contact pads or pins on the integrated circuit memory <b>500</b>. A power supply in the test platform <b>501</b> can be used to generate a forming voltage Vf, and apply that voltage on line <b>506</b> to the forming voltage pad <b>505</b> on the integrated circuit memory <b>500</b>, directly using a probe or via a pin on a packaged version of the integrated circuit memory <b>500</b> for example.

0076<figref idref="DRAWINGS">FIG. 10B</figref> illustrates the integrated circuit memory <b>500</b> mounted on an operational device <b>600</b>. The operational device <b>600</b> can comprise, for a generic example, a printed circuit board with a variety of other circuits in integrated circuits mounted thereon, for example. The operational device <b>600</b> includes a power supply <b>601</b> that applies a power supply voltage Vdd and a ground voltage GND on lines <b>602</b> and <b>603</b>, respectively, to power supply and ground pads on the integrated circuit memory <b>500</b>. In this operational device <b>600</b>, a reference voltage such as ground GND is applied on line <b>604</b> to the forming voltage pad <b>505</b> when it is mounted on the operational device.

0077A method for performing a forming operation on integrated circuit memory is provided. <figref idref="DRAWINGS">FIG. 11</figref> is a simplified flowchart illustrating steps in the method. The first step in the illustrated flowchart is providing an integrated circuit memory, such as that illustrated in <figref idref="DRAWINGS">FIG. 1</figref>. (<b>700</b>). The integrated circuit memory is mounted on a test platform, or other forming pulse system (<b>701</b>). A power supply on the test platform is used to apply a forming voltage Vf to the forming voltage pad on the integrated circuit (<b>702</b>). The forming operation is executed by bias in the access lines as required in order to deliver forming pulses to all of the memory cells in the array, such as in a bank-by-bank sequence (<b>703</b>). After the forming operation, the test platform can execute other testing operations in some embodiments, and packaging of the integrated circuit can be completed if it has not been completed prior to mounting on the test platform (<b>704</b>). Thereafter, the integrated circuit is mounted on an operational device (<b>705</b>). The forming voltage pad is tied on the operational device to ground or another reference voltage necessary to maintain the diodes on the integrated circuit memory reverse biased during normal operations (<b>706</b>).

0078For the purposes of the flowchart, the steps are illustrated in a sequence. In some embodiments, some of the steps may be performed in a different sequence than that shown in the flowchart.

0079The technology described herein is applicable for integrated circuit memory based on memory cells including phase change memory elements in series with ovonic threshold switches, which can require a forming operation. Because high voltage is required for forming operations on devices like this, standard CMOS processes cannot be relied upon unless modified to support high voltage devices. As described herein, the technology is provided enabling the application of a forming operation compatible with standard CMOS processes.

0080While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.