Coordinating multiple real-time functions of a peripheral over a synchronous serial bus

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FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT

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APPENDICES

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FIELD

0004Related fields include dedicated baseband/transceiver processors (B/TRs) and their associated hardware, and more particularly handling multiple component functions, which may be simultaneous or otherwise time-critical, over a synchronous serial bus.

BRIEF DESCRIPTION OF DRAWINGS

0005<figref idref="DRAWINGS">FIG. 1</figref> is a diagram illustrating an embodiment of a block diagram for a computing system including a multicore processor.

0006<figref idref="DRAWINGS">FIGS. 2A-C</figref> illustrate examples of multiple time-critical actions on peripherals sharing a serial bus.

0007<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram of an exemplary dedicated microcontroller controlling an associated peripheral over a synchronous serial bus (SSB).

0008<figref idref="DRAWINGS">FIGS. 4A-E</figref> are graphical representations of exemplary telegrams generated by a microcontroller, processed by a time protocol engine, and sent to a peripheral.

0009<figref idref="DRAWINGS">FIG. 5</figref> is a flowchart of an example of telegram processing in a time protocol engine and subsequent actions at the receiving peripheral.

0010<figref idref="DRAWINGS">FIGS. 6A-B</figref> are schematic timing diagrams illustrating how the pre-loading process may enable closely-timed execution of multiple time-critical functions sent through a serial bus.

DETAILED DESCRIPTION

0011In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etcetera in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present disclosure. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven't been described in detail in order to avoid unnecessarily obscuring the present disclosure.

0012Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that may perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatus', and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a ‘green technology’ future balanced with performance considerations.

0013As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth preferences are met for optimal component operation. Furthermore, different market segments demand different aspects of interconnect architectures to suit the market's needs. For example, servers intend higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Yet, it's a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Below, a number of interconnects are discussed, which would potentially benefit from aspects of the disclosure described herein.

0014Note that the apparatus, methods, and systems described above may be implemented in any electronic device or system as aforementioned. As specific illustrations, the figures below provide exemplary systems for utilizing the invention as described herein. As the systems below are described in more detail, a number of different interconnects are disclosed, described, and revisited from the discussion above. And as is readily apparent, the advances described above may be applied to any of those interconnects, fabrics, or architectures.

0015Referring to <figref idref="DRAWINGS">FIG. 1</figref>, an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor <b>100</b> includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor <b>100</b>, in one embodiment, includes at least two cores—core <b>101</b> and <b>102</b>, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor <b>100</b> may include any number of processing elements that may be asymmetric or symmetric.

0016In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

0017A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.

0018Physical processor <b>100</b>, as illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, includes two cores—core <b>101</b> and <b>102</b>. Here, core <b>101</b> and <b>102</b> are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core <b>101</b> includes an out-of-order processor core, while core <b>102</b> includes an in-order processor core. However, cores <b>101</b> and <b>102</b> may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core <b>101</b> are described in further detail below, as the units in core <b>102</b> operate in a similar manner in the depicted embodiment.

0019As depicted, core <b>101</b> includes two hardware threads <b>101</b><i>a </i>and <b>101</b><i>b</i>, which may also be referred to as hardware thread slots <b>101</b><i>a </i>and <b>101</b><i>b</i>. Therefore, software entities, such as an operating system, in one embodiment potentially view processor <b>100</b> as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers <b>101</b><i>a</i>, a second thread is associated with architecture state registers <b>101</b><i>b</i>, a third thread may be associated with architecture state registers <b>102</b><i>a</i>, and a fourth thread may be associated with architecture state registers <b>102</b><i>b</i>. Here, each of the architecture state registers (<b>101</b><i>a</i>, <b>101</b><i>b</i>, <b>102</b><i>a</i>, and <b>102</b><i>b</i>) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers <b>101</b><i>a </i>are replicated in architecture state registers <b>101</b><i>b</i>, so individual architecture states/contexts are capable of being stored for logical processor <b>101</b><i>a </i>and logical processor <b>101</b><i>b</i>. In core <b>101</b>, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block <b>130</b> may also be replicated for threads <b>101</b><i>a </i>and <b>101</b><i>b</i>. Some resources, such as re-order buffers in reorder/retirement unit <b>135</b>, ILTB <b>120</b>, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB <b>115</b>, execution unit(s) <b>140</b>, and portions of out-of-order unit <b>135</b> are potentially fully shared.

0020Processor <b>100</b> often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In <figref idref="DRAWINGS">FIG. 1</figref>, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core <b>101</b> includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer <b>120</b> to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) <b>120</b> to store address translation entries for instructions.

0021Core <b>101</b> further includes decode module <b>125</b> coupled to fetch unit <b>120</b> to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots <b>101</b><i>a</i>, <b>101</b><i>b</i>, respectively. Usually core <b>101</b> is associated with a first ISA, which defines/specifies instructions executable on processor <b>100</b>. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic <b>125</b> includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders <b>125</b>, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders <b>125</b>, the architecture or core <b>101</b> takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders <b>126</b>, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders <b>126</b> recognize a second ISA (either a subset of the first ISA or a distinct ISA).

0022In one example, allocator and renamer block <b>130</b> includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads <b>101</b><i>a </i>and <b>101</b><i>b </i>are potentially capable of out-of-order execution, where allocator and renamer block <b>130</b> also reserves other resources, such as reorder buffers to track instruction results. Allocator and renamer block <b>130</b> may also include a register renamer to rename program/instruction reference registers to other registers internal to processor <b>100</b>. Reorder/retirement unit <b>135</b> includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

0023Scheduler and execution unit(s) block <b>140</b>, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

0024Lower level data cache and data translation buffer (D-TLB) <b>150</b> are coupled to execution unit(s) <b>140</b>. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.

0025Here, cores <b>101</b> and <b>102</b> share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface <b>110</b>. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache is a last-level data cache—last cache in the memory hierarchy on processor <b>100</b>—such as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder <b>125</b> to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).

0026In the depicted configuration, processor <b>100</b> also includes on-chip interface module <b>110</b>.

0027Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor <b>100</b>. In this scenario, on-chip interface <b>110</b> is to communicate with devices external to processor <b>100</b>, such as system memory <b>175</b>, a chipset (often including a memory controller hub to connect to memory <b>175</b> and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus <b>105</b> may include any known interconnect, such as a multi-drop bus, point-to-point interconnect, serial interconnect, parallel bus, coherent (e.g. cache coherent) bus, layered protocol architecture, differential bus, or a GTL bus.

0028Memory <b>175</b> may be dedicated to processor <b>100</b> or shared with other devices in a system. Common examples of types of memory <b>175</b> include DRAM, SRAM, non-volatile memory, and other known storage devices. Note that device <b>180</b> may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

0029Recently however, as more logic and devices are being integrated on a single die, such as

0030SOC, each of these devices may be incorporated on processor <b>100</b>. For example in one embodiment, a memory controller hub is on the same package and/or die with processor <b>100</b>. Here, a portion of the core (an on-core portion) <b>110</b> includes one or more controller(s) for interfacing with other devices such as memory <b>175</b> or a graphics device <b>180</b>. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface <b>110</b> includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link <b>105</b> for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory <b>175</b>, graphics processor <b>180</b>, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

0031In one embodiment, processor <b>100</b> is capable of executing a compiler, optimization, and/or translator code <b>177</b> to compile, translate, and/or optimize application code <b>176</b> to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

0032Larger compilers often include multiple phases, but most often these phases are included within two general phases: (1) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (2) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etcetera in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. In some implementations, during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.

0033Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (1) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (3) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (4) a combination thereof.

0034Systems and methods of the present disclosure include transmitter devices. The transmitter devices include a high-speed driver domain having a low-dropout regulator. The low-dropout regulator reduces a voltage level from an input voltage source to the high-speed driver domain. In addition, the transmitter devices include a low-speed driver domain. The low-speed driver domain includes a pre-driver which reduces a voltage level from an input voltage source to the low-speed driver domain.

0035New electronic devices are under constant market pressure to provide more and more versatility in a smaller space while using less power. For example, a smartphone that fits easily in the hand may be equipped to transmit and receive cellular signals, WiFi signals, GPS signals, short-range signals, and FM radio signals. Each of these transceiver modules may need to be connected to the application processor. Preferably, enough physical space is allocated to the interconnections to produce a satisfactory signal quality. Smartphones and tablets, as portable wireless devices, benefit greatly from reducing power consumption and thereby extending battery life.

0036Each type of signal may be transmitted and received at more than one rate. For example, each signal may include both low-rate traffic (e.g., audio) and high-rate traffic (e.g., WiFi). In many applications, a low-rate link is intended to be available at all times. Traditionally, separate bidirectional buses have been provided for the different data rates. For example, in some multiple communications (“multi-com”) chipsets and system-on-chip (“SoC”) devices, industry standard Synchronous Backplane Interconnect (SBI), Inter-Integrated Circuit (I²C) or Universal Asynchronous Receiver/Transmitter (UART) buses are provided for low-rate traffic, and either standard Peripheral Component Interconnect Express (PCIe) or Universal Serial Bus (USBx) buses or proprietary buses are provided for high-rate traffic. Pairs of these low-rate and high-rate bidirectional buses may connect multiple cores and other chipset components on SoCs.

0037Alternative shared-bus embodiments of the solutions are applicable not only to multi-com chips but also to ARM-based SoCs and system-level external bus interfaces such as PCIe, Secure Digital Input/Output (SDIO), Mobile Industry Processor Interface Low Latency Interface (MIPI LLI), etc. Various embodiments save power, improve cost structure of cost-sensitive devices, reduce footprint, improve connectivity, and enable a wider range of form factor designs.

0038Electronic devices that perform some or all of their functions by digital processing may include two or more physically separate microcontrollers, with each microcontroller controlling one or more peripherals. A microcontroller includes at least: (1) an arithmetic logic unit; (2) program-count, stack-pointer, and status registers; (3) temporary data-storage registers for non-final computation results; and (4) message decoder, microcontroller control logic, and one or more handle resets or interrupts.

0039The terms “microcontroller” and “peripheral” originally referred to hardware residing in separate pieces of equipment, such as a desktop computer tower and its printer. The meanings of the terms have broadened with the evolution and miniaturization of technology. They now may also refer to connected boards in the same piece of equipment (e.g., motherboard and sound card); chips on the same board; or, most recently, components on the same chip, for example in system-on-chip (SoC) hardware. In some systems, two or more microcontrollers and/or two or more peripherals may be located on a single chip.

0040The use of multiple microcontrollers can confer several advantages. Multiple microcontrollers can control different peripherals, or different parts of the same peripheral, simultaneously. In some cases, the parallel processing made possible by separate microcontrollers increases the speed of computation-intensive tasks (e.g., graphic animation) or facilitates multitasking. In other cases, a safety-critical or otherwise highly regulated function may be given its own dedicated microcontroller, physically separated from the application processor, which helps prevent changes in other functions (executed on one or more other microcontrollers) from potentially affecting processes executed by the dedicated microcontroller. Thus the device is subject to regulatory re-certification only when the firmware on the dedicated microcontroller(s) is changed, rather than every time any of its firmware is changed.

0041One application of a dedicated microcontroller is to perform time-critical actions. Time-critical actions intend for a microcontroller or peripherals to respond to certain incoming signals within a predetermined interval of time, and/or to produce certain outgoing signals at predetermined intervals (e.g., every 10 minutes) or at predetermined external (“real”) times (e.g., at 5 PM local time). Time-critical processes may benefit from running on a specialized real-time operating system (RTOS) rather than the type of general-purpose operating system used in application processors (e.g., iOS® or Android®).

0042A dedicated microcontroller may run an RTOS tailored to its specific actions. The commands for executing the actions may be transmitted from the dedicated microcontroller to the peripheral over a synchronous serial bus (SSB). Interface standards for such buses include, but are not limited to, Inter-Integrated Circuit (I²C), Serial Peripheral Interface (SPI), Series Voltage Identification (SVID), and Radio Frequency Front-End (RFFE). The dedicated microcontroller sends command signals over the SSB that cause programming (overwriting) of one or more registers in the peripheral. The command signals include structured telegrams that may include a “type” designation, a “header” (e.g., the address of the register to be programmed), and a “payload” (the data to be put into the register). Typically, function-control registers are overwritten with the incoming payload immediately after the peripheral receives the telegram, and the changed register values trigger an immediate action of the peripheral.

0043Some systems intend for multiple time-critical actions to be performed simultaneously or very nearly so (e.g., within a few microseconds) on one or more peripherals. Sending the messages for such “overlapping” actions in parallel would be straightforward with a sufficient number of interconnects between the dedicated microcontroller and the affected peripheral(s). However, space constraints or other priorities may limit the number of interconnects. For example, the number of balls in a ball-grid array (BGA) is limited by the size of the overlying component and the spacing expected to avoid crosstalk. In some devices, a dedicated microcontroller may control several (or all) of its peripherals through a single shared SSB. When multiple time-critical actions overlap, the telegrams may still be sent serially through the bus. If the timed telegrams become too numerous and/or their intended real times are too closely spaced, one or more real-time constraints may be violated or the overloaded serial bus may stall. Yet at other times the serial bus may be idle.

0044In summary, the constraints on time-critical actions may come into conflict (1) at times that two or more time-critical actions are intended to start nearly simultaneously, (2) when telegrams, each taking a finite time to transmit, may be sent sequentially down a single serial bus, and (3) at times that telegrams for time-critical actions may be sent just before the actions are to be performed, because the changes take effect immediately after a telegram is received at the peripheral. Relaxation of constraint (1) may degrade device performance. Relaxation of constraint (2) may involve more interconnects (e.g., BGA balls) and sufficient space for them, which may make the device too expensive or force it into an undesirable form factor. However, constraint (3) is often not a design constraint, but merely a default behavior that may be changeable without a negative impact on the system. If telegrams for time-critical tasks could be sent in advance (for instance, while the SSB is otherwise idle) and then prevented from taking effect until the intended time of the task, multiple time-critical tasks could be triggered within a very short time interval from within the peripheral(s) without requiring further signal traffic on the SSB.

0045Most of the following examples in this Description relate to dedicated microcontrollers for RF transmission and reception. In some countries, including the US, RF transmission is heavily regulated; RF-emitting devices may receive certification involving rigorous testing, and may be subject to re-certification after any change that could affect the RF emissions. In addition, many RF devices may continue transmitting and/or receiving signals while simultaneously performing other tasks such as responding to user input. However, the described techniques may be used where any RTOS microcontroller controls one or more peripherals.

0046<figref idref="DRAWINGS">FIGS. 2A-C</figref> illustrate examples of multiple time-critical actions on peripherals sharing a serial bus. <figref idref="DRAWINGS">FIG. 2A</figref> is a simplified block diagram of a portion of a telecommunications device. Some or all of the blocks may be integrated modules fabricated on the same chip, or they may be separate chips interconnected on a circuit board.

0047Application processor <b>202</b> runs an application operating system. The communication hardware, however, is controlled by baseband processor <b>204</b>. This leaves the manufacturer free to change many aspects of application processor <b>202</b>; as long as no changes are made to baseband processor <b>204</b>, regulatory re-certification is not an issue. In some embodiments, baseband processor <b>204</b> may run some type of RTOS.

0048Baseband processor <b>204</b> controls transceiver <b>206</b>, amplifier <b>208</b>, antenna <b>209</b>, and any other suitable communication hardware through serial bus <b>224</b>. In some embodiments, baseband processor <b>204</b> may control hardware for multiple communication channels. As well as transceiver <b>206</b>, amplifier <b>208</b>, and antenna <b>209</b>, one or more additional transceivers <b>216</b>, their amplifiers <b>218</b>, and their antennas <b>219</b> may be controlled by a baseband processor <b>204</b> through serial bus <b>224</b>. In these configurations, baseband processor <b>204</b> may be referred to as a “bus master” or a “system controller,” and the devices controlled by baseband processor <b>204</b> through serial bus <b>224</b>, such as transceivers <b>206</b> and <b>216</b>, may be referred to as a “bus client” or “peripheral.” In some embodiments, application processor <b>202</b> and one or more auxiliary processors such as baseband processor <b>204</b> may be powered by a shared power source <b>222</b> and a shared power-management module <b>212</b>.

0049Often, multiple actions may be performed simultaneously, or very close in time (e.g., a few microseconds) by low-level components of one or more multiple peripherals sharing a single serial bus as illustrated in <figref idref="DRAWINGS">FIG. 2A</figref>. For example, a setting change on a power amplifier's input switch may need to be closely followed (or closely preceded) by a DC/DC converter ramping up the amplifier gain.

0050<figref idref="DRAWINGS">FIG. 2B</figref> is a timing diagram illustrating an example of such “time-critical” actions, the effectiveness of which depends on execution in a desired order, at a highly accurate time or within a very precise time interval. Pulse <b>237</b> in system-controller swim-lane <b>207</b> represents a trigger signal received by the system controller; for example, a command from the application processor as part of the running of the application, or a signal from a clock or timer that it is time to perform a scheduled action. The switching action in peripheral component swim-lane <b>208</b>.<b>1</b> is intended to occur at a deadline time T_d1coincident with the falling edge T₀of pulse <b>237</b>, while the ramping action in peripheral component swim-lane <b>208</b>.<b>2</b> is intended to commence at a deadline time T_d2, which is later than the falling edge T₀of pulse <b>237</b> by a predetermined “time-to-strobe” TTS₂. Note: for the purposes of this document, the “deadline time” of a time-critical action is the exact time when the action is intended to be executed; the action will be unsuccessful if executed either later or earlier.

0051The actions may be executed at the peripherals by programming, or “writing to,” function-control registers in the power amplifier and the DC/DC converter. Commonly, function-control registers execute actions immediately after being programmed. Therefore, one approach has been for the system controller/baseband processor to delay sending the messages to the peripheral to until just before the deadline time; the message only has time to travel through the bus and be written to the peripheral's function control register before the deadline time. This “just in time” approach may encounter, among others, the following two challenges:

0052First, if many devices are being controlled by the same serial bus, the bus may experience some high-traffic times and some idle times. If the deadline time occurs in a period of high traffic, the system-controller preferably determines how the message for the time-critical action can be sent within an extremely narrow window of time without compromising other functions.

0053Second, if messages may travel through the bus in series, a minimum is imposed on the time interval between two consecutive actions by the amount of time it takes the system controller to transmit the second action to the bus. <figref idref="DRAWINGS">FIG. 2C</figref> is a timing diagram illustrating this effect. The second line, “SCLK,” illustrates ticks <b>252</b> of the bus clock. For visibility, the tick length is exaggerated; as of this writing, bus clocks may operate at frequencies between several kHz and several hundred MHz. The top line, “SDATA,” illustrates messages transmitted to the bus by the system controller.

0054In this example, the messages are single telegrams including, possibly among other things, the address of the peripheral assigned to perform the action (P<b>1</b> or P<b>2</b>), and the identifier for the action (A<b>1</b> or A<b>2</b>). The telegram length <b>262</b>, <b>272</b> is proportional to the number of clock-ticks the system controller takes to transmit the telegram to the serial bus. A<b>1</b> is a time-critical action with deadline time T_d1; A<b>2</b> is a time-critical action with deadline time T_d2. The first telegram of length <b>262</b> is sent “just in time,” so that it is received at the first peripheral (Peri-<b>1</b>) at time <b>264</b> and written to the function control register at time <b>266</b>, which immediately (at time <b>268</b>) executes action A<b>1</b> at deadline time T_d1. Now, though, the second telegram has a length <b>272</b>, and, because of the serial nature of the bus, the earliest it can begin to be transmitted is directly after the end of the first telegram of length <b>262</b>. Therefore, the earliest time that action A<b>2</b> can be received and executed is time <b>274</b>, which is later than T_d2by a timing error ERR. The length <b>272</b> of the second message thus corresponds to a minimum time-to-strobe ΔT_min. Actions sent “just in time” directly to function control registers can never be executed closer together than ΔT_min.

0055<figref idref="DRAWINGS">FIG. 3</figref> is a block diagram of an exemplary dedicated microcontroller controlling an associated peripheral over a synchronous serial bus (SSB). SSB <b>324</b> links system controller (or “serial bus master” <b>302</b> to peripheral (or “serial bus client”) <b>352</b>. For simplicity, only one peripheral <b>352</b> is illustrated, but in practice an SSB <b>324</b> may link a single system controller <b>302</b> to any practical number of peripherals <b>352</b>. System controller <b>302</b> includes a source of a clock signal C (the dotted-line arrows) which functions as the bus clock and the timer clock. A clock signal C may originate from a clock <b>304</b> inside system controller <b>302</b> as illustrated. Alternatively, clock signal (dotted-line arrows) C may come to system controller <b>302</b> from an external location. A system timer <b>306</b> uses clock signal C to constantly update a time value it sends out as timer signal T (the dashed-line arrow). Timer signal T may or may not be adjusted to match local time outside the device. Microcontroller <b>308</b> uses the timer signal T to generate a data signal D (the solid-line arrows). Data signal D includes all the time-critical messages for the peripherals, with deadline times derived from timer signal T. In addition, microcontroller <b>308</b> also generates messages that are not time-critical.

0056Time protocol engine <b>312</b> receives the data signal D for microcontroller <b>308</b>, a timer signal from system timer <b>306</b>, and a clock signal from bus clock <b>304</b>. In time protocol engine <b>312</b>, deadline times in data signal D are converted on the fly to relative numbers of clocks signals from “right now” (the time at which time protocol engine <b>312</b> releases the data to transmission serial buffer <b>314</b>) to the deadline time. To help time protocol engine <b>312</b> recognize deadline times within the stream of data signals D, an identifier signal may precede the deadline times. The identifier signal may be as simple as a single periodic bit set to one value (e.g., 1) when preceding a deadline time and to the other value (e.g., 0) when preceding other types of data. In some embodiments, time protocol engine <b>312</b> passes all non-deadline data without alteration. In some embodiments, time protocol engine <b>312</b> strips the identifier signals, which are no longer needed, before releasing the data to transmission serial buffer <b>314</b>. Time protocol engine <b>312</b> may forward the clock signal C to a shift-register of transmission serial buffer <b>314</b> and to SSB <b>324</b>.

0057In some embodiments, time protocol engine <b>312</b> keeps track of the latest deadline time received, either as a system time in or a number of clock signals out, and microcontroller <b>308</b> continues to transmit clock signal C until the latest deadline time has passed, rather than turning off clock signal C after a telegram transmission.

0058In some embodiments, transmission serial buffer <b>314</b> may be first-in, first-out (FIFO). Alternatively, it may provide a separate path for high-priority signals, such as messages with imminent deadline times, so that, if desired, they may be sent to SSB <b>324</b> ahead of lower-priority traffic. SSB <b>324</b> also carries a clock signal C, which may come through transmission buffer <b>314</b>, through time protocol engine <b>312</b> as illustrated, or directly from bus clock <b>304</b>. Structured signals passing through SSB <b>324</b> may be referred to as “telegrams,” because they take time to transmit and receive from beginning to end.

0059Among the components of peripheral <b>352</b> will be a reception serial buffer <b>332</b>. In some embodiments, the peripheral can recognize different types of telegrams and hold certain types in reception buffer <b>332</b> while forwarding others for immediate processing. From reception buffer <b>332</b>, the data travels through register bus <b>334</b> to various destination registers. Counting (either count-down or count-up) register <b>342</b>, which has access to the bus clock signal C, receives the deadline times converted to numbers of clock cycles and immediately begins counting up or down from those numbers. The count depends on the peripheral's sensing the bus clock signal, or compensating for predictable pauses, hence the preference in some embodiments to continue the clock signal C unless none of the counting registers in any of the peripherals are finished counting. The actions to be performed at the deadline times, instead of being written directly to function-control register <b>344</b>, are initially written to shadow register <b>346</b>. Shadow register <b>346</b> has no immediate reaction to being written and simply stores the action data while counting register <b>342</b> counts up or down.

0060When counting register <b>342</b> reaches a triggering value (e.g., zero), it triggers the copying of the action data from shadow register <b>346</b> to function-control measure register <b>344</b>. The count reaching the triggering value signifies the deadline time has arrived. Function-control register <b>344</b> immediately executes any action written to it; therefore the action is triggered exactly at the deadline time.

0061In the illustrated system, the action has a place in the peripheral where it can wait without being executed (i.e., the shadow register <b>346</b>, or in some embodiments the reception buffer <b>332</b>). The action also arrives accompanied by information on how many clock cycles will pass until deadline time when it will be executed. Therefore, the action no longer needs to be kept back until just before its deadline time, but may be sent almost any time before the deadline time for holding until the deadline time arrives. For example, time-critical action telegrams may be sent during idle periods on SSB <b>324</b>, easing congestion and reducing the possibility of error during high-traffic periods. Counting registers, if not already present in the peripheral, are fairly easy and inexpensive to add, and compatible with the relatively simplified logic customarily used for peripherals.

0062<figref idref="DRAWINGS">FIGS. 4A-E</figref> are graphical representations of exemplary telegrams generated by a microcontroller, processed by a time protocol engine, and sent to a peripheral. <figref idref="DRAWINGS">FIG. 4A</figref> is an example of a “standard” telegram carrying a message for an action that is not time-critical (i.e., it has no deadline time) as initially generated by the microprocessor. In this example, initial bit <b>402</b> flags the “type” of the telegram, (time-critical or timing-noncritical) and shall be referred to as the “T-bit.” In this example set, the T-bit is 0 for a timing-noncritical telegram and 1 for a time-critical telegram, but in some embodiments the reverse may be true or other values or bits may be used to the same effect. The telegram may also include a header <b>404</b> (for example, an address H₁of the peripheral and a target register within the peripheral) and a data payload <b>406</b> including action code A to be written to the target register to cause the peripheral to perform an action.

0063As discussed with reference to <figref idref="DRAWINGS">FIG. 2</figref>, newly generated telegrams from the microprocessor enter the time protocol engine. <figref idref="DRAWINGS">FIG. 4B</figref> represents a possible embodiment of the timing-noncritical telegram being sent to a transmission buffer after being processed by the time protocol engine. Header <b>404</b> and payload <b>406</b> are not modified. In some embodiments, T-bit <b>402</b> may be deleted (signified by the dotted outline), since it will not be needed downstream. However, the approach will still work even if the T-bit is not deleted.

0064<figref idref="DRAWINGS">FIG. 4C</figref> is an example of a time-critical telegram as initially generated by the microprocessor. It includes a T-bit <b>412</b> with a value that is only used for time-critical telegrams (in this illustration, 1). Header <b>414</b> may include the address H₂of the peripheral and a counting register in the peripheral. Payload <b>415</b> includes the deadline time T_dexpressed as a system time.

0065<figref idref="DRAWINGS">FIG. 4D</figref> is an example of the time-critical telegram after processing by the time protocol engine. As with a timing-noncritical telegram, T-bit <b>412</b> may be deleted, or not, depending on the embodiment. The time protocol engine may pass peripheral counting-register address H₂along without modification. The time protocol engine notes the system time Ts coming in on the timer signal and a clock frequency on the clock signal, and initially converts the deadline time T_dto a time-to-strobe (TTS_@send=T_d−T_s). TTS_@sendis the number of clock cycles until the deadline time T_dfrom the system time when the telegram is loaded from the time protocol engine into the transmission buffer. Preferably, though, the TTS should reflect the TTS as of its arrival at the peripheral receiver. accounting for the travel time T_twhile the telegram is loaded into the bus, transported to the peripheral, and its payload to written to the target register. At least the first order, T_tis proportional to the length of the telegram, so the time protocol engine can measure the length and use it to calculate T_tsynchronously with the bus clock. The TTS output from the time protocol engine is TTS=TTS_@send−T_t.

0066<figref idref="DRAWINGS">FIG. 4E</figref> shows the pair of telegrams sent by some embodiments for each time-critical action. Using two telegrams is one way to route the TTS to a counting register and the action A to a different register, such as a shadow register. The action telegram has a header <b>404</b> that includes the peripheral and target register (e.g., shadow register) address H₁and the payload <b>406</b> that includes the action data A to be written to the shadow register. The counting has a header <b>414</b> including the peripheral and target-register (e.g., counting register) address H₂, while payload <b>416</b> includes the time-to-strobe TTS to be written to the counting register.

0067<figref idref="DRAWINGS">FIG. 5</figref> is a flowchart of an example of telegram processing in a time protocol engine and subsequent actions at the receiving peripheral. In step <b>502</b>, the time protocol engine receives a new telegram from the microcontroller. In step <b>504</b>, the time protocol engine reads the T-bit to determine whether this telegram is time-critical. Continuing with the example of <figref idref="DRAWINGS">FIGS. 4A-E</figref>, finding a T-bit=0 at decision point <b>506</b> means that the telegram is not time-critical, i.e., that it does not contain a deadline time. In some embodiments, the time protocol engine may remove the T-bit in step <b>508</b>, shortening the telegram so that it may be sent faster. However, the system and method will still function if the T-bit is not removed. The remainder of the telegram is sent to the synchronous serial bus (SSB) in step <b>512</b> and received at the peripheral in step <b>514</b>. If the telegram is for a time-critical action, it is written to the shadow register, the address of which is part of the telegram header. If instead the telegram carries some other data, it may be written to a different register addressed in the header.

0068Unlike the function-control register, the shadow register does not automatically cause the peripheral to execute any action written to it. An action written to the shadow register can instead be stored for a wait time <b>518</b>.

0069Going back to decision point <b>506</b>, if the T-bit=1, it may be removed in step <b>522</b> at any time before being sent to the transmission buffer and onto the bus, or in some embodiments it may be left in place. The deadline time T_dcontained in the telegram is read at step <b>524</b>. Based on the telegram's length, the expected travel time T_tis calculated at step <b>526</b>. In some embodiments, the time protocol engine then examines the transmission buffer to determine the status of the SSB (free or busy). If the bus is busy, the telegram cannot yet be sent, and it is not known with precision when the bus will become free to allow the telegram to be sent. Therefore, the time protocol engine loops back and continues to monitor the transmission buffer for bus status as long as the bus appears busy at decision point <b>532</b>. On the other hand, if the bus is free at decision point <b>532</b>, the time protocol engine reads the current system time T_sfrom the system timer at step <b>534</b> and calculates the time-to-strobe TTS=T_d−T_s−T_tin clock cycles per second (or other unit of system time). The time protocol engine replaces deadline time T_din the telegram payload with time-to-strobe TTS in step <b>542</b> and sends the telegram through the transmission buffer to the bus in step <b>544</b>. A constant number of clock cycles (in some embodiments, only one), pass between completing the on-the-fly TTS calculation of step <b>542</b> and transmitting the first bit in step <b>544</b>.

0070At step <b>546</b>, the TTS telegram is received at the peripheral. If the value in the counting register is zero, the counting register is overwritten with the TTS and the value begins decreasing by a constant decrement for each clock cycle. The peripheral monitors the counting register at step <b>552</b>. As long as the counting register contains a value greater than zero at decision point <b>554</b>, the peripheral simply continues to monitor the count. When the value in the counting register reaches zero (signifying that deadline time T_dhas arrived for the action stored in the shadow register), the peripheral copies the action code in the shadow register to the function-control register at step <b>556</b>, triggering the immediate execution of the action exactly at the deadline time.

0071In some embodiments, the microprocessor of the system controller keeps track of all actions still pending and their deadline times, and maintains the bus clock signal to the peripherals until the last deadline time is past. In some embodiments, the system controller may keep the bus clock running continuously. Many existing SSBs already tolerate clock signals that exceed telegram length.

0072With the shadow register storing the time-critical action and the counting register given the number of clock cycles before the action's deadline time, the peripheral is equipped to execute the action exactly at the deadline time autonomously; there is no need for further communication from the system controller in order to execute that action on time. Time-critical action messages can thus be sent at any suitable time before the deadline time, limited only by the size of the counting register (the more bits in the counting register, the earlier the telegrams can be sent.

0073The flexibility conferred by the decoupling of register programming from action execution reduces the importance of transmitting time-critical actions from “highest” to “medium” or “low.” Unlike some other approaches, this system does not need extra strobe telegrams or strobe signals. This process does not interfere with other traffic on the bus; on the contrary, enables the bus to tolerate more traffic in general, including time-accurate telegrams. The relaxation of the real-time constraints can allow more peripherals to share the same bus, allow the bus to function at a lower speed so that the bus clock rate accommodates the desired timing precision.

0074<figref idref="DRAWINGS">FIGS. 6A-B</figref> are schematic timing diagrams illustrating how the pre-loading process may enable closely-timed execution of multiple time-critical functions sent through a serial bus. <figref idref="DRAWINGS">FIG. 6A</figref> illustrates one of the extreme cases of closely-timed actions on different peripherals: where the actions are intended to be simultaneous at a single deadline time T_{d1, 2}. The top “SDATA” row illustrates the two pairs of telegrams sent from the system controller: action telegram <b>612</b> for the shadow register of peripheral <b>1</b>, TTS telegram <b>613</b> for the counting register of peripheral <b>1</b>, action telegram <b>622</b> for the shadow register of peripheral <b>2</b>, and TTS telegram <b>623</b> for the counting register of peripheral <b>2</b>. The “SCLK” row shows the bus-clock cycles <b>602</b>, with exaggeratedly low frequency to aid visibility. The two bottom rows illustrate what happens at peripheral <b>1</b> and peripheral <b>2</b>.

0075Action telegram <b>612</b> arrives at peripheral <b>1</b> where its payload, action A<b>1</b>, is written to the shadow register at time <b>614</b>. Then TTS telegram <b>613</b> arrives at peripheral <b>1</b> where its payload, number of clock cycles TTS<b>1</b>, is written to the counting register at time <b>615</b>. The counting register immediately begins counting up or down from TTS<b>1</b>. As TTS<b>1</b> is counted, action telegram <b>622</b> arrives at peripheral <b>2</b> where its payload, action A<b>2</b>, is written to the shadow register at time <b>624</b>. Then TTS telegram <b>623</b> arrives at peripheral <b>2</b> where its payload, number of clock cycles TTS<b>2</b>, is written to the counting register at time <b>625</b>. This counting register immediately begins counting up or down from TTS<b>2</b>. Although (in fact, because) the deadline times for peripheral <b>1</b> and peripheral <b>2</b> are the same T_d1,2, TTS<b>2</b> is different from TTS<b>1</b>. TTS<b>2</b> is shortened to compensate for the later transmission of telegrams <b>622</b> and <b>623</b> down the SSB.

0076The counting register of peripheral <b>1</b> reaches zero at time <b>617</b>, to be followed by the virtually instantaneous writing of action Al to the function-control register, <b>616</b>, and execution of action A<b>1</b>, <b>618</b>. The counting register of peripheral <b>2</b> reaches zero at time <b>627</b> (which in this example is equal to time <b>617</b>) to be followed by the virtually instantaneous writing of action A<b>1</b> to the function-control register, <b>626</b>, and execution of action A<b>1</b>, <b>628</b>. Two simultaneous actions on different peripherals connected to the same serial bus would not be possible with telegrams that write the actions directly to the function-control register; because of the finite time it takes to send the second telegram, the second action would always be later than the first action.

0077The “SCLK” row of <figref idref="DRAWINGS">FIG. 6A</figref> also illustrates a feature of some SSB standards that may affect the process: clock pulses <b>622</b> coinciding with beginnings or ends of telegrams may be suppressed or “swallowed” (symbolized by the dotted outlines of some of the clock pulses). Two examples are the “sequence start condition” (SSC) of the MIPI RFFE standard and the “start, stop and restart” of the I²C standard. Normally, the counting registers on the peripherals only count up or down in response to clock pulses; any swallowed pulses could throw off the count and result in a timing error for the action execution. To prevent this undesirable result, the system-controller may temporarily speed up the clock, fitting one or more extra pulses into the time interval to replace the swallowed pulses; this compensation will be completely transparent to the peripherals. An alternative solution is to offset the value in the counting register by the number of swallowed pulses after each clock interruption.

0078<figref idref="DRAWINGS">FIG. 6B</figref> is a timing diagram for the case of two time-critical actions of the same function to be executed on the same counting register, shadow register and function-control register of the same peripheral. As illustrated, these two actions are scheduled for deadline times Td₁and Td₂, which are separated by less time than it takes to transmit telegrams <b>652</b> and <b>653</b> for the second action. In a system that writes the actions directly to the function-control registers for immediate execution, this would be impossible without an extra bus between the system controller and peripheral <b>1</b>.

0079In some embodiments, the time protocol engine on the system controller detects when two consecutive actions addressed to the same peripheral at deadline times separated by less than the time to send the second pair of telegrams through the SSB. Upon detecting this condition, the two action telegrams and the first TTS telegram are treated normally, but the second TTS telegram is given a difference time-to-strobe dTTS=TTS<b>2</b>−TTS<b>1</b> instead of the normally calculated TTS<b>2</b>.

0080The system controller sends telegrams <b>642</b> and <b>643</b> for the first action, followed by telegrams <b>652</b> and <b>653</b> for the second action, through the SSB. Action code A<b>1</b> is written to the shadow register of peripheral <b>1</b> at time <b>644</b>, and TTS<b>1</b> is written to the counting register of peripheral <b>1</b> at time <b>645</b>, one telegram-duration after time <b>644</b>. The counting register immediately starts the count <b>647</b> (in the illustrated example, a countdown). However, when telegrams <b>652</b> and <b>653</b> arrive at peripheral <b>1</b>, the shadow register is already occupied by A<b>1</b> waiting for Td₁, and the counting register is already busy counting up or down from TTS<b>1</b> toward Td₁. In this event, telegrams <b>652</b> and <b>653</b> are held temporarily in peripheral <b>1</b>'s reception buffer <b>631</b>. Alternatively, there may be dedicated FIFO buffers for the shadow register and the counting register, in which case A<b>2</b> is written to the shadow-register buffer and dTTS is written to the counting-register buffer.

0081At Td₁, the count <b>647</b> for TTS<b>1</b> reaches the triggering value of zero; A<b>1</b> is written to peripheral <b>1</b>'s function-control register and immediately executed. This being done, the shadow register and the counting register become free, allowing telegrams <b>652</b> and <b>653</b> to be released from the buffer(s), action code A<b>2</b> to be written to the shadow register at time <b>654</b>, and dTTS to be written to the counting register at time <b>655</b>. For visibility, time <b>655</b> is later than time <b>654</b> in the illustration, but in practice they may be virtually simultaneous. At Td₂, the count <b>657</b> for dTTS reaches the triggering value of zero, and A<b>2</b> is written to the function-control register and immediately executed precisely at the intended deadline. This is another scenario where the decoupling of the transmission timing from the execution timing allows the system greater flexibility.

0082Although this example described two closely spaced time-critical actions, the same approach can be used for three or more closely spaced time-critical actions, whether the actions are performed by the same peripheral or by different peripherals on the same bus.

0083The preceding Description and accompanying Drawings describe example embodiments in detail to aid understanding. However, the scope of the claims may cover equivalents, permutations, and combinations that are not explicitly described herein.