Systems and methods for integrated rotation of processor cores

TECHNICAL FIELD

0001The present disclosure relates in general to information handling systems, and more particularly to thermal management in a multi-core processor.

BACKGROUND

0002As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.

0003To maximize processing throughput, an operating system executing on an information handling system may be capable of scheduling threads among a plurality of cores of a multi-core processor. While such scheduling may increase cache hit rates and/or other performance parameters, it may also have a tendency to cause long durations of execution upon a particular core, which may in turn cause heat increases at or near such core, which may decrease performance, as overheated cores may throttle performance in order to reduce temperature.

0004Further complicating matters, sizes of transistors used in processors continue to shrink with each new generation. Accordingly, heat generated by thread execution of a core may further be exacerbated as the heat is generated from a smaller area of the processor die. This has the tendency to increase the thermal resistance of processors which each new generation, making it more and more difficult to transfer heat generated by a core to the air using heat pipes, heat fins, heat sinks, or other thermal transfer techniques.

SUMMARY

0005In accordance with the teachings of the present disclosure, the disadvantages and problems associated with thermal control in a multi-core processor may be substantially reduced or eliminated.

0006In accordance with embodiments of the present disclosure, a processor may include a plurality of cores integrated within an integrated circuit package and a thermal rotation management module communicatively coupled to each of the plurality of cores and integrated within the integrated circuit package. The thermal rotation management module may be configured to, responsive to a temperature of a first core of the plurality of cores exceeding a threshold temperature, identify a second core of the plurality of cores for relocating a workload executing on the first core and relocate the workload executing on the first core to the second core.

0007In accordance with these and other embodiments of the present disclosure, a method may include, responsive to a temperature of a first core of a plurality of cores integrated within an integrated circuit package exceeding a threshold temperature, identifying a second core of the plurality of cores for relocating a workload executing on the first core and relocating the workload executing on the first core to the second core.

0008In accordance with these and other embodiments of the present disclosure, an information handling system may include a processor and a memory communicatively coupled to the processor. The processor may include a plurality of cores integrated within an integrated circuit package and a thermal rotation management module communicatively coupled to each of the plurality of cores and integrated within the integrated circuit package. The thermal rotation management module may configured to responsive to a temperature of a first core of the plurality of cores exceeding a threshold temperature, identify a second core of the plurality of cores for relocating a workload executing on the first core, and relocate the workload executing on the first core to the second core.

0009Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

0010It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

0011A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

0012<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block diagram of an example information handling system, in accordance with embodiments of the present disclosure;

0013<figref idref="DRAWINGS">FIG. 2</figref> illustrates a block diagram of an example processor, in accordance with embodiments of the present disclosure; and

0014<figref idref="DRAWINGS">FIG. 3</figref> illustrates a flow chart of an example method for thermal control of a multi-core processor, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

0015Preferred embodiments and their advantages are best understood by reference to <figref idref="DRAWINGS">FIGS. 1 through 3</figref>, wherein like numbers are used to indicate like and corresponding parts.

0016For the purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, an information handling system may be a personal computer, a PDA, a consumer electronic device, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include memory, one or more processing resources such as a central processing unit (CPU) or hardware or software control logic. Additional components of the information handling system may include one or more storage devices, one or more communications ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communication between the various hardware components.

0017For the purposes of this disclosure, computer-readable media may include any instrumentality or aggregation of instrumentalities that may retain data and/or instructions for a period of time. Computer-readable media may include, without limitation, storage media such as a direct access storage device (e.g., a hard disk drive or floppy disk), a sequential access storage device (e.g., a tape disk drive), compact disk, CD-ROM, DVD, random access memory (RAM), read- only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and/or flash memory; as well as communications media such as wires, optical fibers, microwaves, radio waves, and other electromagnetic and/or optical carriers; and/or any combination of the foregoing.

0018For the purposes of this disclosure, information handling resources may broadly refer to any component system, device or apparatus of an information handling system, including without limitation processors, buses, memories, I/O devices and/or interfaces, storage resources, network interfaces, motherboards, integrated circuit packages; electro-mechanical devices (e.g., air movers), displays, and power supplies.

0019<figref idref="DRAWINGS">FIG. 1</figref> illustrates a block diagram of an example information handling system <b>102</b>, in accordance with the present disclosure. In some embodiments, information handling system <b>102</b> may comprise a server chassis configured to house a plurality of servers or “blades.” In other embodiments, information handling system <b>102</b> may comprise a personal computer (e.g., a desktop computer, laptop computer, mobile computer, and/or notebook computer). In yet other embodiments, information handling system <b>102</b> may comprise a mobile device sized and shaped to be readily transportable on the person of a user (e.g., a mobile phone, tablet, personal digital assistant, digital music player, etc.). In yet other embodiments, information handling system <b>102</b> may comprise a storage enclosure configured to house a plurality of physical disk drives and/or other computer-readable media for storing data. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, information handling system <b>102</b> may comprise a processor <b>103</b>, a memory <b>104</b>, and a BIOS <b>105</b>.

0020Processor <b>103</b> may comprise any system, device, or apparatus operable to interpret and/or execute program instructions and/or process data, and may include, without limitation a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, processor <b>103</b> may interpret and/or execute program instructions and/or process data stored in memory <b>104</b> and/or another component of information handling system <b>102</b>. In these and other embodiments, processor <b>103</b> may comprise a multi-core processor, as described in greater detail below. Memory <b>104</b> may be communicatively coupled to processor <b>103</b> and may comprise any system, device, or apparatus operable to retain program instructions or data for a period of time. Memory <b>104</b> may comprise random access memory (RAM), electrically erasable programmable read-only memory (EEPROM), a PCMCIA card, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and/or array of volatile or non-volatile memory that retains data after power to information handling system <b>102</b> is turned off.

0021A BIOS <b>105</b> may include any system, device, or apparatus configured to identify, test, and/or initialize information handling resources of information handling system <b>102</b>, and/or initialize interoperation of information handling system <b>102</b> with other information handling systems. “BIOS” may broadly refer to any system, device, or apparatus configured to perform such functionality, including without limitation, a Unified Extensible Firmware Interface (UEFI). In some embodiments, BIOS <b>105</b> may be implemented as a program of instructions that may be read by and executed on processor <b>103</b> to carry out the functionality of BIOS <b>105</b>. In these and other embodiments, BIOS <b>105</b> may comprise boot firmware configured to be the first code executed by processor <b>103</b> when information handling system <b>102</b> is booted and/or powered on. As part of its initialization functionality, code for BIOS <b>105</b> may be configured to set components of information handling system <b>102</b> into a known state, so that one or more applications (e.g., an operating system or other application programs) stored on compatible media (e.g., disk drives) may be executed by processor <b>103</b> and given control of information handling system <b>102</b>. In some embodiments, BIOS <b>105</b> may also be configured to store user settings for selectively enabling or disabling thermal control of processor <b>103</b> using integrated thermal rotation of processor cores, as described in greater detail below.

0022In addition to processor <b>103</b>, memory <b>104</b>, and BIOS <b>105</b>, information handling system <b>102</b> may include one or more other information handling resources.

0023<figref idref="DRAWINGS">FIG. 2</figref> illustrates a block diagram of an example multi-core processor <b>103</b>, in accordance with embodiments of the present disclosure. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, processor <b>103</b> may comprise a plurality of cores <b>202</b> (e.g., cores <b>202</b><i>a</i>-<b>202</b><i>p</i>), each core <b>202</b> integrated or formed on the same integrated circuit die or onto multiple dies in a single chip package. Each core <b>202</b> may be communicatively coupled to a thermal rotation management module <b>208</b>, also formed on the same integrated circuit die as cores <b>202</b> or onto a die in a single chip package comprising cores <b>202</b>.

0024Each core <b>202</b> may comprise an independent actual central processing unit to read and execute program instructions, and cores <b>202</b> may operate in parallel to execute multiple instructions simultaneously on processor <b>103</b>. As described above, at the direction of a thread scheduler, each of one or more threads of executable instructions may be scheduled for execution on a particular core <b>202</b>.

0025As shown in <figref idref="DRAWINGS">FIG. 2</figref>, each core <b>202</b> may be coupled to an associated temperature sensor <b>204</b> and an associated cache <b>206</b>. A temperature sensor <b>204</b> may be any system, device, or apparatus (e.g., a thermometer, thermistor, etc.) configured to communicate a signal to its associated core <b>202</b> indicative of a temperature within such core <b>202</b>.

0026A cache <b>206</b> is a memory used by a core <b>202</b> to reduce the average time to access data from main memory <b>104</b>. A cache <b>206</b> may be a smaller, faster memory than memory <b>104</b> and may store copies of frequently-used data and instructions from memory <b>104</b>. In some embodiments, a cache <b>206</b> may comprise an independent data cache and instruction cache. In these and other embodiments, a cache may be organized in a hierarchy of multiple cache levels (e.g., level 1, level 2, etc.). In these or other embodiments, all or part of cache <b>206</b> associated with one core <b>202</b> may be shared with another core <b>202</b>.

0027A thermal rotation management module <b>208</b> may include any system, device, or apparatus for monitoring when a workload may produce high temperatures in a core <b>202</b>, and in advance of that condition, reschedule that workload onto a different core <b>202</b> which is much cooler. In order to reschedule the workload, thermal rotation management module <b>208</b> may be configured to, ahead of such rescheduling, prepare or “prime” a cache <b>206</b> associated with the core <b>202</b> to which the workload is to be rescheduled, in order to reduce or eliminate any performance penalty associated with the migration of the workload from core to core. In addition, because thermal rotation management module <b>208</b> is local to processor <b>103</b>, it may be configured to group multiple cores <b>202</b> together and expose them to an operating system executing on information handling system <b>102</b> as a single logical core. For example, in the sixteen-core embodiment depicted in <figref idref="DRAWINGS">FIG. 2</figref>, thermal rotation management module <b>208</b> may, with core rotation enabled, report as having only eight logical cores. This would then provide, internal to processor <b>103</b>, a rotation mechanism whereby a thread could be migrated back and forth between two physical cores <b>202</b> making up a logical core, independent of operating system or upper-level software interaction.

0028In some embodiments, a logical core may include more than two physical cores <b>202</b>. For example, in the sixteen-core embodiment depicted in <figref idref="DRAWINGS">FIG. 2</figref>, thermal rotation management module <b>208</b> may, with core rotation enabled, report as having only four logical cores, each logical core comprising four physical cores <b>202</b>. In such embodiments, the level of core redundancy may be selectable by a user via configuration options of BIOS <b>105</b>.

0029In these and other embodiments, for situations in which full redundancy of all physical cores <b>202</b> is unnecessary or not desired, a hybrid mode may be available (and configurable via BIOS <b>105</b>) whereby some of physical cores <b>202</b> may be devoted to core rotation while other physical cores <b>202</b> would not. For example, in one example mode of operation, eight physical cores <b>202</b><i>a</i>-<b>204</b><i>d </i>and <b>202</b><i>m</i>-<b>202</b><i>p </i>may be devoted to core rotation (e.g., two physical cores for each of four logical cores) while eight physical cores <b>202</b><i>e</i>-<b>202</b><i>l </i>would not participate in core rotation, with each of such physical cores <b>202</b> being reported as a logical core.

0030By intelligently rotating core workloads throughout processor <b>103</b>, processor <b>103</b> may experience dramatic reductions in package temperature as compared to approaches which do not use thermal rotation, as thermal rotation may effectively add as a heat spreader, allowing regions of processor <b>103</b> to heat up and cool down independently of one another, assuming rotation is performed between cores with sufficient distance from each other on processor <b>103</b>.

0031For ease of exposition, <figref idref="DRAWINGS">FIG. 2</figref> depicts sixteen cores <b>202</b> within processor <b>103</b>. However, it is understood that processor <b>103</b> may comprise any suitable number of cores <b>202</b>. Also, in addition to cores <b>202</b>, temperature sensors <b>204</b>, caches <b>206</b>, and thermal rotation management module <b>208</b>, processor <b>103</b> may include one or more other components.

0032<figref idref="DRAWINGS">FIG. 3</figref> illustrates a flow chart of an example method <b>300</b> for thermal control of a multi-core processor (e.g., processor <b>103</b>), in accordance with embodiments of the present disclosure. According to one or more embodiments, method <b>300</b> may begin at step <b>302</b>. As noted above, teachings of the present disclosure may be implemented in a variety of configurations of information handling system <b>102</b>. As such, the preferred initialization point for method <b>300</b> and the order of the steps comprising method <b>300</b> may depend on the implementation chosen.

0033At step <b>302</b>, thermal rotation management module <b>208</b> may determine if thermal rotation is enabled for processor <b>103</b>. For example, in some embodiments, thermal rotation management module <b>208</b> may determine if a configuration option of BIOS <b>105</b> indicates that thermal rotation is enabled. If thermal rotation is enabled for processor <b>103</b>, method <b>300</b> may proceed to step <b>304</b>. Otherwise, method <b>300</b> may end, and traditional thermal management and/or thread scheduling approaches may be used.

0034At step <b>304</b>, responsive to thermal rotation being enabled for processor <b>103</b>, thermal rotation management module <b>208</b> may determine if a temperature associated with a core <b>202</b> within processor <b>103</b> has exceeded a threshold temperature. In some embodiments, an individual core <b>202</b> may determine if its associated temperature sensor <b>204</b> is above the threshold temperature, and communicate an indication to thermal rotation management module <b>208</b> that its temperature has exceeded the threshold. In other embodiments, an individual core <b>202</b> may communicate an indication of a temperature reported by its associated temperature sensor <b>204</b> to thermal rotation management module <b>208</b>, and thermal rotation management module <b>208</b> may in turn compare temperatures reported from the multiple cores <b>202</b> against the threshold temperature. In response to a temperature associated with a core <b>202</b> exceeding the threshold temperature, method <b>300</b> may proceed to step <b>306</b>.

0035Otherwise, method <b>300</b> may remain at step <b>304</b> until a temperature associated with a core <b>202</b> exceeds the threshold temperature.

0036At step <b>306</b>, responsive to a temperature associated with a core <b>202</b> exceeding a threshold temperature, thermal rotation management module <b>208</b> may determine a target core <b>202</b> to which a workload executing on the overheated core <b>202</b> may be relocated. In some embodiments, cores <b>202</b> of processor <b>103</b> may each be assigned to a particular logical core. For example, in an embodiment in which each logical core has two physical cores <b>202</b>, each core <b>202</b> may be paired with another core <b>202</b>. To maximize the benefit of core rotation, paired cores <b>202</b> may be located in another portion of processor <b>103</b>. As a specific example, cores <b>202</b><i>a, </i><b>202</b><i>b, </i><b>202</b><i>c, </i>and <b>204</b><i>d </i>may be paired with cores <b>202</b><i>m, </i><b>202</b><i>n, </i><b>202</b><i>o, </i>and <b>202</b><i>p, </i>respectively, while cores <b>202</b><i>e, </i><b>202</b><i>f, </i><b>202</b><i>g, </i>and <b>204</b><i>h </i>may be paired with cores <b>202</b><i>i, </i><b>202</b><i>j, </i><b>202</b><i>k, </i>and <b>202</b><i>l, </i>respectively. In such embodiments, when the temperature of one core <b>202</b> of a pair has exceeded the threshold temperature, thermal rotation management module <b>208</b> may identify or select the other core <b>202</b> of the pair as the target core for relocating the workload.

0037As another example, in an embodiment in which each logical core has four physical cores <b>202</b>, cores <b>202</b><i>a, </i><b>202</b><i>e, </i><b>202</b><i>i, </i>and <b>202</b><i>m </i>may be members of one logical core, cores <b>202</b><i>b, </i><b>202</b><i>f, </i><b>202</b><i>j, </i>and <b>202</b><i>n </i>may be members of another logical core, cores <b>202</b><i>c, </i><b>202</b><i>g, </i><b>202</b><i>k, </i>and <b>202</b><i>o </i>may be members of another logical core, and cores <b>202</b><i>d, </i><b>202</b><i>h, </i><b>202</b><i>l, </i>and <b>202</b><i>p </i>may be members of another logical core. In such embodiments, when the temperature of one core <b>202</b> of a logical core has exceeded the threshold temperature, thermal rotation management module <b>208</b> may identify or select a target core from the remaining cores in any suitable manner. For example, a round robin approach may be used wherein thermal rotation management module <b>208</b> rotates execution among cores <b>202</b> of a logical core in a defined, hard-coded order (e.g., core <b>202</b><i>a </i>to core <b>202</b><i>e </i>to core <b>202</b><i>i </i>to core <b>202</b><i>m </i>and back to core <b>202</b><i>a</i>). As another example, an approach may be used wherein the target core <b>202</b> selected is the one within the logical core having the lowest temperature. As a further example, the target core <b>202</b> may be selected based on cache content of the workload to be relocated. In some embodiments, a combination of two or more of the foregoing factors, or other factors, may be considered to identify a target core <b>202</b>.

0038At step <b>308</b>, thermal rotation management module <b>208</b> may prepare a cache <b>206</b> associated with the target core <b>202</b> with anticipated cache data for the workload to be relocated, in order to reduce or eliminate any latency associated with the transfer of the workload. The anticipated cache data may be based on data in a cache <b>206</b> associated with the overheated core, branch prediction logic of processor <b>103</b>, or any other suitable approach.

0039At step <b>310</b>, after preparation of the cache <b>206</b> associated with the target core <b>202</b>, thermal rotation management module <b>208</b> may migrate the workload to the target core <b>202</b> in a manner transparent to software executing on information handling system <b>102</b>. After completion of step <b>310</b>, method <b>300</b> may end.

0040Although <figref idref="DRAWINGS">FIG. 3</figref> discloses a particular number of steps to be taken with respect to method <b>300</b>, method <b>300</b> may be executed with greater or fewer steps than those depicted in <figref idref="DRAWINGS">FIG. 3</figref>. In addition, although <figref idref="DRAWINGS">FIG. 3</figref> discloses a certain order of steps to be taken with respect to method <b>300</b>, the steps comprising method <b>300</b> may be completed in any suitable order.

0041Method <b>300</b> may be implemented using information handling system <b>102</b> or any other system operable to implement method <b>300</b>. In certain embodiments, method <b>300</b> may be implemented partially or fully in software and/or firmware embodied in computer-readable media and executable on a processor or controller of information handling system <b>102</b>.

0042As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

0043This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.

0044All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.