Image sensor for improving nonlinearity of row code region, and device including the same

CROSS-REFERENCE TO THE RELATED APPLICATION

0001This application claims priority from Korean Patent Application No. 10-2014-0173996 filed on Dec. 5, 2014, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

00021. Field

0003Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to an image sensor, and more particularly, to an image sensor for improving nonlinearity of a row code region in a single-slope analog-to-digital (AD) converter, a method of operating the same, and a device including the same.

00042. Description of the Related Art

0005A complementary metal oxide semiconductor (CMOS) image sensor is a solid-state image pickup device manufactured using CMOS processes. The CMOS image sensor has lower manufacturing costs and a smaller size than a charge coupled device (CCD) image sensor which includes a high-voltage analog circuit, and thus, has an advantage of low power consumption. In addition, as the performance of the CMOS image sensor has been improved, this solid-state image pickup device has gained more popularity that the CCD image sensor for various electronic appliances including portable devices such as a smart phone and a digital camera.

0006A pixel array included in the CMOS image sensor may include a photoelectric conversion element in each pixel. The photoelectric conversion element generates an electrical signal varying with a quantity of incident light. The CMOS image sensor processes electrical signals to produce image data. The CMOS image sensor generally uses a single-slope AD conversion method for AD conversion. In the single-slope AD conversion method, a ramp signal monotonously changing in one direction over time is compared with a pixel signal having a predetermined voltage level, and time (or a time point) when a voltage level of the ramp signal is equal to a voltage level of the pixel signal is converted into a digital signal.

0007A CMOS image sensor includes AD converters which convert analog pixel signals output from pixels into digital signals. Nonlinearity may occur in the AD converters. Nonlinearity adversely affects AD conversion.

SUMMARY

0008According to an exemplary embodiment of the inventive concept, there is provided an image sensor which may include: a pixel configured to generate a reset signal and an image signal, a comparator configured to compare the reset signal with a reference signal and generate a first comparison signal, a counter configured to generate a first count value corresponding to the reset signal based on a clock signal and the first comparison signal, and a reference signal generator configured to generate the reference signal which changes between a first level corresponding to a maximum reset count value of the counter and a second level corresponding to a minimum reset count value of the counter during a reset signal period. The image sensor may further include an output circuit configured to output a reset count value corresponding to a difference between the maximum reset count value and the first count value.

0009The reference signal generator may generate, as the reference signal, either a first reference signal ramping up from the first level to the second level or a second reference signal ramping down from the second level to the first level in response to control signals during the reset signal period.

0010The reference signal generator may include a first reference signal generator configured to generate the first reference signal ramping up from the first level to the second level during the reset signal period, a second reference signal generator configured to generate the second reference signal ramping down from the second level to the first level during the reset signal period, and a selection circuit configured to output either the first reference signal or the second reference signal as the reference signal in response to a selection signal.

0011The reference signal generator may further control the reference signal to change between a third level corresponding to a maximum image signal count value of the counter and a fourth level corresponding to a minimum image signal count value of the counter during an image signal period.

0012Alternatively, the image sensor may further include an output circuit configured to calculate a first difference between the maximum reset count value and the first count value and a second difference between the maximum image signal count value and a second count value and to output a final count value corresponding to a difference between the second difference and the first difference. At this time, the comparator may compare the image signal with the second reference signal and generate a second comparison signal and the counter may generate the second count value corresponding to the image signal based on the clock signal and the second comparison signal.

0013According to another exemplary embodiment of the inventive concept, there is provided a mobile computing device which may include the above image sensor and an application processor which is connected to the image sensor and configured to select a direction of the reference signal generated by the reference signal generator from among a ramping up direction from the first level to the second level and a ramping down direction from the second level to the first level using an application program installed thereon.

0014The mobile computing device may further include an image signal processor configured to generate brightness information based on image data, corresponding to the image signal, output from the image sensor, and set the direction of the reference signal generated from the reference signal generator based on the brightness information.

0015The application processor may be configured to provide a user interface allowing a user to select one of at least two modes of the mobile computing device corresponding to the ramping up direction and the ramping down direction, respectively.

0016In the above, a mode of the at least two modes corresponding to the ramping up direction may include a high-speed mode, and another mode of the at least two modes corresponding to the ramping down direction may include a low-power mode.

0017According to a further exemplary embodiment of the inventive concept, there is provided a method of operating an image sensor. The method may include generating a reference signal which changes between a first level corresponding to a maximum reset count value of a counter and a second level corresponding to a minimum reset count value of the counter during a reset signal period of the image sensor, comparing a reset signal output from a pixel with the reference signal to generate a first comparison signal as a result of the comparing, and generating a first count value corresponding to the reset signal based on a clock signal and the first comparison signal.

0018The method may further include controlling the reference signal to change between a third level corresponding to a maximum image signal count value of the counter and a fourth level corresponding to a minimum image signal count value of the counter during an image signal period, comparing an image signal output from the pixel with the reference signal that changes between the third level and the fourth level and generating a second comparison signal, and generating a second count value corresponding to the image signal based on the clock signal and the second comparison signal.

0019The method may further include calculating a first difference between the maximum reset count value and the first count value, calculating a second difference between the maximum image signal count value and the second count value, and outputting a final count value corresponding to a difference between the second difference and the first difference.

BRIEF DESCRIPTION OF THE DRAWINGS

0020The above and other features and advantages of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

0021<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of an image sensor according to an exemplary embodiment of the inventive concept;

0022<figref idref="DRAWINGS">FIG. 2</figref> is a circuit diagram of a pixel illustrated in <figref idref="DRAWINGS">FIG. 1</figref> according to an exemplary embodiment of the inventive concept;

0023<figref idref="DRAWINGS">FIG. 3</figref> is a circuit diagram of an example of a ramp signal generator illustrated in <figref idref="DRAWINGS">FIG. 1</figref>;

0024<figref idref="DRAWINGS">FIG. 4</figref> is a circuit diagram of another example of the ramp signal generator illustrated in <figref idref="DRAWINGS">FIG. 1</figref>;

0025<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are conceptual diagrams for explaining analog-to-digital (AD) conversion performed based on a ramp signal in an image sensor using electrons output from a photoelectric conversion element of a pixel, according to exemplary embodiments of the inventive concept;

0026<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are conceptual diagrams for explaining AD conversion performed based on a ramp signal in an image sensor using holes output from a photoelectric conversion element of a pixel, according to exemplary embodiments of the inventive concept;

0027<figref idref="DRAWINGS">FIG. 7</figref> is a flowchart of a method of operating the image sensor illustrated in <figref idref="DRAWINGS">FIG. 1</figref> according to an exemplary embodiment of the inventive concept;

0028<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart of an operation of the ramp signal generator illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, according to an exemplary embodiment of the inventive concept;

0029<figref idref="DRAWINGS">FIG. 9</figref> is a flowchart of a method of operating the image sensor illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, which includes the ramp signal generator illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, according to an exemplary embodiment of the inventive concept;

0030<figref idref="DRAWINGS">FIG. 10</figref> is a block diagram of a computing device including the image sensor illustrated in <figref idref="DRAWINGS">FIG. 1</figref> according to an exemplary embodiment of the inventive concept; and

0031<figref idref="DRAWINGS">FIG. 11</figref> is a block diagram of a computing device including the image sensor illustrated in <figref idref="DRAWINGS">FIG. 1</figref> according to another exemplary embodiment of the inventive concept.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

0032The inventive concept now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout this disclosure.

0033It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

0034It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the teachings of the disclosure.

0035The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

0036Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

0037“To determine from a low code” means herein to perform analog-to-digital (AD) conversion on a reset signal output from a pixel using a reference signal (e.g., a ramp signal) that changes (or ramps) from a level corresponding to a minimum reset count value of a counter or to perform AD conversion on an image signal output from the pixel using a reference signal (e.g., a ramp signal) that changes (or ramps) from a level corresponding to a minimum image signal count value of the counter. The determination from a low code will be described in detail with reference to <figref idref="DRAWINGS">FIGS. 5A and 6A</figref>.

0038“To determine from a high code” means herein to perform AD conversion on a reset signal output from a pixel using a ramp signal that ramps from a level corresponding to a maximum reset count value of a counter or to perform AD conversion on an image signal output from the pixel using a ramp signal that ramps from a level corresponding to a maximum image signal count value of the counter. The determination from a high code will be described in detail with reference to <figref idref="DRAWINGS">FIGS. 5B and 6B</figref>.

0039Determination from a low code may refer to AD conversion from a low code. Determination from a high code may refer to AD conversion from a high code. According to some embodiments of the inventive concept, an image sensor may basically perform determination from a high code. In other embodiments, an image sensor may selectively perform either determination from a low code or determination from a high code based on a selection signal.

0040<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of an image sensor <b>100</b>, according to an exemplary embodiment of the inventive concept. Referring to <figref idref="DRAWINGS">FIG. 1</figref>, the image sensor <b>100</b> may include a pixel array <b>110</b>, a row controller <b>120</b>, an amplifier circuit <b>130</b>, a ramp signal generator <b>135</b>, a comparator circuit <b>140</b>, a clock signal generator <b>145</b>, a counter circuit <b>150</b>, a timing generator <b>160</b>, a column controller <b>170</b>, and an output circuit <b>180</b>. An AD converter circuit may include the comparator circuit <b>140</b> and the counter circuit <b>150</b>.

0041The image sensor <b>100</b> may also include a register REG that stores information about determination from a low code or determination from a high code. The register REG may be implemented as a special function register (SFR), but the inventive concept is not restricted to this example. The image sensor <b>100</b> may be a front side illumination (FSI) image sensor or a back side illumination (BSI) image sensor depending on whether a light receiving surface is at the front or back side of a substrate.

0042The pixel array <b>110</b> may be an active pixel sensor (APS) array. The pixel array <b>110</b> may include a plurality of pixels <b>111</b>. The pixels <b>11</b> may include a red pixel, a green pixel, and a blue pixel, but the inventive concept is not restricted to the current embodiment. The pixels <b>111</b> may include a cyan pixel, a yellow pixel, a magenta pixel, or a white pixel.

0043A red pixel may generate a pixel signal (or charges) corresponding to a red signal in response to wavelengths in the red range of the visible spectrum. A green pixel may generate a pixel signal (or charges) corresponding to a green signal in response to wavelengths in the green range of the visible spectrum. A blue pixel may generate a pixel signal (or charges) corresponding to a blue signal in response to wavelengths in the blue range of the visible spectrum.

0044Some of the pixels <b>111</b> may be controlled to have a relatively long exposure time and the rest of the pixels <b>111</b> may be controlled to have a relatively short exposure time. Each of the pixels <b>111</b> may include a first photoelectric conversion element controlled with a long exposure time and a second photoelectric conversion element controlled with a short exposure time. In other words, each of the pixels <b>111</b> may include at least two photoelectric conversion elements.

0045Rows ROW<b>1</b> through ROWn (where “n” is a natural number of at least 4) may respectively include control lines <b>112</b>-<b>1</b> through <b>112</b>-<i>n </i>that control operations of the pixels <b>111</b> arranged in the rows ROW<b>1</b> through ROWn. The row controller <b>120</b> may generate control signals for controlling operations of the pixels <b>111</b> in the rows ROW<b>1</b> through ROWn according to a control of the timing generator <b>160</b>. The row controller <b>120</b> may be a row driver.

0046Bias circuits <b>113</b> may be respectively connected to column lines COL<b>1</b> through COLm (where “m” is a natural number of at least 4). Each of the bias circuits <b>113</b> may function as a constant current source.

0047The amplifier circuit <b>130</b> may receive and amplify pixel signals output from the column lines COL<b>1</b> through COLm. The pixels <b>111</b> arranged in each of the column lines COL<b>1</b> through COLm may be connected to a corresponding one of the column lines COL<b>1</b> through COLm. The amplifier circuit <b>130</b> may include amplifiers <b>130</b>-<b>1</b> through <b>130</b>-<i>m</i>. Each of the amplifiers <b>130</b>-<b>1</b> through <b>130</b>-<i>m </i>may receive and amplify a pixel signal output from one of the column lines COL<b>1</b> through COLm.

0048The ramp signal generator <b>135</b> may generate a ramp signal Vramp that monotonously changes over time from a level corresponding to a maximum count value of counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>to a level corresponding to a minimum count value of the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m</i>, according to a control of the timing generator <b>160</b>. At this time, the ramp signal generator <b>135</b> generates the ramp signal Vramp for the determination from a high code.

0049In addition, the ramp signal generator <b>135</b> may generate a ramp signal Vramp that monotonously changes over time from a level corresponding to a minimum count value of counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>to a level corresponding to a maximum count value of the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>according to the control of the timing generator <b>160</b>. At this time, the ramp signal generator <b>135</b> generates a ramp signal Vramp for the determination from a low code.

0050Although the ramp signal generator <b>135</b> is illustrated and described as an example of a reference signal generator, the reference signal generator is not restricted to the ramp signal generator <b>135</b>. The reference signal generator may be any type of signal generator that can generate a reference signal for the determination from a high or low code. The structure and operations of the ramp signal generator <b>135</b> will be described in detail with reference to <figref idref="DRAWINGS">FIGS. 3 through 6</figref> later.

0051The comparator circuit <b>140</b> may convert analog signals amplified by the amplifier circuit <b>130</b> into digital signals. The comparator circuit <b>140</b> may include comparators <b>140</b>-<b>1</b> through <b>140</b>-<i>m</i>. Each of the comparators <b>140</b>-<b>1</b> through <b>140</b>-<i>m </i>may convert an analog signal output from one of the amplifiers <b>130</b>-<b>1</b> through <b>130</b>-<i>m </i>into a digital signal based on the ramp signal Vramp.

0052Each of the comparators <b>140</b>-<b>1</b> through <b>140</b>-<i>m </i>may output a comparison signal that transits from a first level to a second level when a level of the ramp signal Vramp is equal to a level of an output signal of one of the amplifiers <b>130</b>-<b>1</b> through <b>130</b>-<i>m</i>. A level transition time of the comparison signal may be determined depending on a level of a pixel signal output from one of the pixels <b>111</b>. The first level may be either a high level or a low level and the second level may be the other.

0053The clock signal generator <b>145</b> may generate a clock signal CLK applied to the counter circuit <b>150</b>. Generation timing and frequency of the clock signal CLK may be controlled by the timing generator <b>160</b>. The counter circuit <b>150</b> may include the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>and memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m</i>. Each of the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>may count the level transition time of the comparison signal output from one of the comparators <b>140</b>-<b>1</b> through <b>140</b>-<i>m </i>in response to the clock signal CLK and may output a count value CNTV.

0054Each of the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>may be implemented as an up-counter or a down-counter. It is assumed that the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>are up-counters in the current embodiment. In other words, each of the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>may output the count value CNTV that sequentially increases till the level transition time of the comparison signal and may hold the count value CNTV at the level transition time.

0055However, when the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>are implemented as down-counters, the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>may operate in the manner opposite to the up-counters. The counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>may be implemented as K-bit up-counters, where K is a natural number of at least 2. For instance, the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m </i>may be 10-bit up-counters or 12-bit up-counters but are not restricted thereto.

0056Each of the memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m </i>may store the count value CNTV output from each of the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m</i>. Each of the memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m </i>may be implemented as static random access memory (SRAM), a latch, a flip-flop, or a combination thereof, but the inventive concept is not restricted to the current embodiment. When the count value CNTV is composed of K bits, each of the memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m </i>may store K bits. A clock signal for controlling operations of the memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m </i>may be generated by the clock signal generator <b>145</b> or the timing generator <b>160</b>. The clock signal may be different from the clock signal CLK.

0057The timing generator <b>160</b> may generate control signals for controlling the operations of the row controller <b>120</b>, the ramp signal generator <b>135</b>, the clock signal generator <b>145</b>, the counter circuit <b>150</b>, and the column controller <b>170</b>. The operation of the timing generator <b>160</b> may be controlled according to values stored in the register REG. The values stored in the register REG may be programmed or set by an external device.

0058The column controller <b>170</b> may control an output timing of the count value CNTV stored in each of the memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m </i>according to the control of the timing generator <b>160</b>. The memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m </i>may sequentially output the count value CNTV to the output circuit <b>180</b> according to a control of the column controller <b>170</b>.

0059During the determination from a high code, the output circuit <b>180</b> may receive the count value CNTV from one of the memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m</i>, and may generate a final count value OUT based on the count value CNTV, a maximum reset count value res_max, and a maximum image signal count value sig_max. Operations of the output circuit <b>180</b> will be described in detail with reference to <figref idref="DRAWINGS">FIGS. 5A through 6B</figref>. However, during the determination from a low code, the output circuit <b>180</b> may output the count value CNTV from one of the memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m </i>as the final count value OUT.

0060The maximum reset count value res_max and the maximum image signal count value sig_max may be output from the timing generator <b>160</b>. The maximum reset count value res_max and the maximum image signal count value sig_max may be stored in the register REG that can be accessed by the timing generator <b>160</b>.

0061<figref idref="DRAWINGS">FIG. 2</figref> is a circuit diagram of a pixel <b>111</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref> according to an exemplary embodiment of the inventive concept. Referring to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, the structure and operations are substantially the same or similar among the pixels <b>111</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref>. The pixel <b>111</b> may include one photoelectric conversion element PD and four transistors TX, RX, SF, and SX. According to another exemplary embodiment, the pixel <b>111</b> may include one photoelectric conversion element PD and three or five transistors.

0062The photoelectric conversion element PD may be implemented as a photodiode, a phototransistor, a photogate, or a pinned photodiode. The photoelectric conversion element PD may generate charges (e.g., electrons and/or holes) in response to light coming through a filter. The filter may be a red filter, a green filter, or a blue filter but is not restricted thereto. A reference character Vpix may denote an operating voltage and a reference character VSS may denote a ground voltage.

0063The transfer transistor TX may transfer charges generated by the photoelectric conversion element PD to a floating diffusion region FD in response to a transfer control signal TG. The reset transistor RX may reset the floating diffusion region FD in response to a reset signal RS. The source follower SF may perform source following in response to a voltage corresponding to charges accumulated at the floating diffusion region FD. The select transistor SX may output a signal output from the source follower SF as a pixel signal to a corresponding column line COLi (where 1≦i≦m) in response to a selection signal SEL.

0064Enabling or disabling timings of the control signals TG, RS, and SEL may be controlled by the row controller <b>120</b> controlled by the timing generator <b>160</b>. Enabling may be transition from either a low level or a high level to the other level and disabling may be reverse transition. The control signals TG, RS, and SEL may be transmitted to the pixel <b>111</b> through the control lines <b>112</b>-<b>1</b> through <b>112</b>-<i>n </i>arranged in the respective rows ROW<b>1</b> through ROWn.

0065<figref idref="DRAWINGS">FIG. 3</figref> is a circuit diagram of an example <b>135</b>A of the ramp signal generator <b>135</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref>. Referring to <figref idref="DRAWINGS">FIG. 3</figref>, the ramp signal generator <b>135</b>A may be implemented as a current digital-to-analog (DA) converter type ramp signal generator. For instance, the ramp signal generator <b>135</b>A may generate the ramp signal Vramp using a current mirror. A comparator COMP may compare a reference voltage VREF with a feedback voltage Vfed, and generate a switch signal BP corresponding to a comparison result.

0066Transistors P<b>1</b> through P<b>3</b> included in a biasing branch are connected in series between a first line for supplying an operating voltage VDDA and a first node <b>135</b>-<b>1</b>. A reference resistor Rref is connected between the first node <b>135</b>-<b>1</b> and a second line for the supply of a ground voltage VSSA. A reference current IREF flows across the reference resistor Rref.

0067P-channel metal oxide semiconductor (PMOS) transistors P<b>11</b>, P<b>21</b>, and P<b>31</b> included in a first mirror branch are connected in series between the first line and a second node <b>135</b>-<b>2</b>. PMOS transistors P<b>12</b>, P<b>22</b>, and P<b>32</b> included in a second mirror branch are connected in series between the first line and the second node <b>135</b>-<b>2</b>. PMOS transistors P<b>1</b><i>k</i>, P<b>2</b><i>k</i>, and P<b>3</b><i>k </i>included in a k-th (where “k” is a natural number of at least 3) mirror branch are connected in series between the first line and the second node <b>135</b>-<b>2</b>. A load resistor Rload is connected between the second node <b>135</b>-<b>2</b> and the second line. Although the PMOS transistors P<b>1</b> through P<b>3</b>, P<b>11</b> through P<b>1</b><i>k</i>, P<b>21</b> through P<b>2</b><i>k</i>, and P<b>31</b> through P<b>3</b><i>k </i>are illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, they are just examples.

0068Control signals VCASP, VSW, and VSW<b>1</b> through VSWk may be output from the timing generator <b>160</b>. Enabling timings and disabling timings of the control signals VCASP, VSW, and VSW<b>1</b> through VSWk may be controlled by the timing generator <b>160</b>. It is assumed that biasing signals BP, VCASP and VSW are at a low level. Accordingly, the PMOS transistors P<b>1</b> through P<b>3</b>, P<b>11</b> through P<b>1</b><i>k</i>, and P<b>21</b> through P<b>2</b><i>k </i>may be turned on.

0069In a first case CASE<b>1</b>, the switch signals VSW<b>1</b> through VSWk are at a high level H before a first time point T<b>1</b>, and therefore, the PMOS transistors P<b>31</b> through P<b>3</b><i>k </i>remain in an off-state. When the switch signal VSW<b>1</b> transits from the high level H to a low level L at the first time point T<b>1</b>, only the PMOS transistor P<b>31</b> is turned on. Accordingly, a first mirror current corresponding to the reference current IREF flows in the load resistor Rload through the first mirror branch. As a result, the level of the ramp signal Vramp is determined by the first mirror current and the resistance of the load resistor Rload.

0070When the switch signal VSW<b>2</b> transits from the high level H to the low level L at a second time point T<b>2</b>, the PMOS transistor P<b>32</b> is turned on. Accordingly, a second mirror current corresponding to the reference current IREF flows in the second mirror branch and a current Iload corresponding to the sum of the first mirror current and the second mirror current flows in the load resistor Rload. In other words, the current Iload corresponding to 2×IREF flows in the load resistor Rload. Therefore, the level of the ramp signal Vramp is determined by 2×IREF and the resistance of the load resistor Rload.

0071When the switch signal VSWk transits from the high level H to the low level L at a k-th time point Tk, the PMOS transistor P<b>3</b><i>k </i>is turned on. Accordingly, a k-th mirror current corresponding to the reference current IREF flows in the k-th mirror branch and the current Iload corresponding to a sum of the first through k-th mirror currents flows in the load resistor Rload. In other words, the current Iload corresponding to k×IREF flows in the load resistor Rload. Therefore, the level of the ramp signal Vramp is determined by k×IREF and the resistance of the load resistor Rload.

0072In other words, when the PMOS transistors P<b>31</b> through P<b>3</b><i>k </i>are sequentially turned on, the ramp signal generator <b>135</b>A may generate the ramp signal Vramp that monotonously increases over time. The ramp signal generator <b>135</b>A may generate the ramp signal Vramp that can be used for the determination from a high code. It is assumed that the PMOS transistors P<b>31</b> through P<b>3</b><i>k </i>have the same physical characteristics.

0073In a second case CASE<b>2</b>, the switch signals VSW<b>1</b> through VSWk are at the low level L before the first time point T<b>1</b>, and therefore, the PMOS transistors P<b>31</b> through P<b>3</b><i>k </i>remain in an on-state. In other words, before the first time point T<b>1</b>, the current Iload corresponding to k×IREF flows in the load resistor Rload, and therefore, the level of the ramp signal Vramp is determined by the current Iload (=k×IREF) flowing in the load resistor Rload and the resistance of the load resistor Rload.

0074When the switch signal VSW<b>1</b> transits from the low level L to the high level H at the first time point T<b>1</b>, only the PMOS transistor P<b>31</b> is turned off. Accordingly, the first mirror current corresponding to the reference current IREF is not generated in the first mirror branch. The level of the ramp signal Vramp is determined by the current Iload (=(k−1)×IREF) flowing in the load resistor Rload and the resistance of the load resistor Rload.

0075When the switch signal VSW<b>2</b> transits from the low level L to the high level H at the second time point T<b>2</b>, the PMOS transistor P<b>32</b> is turned off. Accordingly, the second mirror current corresponding to the reference current IREF is not generated in the second mirror branch. The level of the ramp signal Vramp is determined by the current Iload (=(k−2)×IREF) flowing in the load resistor Rload and the resistance of the load resistor Rload.

0076When the switch signal VSWk transits from the low level L to the high level H at the k-th time point Tk, the PMOS transistor P<b>3</b><i>k </i>is turned off. Accordingly, the k-th mirror current corresponding to the reference current IREF is not generated in the k-th mirror branch. The level of the ramp signal Vramp is determined by the current load (=(k−k)×IREF) flowing in the load resistor Rload and the resistance of the load resistor Rload.

0077In other words, when the PMOS transistors P<b>31</b> through P<b>3</b><i>k </i>are sequentially turned off, the ramp signal generator <b>135</b>A may generate the ramp signal Vramp that monotonously decreases over time. The ramp signal generator <b>135</b>A may generate the ramp signal Vramp that can be used for the determination from a low code.

0078As described above with reference to <figref idref="DRAWINGS">FIG. 3</figref>, when the enabling and disabling timings of the switch signals VSW<b>1</b> through VSWk are appropriately adjusted, the ramp signal generator <b>135</b>A may generate the ramp signal Vramp that increases or decreases over time. In addition, when the number of the switch signals VSW<b>1</b> through VSWk enabled and/or disabled is appropriately adjusted, the ramp signal generator <b>135</b>A may adjust the maximum or minimum level of the ramp signal Vramp.

0079<figref idref="DRAWINGS">FIG. 4</figref> is a circuit diagram of another example <b>135</b>B of the ramp signal generator <b>135</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref>. Referring to <figref idref="DRAWINGS">FIG. 4</figref>, the ramp signal generator <b>135</b>B may include an up-ramping ramp signal generator <b>135</b>-<b>1</b>, a down-ramping ramp signal generator <b>135</b>-<b>2</b>, and a selection circuit <b>135</b>-<b>3</b>.

0080The up-ramping ramp signal generator <b>135</b>-<b>1</b> may generate a first ramp signal Uramp which ramps up. The down-ramping ramp signal generator <b>135</b>-<b>2</b> may generate a second ramp signal Dramp which ramps down. Enabling of the up-ramping ramp signal generator <b>135</b>-<b>1</b> and generation timing of the first ramp signal Uramp may be controlled by the timing generator <b>160</b>. Enabling of the down-ramping ramp signal generator <b>135</b>-<b>2</b> and generation timing of the second ramp signal Dramp may also be controlled by the timing generator <b>160</b>.

0081The selection circuit <b>135</b>-<b>3</b> may output either the first ramp signal Uramp or the second ramp signal Dramp as the ramp signal Vramp in response to the selection signal SEL. For instance, when the selection signal SEL is at the low level L or is logic 0, the selection circuit <b>135</b>-<b>3</b> may output the second ramp signal Dramp. The selection circuit <b>135</b>-<b>3</b> may be implemented as a multiplexer. When the selection signal SEL is at the high level H or is logic 1, the selection circuit <b>135</b>-<b>3</b> may output the first ramp signal Uramp. The selection signal SEL may be output from the timing generator <b>160</b>. Information regarding the generation of the selection signal SEL may be programmed or set in the register REG.

0082When there is a request for a low-power operation, the selection signal SEL may be generated at the low level L and the second ramp signal Dramp output from the down-ramping ramp signal generator <b>135</b>-<b>2</b> may be selected as the ramp signal Vramp. When there is a request for a high-speed operation or for the improvement of picture quality, the selection signal SEL may be generated at the high level H and the first ramp signal Uramp output from the up-ramping ramp signal generator <b>135</b>-<b>1</b> may be selected as the ramp signal Vramp.

0083<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are conceptual diagrams for explaining AD conversion performed based on a ramp signal in an image sensor using electrons output from a photoelectric conversion element of a pixel. A pixel signal output from the pixel <b>111</b> may include a reset signal Vrst and an image signal Vsig.

0084A 1-horizontal time may include an auto zero period AUTO ZERO, a reset signal AD conversion (ADC) period RESET ADC, a transfer control signal enabling period TGI, an image signal ADC period SIGNAL ADC, and a horizontal blank period H-BLANK. When a frame rate is Z (where Z is a natural number of at least 2), the 1-horizontal time may be defined as 1/(Z×n), where “n” may be the number of rows in the pixel array <b>110</b>. The 1-horizontal time may refer to a time needed to convert pixel signals corresponding to a line or pixel signals output from pixels in a row from an analog format into a digital format.

0085The auto zero period AUTO ZERO may be a duration (or interval) necessary to determine a decision point of each of the comparators <b>140</b>-<b>1</b> through <b>140</b>-<i>m </i>included in the comparator circuit <b>140</b>. The decision point may be for ADC, and the auto zero period AUTO ZERO may be a duration necessary to store or determine an offset of each of the comparators <b>140</b>-<b>1</b> through <b>140</b>-<i>m</i>. The reset signal ADC period RESET ADC may be a duration in which the reset signal Vrst is converted into a digital signal based on the ramp signal Vramp. The transfer control signal enabling period TGI may be a duration while the transfer control signal TG is enabled. The image signal ADC period SIGNAL ADC may be a duration while the image signal Vsig is converted into a digital signal based on the ramp signal Vramp. The horizontal blank period H-BLANK may be a duration while ADC for the next line is prepared. The reset signal ADC period RESET ADC may be simply referred to as a “reset signal period” and the image signal ADC period SIGNAL ADC may be simply referred to as an “image signal period.

0086<figref idref="DRAWINGS">FIG. 5A</figref> illustrates an example of the determination from a low code. “OFFSET” may denote an offset of the ramp signal Vramp. The counter <b>150</b>-<b>1</b> may generically refer to the counters <b>150</b>-<b>1</b> through <b>150</b>-<i>m</i>, and the memory <b>152</b>-<b>1</b> may generically refer to the memories <b>152</b>-<b>1</b> through <b>152</b>-<i>m</i>. A reference character C1 may denote the maximum cycle of the clock signal CLK applied to the counter <b>150</b>-<b>1</b> during the reset signal ADC period RESET ADC and “C1+C2” may denote the maximum cycle of the clock signal CLK applied to the counter <b>150</b>-<b>1</b> during the image signal ADC period SIGNAL ADC. When C1 is 256, C2 may be 1024, but these are just examples.

0087Referring to <figref idref="DRAWINGS">FIG. 5A</figref>, the ramp signal generator <b>135</b> may output the ramp signal Vramp that (monotonously) decreases over time from a second level corresponding to a minimum reset count value res_min of the counter <b>150</b>-<b>1</b> down to a first level corresponding to a maximum reset count value res_max of the counter <b>150</b>-<b>1</b> during the reset signal ADC period RESET ADC. At this time, the ramp signal Vramp is referred to as a down-ramping ramp signal or a ramp signal for the determination from a low code. A down-ramping ramp signal may be generated according to the second case CASE<b>2</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref> or may be generated by the down-ramping ramp signal generator <b>135</b>-<b>2</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref>.

0088The counter <b>150</b>-<b>1</b> may generate the count value CNTV that increases sequentially from “0” to “A” in response to the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> until the level of the reset signal Vrst is equal to the level of the ramp signal Vramp. The memory <b>152</b>-<b>1</b> may store “A” as the count value CNTV generated by the counter <b>150</b>-<b>1</b>. In other words, when the level of the reset signal Vrst is the same as the level of the ramp signal Vramp, the counter <b>150</b>-<b>1</b> may hold “A” as the count value CNTV.

0089The pixel <b>111</b> may output a pixel signal corresponding to the image signal Vsig during the transfer control signal enabling period TGI. The counter <b>150</b>-<b>1</b> or the memory <b>152</b>-<b>1</b> may generate “−A”, i.e., ones' complement of “A”, during the transfer control signal enabling period TGI. A method of generating “−A” in the image sensor <b>100</b> may be variously modified in different embodiments.

0090The ramp signal generator <b>135</b> may output the ramp signal Vramp that (monotonously) decreases over time from a fourth level corresponding to a minimum image signal count value sig_min of the counter <b>150</b>-<b>1</b> down to a third level corresponding to a maximum image signal count value sig_max of the counter <b>150</b>-<b>1</b> during the image signal ADC period SIGNAL ADC. In other words, the ramp signal generator <b>135</b> may output the ramp signal Vramp that can be used for the determination from a low code. Here, according to an exemplary embodiment, the ramp signal Vramp may be a single reference signal that changes over time between the second, first, fourth and third levels during the reset signal ADC period RESET ADC through the image signal ADC period SIGNAL ADC in the case of <figref idref="DRAWINGS">FIG. 5A</figref>. However, according to another exemplary embodiment, the ramp signal generator <b>135</b> may output two different ramp signals, one changing between the second and first levels during the reset signal ADC period RESET ADC, and another changing between the fourth and third levels during the image signal ADC period SIGNAL ADC in the case of <figref idref="DRAWINGS">FIG. 5A</figref>.

0091The counter <b>150</b>-<b>1</b> may generate the count value CNTV that increases sequentially from “−A” to “B” in response to the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> until the level of the image signal Vsig is equal to the level of the ramp signal Vramp. The memory <b>152</b>-<b>1</b> may store a count value corresponding to “−A+B” as the count value CNTV. Accordingly, the output circuit <b>180</b> may output the final count value OUT (=B−A).

0092The image sensor <b>100</b> using single-slope ADC may perform ADC sequentially from a low code, as shown in <figref idref="DRAWINGS">FIG. 5A</figref>. Nonlinearity of a low code region may be amplified and increased due to gamma gain or the like.

0093It takes a lot of time for an output signal of the comparator <b>140</b>-<b>1</b> or a pixel signal of the pixel <b>111</b> to be stabilized right after the auto zero period AUTO ZERO (or right before the reset signal ADC period RESET ADC) or right after the transfer control signal enabling period TGI (or right before the image signal ADC period SIGNAL ADC). When ADC is performed on the pixel signal of the pixel <b>111</b> in a state where the output signal of the comparator <b>140</b>-<b>1</b> or the pixel signal of the pixel <b>111</b> has not been stabilized, a nonlinear ADC value may be output from the low code region. In <figref idref="DRAWINGS">FIGS. 5A and 5B</figref>, “NLR” denotes a nonlinear region.

0094<figref idref="DRAWINGS">FIG. 5B</figref> illustrates an example of the determination from a high code. Referring to <figref idref="DRAWINGS">FIG. 5B</figref>, the ramp signal generator <b>135</b> may output the ramp signal Vramp that (monotonously) increases over time from the first level corresponding to the maximum reset count value res_max of the counter <b>150</b>-<b>1</b> up to the second level corresponding to the minimum reset count value res_min of the counter <b>150</b>-<b>1</b> during the reset signal ADC period RESET ADC. At this time, the ramp signal Vramp is referred to as an up-ramping ramp signal or a ramp signal for the determination from a high code. An up-ramping ramp signal may be generated according to the first case CASE<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref> or may be generated by the up-ramping ramp signal generator <b>135</b>-<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref>.

0095The counter <b>150</b>-<b>1</b> may generate the count value CNTV that increases sequentially from “0” to “A′” in response to the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> until the level of the reset signal Vrst is equal to the level of the ramp signal Vramp. The memory <b>152</b>-<b>1</b> may store “A′” as the count value CNTV generated by the counter <b>150</b>-<b>1</b>.

0096The pixel <b>111</b> may output a pixel signal corresponding to the image signal Vsig during the transfer control signal enabling period TGI. The counter <b>150</b>-<b>1</b> or the memory <b>152</b>-<b>1</b> may generate “−A′”, i.e., ones' complement of “A′”, during the transfer control signal enabling period TGI. A method of generating “−A′” in the image sensor <b>100</b> may be variously modified in different embodiments.

0097The ramp signal generator <b>135</b> may output the ramp signal Vramp that (monotonously) increases over time from the third level corresponding to the maximum image signal count value sig_max of the counter <b>150</b>-<b>1</b> up to the fourth level corresponding to the minimum image signal count value sig_min of the counter <b>150</b>-<b>1</b> during the image signal ADC period SIGNAL ADC. In other words, the ramp signal generator <b>135</b> may output the ramp signal Vramp that can be used for the determination from a high code. Here, according to an exemplary embodiment, the ramp signal Vramp may be a single reference signal that changes over time between the first, second, third and fourth levels during the reset signal ADC period RESET ADC through the image signal ADC period SIGNAL ADC in the case of <figref idref="DRAWINGS">FIG. 5B</figref>. However, according to another exemplary embodiment, the ramp signal generator <b>135</b> may output two different ramp signals, one changing between the first and second levels during the reset signal ADC period RESET ADC, and another changing between the third and fourth levels during the image signal ADC period SIGNAL ADC in the case of <figref idref="DRAWINGS">FIG. 5B</figref>.

0098The counter <b>150</b>-<b>1</b> may generate the count value CNTV that increases sequentially from “−A′” to “B′” in response to the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> until the level of the image signal Vsig is equal to the level of the ramp signal Vramp. The memory <b>152</b>-<b>1</b> may store a count value corresponding to “−A′+B′” as the count value CNTV.

0099During the determination from a high code, the output circuit <b>180</b> may calculate a second difference sig_max-B′ between the maximum image signal count value sig_max and the count value B′, may calculate a first difference res_max-A′ between the maximum reset count value res_max and the count value A′, and may output the final count value OUT corresponding to a difference between the second difference sig_max-B′ and the first difference res_max-A′. The first difference res_max-A′ may refer to a reset count value and the second difference sig_max-B′ may refer to an image signal count value. Referring to <figref idref="DRAWINGS">FIG. 5B</figref>, the comparator <b>140</b>-<b>1</b> performs ADC starting from a high code, so that noise characteristics occurring in the low code region are improved.

0100<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are conceptual diagrams for explaining ADC performed based on a ramp signal in an image sensor using holes output from a photoelectric conversion element of a pixel. <figref idref="DRAWINGS">FIG. 6A</figref> illustrates an example of the determination from a low code.

0101Referring to <figref idref="DRAWINGS">FIG. 6A</figref>, the ramp signal generator <b>135</b> may output the ramp signal Vramp that (monotonously) increases over time from the second level corresponding to the minimum reset count value res_min of the counter <b>150</b>-<b>1</b> to the first level corresponding to the maximum reset count value res_max of the counter <b>150</b>-<b>1</b> during the reset signal ADC period RESET ADC. At this time, the ramp signal Vramp is referred to as an up-ramping ramp signal or a ramp signal for the determination from a low code. An up-ramping ramp signal may be generated according to the first case CASE<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref> or may be generated by the up-ramping ramp signal generator <b>135</b>-<b>1</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref>.

0102The counter <b>150</b>-<b>1</b> may generate the count value CNTV that increases sequentially from “0” to “A” in response to the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> until the level of the reset signal Vrst is equal to the level of the ramp signal Vramp. The memory <b>152</b>-<b>1</b> may store “A” as the count value CNTV generated by the counter <b>150</b>-<b>1</b>. In other words, when the level of the reset signal Vrst is the same as the level of the ramp signal Vramp, the counter <b>150</b>-<b>1</b> may hold “A” as the count value CNTV.

0103The pixel <b>111</b> may output a pixel signal corresponding to the image signal Vsig during the transfer control signal enabling period TGI. The counter <b>150</b>-<b>1</b> or the memory <b>152</b>-<b>1</b> may generate “−A”, i.e., ones' complement of “A”, during the transfer control signal enabling period TGI. A method of generating “−A” in the image sensor <b>100</b> may be variously modified in different embodiments.

0104The ramp signal generator <b>135</b> may output the ramp signal Vramp that (monotonously) increases over time from the fourth level corresponding to the minimum image signal count value sig_min of the counter <b>150</b>-<b>1</b> to the third level corresponding to the maximum image signal count value sig_max of the counter <b>150</b>-<b>1</b> during the image signal ADC period SIGNAL ADC. In other words, the ramp signal generator <b>135</b> may output the ramp signal Vramp that can be used for the determination from a low code.

0105The counter <b>150</b>-<b>1</b> may generate the count value CNTV that increases sequentially from “−A” to “B” in response to the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> until the level of the image signal Vsig is equal to the level of the ramp signal Vramp. The memory <b>152</b>-<b>1</b> may store a count value corresponding to “−A+B” as the count value CNTV. Accordingly, the output circuit <b>180</b> may output the final count value OUT (=B−A).

0106<figref idref="DRAWINGS">FIG. 6B</figref> illustrates an example of the determination from a high code. Referring to <figref idref="DRAWINGS">FIG. 6B</figref>, the ramp signal generator <b>135</b> may output the ramp signal Vramp that (monotonously) decreases over time from the first level corresponding to the maximum reset count value res_max of the counter <b>150</b>-<b>1</b> to the second level corresponding to the minimum reset count value res_min of the counter <b>150</b>-<b>1</b> during the reset signal ADC period RESET ADC. At this time, the ramp signal Vramp is referred to as a down-ramping ramp signal or a ramp signal for the determination from a high code. A down-ramping ramp signal may be generated according to the second case CASE<b>2</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref> or may be generated by the down-ramping ramp signal generator <b>135</b>-<b>2</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref>.

0107The counter <b>150</b>-<b>1</b> may generate the count value CNTV that increases sequentially from “0” to “A′” in response to the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> until the level of the reset signal Vrst is equal to the level of the ramp signal Vramp. The memory <b>152</b>-<b>1</b> may store “A′” as the count value CNTV generated by the counter <b>150</b>-<b>1</b>.

0108The pixel <b>111</b> may output a pixel signal corresponding to the image signal Vsig during the transfer control signal enabling period TGI. The counter <b>150</b>-<b>1</b> or the memory <b>152</b>-<b>1</b> may generate “−A′”, i.e., ones' complement of “A′”, during the transfer control signal enabling period TGI.

0109The ramp signal generator <b>135</b> may output the ramp signal Vramp that (monotonously) decreases over time from the third level corresponding to the maximum image signal count value sig_max of the counter <b>150</b>-<b>1</b> to the fourth level corresponding to the minimum image signal count value sig_min of the counter <b>150</b>-<b>1</b> during the image signal ADC period SIGNAL ADC. In other words, the ramp signal generator <b>135</b> may output the ramp signal Vramp that can be used for the determination from a high code.

0110The counter <b>150</b>-<b>1</b> may generate the count value CNTV that increases sequentially from “−A′” to “B′” in response to the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> until the level of the image signal Vsig is equal to the level of the ramp signal Vramp. The memory <b>152</b>-<b>1</b> may store a count value corresponding to “−A′+B′” as the count value CNTV.

0111During the determination from a high code, the output circuit <b>180</b> may calculate the second difference sig_max-B′ between the maximum image signal count value sig_max and the count value B′, may calculate the first difference res_max-A′ between the maximum reset count value res_max and the count value A′, and may output the final count value OUT corresponding to a difference between the second difference sig_max-B′ and the first difference res_max-A′.

0112<figref idref="DRAWINGS">FIG. 7</figref> is a flowchart of a method of operating the image sensor <b>100</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref> according to an exemplary embodiment of the inventive concept. The operations of the image sensor <b>100</b> determining from a high code will be described with reference to <figref idref="DRAWINGS">FIGS. 1 through 7</figref>.

0113The ramp signal generator <b>135</b> may generate the ramp signal Vramp that changes from the first level corresponding to the maximum reset count value res_max to the second level corresponding to the minimum reset count value res_min during the reset signal ADC period RESET ADC in operation S<b>110</b>.

0114As shown in <figref idref="DRAWINGS">FIG. 5B</figref>, the ramp signal generator <b>135</b> may generate the ramp signal Vramp that (monotonously) increases over time from the first level corresponding to the maximum reset count value res_max to the second level corresponding to the minimum reset count value res_min in operation S<b>110</b>. As shown in <figref idref="DRAWINGS">FIG. 6B</figref>, the ramp signal generator <b>135</b> may generate the ramp signal Vramp that (monotonously) decreases over time from the first level corresponding to the maximum reset count value res_max to the second level corresponding to the minimum reset count value res_min in operation S<b>110</b>.

0115The counter <b>150</b>-<b>1</b> may generate a first count value of A′ based on the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b>, and the memory <b>152</b>-<b>1</b> may store the first count value A′ in operation S<b>112</b>.

0116The ramp signal generator <b>135</b> may generate the ramp signal Vramp that changes from the third level corresponding to the maximum image signal count value sig_max to the fourth level corresponding to the minimum image signal count value sig_min during the image signal ADC period SIGNAL ADC in operation S<b>114</b>.

0117As shown in <figref idref="DRAWINGS">FIG. 5B</figref>, the ramp signal generator <b>135</b> may generate the ramp signal Vramp that (monotonously) increases over time from the third level corresponding to the maximum image signal count value sig_max to the fourth level corresponding to the minimum image signal count value sig_min in operation S<b>114</b>. As shown in <figref idref="DRAWINGS">FIG. 6B</figref>, the ramp signal generator <b>135</b> may generate the ramp signal Vramp that (monotonously) decreases over time from the third level corresponding to the maximum image signal count value sig_max to the fourth level corresponding to the minimum image signal count value sig_min in operation S<b>114</b>.

0118The counter <b>150</b>-<b>1</b> may generate a second count value of B′ based on the clock signal CLK and a comparison signal output from the comparator <b>140</b>-<b>1</b> and the memory <b>152</b>-<b>1</b> may store the second count value B′ in operation S<b>116</b>. According to an exemplary embodiment, the counter <b>150</b>-<b>1</b> may also generate a third count value of −A′+B′ corresponding to a difference between the first count value A′ and the second count value B′, and the memory <b>152</b>-<b>1</b> may store the third count value of −A′+B′ in operation S<b>118</b>.

0119The output circuit <b>180</b> may calculate the second difference sig_max-B′ between the maximum image signal count value sig_max and the second count value B′ and the first difference res_max-A′ between the maximum reset count value res_max and the first count value A′ in operation S<b>120</b>. The output circuit <b>180</b> may generate the final count value OUT corresponding to the difference between the second difference sig_max-B′ and the first difference res_max-A′ in operation S<b>122</b>.

0120<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart of an operation of the ramp signal generator <b>135</b> illustrated in <figref idref="DRAWINGS">FIG. 3</figref>. Referring to <figref idref="DRAWINGS">FIGS. 1 and 3</figref>, <figref idref="DRAWINGS">FIGS. 5A through 6B</figref>, and <figref idref="DRAWINGS">FIG. 8</figref>, whether to generate an up-ramping ramp signal or a down-ramping ramp signal may be determined in operation S<b>210</b>. In other words, the ramp signal generator <b>135</b> may generate a ramp signal used for the determination from a low code or a ramp signal used for the determination from a high code according to the control of the timing generator <b>160</b> in operation S<b>210</b>.

0121The ramping direction may be manually set by a user in operation S<b>210</b>-<b>1</b>. The user may set the ramping direction using an application program APP executed by an application processor (e.g., <b>230</b>A in <figref idref="DRAWINGS">FIG. 10</figref> of <b>230</b>B in <figref idref="DRAWINGS">FIG. 11</figref>). For instance, when a user wants a low-power operation, the user may select a user input using the application program APP so that a ramp signal used for the determination from a high or low code is generated. Information corresponding to the user input may be programmed or set in the register REG of the image sensor <b>100</b>.

0122Alternatively, the ramping direction may be automatically set based on brightness information in operation S<b>210</b>-<b>2</b>. An image signal processor <b>220</b> shown in <figref idref="DRAWINGS">FIG. 10 or 11</figref> may extract brightness information about image data based on the image data output from the image sensor <b>100</b>, and may set the ramping direction according to the extraction result. Information about the ramping direction may be programmed or set by the image signal processor <b>220</b> in the register REG of the image sensor <b>100</b>.

0123As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the timing generator <b>160</b> may generate the control signals VCASP and VSW and the switch signals VSW<b>1</b> through VSWk for controlling the operation of the ramp signal generator <b>135</b> based on values stored in the register REG in operation S<b>220</b>.

0124When the switch signals VSW<b>1</b> through VSWk are sequentially turned off (in case of YES) in operation S<b>230</b>, the ramp signal generator <b>135</b> may generate the ramp signal Vramp that ramps from a level corresponding to the minimum count value res_min or sig_min of the counter <b>150</b>-<b>1</b> according to the second case CASE<b>2</b> in <figref idref="DRAWINGS">FIG. 3</figref> in operation S<b>240</b>. However, when the switch signals VSW<b>1</b> through VSWk are sequentially turned on (in case of NO) in operation S<b>230</b>, the ramp signal generator <b>135</b> may generate the ramp signal Vramp that ramps from a level corresponding to the maximum count value res_max or sig_max of the counter <b>150</b>-<b>1</b> according to the second case CASE<b>1</b> in <figref idref="DRAWINGS">FIG. 3</figref> in operation S<b>250</b>.

0125<figref idref="DRAWINGS">FIG. 9</figref> is a flowchart of a method of operating the image sensor <b>100</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, which includes the ramp signal generator <b>135</b>B illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, according to an exemplary embodiment of the inventive concept.

0126Referring to <figref idref="DRAWINGS">FIGS. 1, 4, 5A, 5B, and 9</figref>, the selection circuit <b>135</b>-<b>3</b> selects either the first ramp signal generator <b>135</b>-<b>1</b> which ramps from a level corresponding to the maximum count value res_max or sig_max of the counter <b>150</b>-<b>1</b> or the second ramp signal generator <b>135</b>-<b>2</b> which ramps from a level corresponding to the minimum count value res_min or sig_min of the counter <b>150</b>-<b>1</b> in operation <b>5310</b>. The selection circuit <b>135</b>-<b>3</b> outputs the ramp signal Uramp or Dramp output from the selected ramp signal generator <b>135</b>-<b>1</b> or <b>135</b>-<b>2</b> as the ramp signal Vramp. The AD converter circuit including the comparator circuit <b>140</b> and the counter circuit <b>150</b> may convert pixel signals output from the pixel array <b>110</b> into digital signals using the ramp signal Vramp output from the selection circuit <b>135</b>-<b>3</b> in operation <b>5320</b>.

0127<figref idref="DRAWINGS">FIG. 10</figref> is a block diagram of a computing device <b>200</b>A including the image sensor <b>100</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref> according to an exemplary embodiment of the inventive concept. Referring to <figref idref="DRAWINGS">FIGS. 1 through 10</figref>, the computing device <b>200</b>A may be a mobile computing device. The mobile computing device may be implemented as a laptop computer, a cellular phone, a smart phone, tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, a mobile internet device (MID), a wearable computer, an internet of things (IoT) device, an internet of everything (IoE) device, or an e-book.

0128The computing device <b>200</b>A may include a camera <b>210</b> including the image sensor <b>100</b>, the image signal processor (ISP) <b>220</b>, a controller <b>230</b>A, a modem <b>240</b>, a radio frequency (RF) transceiver <b>245</b>, a memory <b>250</b>, and a display <b>262</b> including a touch screen <b>260</b>. The image sensor <b>100</b> may be the one described with reference to <figref idref="DRAWINGS">FIGS. 1 through 9</figref> above.

0129The camera <b>210</b> may generate image data using the image sensor <b>100</b>. The ISP <b>220</b> may process the image data and output the processed image data to the controller <b>230</b>A. The ISP <b>220</b> may convert image data from a first format into a second format. The first format may be a Bayer pattern and the second format may be a YUV format or RGB format, but the inventive concept is not restricted the current embodiments.

0130The ISP <b>220</b> may generate brightness information based on image data output from the image sensor <b>100</b>, and may set the brightness information in the register REG of the image sensor <b>100</b>. The RF transceiver <b>245</b> may transmit RF data received through an antenna ANT to the modem <b>240</b>. The RF transceiver <b>245</b> may also convert data output from the modem <b>240</b> into RF data, and transmit the RF data to an external device through the antenna ANT. The modem <b>240</b> may process data transferred between the RF transceiver <b>245</b> and the controller <b>230</b>A.

0131The controller <b>230</b>A may control the camera <b>210</b>, the ISP <b>220</b>, the modem <b>240</b>, the RF transceiver <b>245</b>, the memory <b>250</b>, the touch screen <b>260</b>, and/or the display <b>262</b>. The controller <b>230</b>A may be implemented as an integrated circuit (IC), a system on chip (SoC), an application processor (AP), or a mobile AP. The controller <b>230</b>A may include a bus architecture <b>231</b>, an interface <b>232</b>, a modem interface <b>233</b>, a central processing unit (CPU) <b>234</b>, a memory controller <b>236</b>, and a display controller <b>238</b>.

0132The CPU <b>234</b> may control the interface <b>232</b>, the modem interface <b>233</b>, the memory controller <b>236</b>, and the display controller <b>238</b> via the bus architecture <b>231</b>. The CPU <b>234</b> may execute the application program APP to select the determination from a low code or the determination from a high code.

0133A graphics user interface produced by the application program APP may be displayed on the display <b>262</b>. A user may select the graphics user interface corresponding to the determination from a low code or the determination from a high code using the touch screen <b>260</b>. Information selected by the user may be transmitted to the CPU <b>234</b> and the CPU <b>234</b> may set the selected information in the register REG of the image sensor <b>100</b>.

0134The bus architecture <b>231</b> may be implemented as advanced microcontroller bus architecture (AMBA), an advanced high-performance bus (AHB), an advanced peripheral bus (APB), an advanced extensible interface (AXI), or an advanced system bus (ASB), but the inventive concept is not restricted to the current embodiments.

0135The interface <b>232</b> may transmit image data from the ISP <b>220</b> to the bus architecture <b>231</b>. The image data may be transmitted to the memory controller <b>236</b> or the display controller <b>238</b>. The modem interface <b>233</b> may control processing and/or transmission of data communicated with the modem <b>240</b> according to the control of the CPU <b>234</b>. The memory controller <b>236</b> may control an access operation on the memory <b>250</b> according to the control of the CPU <b>234</b>. The access operation may include a write operation for writing data to the memory <b>250</b> and a read operation for reading data from the memory <b>250</b>.

0136The memory <b>250</b> may include volatile memory and/or non-volatile memory. Although one memory controller <b>236</b> and one memory <b>250</b> are illustrated in <figref idref="DRAWINGS">FIG. 10</figref> for clarity of the description, the memory controller <b>236</b> may refer to a group of memory controllers that control different types of memory devices. The memory <b>250</b> may refer to a group of different types of memory devices.

0137The memory <b>250</b> may be formed with dynamic random access memory (DRAM). The memory <b>250</b> may be flash-based memory such as NAND-type flash memory, NOR-type flash memory, multimedia card (MMC), embedded MMC (eMMC), or universal flash storage (UFS), but the inventive concept is not restricted to these examples.

0138The display controller <b>238</b> may transmit data to be displayed on the display <b>262</b> to the display <b>262</b> according to the control of the CPU <b>234</b>. The display controller <b>238</b> and the display <b>262</b> may communicate data with each other using mobile industry processor interface (MIPI) display serial interface or embedded DisplayPort (eDP).

0139The touch screen <b>260</b> may transmit a user input for controlling the operation of the computing device <b>200</b>A to the controller <b>230</b>A. The user input may be generated when a user touches the touch screen <b>260</b>. The CPU <b>234</b> may control the operation of the image sensor <b>100</b>, the camera <b>210</b>, the controller <b>230</b>A, the memory <b>250</b>, and/or the display <b>262</b> according to the user input transmitted from the touch screen <b>260</b>.

0140<figref idref="DRAWINGS">FIG. 11</figref> is a block diagram of a computing device <b>200</b>B including the image sensor <b>100</b> illustrated in <figref idref="DRAWINGS">FIG. 1</figref> according to another exemplary embodiment of the inventive concept. Apart from the ISP <b>220</b> and the interface <b>232</b>, the structure and operations of the computing device <b>200</b>B including a controller <b>230</b>B illustrated in <figref idref="DRAWINGS">FIG. 11</figref> are substantially the same as or similar to those of the computing device <b>200</b>A including the controller <b>230</b>B illustrated in <figref idref="DRAWINGS">FIG. 10</figref>.

0141The ISP <b>220</b> may be included within the controller <b>230</b>B in the embodiments illustrated in <figref idref="DRAWINGS">FIG. 11</figref>. The ISP <b>220</b> may receive and process image data from the image sensor <b>100</b>, and may transmit the processed image data to the bus architecture <b>231</b>. The image sensor <b>100</b> and the controller <b>230</b>B may communicate data with each other using MIPI camera serial interface.

0142As described above, according to the exemplary embodiments of the inventive concept, an image sensor is able to determine ADC on a pixel signal output from a pixel from a high code, thereby improving nonlinearity in a low code region, operating in high speed, and increasing the quality of pictures. In addition, noise characteristics in the low code region are improved.

0143While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in forms and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.