Semiconductor package structure and manufacturing method thereof

FIELD

0001The present disclosure relates to a semiconductor package structure, and more specifically to a structure of a chip on wafer on substrate.

BACKGROUND

0002A significant trend throughout integrated circuit (IC) development is the downsizing of IC components. These integration improvements are two-dimensional (2D) in nature where the ICs are integrated on a surface of a semiconductor wafer. Although dramatic improvement in lithography has enabled greater results in 2D IC formation, there are physical limits to the density that can be achieved in two dimensions. Also, when more devices are put into one chip, more complex design costs are required.

0003In an attempt to further increase circuit density, three-dimensional (3D) ICs have been developed. For example, two dies are bonded together; and electrical connections are formed between each die. The stacked dies are then bonded to a carrier substrate by using wire bonds and conductive pads. In another example, a chip on (chip on substrate) (Co(CoS)) or (Chip on wafer) on substrate ((CoW)oS) technique is developed.

0004However, conductive bumps adjacent to edges or corners of an interposer or dies can result in cracking during cooling down or a stressing test. During cooling down of chip joints, conductive bumps disposed between the interposer and the circuit board are subject to shearing and stress, which results from the different thermal expansion due to different thermal coefficients.

BRIEF DESCRIPTION OF THE DRAWINGS

0005Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

0006<figref idref="DRAWINGS">FIGS. 1-4</figref> represent a method of manufacturing a semiconductor package structure in accordance with some embodiments of the present disclosure.

0007<figref idref="DRAWINGS">FIGS. 5A-5C</figref> depict a top view and a cross-sectional view of a configuration of a polymeric layer in accordance with some embodiments of the present disclosure.

0008<figref idref="DRAWINGS">FIG. 6</figref> represents a semiconductor package structure in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

0009The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

0010Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

0011The terms “wafer” and “substrate,” as used herein, are to be understood as including silicon, silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous processing steps may have been utilized to form regions, junctions, or material layers in or over the base semiconductor structure or foundation. In addition, the semiconductor does not need to be silicon-based, but could be based on silicon-germanium, germanium, gallium arsenide or other semiconductor structures.

0012The terms “deposition” and “deposit,” as used herein, refer to operations of depositing materials on a substrate using a vapor phase of a material to be deposited, a precursor of the material, and an electrochemical reaction or sputtering/reactive sputtering. Depositions using a vapor phase of a material include any operations such as, but not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). Examples of vapor deposition methods include hot filament CVD, rf-CVD, laser CVD (LCVD), conformal diamond coating operations, metal-organic CVD (MOCVD), thermal evaporation PVD, ionized metal PVD (IMPVD), electron beam PVD (EBPVD), reactive PVD, atomic layer deposition (ALD), plasma enhanced CVD (PECVD), high density plasma CVD (HDPCVD), low pressure CVD (LPCVD), and the like. Examples of deposition using an electrochemical reaction include electroplating, electro-less plating, and the like. Other examples of deposition include pulse laser deposition (PLD) and atomic layer deposition (ALD).

0013A current common requirement for an advanced electronic circuit is the use of multiple integrated circuit devices (“dies”) integrated in a single packaged component. As such, the configuration of a three-dimensional package is developed; for example, chip on substrate (CoS) or chip-on-wafer-on-substrate (CoWoS) techniques. The integrated circuit dies with different functions are mounted to a wafer by using conductive bumps, such as micro bumps. A thermal reflow step is performed to complete the mechanical and electrical connection between the dies and the wafer by melting and reflowing the solder balls or bumps. The integrated circuit dies communicate with each other through the redistribution layer (“RDL) or conductors within the wafer. In addition, the integrated circuit dies are coupled with conductive bumps of the opposite side of the wafer by through substrate vias. The conductive bumps of the opposite side of the wafer are larger than the conductive bumps between the IC dies and the wafer, which refers to “ball grid array” or controlled collapse chip connection (C4) bumps. After the IC dies are mounted to the wafer and the C4 bumps are prepared, a singulation process is performed on the wafer to form pieces of interposers stacked with IC dies. During the singulation performed on wafers, the interposers are diced as rectangular shapes with edges and corners. Later, the interposers are mounted on a circuit board by using the C4 bumps. The IC dies thus are able to receive and transmit signals from outer devices by the chip-on-wafer-on-substrate package. As the amount and complexity of the dies mounted in such a package increase, the multi-chip package can achieve the configuration of a system on a chip (SoC).

0014However, since there is a thermal mismatch between the interposer and the circuit board, the conductive bumps are subject to damages caused by the physical stress of different temperature coefficients. During mounting processes, the stack of the interposer and the circuit board is heated and cooled down repeatedly in a thermal cycling. Since the interposer has a temperature coefficient different from that of the circuit board, the different temperature coefficients cause different thermal expansion. The different thermal expansion causes physical stress on the conductive bumps, underfill layer and underlying laminates. Particularly, the conductive bumps and underlying dielectric materials adjacent to the corners/edges of the interposer are subject to serious stress, which causes conductive bump cracks and dielectric film delamination. Sometimes, the underfill material adjacent to the corners/edges also suffers from the stress, thus causing an underfill delamination, which exacerbates the delamination problem. The present disclosure provides a semiconductor package structure and a method thereof to protect a CoWoS package from conductive bump cracks or dielectric film delamination during thermal cycling or reliability stressing. The semiconductor package structure has a polymeric layer on the corner/edge regions as a stress buffer.

0015<figref idref="DRAWINGS">FIGS. 1-6</figref> represent a method of manufacturing a semiconductor package structure in accordance with some embodiments of the present disclosure. Each figure represents a stage of the method in a cross-sectional perspective view.

0016Referring to <figref idref="DRAWINGS">FIG. 1</figref>, several dies <b>10</b> are positioned to mount on a wafer <b>30</b>, which refers to a chip-on-wafer process. Each die <b>10</b> has terminals <b>12</b>, which refer to conductive pads or bond pads. A dielectric layer <b>13</b> or a passivation layer is deposited on the terminals <b>12</b> by chemical vapor deposition (CVD) and physical vapor deposition (PVD). Later, lithography and etching processes are performed to expose the terminals <b>12</b>, thus forming an opening. An under bump metallization (UBM) layer is deposited on the terminals <b>12</b> and then patterned to form the UBM <b>14</b>, which is also referred to as ball-limiting metallurgy (BLM). The UBM <b>14</b> defines a size of a conductive bump after reflow and reacts with the conductive bump so as to provide effective adhesion and a barrier between the conductive bump and underlying wirings. As such, the UBM <b>14</b> provides additional adhesion between the terminals <b>12</b> and conductive bumps <b>15</b> and increases solderability. Materials of the UBM <b>14</b> include, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), copper alloys, nickel (Ni), tin (Sn), gold (Au), or combinations thereof. The conductive bumps <b>15</b> are formed on the UBM <b>14</b> by evaporation or an electroplating process. Further, the dies <b>10</b> are chosen and put together for certain functions and include, for example, microprocessor devices with program memory storage such as FLASH or EEPROM devices, or microprocessors with application specific processors such as baseband transceivers, graphics processors, cache memory devices, memory management devices, and analog to digital converters for sensor applications.

0017The wafer <b>30</b> herein is made of, for example, silicon or other suitable materials such as ceramic, glass, plastic, resin or epoxy. The wafer <b>30</b> includes through substrate vias (TSVs) <b>32</b> extending from a first surface <b>31</b> to a second surface <b>33</b>, wherein the TSVs <b>32</b> are also regarded as through interposer vias (TIV) if the wafer <b>30</b> is diced. A carrier <b>21</b> is formed in contact with a second surface <b>33</b>, which is temporary and made of any strippable or easily removed material, for example, films, tapes, liquid adhesives and the like. The carrier <b>21</b> holds and supports the wafer <b>30</b> during the following processes. A redistribution layer (RDL) <b>34</b> formed in contact with the first surface <b>31</b> includes patterned conductors <b>35</b> and a dielectric layer <b>36</b>. The dielectric layer <b>36</b> is made of dielectric material for insulating the wiring including, for example, oxide or nitride. The patterned conductors <b>35</b> are arranged as horizontal and vertical portions so as to remap a layout for the dies <b>10</b>. Further, the patterned conductors <b>35</b> are coupled with the TSVs <b>32</b> in order to create an electrical connection. The patterned conductors <b>35</b> are made of conductive material suitable for interconnection, for example, copper or tungsten. By using the RDL <b>34</b>, changes of the dies <b>10</b> or the conductive bump patterns are made without modifying the system board since the dies <b>10</b> are allowed to communicate each other through the RDL <b>34</b>. The RDL <b>34</b> thus is able to change the layout of new dies or new bump patterns for particular functions. This flexibility saves cost and allows any changes of dies or die vendors.

0018A conductive layer is formed on the RDL <b>34</b> and then patterned to form conductive pads <b>37</b>. Later, a dielectric layer <b>38</b> is deposited on the RDL <b>34</b> and the conductive pads <b>37</b> by chemical vapor deposition (CVD) and physical vapor deposition (PVD). Later, lithography and etching processes are performed to expose the conductive pads <b>37</b>, thus forming openings. An under bump metallization (UBM) layer is deposited on the conductive pads <b>37</b> and then patterned to form the UBM <b>39</b>. The UBM <b>39</b> is in contact with the conductive pads <b>37</b> and supported by the dielectric layer <b>38</b>. Conductive bumps <b>40</b> are formed on the UBM <b>39</b> by evaporation, an electroplating process, dropping balls, solder paste in a screen printing operation, electroless or electroplating approaches, controlled collapse chip connection (C4) plating or C4NP (C4 New Process) solder transfers. The conductive bumps <b>15</b> are aligned with the conductive bumps <b>40</b> respectively in this operation.

0019Referring to <figref idref="DRAWINGS">FIG. 2</figref>, a thermal reflow process is used to cause the conductive bumps <b>15</b> and the conductive bumps <b>40</b> to be softened. After cooling these reflown bumps, the conductive bumps <b>15</b> and the conductive bumps <b>40</b> are melted to form conductive bumps <b>41</b> between the dies <b>10</b> and the wafer <b>30</b>. The conductive bumps <b>40</b> provide an attachment and an electrical connection, wherein the conductive bumps <b>40</b> are implemented by micro bumps or controlled collapse chip connection (C4) bumps. Following the thermal reflow process, an underfill material is dispensed to form an underfill layer <b>42</b> between the dies <b>10</b> and the wafer <b>30</b>. The underfill material is dispensed along edges of the dies <b>10</b> by using syringes or needles and drawn into the gaps between the wafer <b>30</b> and the dies <b>10</b> by capillary action. The underfill material is also disposed, thereby surrounding the conductive bumps <b>41</b>. The underfill material includes, for example, compliant epoxies that are liquid at temperatures above room temperature, and have rapid cure times especially at elevated temperatures and low viscosity during dispensing. The underfill layer <b>42</b> includes fillets <b>43</b> at each edge of the dies <b>10</b>, wherein the fillets <b>43</b> are formed outside of the dies <b>10</b> after the underfill layer <b>42</b> is cured. The fillets <b>43</b> have an outside surface that slopes up from the dielectric layer <b>13</b> to the dielectric layer <b>38</b>, thus sealing the gaps between the dies <b>10</b> and the wafer <b>30</b>. The underfill layer <b>42</b> provides a flexible compliant material surrounding the conductive bumps <b>40</b> and an adhesion between the dies <b>10</b> and the wafer <b>30</b>. Further, the underfill layer <b>42</b> provides a stress relief during thermal cycling so as to prevent the conductive bumps <b>41</b> and the dies <b>10</b> from cracking.

0020A molding layer <b>44</b> is formed over the wafer <b>30</b> and surrounds the dies <b>10</b>, wherein the molding layer <b>44</b> covers the dielectric layer <b>38</b> and sidewalls <b>17</b> of the dies <b>10</b>. A portion of the molding layer <b>44</b> is removed by using a backside grinding <b>45</b> or another mechanical operation, thus exposing a top surface <b>16</b> of the dies <b>10</b>. After the molding process and the backside grinding <b>45</b>, molded dies or molded chips <b>47</b> connected to the wafer <b>30</b> are provided. A thermal interface material (“TIM”) or a heat spreader (not shown) is applied on the top surface <b>16</b>. The use of the heat spreader or the TIM layer greatly improves the thermal performance of the dies <b>10</b> and decreases the temperatures of the dies <b>10</b> during operations.

0021Referring to <figref idref="DRAWINGS">FIG. 3</figref>, a carrier <b>22</b> is formed on the top surface <b>16</b> in advance, which is temporary and made of any strippable or easily removed material, for example, films, tapes, liquid adhesives and the like. The carrier <b>22</b> holds and supports the wafer <b>30</b> during the following processes. After the carrier <b>22</b> is formed, the carrier <b>21</b> is then removed. The wafer <b>30</b> is turned upside down for further processes on the second surface <b>33</b>, wherein the second surface <b>33</b> faces upward. A conductive layer is deposited on the second surface <b>33</b> and then patterned to form conductive pads <b>51</b> connected to the TSVs <b>32</b>. The conductive pads <b>51</b> are made of conductive material, for example, copper (Cu), copper alloys, or nickel (Ni). A polymeric layer <b>52</b> is deposited on the second surface <b>33</b> and the conductive pads <b>51</b> by a deposition <b>46</b>, wherein the polymeric layer <b>52</b> is formed on predetermined areas where the positions are reserved for interposers. The predetermined areas of interposers have a triangular shape or other shapes where the positions of each interposer shall be determined before a dicing process. The polymeric layer <b>52</b> is made of one or two suitable polymer materials such as epoxy, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), photosensitive polyimide material (PSPI), or soft organic materials.

0022Referring to <figref idref="DRAWINGS">FIG. 4</figref>, it depicts a top view and a cross-sectional view for illustrating one of the predetermined areas for interposers, for example, a predetermined area <b>60</b>. The top view is corresponding to the cross-sectional view. In the top view, the predetermined area <b>60</b> is implemented as a triangular or a square shape. A dash line A-A′ is drawn across the top view of the predetermined area <b>60</b>, wherein the dash line A-A′ cuts the predetermined area <b>60</b> so as to show the cross-sectional view. Before patterning the polymeric layer <b>52</b>, a core region <b>55</b> and a periphery region <b>56</b> of the predetermined area <b>60</b> are determined, wherein the periphery region <b>56</b> includes a bandwidth of at least 3 times that of a minimum pitch of the conductive pads <b>51</b>. Concerning the core region <b>55</b> in the top view, the core region <b>55</b> is located on a central region of the predetermined area <b>60</b>, which can be a triangular or a square shape. Concerning the periphery region <b>56</b> in the top view, the periphery region <b>56</b> is an outer portion of the predetermined area <b>60</b> extending from a virtual boundary <b>55</b>′ to edges <b>60</b>A of the predetermined area <b>60</b>. The bandwidth measured orthogonally from the virtual boundary <b>55</b>′ to the edges <b>60</b>A is equivalent to at least 3 times that of a smallest pitch between the conductive pads <b>51</b>. The smallest pitch is measured form a center of a conductive pad <b>51</b> to a center of an adjacent conductive pad.

0023The polymeric layer <b>52</b> covering the predetermined area <b>60</b> is then patterned to form a polymeric layer <b>52</b>′, wherein a portion of the polymeric layer <b>52</b> is removed in order to expose the conductive pads <b>51</b> by using lithography or etching processes, thus forming openings <b>53</b>. The openings <b>53</b> in the top view are a plurality of circles in the polymeric layer <b>52</b>′, wherein the conductive pads <b>51</b> underneath the openings <b>53</b> can be observed. Further, the openings <b>53</b> in the cross-sectional view are located on the conductive pads <b>51</b> and are surrounded by the polymeric layer <b>52</b>′ with a thickness.

0024Before patterning the polymeric layer <b>52</b>, positions of isolated circles <b>57</b> in the core region <b>55</b> of the predetermined area <b>60</b> are also determined. During the patterning, another portion of the polymeric layer <b>52</b> is also removed so as to form trenches <b>54</b> in the core region <b>55</b> of the predetermined area <b>60</b>. The trenches <b>54</b> in the top view hollow out the polymeric layer <b>52</b> in the core region <b>55</b> so as to form isolated circles <b>57</b> or ovals. That is, the trenches <b>54</b> isolate the isolated circles <b>57</b> and expose portions of the second surface <b>33</b> in the core region <b>55</b>. In each of the isolated circles <b>57</b>, the openings <b>53</b> also expose the conductive pads <b>51</b> and located in the center of the isolated circles <b>57</b>. Diameters of the isolated circles <b>57</b> are greater than diameters of the openings <b>53</b> as shown in the top view. The isolated circles <b>57</b> in the cross-sectional view are regarded as islands elevated above the second surface <b>33</b>.

0025Therefore, after the patterning of the polymeric layer <b>52</b>, the polymeric layer <b>52</b>′ covering the periphery region <b>56</b> of the predetermined area <b>60</b> is remained. The polymeric layer <b>52</b>′ includes a first portion <b>58</b>A and a second portion <b>58</b>B, wherein the first portion <b>58</b>A is configured as a blanket covering the periphery region <b>56</b> of the predetermined area <b>60</b>. The second portion <b>58</b>B is located in the core region <b>55</b> of the predetermined area <b>60</b> and configured as the isolated circles <b>57</b> or ovals. Specifically, the polymeric layer <b>52</b>′ covers the edges <b>60</b>A and the corners <b>60</b>B of the predetermined area <b>60</b>, wherein the first portion <b>58</b>A includes a sidewall <b>61</b> coplanar with a sidewall <b>30</b>′ of the wafer <b>30</b>. Since the conductive bumps and underlying dielectric materials adjacent to the corners <b>60</b>B/edges <b>60</b>A of an interposer are subject to serious stress, the polymeric layer <b>52</b>′ is deposited particularly in contact with the corners <b>60</b>B/edges <b>60</b>A in order to release the stress. That is, the polymeric layer <b>52</b>′ provides a stress relief for the conductive bumps and wirings adjacent to the corners <b>60</b>B/edges <b>60</b>A during thermal cycles or a stress testing.

0026In some embodiments, the coverage of the polymeric layer <b>52</b>′ on the second surface <b>33</b> is at least 30% of the predetermined area <b>60</b>. Alternatively, the coverage of the polymeric layer <b>52</b>′ on the second surface <b>33</b> is about 30% to 60% of the predetermined area <b>60</b>. In an embodiment, the coverage of the polymeric layer <b>52</b>′ on the second surface <b>33</b> is about 40% to 50% of the predetermined area <b>60</b>. In an embodiment, the polymeric layer <b>52</b>′ in the periphery region <b>56</b> includes a thickness greater than a thickness of the polymeric layer <b>52</b>′ in the core region <b>55</b>. As such, the ability to release mechanical stress of the polymeric layer <b>52</b>′ on the edges <b>60</b>A can be improved.

0027Referring to <figref idref="DRAWINGS">FIG. 5A</figref>, an under bump metallization (UBM) layer is deposited over the second surface <b>33</b> and patterned to form UBMs <b>63</b>. The UBMs <b>63</b> electrically connect with the conductive pads <b>51</b>, wherein the UBMs <b>63</b> are surrounded and supported by the polymeric layer <b>52</b>′. Materials of the UBMs <b>63</b> provide additional adhesion to the conductive pads <b>51</b> and increase solderability, wherein the materials include at least one metallization layer including titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), copper alloys, nickel (Ni), tin (Sn), gold (Au), or combinations thereof. The UBMs <b>63</b> serve as an adhesion layer between conductive pads <b>51</b> and conductive bumps. Alternatively, the UBMs <b>63</b> can be omitted by directly soldering on the conductive pads <b>51</b>.

0028Next, conductive bumps <b>65</b> are disposed on the UBMs <b>63</b>, wherein the conductive bumps <b>65</b> are implemented by controlled collapse chip connection (C4) bumps. The polymeric layer <b>52</b>′ surrounds a lower portion of a corresponding conductive bump <b>65</b>. The conductive bumps <b>65</b> are formed by several ways, for example, using solder paste in a screen printing operation, electroless or electroplating approaches, controlled collapse chip connection (C4) plating or C4NP (C4 New Process) solder transfers. The conductive bumps <b>65</b> are made of lead based material such as lead-tin (Pb/Sn) compounds or lead free eutectics including tin, copper, silver, (Sn/Ag/Cu solder bumps may be used and are sometimes called “SAC” bumps), nickel, gold, and other lead free materials. After the conductive bumps <b>65</b> are deposited or electroplated on the UBMs <b>63</b>, a thermal reflow process is performed to soften and reshape the conductive bumps <b>65</b>. During melting, the conductive bumps <b>65</b> are limited by the UBMs <b>63</b>. Further, the conductive bumps <b>65</b> are larger than the conductive bumps <b>41</b> interconnected between the RDL <b>34</b> and the dies <b>10</b> since the scale of the dies <b>10</b> is smaller than the following circuit board. The conductive bumps <b>65</b> are coupled with the molded chips <b>47</b> mounted to the wafer <b>30</b> through the TSVs <b>32</b>. In an embodiment, the conductive bumps <b>65</b> have an oval shape, which is sufficient to reduce a shear force induced between two different layers.

0029Referring to <figref idref="DRAWINGS">FIG. 5B</figref>, it depicts a corresponding top view and a cross-sectional view of a configuration of the second surface <b>33</b>. The top view is corresponding to the cross-sectional view. A dash line A-A′ is drawn across a top view of the predetermined area <b>60</b>, wherein the dash line A-A′ cuts the predetermined area <b>60</b> so as to show a cross-sectional view. Particularly, the dash line A-A′ is drawn across the conductive bumps <b>65</b> both in the core region <b>55</b> and the periphery region <b>56</b>. The conductive bumps <b>65</b> extrude from the polymeric layer <b>52</b>′ and are coupled with the TSVs <b>32</b> in the cross-sectional view. The conductive bumps <b>65</b> in the top view are disposed in the core region <b>55</b> and the periphery region <b>56</b>, wherein a portion of the conductive bumps <b>65</b> are located adjacent to edges <b>60</b>A of the predetermined area <b>60</b>. In an embodiment, the conductive bumps <b>65</b> are distal from corners <b>60</b>B of the predetermined area <b>60</b> because serious stresses will occur at the corners <b>60</b>B after dicing. The conductive bumps <b>65</b> and underlying layers adjacent to the corners <b>60</b>B/edges <b>60</b>A of the predetermined area <b>60</b> are subject to serious stress, which causes conductive bump cracking and film delamination. The polymeric layer <b>52</b>′ in the cross-sectional view surrounds and supports a lower portion of a corresponding conductive bump <b>65</b> so as to release a physical stress. In addition, the polymeric layer <b>52</b>′ in the top view covering the edges <b>60</b>A and corners <b>60</b>B of the predetermined area <b>60</b> provides a stress relief so as to prevent failures of the conductive bumps <b>65</b> due to thermal mismatch among different materials. Further, the polymeric layer <b>52</b>′ covering the periphery region <b>56</b> is able to absorb or disperse the stress caused by different thermal expansion among the wafer <b>30</b>, the UBMs <b>63</b> or other laminates, thus sufficiently preventing the conductive bumps <b>65</b> from cracking or die cracking. The polymeric layer <b>52</b>′ circulating the conductive bumps <b>65</b> in the core region <b>55</b> forms isolated belts <b>59</b> or isolated rings as shown in the top view, wherein each of the isolated belts <b>59</b> surrounds a corresponding conductive bump <b>65</b>. In addition, each of the isolated belts <b>59</b> includes a circular shape or an oval shape, wherein the isolated belts <b>59</b> have a diameter greater than a diameter of the conductive bump <b>65</b>. Further, the isolated belts <b>59</b> encompass a corresponding conductive bump <b>65</b> so that the isolated belts <b>59</b> are able to disperse the effect of stresses, thus sufficiently preventing conductive bump cracking or die cracking. Therefore, the conductive bumps <b>65</b> adjacent to edges <b>60</b>A of the predetermined area <b>60</b> will not be abandoned since the polymeric layer <b>52</b>′ prevents the conductive bumps <b>65</b> from cracking.

0030Referring to <figref idref="DRAWINGS">FIG. 5C</figref>, it depicts a wafer-level view of the second surface <b>33</b>, wherein the first surface <b>31</b> cannot be seen at this angle of viewing. The polymeric layer <b>52</b>′ is coated on the predetermined areas <b>60</b>, thus forming boundaries or profiles ready for dicing into interposers. Each of the predetermined areas <b>60</b> is determined as a triangular shape, wherein the polymeric layer <b>52</b>′ on the periphery region <b>56</b> is a strip line along edges <b>60</b>A of the predetermined areas <b>60</b> and frames the core region <b>55</b>. An opposite side (not shown) of each predetermined areas <b>60</b> includes a set of the dies <b>10</b> integrated as a complete system with particular functions. The quantity of the conductive bumps <b>65</b> is not limited to the illustrations in <figref idref="DRAWINGS">FIG. 5C</figref>. In an embodiment, there are not limited to one row of the conductive bumps <b>65</b> in the periphery region <b>56</b>, instead, there are a few rows of the conductive bumps <b>65</b> arranged in the periphery region <b>56</b>. Next, a singulation (not shown) is performed on the wafer <b>30</b> so as to dice the wafer <b>30</b> into interposers according to the predetermined areas <b>60</b>.

0031Referring to <figref idref="DRAWINGS">FIG. 6</figref>, it depicts that an interposer <b>70</b> stacked with the molded chip <b>47</b> is mounted on a circuit board <b>80</b>. During the mounting process with the circuit board <b>80</b>, the conductive bumps <b>65</b> are in contact with conductive pads <b>73</b> of the circuit board <b>80</b>. A reflow process is performed to soften the conductive bumps <b>65</b> for electrical connection and mechanical attachment between the interposer <b>70</b> and the circuit board <b>80</b>. After the interposer <b>70</b> is connected to the circuit board <b>80</b>, an underfill material is dispensed into gaps between the interposer <b>70</b> and the circuit board <b>80</b>. Further, the underfill material is interposed between the isolated belts <b>57</b> and then cured to form an underfill layer <b>74</b>. A CoWoS package <b>100</b> mounting the molded chip <b>47</b>, the interposer <b>70</b> and the circuit board <b>80</b> together is formed. While the CoWoS package <b>100</b> is cooling down, the conductive bumps <b>65</b> are subject to rotational shearing, which results from the different thermal expansion between the circuit board <b>80</b> and the interposer <b>70</b> due to different thermal coefficients. For example, while cooling down, the circuit board <b>80</b> shrinks to an extent that is greater than that of the interposer <b>70</b>. The conductive bumps <b>65</b> will be rotated, which causes squeezing or pulling to the joint regions with the conductive bumps <b>65</b> and forms a stress. The polymeric layer <b>52</b>′ is able to mitigate or disperse the rotational shearing, which transmits a stress from the conductive bumps <b>65</b> into the UBMs <b>63</b> where the UBMs <b>63</b> or the conductive bumps <b>65</b> are subject to delamination. In other situations, the CoWoS package <b>100</b> shall receive a stressing test before the products are transported to the clients. During reliability stressing, mechanical pressure is imposed on the CoWoS packages <b>100</b>. The polymeric layer <b>52</b>′ disperses the stressing so as to protect the conductive bumps <b>65</b>, the conductive pads <b>73</b>, the UBMs <b>63</b>, the underfill layer <b>74</b> and the underlying wirings adjacent to the edges of the interposer <b>70</b> from cracking.

0032In brief, a polymeric layer formed on a periphery region of an interposer is able to absorb or disperse the stress caused by different thermal expansion between the interposer and the circuit board, thus sufficiently preventing conductive bumps near edges of the interposer from cracking. In addition, the polymeric layer is able to mitigate or disperse the rotational shear, which transmits a stress from conductive bumps into UBMs and underlying wirings where the UBMs or the conductive bumps are subject to delamination.

0033A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.

0034In some embodiments, the periphery region includes a bandwidth of at least 3 times that of a minimum pitch of the plurality of conductive bumps.

0035In some embodiments, the first portion includes a sidewall coplanar with a sidewall of the semiconductor substrate.

0036In some embodiments, the semiconductor package structure further includes a molded chip over the first surface, wherein the molded chip is coupled with the plurality of conductive bumps.

0037In some embodiments, the semiconductor package structure further includes a redistribution layer (RDL) between the molded chip and the first surface; and a plurality of conductive micro bumps interconnected to the RDL and the molded chip. The RDL is coupled with the corresponding TSV. The plurality of conductive micro bumps are smaller than the plurality of conductive bumps.

0038In some embodiments, the semiconductor package structure further includes a circuit board over the second surface and connected to the plurality of conductive bumps.

0039In some embodiments, the semiconductor package structure further includes an underfill material between the circuit board and the semiconductor substrate, wherein the underfill material is interposed between each of the isolated belts.

0040In some embodiments, each of the isolated belts includes an oval shape.

0041In some embodiments, the plurality of conductive bumps are distal from corners of the semiconductor substrate.

0042A semiconductor package structure includes an interposer including a front side, a back side, a first, and a second through interposer via (TIV); a polymeric layer covering a periphery region of the front side; a first conductive bump extruding from the polymeric layer and coupled with the first through interposer via; a polymeric ring over a central region of the front side; and a molded chip mounted on the back side. The polymeric ring is isolated and encompasses a second conductive bump coupled with the second through interposer via. The molded chip is coupled with the first and second conductive bumps through the first and second through interposer vias.

0043In some embodiments, the polymeric layer is a strip line along edges of the interposer and frames the central region.

0044In some embodiments, the coverage of the polymeric layer on the front side is at least 30%.

0045In some embodiments, the polymeric layer includes a thickness greater than a thickness of the polymeric ring.

0046In some embodiments, the polymeric ring includes a diameter greater than a diameter of the second conductive bump.

0047In some embodiments, the second conductive bump includes an oval shape.

0048In some embodiments, the semiconductor package structure further includes a circuit board over the front side and connected to the first and second conductive bumps.

0049A method for manufacturing a semiconductor package structure includes providing a wafer including a first surface and a second surface, wherein the second surface is opposite to the first surface; forming a plurality of conductive pads on the second surface; forming a polymeric layer over the second surface, wherein the polymeric layer is formed on a predetermined area of an interposer; removing a portion of the polymeric layer so as to expose the plurality of conductive pads; forming trenches in a core region of the predetermined area so as to expose a portion of the second surface, thus allowing the polymeric layer on a periphery region of the predetermined area to remain; and forming a plurality of conductive bumps extruding from the plurality of conductive pads.

0050In some embodiments, the method further includes determining the periphery region and the core region of the predetermined area, wherein the periphery region includes a bandwidth of at least 3 times that of a minimum pitch of the plurality of conductive pads.

0051In some embodiments, the method further includes determining positions of a plurality of isolated circles in the core region of the predetermined area.

0052In some embodiments, the method further includes mounting an integrated circuit die over the first surface of the wafer; dicing the wafer into a plurality of interposers; and mounting the plurality of interposers on a circuit board.

0053The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.