Physical unclonable function generation and management

BACKGROUND

00011. Technical Field

0002The present invention relates to physical unclonable functions, and more particularly, to on-chip physical unclonable function generation and management thereof.

00032. Description of the Related Art

0004Process variations of integrated circuits present a fundamental reliability challenge with regard to generation and measurement of physical unclonable functions. In particular, there is an inherent contradiction between forming a physical unclonable function (PUF) which depends on large variability and fabricating a reliable PUF measurement system which depends on low variability while integrating both functions monolithically on the same chip. For example, although process variability maximizes the effectiveness of a PUF, process variability degrades the performance of the measurement circuit. As such, a manufacturing design goal is to maximize process variability for the PUF (σ_PUF) circuit and minimize process variability for the measurement circuit. In addition, process, voltage supply, temperature, and aging variability results in measurement incertitude that forms an incertitude zone defined by a measurement standard deviation (σ_meas).

0005For example, diagram <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref> illustrates an example of a voltage normal distribution due to process variability for a PUF and its binarization by a perfect measurement system. As illustrated in diagram <b>200</b> of <figref idref="DRAWINGS">FIG. 2</figref>, measurement error results in an incertitude zone <b>202</b> that stems from process variability. Although the measurement error cannot be reduced to zero, any PUF scheme should incorporate a measurement system that minimizes measurement variability. However, this is difficult to achieve when the PUF scheme is implemented on-chip due to the conflicting goals of maximizing process variability for PUF generation and minimizing process variability to manufacture a reliable integrated circuit.

SUMMARY

0006One embodiment is directed to a circuit authentication system including a plurality of PUF elements and a measurement unit. The PUF elements include a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the measurement unit is configured to measure at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Here, the one or more differentials of states form a basis of at least part of a bit sequence of an authentication signature for the circuit.

0007Another embodiment is directed to a method for authenticating a circuit. In accordance with the method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the PUF system is measured to obtain at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Further, the method includes outputting an authentication sequence for the circuit that is based on the one or more differentials of states.

0008Another embodiment is directed to a method for identifying unreliable PUF states of a PUF system. In accordance with the method, a positive differential of states between a first element in a PUF system and a second element in the PUF system is generated. The method further includes generating a negative differential of the states between the first element and the second element in the PUF system. In addition, the states of the first and second elements are marked as unreliable states if the negative differential is different from the positive differential.

0009These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

0010The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:

0011<figref idref="DRAWINGS">FIG. 1</figref> is a graph illustrating an exemplary PUF probability distribution function;

0012<figref idref="DRAWINGS">FIG. 2</figref> is a graph illustrating a measurement incertitude for a PUF due to process variability;

0013<figref idref="DRAWINGS">FIG. 3</figref> is a high-level block/flow diagram of an exemplary system/method for generating PUF information in accordance with an exemplary embodiment of the present invention;

0014<figref idref="DRAWINGS">FIG. 4</figref> is a high-level block/flow diagram of an exemplary PUF system in accordance with an exemplary embodiment of the present invention;

0015<figref idref="DRAWINGS">FIG. 5</figref> is a high-level block diagram of an exemplary PUF system that employs transistors in a diode configuration in accordance with an exemplary embodiment of the present invention;

0016<figref idref="DRAWINGS">FIG. 6</figref> is a high-level block diagram of an exemplary PUF system that employs resistors as PUF elements in accordance with an exemplary embodiment of the present invention;

0017<figref idref="DRAWINGS">FIG. 7</figref> is a high-level block diagram of an exemplary PUF system that employs a strongarm latch configuration in accordance with an exemplary embodiment of the present invention;

0018<figref idref="DRAWINGS">FIG. 8</figref> is a high-level block diagram of an exemplary PUF system that employs a differential pair and current mode logic latch configuration in accordance with an exemplary embodiment of the present invention;

0019<figref idref="DRAWINGS">FIG. 9</figref> is a high-level flow diagram of an exemplary method for providing authentication information from a PUF system for an integrated circuit in accordance with an embodiment of the present invention;

0020<figref idref="DRAWINGS">FIG. 10</figref> is a high-level flow diagram of an exemplary method for filtering PUF states in accordance with an exemplary embodiment of the present invention;

0021<figref idref="DRAWINGS">FIG. 11</figref> is a high-level block diagram of an alternative exemplary PUF system that employs a strongarm latch configuration in accordance with an exemplary embodiment of the present invention;

0022<figref idref="DRAWINGS">FIG. 12</figref> is a high-level block diagram of an alternative exemplary PUF system that employs a differential pair and current mode logic latch configuration in accordance with an exemplary embodiment of the present invention;

0023<figref idref="DRAWINGS">FIG. 13</figref> is a high-level block/flow diagram of another exemplary system/method for generating PUF information and authenticating a chip in accordance with an exemplary embodiment of the present invention; and

0024<figref idref="DRAWINGS">FIG. 14</figref> is a high-level flow diagram of an exemplary method for authenticating a chip or an integrated circuit including a PUF system in accordance with an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

0025As noted above, process variability leads to an inherent incertitude in measurement of PUF states. However, other factors also contribute to measurement error. For example, the temperature of circuit elements, noise, aging effects, radiation and supply voltage variations can lead to a drift in the PUF probability distribution function (PDF) and also to an expansion of the measurement error. For example, these additional factors can cause a drift of the PDF <b>102</b> in <figref idref="DRAWINGS">FIG. 1</figref> to the right or left and can cause an expansion of the incertitude zone <b>202</b> in <figref idref="DRAWINGS">FIG. 2</figref> to the right and/or to the left. Thus, these additional factors can decrease the effectiveness of on-chip PUF systems.

0026The exemplary embodiments described herein incorporate features that can mitigate the dependence of a PUF on temperature, noise, aging, radiation and/or supply voltage variations to provide a robust and reliable PUF scheme. For example, PUF variability can be reduced by employing a differential of PUF states, which has a reduced sensitivity to temperature, noise and variations. In particular, preferred embodiments employ a PUF design that arranges PUF devices in series and in parallel to provide a simple and effective means for obtaining the differential of PUF states. As discussed herein below, the element design can be implemented using a wide variety of devices, including field effect transistors (FETs) in a variety of configurations, resistors, wires in back end of line (BEOL) wires, wires in front end of line (FEOL) wires and vias.

0027As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method, device or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, or an embodiment combining software (including firmware, resident software, micro-code, etc.) and hardware aspects that may all generally be referred to herein as a “module” or “system.” Furthermore, certain aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

0028Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

0029A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

0030Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

0031Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and devices according to embodiments of the invention. It will be understood that certain blocks of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

0032These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks. The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

0033The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and devices according to various embodiments of the present invention. In this regard, certain blocks in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer software instructions.

0034A design for an integrated circuit chip in accordance with embodiments of the present invention may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

0035Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

0036Reference in the specification to “one embodiment” or “an embodiment” of the present invention, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

0037It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

0038Referring again to the drawings in which like numerals represent the same or similar elements, <figref idref="DRAWINGS">FIG. 3</figref> illustrates an exemplary system/method <b>300</b> for generating PUF information. It should be noted that each of the elements of the system <b>300</b> may be implemented on-chip as hardware processors or elements. In accordance with one exemplary aspect, supply voltage variability affecting PUF measurement can be reduced by employing a bandgap voltage generator <b>302</b> that generates a reference voltage which is independent of the supply voltage for the integrated circuit and of the temperature. Further, the voltage regulator <b>304</b> regulates the noisy on-chip power supply V_DD<b>306</b> to provide a stable regulated voltage (VREG) <b>308</b> to one or more PUF units <b>310</b>₁-<b>310</b>_k, one or more multiplexer (MUX) units <b>316</b>₁-<b>316</b>_kand one or more differential quantizers <b>318</b>₁-<b>318</b>_k. The PUF units <b>310</b>₁-<b>310</b>_k, collectively referred to as PUF unit <b>310</b>, can be composed of transistors, resistors, wires, etc., as noted above. Further, states Sp_j<b>312</b> and Sn_j<b>314</b> can be measured from the PUF unit <b>310</b> to obtain a PUF differential Sp-Sn. The difference Sp-Sn has a reduced sensitivity to temperature, noise and supply variations, and, as discussed in further detail herein below, can be employed to generate a PUF identifier or signature for the integrated circuit or chip. Further, one or more multiplexers <b>316</b>₁-<b>316</b>_k, collectively referred to as multiplexer <b>316</b>, are configured to obtain Sp_jand Sn_jstates from the PUF unit <b>310</b> and to combine a total number of Sp_jand Sn_jstates and generate a larger total number of differential states than the total number of PUF elements in the PUF unit <b>310</b>. In addition, one or more or more differential quantizers <b>318</b>₁-<b>318</b>_k, collectively referred to as quantizer <b>318</b>, can be configured to measure the difference Sp and Sn and determine whether the difference is a logic “0” or “1.” Thus, the quantizer <b>318</b> can assess whether each of the differentials of states is a one or a zero to form a bit sequence that denotes the differentials. The quantizer can thereby output the chip unique k-bit sequence, which is a unique PUF identifier or authentication signature for the chip or integrated circuit, to an authentication module <b>320</b>, which can employ an authentication database to authenticate the chip. In accordance with one exemplary aspect, the multiplexer <b>316</b> can be configured to multiplex the differentials Sp_j-Sn_jto the quantizer <b>318</b> such that any one or more of the quantizers <b>318</b>₁-<b>318</b>_kare reused for measurements of several PUF units to conserve chip area employed for the measurement circuitry.

0039Referring now to <figref idref="DRAWINGS">FIG. 4</figref>, with continuing reference to <figref idref="DRAWINGS">FIG. 3</figref>, an exemplary design of a PUF system <b>400</b> in accordance with exemplary embodiments is illustratively depicted. The PUF system <b>400</b> can be implemented as the PUF unit <b>310</b> of <figref idref="DRAWINGS">FIG. 3</figref>. Here, a differential PUF is generated using voltage division. For example, a regulated voltage, VREG <b>402</b>, can be applied to the system <b>400</b> as illustrated in <figref idref="DRAWINGS">FIG. 4</figref>. In one embodiment, the VREG <b>402</b> can be implemented by the VREG <b>308</b>, discussed above with regard to <figref idref="DRAWINGS">FIG. 3</figref>. In the PUF system <b>400</b>, the PUF units <b>404</b> and <b>406</b> are arranged in parallel, while the PUF units <b>408</b> and <b>410</b> are arranged in parallel as well. In addition, the PUF units <b>404</b> and <b>408</b> are arranged in series, while the PUF units <b>406</b> and <b>410</b> are also arranged in series. Thus, in this example, PUFs <b>404</b> and <b>406</b> form a subset of PUF elements that are arranged in series while PUFs <b>408</b> and <b>410</b> form a second subset of PUF elements that are arranged in series. Further, as illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. For example, <figref idref="DRAWINGS">FIG. 5</figref> illustrates a PUF system <b>500</b>, which is an exemplary embodiment of the PUF system <b>400</b>, that employs transistors <b>504</b>, <b>506</b>, <b>508</b> and <b>510</b> as PUF units <b>404</b>, <b>406</b>, <b>408</b> and <b>410</b>, respectively. Here, the transistors <b>504</b>-<b>510</b> are field-effect transistors that are in a diode configuration and are connected to a ground <b>512</b>. Diodes can also be used in the system <b>500</b>. A regulated voltage VREG <b>501</b> can be applied and the arrangement can be tapped at portions <b>518</b> and <b>519</b> to obtain states Sp_j<b>520</b> and Sn_j<b>522</b>, as illustrated in <figref idref="DRAWINGS">FIG. 5</figref>.

0040As indicated above, the design of system <b>400</b> provides a simple and effective means for obtaining and utilizing the differential of PUF states. For example, PUF temperature variability is reduced by using a differential PUF circuit that generates the states Sp <b>412</b> and Sn <b>414</b>, of which voltage states Sp_j<b>520</b> and Sn_j<b>522</b> are respective examples. Here, the measurement of the differential of states Sp <b>412</b> and Sn <b>414</b> corresponds to a differential of states between the first subset of PUF elements <b>404</b>/<b>406</b> and the second subset of PUF elements <b>408</b>/<b>410</b>. As noted above, the difference Sp-Sn has a reduced sensitivity to temperature variations. Another benefit of the differential signals is the elimination of common-mode noise dependence, such as thermal or substrate noise, as well as supply variation dependence. Further, the PUF state need not be inferred from supply current measurements.

0041As discussed above, the system <b>400</b> of <figref idref="DRAWINGS">FIG. 4</figref> can be implemented with a variety of devices. <figref idref="DRAWINGS">FIG. 6</figref> illustrates another exemplary implementation of the PUF system <b>400</b>. For example, <figref idref="DRAWINGS">FIG. 6</figref> illustrates a PUF system <b>600</b> that employs resistors <b>604</b>, <b>606</b>, <b>608</b> and <b>610</b> as PUF units <b>404</b>, <b>406</b>, <b>408</b> and <b>410</b>, respectively. A regulated voltage VREG <b>601</b> can be applied and the arrangement can be tapped at portions <b>618</b> and <b>619</b> to obtain states Sp_j<b>620</b> and Sn_j<b>622</b>, as illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, which are examples of states Sp <b>412</b> and Sn <b>414</b>. The PUF system <b>400</b> can alternatively be implemented with BEOL wires, FEOL wires and vias, among other elements.

0042<figref idref="DRAWINGS">FIGS. 7 and 8</figref> illustrate other examples of the PUF system <b>400</b>. For example, <figref idref="DRAWINGS">FIG. 7</figref> illustrates a strongarm latch configuration <b>700</b>, while <figref idref="DRAWINGS">FIG. 8</figref> illustrates a differential pair and current mode logic latch <b>800</b>. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, a regulated voltage, VREG <b>702</b>, which is an implementation of VREG <b>308</b>, can be applied to the system <b>700</b>, while clock signals CLK <b>704</b>, CLK <b>706</b> and CLK <b>708</b> can be applied to FETs <b>710</b>, <b>712</b> and <b>714</b>, respectively. In addition, a voltage bias <b>716</b> is applied to transistor <b>718</b>, which is coupled to ground <b>719</b>, as illustrated in <figref idref="DRAWINGS">FIG. 7</figref>. Here, the circuit is tapped at portions <b>720</b> and <b>722</b> to obtain outputs OUTN_j<b>724</b> and OUTP_j<b>726</b>, respectively, as shown in <figref idref="DRAWINGS">FIG. 7</figref>. The differential OUTP_j-OUTN_jmodels the differential Sp_j-Sn_jbetween transistors <b>732</b> and <b>730</b> at the latching time, i.e. at the rising edge of the clock signal CLK.

0043In the differential pair and current mode logic latch <b>800</b>, a regulated voltage, VREG <b>802</b>, is applied, as shown in <figref idref="DRAWINGS">FIG. 8</figref>. VREG <b>802</b> is also an implementation of VREG <b>308</b>. As shown in <figref idref="DRAWINGS">FIG. 8</figref>, the latch <b>800</b> can be tapped at portions <b>804</b> and <b>806</b> to obtain outputs OUTP_j<b>808</b> and OUTN_j<b>810</b>, respectively. Similar to the latch of <figref idref="DRAWINGS">FIG. 7</figref>, the differential OUTP_j-OUTN_jmodels the differential Sp_j-Sn_jbetween transistors <b>812</b> and <b>814</b> at the rising edge of the differential clock signal CLKP-CLKN. As illustrated in <figref idref="DRAWINGS">FIG. 8</figref>, clock signals CLKN <b>816</b> and CLKP <b>818</b> are applied to transistors <b>820</b> and <b>822</b>, respectively. In addition, voltage biases <b>824</b> and <b>826</b> are applied to transistors <b>828</b> and <b>830</b>, respectively, which are connected to ground as illustrated in <figref idref="DRAWINGS">FIG. 8</figref>.

0044Referring now to <figref idref="DRAWINGS">FIG. 9</figref>, with continuing reference to <figref idref="DRAWINGS">FIGS. 3-8</figref>, a method <b>900</b> for providing authentication information from a PUF system for an integrated circuit in accordance with an embodiment of the present invention is illustratively depicted. The method can begin at step <b>902</b>, at which the voltage regulator <b>304</b> can apply a test voltage to the PUF system. For example, the voltage regulator <b>304</b> can apply the regulated voltage VREG <b>402</b>, <b>501</b>, <b>601</b>, <b>702</b> and <b>802</b> to systems <b>400</b>, <b>500</b>, <b>600</b>, <b>700</b> and <b>800</b>, respectively, as discussed above.

0045At step <b>904</b>, the differential quantizer <b>318</b> can measure the PUF system to obtain a differential of states Sp_j<b>312</b>-Sn_j<b>314</b>. For example, the differential quantizer <b>318</b> can measure the differential output of the PUF system <b>310</b> through the multiplexer <b>316</b>, as discussed above. In accordance with various embodiments of the present invention, the differential quantizer <b>318</b> can measure the differential Sp_j<b>520</b>-Sn_j<b>522</b> of the system <b>500</b>, Sp_j<b>620</b>-Sn_j<b>622</b> of the system <b>600</b>, OUTP_j<b>726</b>-OUTN_j<b>724</b> of the system <b>700</b> and/or OUTP_j<b>808</b>-OUTN_j<b>810</b> of the system <b>800</b>. Further, the quantizer <b>318</b> can compile the one or more differentials to obtain a bit sequence that is an authentication signature and identifies the integrated circuit or chip. Another advantage of using a differential PUF and differential quantizer, is that it is not possible to infer the state of the PUF by measuring its current consumption, since the current consumption is the same for a measured 0 or a 1.

0046At step <b>906</b>, the differential quantizer <b>318</b> can output authentication information for the circuit. For example, the bit sequence obtained by the quantizer <b>318</b> can be output to the external authentication module <b>320</b>, which can then compare the bit sequence to a value stored in an authentication database to authenticate the circuit. If the sequence matches a corresponding value stored in the database, then the circuit is authenticated. Otherwise, the authentication fails. A more sophisticated embodiment of the authentication scheme is discussed in more detail herein below with respect to <figref idref="DRAWINGS">FIG. 13</figref>.

0047Referring now to <figref idref="DRAWINGS">FIG. 10</figref>, a method <b>1000</b> for filtering PUF states in accordance with an exemplary embodiment of the present invention is depicted. In particular, the method <b>1000</b> can be employed to detect unstable PUF elements and guarantee an arbitrary low measurement error rate. In preferred embodiments of the present invention, the unstable PUF elements are also used to generate a signature or unique bit sequence that can be also be used to authenticate an integrated circuit. Indeed, the location of the unstable PUFs is unique for each manufactured chip, and therefore is useful information for identifying the chip. For illustrative purposes, reference is also made to <figref idref="DRAWINGS">FIGS. 11 and 12</figref>, which respectively show slightly modified versions of the systems <b>700</b> and <b>800</b> of <figref idref="DRAWINGS">FIGS. 7 and 8</figref>. For example, <figref idref="DRAWINGS">FIG. 11</figref> illustrates a system <b>1100</b> which is essentially system <b>700</b> with transistors <b>1102</b> and <b>1104</b> added so that test voltages V_bt1<b>1106</b> and V_bt2<b>1108</b> can be applied thereto for purposes of generating a differential Sp_j-Sn_jbetween transistors T<b>2</b><b>732</b> and T<b>1</b><b>730</b> that is measurable through outputs OUTP_j<b>726</b>-OUTN_j<b>724</b>. As illustrated in <figref idref="DRAWINGS">FIG. 11</figref>, the drains of transistors <b>1102</b> and <b>1104</b> are coupled to the drains of transistors <b>730</b> and <b>732</b>, respectively. Similarly, <figref idref="DRAWINGS">FIG. 12</figref> illustrates a system <b>1200</b> which is essentially system <b>800</b> with transistors <b>1202</b> and <b>1204</b> added so that test voltages V_bt1<b>1206</b> and V_bt2<b>1208</b> can be applied thereto for purposes of generating a differential Sp_j-Sn_jbetween transistors T<b>2</b><b>812</b> and T<b>1</b><b>814</b> that is measurable through outputs OUTP_j<b>808</b>-OUTN_j<b>810</b>. As illustrated in <figref idref="DRAWINGS">FIG. 12</figref>, the sources of transistors <b>1202</b> and <b>1204</b> are coupled to the drains of transistors <b>814</b> and <b>812</b>, respectively.

0048In accordance with one exemplary implementation, the method <b>1000</b> can be performed by an authentication system <b>1300</b>, illustrated in <figref idref="DRAWINGS">FIG. 13</figref>, which is a more sophisticated implementation of the authentication system <b>300</b> of <figref idref="DRAWINGS">FIG. 3</figref>. For example, the power management regulation unit <b>1302</b> is one implementation of the voltage regulator <b>304</b> and the bandgap voltage generator <b>302</b>, the PUF unit <b>1304</b> is an implementation of the PUF unit <b>310</b>, the MUX unit <b>1306</b> is an implementation of the MUX unit <b>316</b>. Further, the differential quantizer unit <b>318</b> is an example of the measurement unit <b>1308</b>. Here, the method <b>1000</b> can be performed by setting the system <b>1300</b> to a filtering mode. The filtering mode can be set during, for example, manufacture of the chip or integrated circuit on which the PUF system is implemented. As discussed above with respect to <figref idref="DRAWINGS">FIG. 3</figref>, each of the elements of the system <b>1300</b> may be implemented on-chip as hardware processors or elements.

0049The method <b>1000</b> can begin at step <b>1002</b>, at which the power management unit <b>1302</b> can generate a positive differential of states between elements in a PUF system. For example, referring again to <figref idref="DRAWINGS">FIGS. 11 and 12</figref>, during normal operation, the voltage V_bt1<b>1106</b> and V_bt2<b>1108</b>, and also V_bt1<b>1206</b> and V_bt2<b>1208</b>, are in the off-state, i.e. V_bt1=V_bt2=0. Here, in the filtering mode, at step <b>1002</b>, the power management unit <b>1302</b> can set V_bt1<b>1106</b>=0, or V_bt1<b>1206</b>=0, and can set V_bt2<b>1108</b>=1, or V_bt2<b>1208</b>=1. By setting V_bt1<b>1106</b>, or V_bt1<b>1206</b>, to an “off” or deactivated state and setting V_bt2<b>1108</b>, or V_bt2<b>1208</b>, to an “on” or activated state in this way, an added positive differential voltage is created between the drains of transistors T<b>1</b><b>730</b> and T<b>2</b><b>732</b>, or transistors T<b>1</b><b>814</b> and T<b>2</b><b>812</b>.

0050At step <b>1004</b>, the measurement unit <b>1308</b> can measure the outputs of the PUF unit. For example, in the examples illustrated in <figref idref="DRAWINGS">FIGS. 11 and 12</figref>, the positive differential voltage between the drains of transistors T<b>1</b><b>730</b> and T<b>2</b><b>732</b> can be measured at outputs OUTN_j<b>724</b> and OUTP_j<b>726</b>, or the positive differential voltage between the drains transistors T<b>1</b><b>814</b> and T<b>2</b><b>812</b> can be measured at outputs OUTN_j<b>810</b> and OUTP_j<b>808</b>.

0051At step <b>1006</b>, the power management unit <b>1302</b> can generate a negative differential of states between elements in a PUF system. For example, the power management unit <b>1302</b> can set V_bt1<b>1106</b>=1, or V_bt1<b>1206</b>=1, and can set V_bt2<b>1108</b>=0, or V_bt2<b>1208</b>=0. By setting V_bt1<b>1106</b>, or V_bt1<b>1206</b>, to an “on” or activated state and setting V_bt2<b>1108</b>, or V_bt2<b>1208</b>, to an “off” or deactivated state in this way, an added negative differential voltage is created between the drains of transistors T<b>1</b><b>730</b> and T<b>2</b><b>732</b>, or transistors T<b>1</b><b>814</b> and T<b>2</b><b>812</b>.

0052At step <b>1008</b>, the measurement unit <b>1308</b> can measure the outputs of the PUF unit. For example, in the example illustrated in <figref idref="DRAWINGS">FIGS. 11 and 12</figref>, the added negative differential between the drains of transistors T<b>1</b><b>730</b> and T<b>2</b><b>732</b> can be measured at outputs OUTN_j<b>724</b> and OUTP_j<b>726</b>, or the added negative differential between the drains of transistors T<b>1</b><b>814</b> and T<b>2</b><b>812</b> can be measured at outputs OUTN_j<b>810</b> and OUTP_j<b>808</b>.

0053At step <b>1010</b>, the comparator <b>1310</b> can determine whether the differential of the outputs measured at step <b>1004</b> and the differential of the outputs measured at step <b>1008</b> are different. If the differentials are the same, then the comparator <b>1310</b> deems the PUF states for the PUF unit being evaluated in the current iteration of the method <b>1000</b> to be reliable at step <b>1014</b>. Thereafter, the method <b>1000</b> can be repeated for another PUF unit or combination of PUF units. If the differentials are different, then the comparator <b>1310</b> deems the PUF states for the PUF unit being evaluated in the current iteration of the method <b>1000</b> to be unreliable and are marked as unreliable at step <b>1012</b>. Thereafter, the method <b>1000</b> can be repeated for another PUF unit or combination of PUF units. To mark the PUF chip positions of the respective unreliable PUF unit or combination of PUF units, the comparator <b>1310</b> can store the chip positions or addresses in a Read Only Memory (ROM) unit, such as efuse, for example, including a database <b>1312</b> of unreliable PUF positions. As discussed herein below, during authentication, the unreliable PUF units can be filtered and/or even utilized for authentication purposes. It should be noted that, by increasing the filter width, it is possible to improve the PUF system error rate at the expense of a reduced number of stable PUF states. Indeed increasing the filter width is equivalent to removing PUF states further away to the measurement system threshold. Therefore, by increasing the filter width it becomes easier for the measurements system to distinguish the different states.

0054Referring now to <figref idref="DRAWINGS">FIG. 14</figref>, with continuing reference to <figref idref="DRAWINGS">FIGS. 3</figref>, <b>9</b> and <b>13</b>, an exemplary method <b>1400</b> for authenticating a chip or an integrated circuit, in which a PUF system embodiment according to the present invention is implemented, is illustratively depicted. The method <b>1400</b> can begin at step <b>1402</b>, at which the authentication system <b>1300</b> can receive an authentication challenge. For example, in accordance with one embodiment, an external authentication module <b>1350</b>, which is a more sophisticated implementation of the authentication module <b>320</b>, can reference a challenge/response database <b>1352</b>, stored in a storage medium, to issue a challenge to the authentication system <b>1300</b> to authenticate a chip or integrated circuit to which the authentication system is attached. Here, the chip authentication method can be used, for example, for supply-chain quality control. Further, encryption can be used to prevent unauthorized access to PUF states by performing an exhaustive search. Thus, the authentication module <b>1350</b> can be configured to encrypt the challenge, which can be a bit sequence, and to send the encrypted challenge to the authentication system <b>1300</b>. When the authentication system <b>1300</b> receives the challenge, the power management module <b>1302</b> can turn on or activate the system <b>1300</b>.

0055Optionally, if the challenge received at step <b>1402</b> is encrypted, at step <b>1404</b>, the encryption/decryption module <b>1320</b> can decrypt the challenge.

0056At step <b>1406</b>, the power management module <b>1302</b> can apply a test voltage to the PUF system or unit <b>1304</b>. For example, the test voltage can be applied to the PUF system or unit <b>1304</b> as discussed above with respect to step <b>902</b> of the method <b>900</b>.

0057At step <b>1408</b>, the measurement unit <b>1308</b> can measure the PUF system to obtain one or more differentials and to generate a bit sequence as a signature for the integrated circuit or chip. For example, the measurement unit <b>1308</b> can measure differentials of the PUF system or unit <b>1304</b> and obtain the sequence or signature as discussed above with respect to step <b>904</b> of the method <b>900</b>. However, here, in this embodiment, the multiplexer <b>1306</b> can be configured to combine or multiplex the challenge bit sequence with the outputs of the PUF system <b>1304</b> for purposes of generating a response. Thus, the measurement module can determine the differentials as discussed above with respect to step <b>904</b> and can modify or combine the measured differentials in a pre-determined manner with the bits of the challenge.

0058The method may proceed to block <b>1409</b>, which is an exemplary implementation of step <b>906</b>. At step <b>1410</b>, the filter module <b>1314</b> can filter unreliable PUF states. For example, the filter module <b>1314</b> can reference the database <b>1312</b> of unreliable PUF positions to determine and identify which of the PUF states received from the measurement module <b>1308</b> are unreliable. In addition, the filter module <b>1314</b> can fill or replace such unreliable PUF states with predetermined bit sequences of zeros and ones. Further, it should be noted that, in certain exemplary embodiments, the unreliable PUF states can be checked for instability and thus be an added layer of copy protection. The unreliable states are indeed also part of the chip “DNA” and therefore this information is also valuable and can be used to prevent the copy of the chip PUF. In the preferred embodiment, the chip PUF is composed of two parts, the set of reliable PUF states and the set of unreliable PUF states, which are both used to identify the chip.

0059Optionally, at step <b>1412</b>, an optional error code correction (ECC) module <b>1318</b> can perform error correction on the PUF states received from the filter <b>1314</b> and output the resulting authentication information. For example, error code correction can be performed based on error correction bits stored in a database <b>1316</b> in ROM to further reduce the error rate.

0060Optionally, at step <b>1414</b>, the encryption/decryption module <b>1320</b> can encrypt the authentication information received, for example, from the optional ECC module <b>1318</b> to generate an authentication response.

0061At step <b>1416</b>, the authentication response, which can be an authentication signature or sequence, can be output by the system <b>1300</b> to the authentication module <b>1350</b>. It should be noted that, in certain exemplary implementations, the authentication response can be the error-corrected sequence of differentials of PUF states provided by the ECC module <b>318</b>, the filtered sequence of differentials of PUF states provided by the filter <b>1314</b> or the sequence of differentials of PUF states provided by the measurement unit <b>1308</b>. For each of these scenarios, in accordance with certain exemplary embodiments, the authentication response or sequence need not be the explicit differentials of states, but can be the result of predetermined modifications of the differentials of states by, for example, combining the differentials with the authentication challenge in a pre-determined manner.

0062After the authentication response is output by the system <b>1300</b>, the power management unit <b>1302</b> can deactivate the system <b>1300</b> by turning off the power supply. After receiving the authentication response, the authentication module <b>1350</b> can compare the response to a master challenge/response database <b>1352</b>. If the authentication response matches the corresponding response listed on the database <b>1352</b> for the challenge sent to the system <b>1300</b>, then the chip or integrated circuit is authenticated. Optionally, if a mismatch is detected, then a new challenge can be sent and the method <b>1400</b> can be repeated, as occasionally, an error may occur.

0063Having described preferred embodiments of systems, devices and methods for PUF generation and management (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.