Diplexer design using through glass via technology

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This application claims the benefit under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/751,539 entitled “DIPLEXER DESIGN USING THROUGH GLASS VIA TECHNOLOGY” filed on Jan. 11, 2013, the disclosure of which is expressly incorporated by reference herein in its entirety.

TECHNICAL FIELD

0002The present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to diplexer designs using through glass via or through substrate via technology.

BACKGROUND

0003For wireless communication, a diplexer can help process signals carried in a carrier aggregation system. In carrier aggregation systems, signals are communicated with both high band and low hand frequencies. In a chipset, the diplexer is usually inserted between an antenna and a tuner (or an RF switch) to ensure high performance. Usually, a diplexer design includes inductors and capacitors. Diplexers can attain high performance by using inductors and capacitors that have a high quality factor (or Q). High performance diplexers can also be attained by reducing the electromagnetic coupling between components, which may be achieved through an arrangement of the geometry and direction of the components. Diplexer performance may be quantified, by measuring the insertion loss and rejection (e.g., quantities expressed in decibels (dB)) at certain frequencies.

0004The diplexer fabrication process may be compatible with standard semiconductor processes, such as processes for fabricating voltage-controlled capacitors (varactors), switched-array capacitors, or other like capacitors. It may be beneficial to fabricate the components of the diplexer design on a single substrate. Fabrication on a single substrate may also enable tunable diplexers that are tuned through a variety of different parameters.

0005Fabricating high performance diplexers in an efficient and cost-effective manner is problematic. Increasing the Q of the inductors and the capacitors in the diplexer is also an issue. Reducing the electromagnetic coupling between the various components in the diplexer, while decreasing the size of the diplexer and making the most economical use of resources, would be beneficial.

SUMMARY

0006In one aspect of the disclosure, a diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the through substrate vias. The through substrate vias and the traces operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

0007Another aspect of the disclosure is directed to a diplexer that includes a first port, a second port and a third port. The diplexer also includes a low pass filter between two of the first port, the second port and the third port. The diplexer further includes a second pass filter between two other of the first port, the second port and the third port. The second pass filter is a band pass filter or a high pass filter.

0008In another aspect of the disclosure, a method of fabricating a diplexer is described. The method includes forming a set of through substrate vias in a substrate. A first set of traces is deposited on a first surface of the substrate. A second set of traces is deposited on a second surface of the substrate. The first traces are coupled to first sides of the through substrate vias. The second traces are coupled to second sides of the set of through substrate vias to form a serpentine 3D inductor. A capacitor is formed on the substrate.

0009Another aspect of the disclosure is directed to a diplexer including a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The diplexer further includes a first means for coupling the through substrate vias on the first surface of the substrate. The diplexer further includes a second means for coupling opposite ends of the through substrate vias on a second surface of the substrate opposite the first surface. The first traces and the first means for coupling and the second means for coupling also operate as a 3D inductor. The diplexer also includes means for storing charge supported by the substrate.

0010This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

0011For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

0012<figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram of a chipset employing a diplexer according to an aspect of the present disclosure.

0013<figref idref="DRAWINGS">FIG. 2A</figref> is a schematic diagram of a diplexer design according to an aspect of the present disclosure.

0014<figref idref="DRAWINGS">FIG. 2B</figref> is a top view of a layout of a diplexer design according to an aspect of the present disclosure.

0015<figref idref="DRAWINGS">FIG. 2C</figref> is a 3D view of a layout of a diplexer design according to an aspect of the present disclosure.

0016<figref idref="DRAWINGS">FIG. 3</figref> is a graph illustrating performance of a diplexer design according to an aspect of the present disclosure.

0017<figref idref="DRAWINGS">FIG. 4A</figref> is a schematic diagram of a diplexer design according to an aspect of the present disclosure.

0018<figref idref="DRAWINGS">FIG. 4B</figref> is a top view of a layout of a diplexer design according to an aspect of the present disclosure.

0019<figref idref="DRAWINGS">FIG. 4C</figref> is a 3D view of a layout of a diplexer design according to an aspect of the present disclosure.

0020<figref idref="DRAWINGS">FIG. 4D</figref> is a top view of a layout of a diplexer design according to an aspect of the present disclosure.

0021<figref idref="DRAWINGS">FIG. 4E</figref> is a 3D view of a layout of a diplexer design according to an aspect of the present disclosure.

0022<figref idref="DRAWINGS">FIG. 5</figref> is a graph illustrating performance of a diplexer design according to an aspect of the present disclosure.

0023<figref idref="DRAWINGS">FIG. 6</figref> is a process flow diagram illustrating a method of making a diplexer design according to an aspect of the present disclosure.

0024<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram showing an exemplary wireless communication system in which a configuration of the disclosure may be advantageously employed.

0025<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component according to one configuration.

DETAILED DESCRIPTION

0026The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may he practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. As described herein, the use of the term “and/or” is intended to represent an “inclusive OR”, and the use of the term “or” is intended to represent an “exclusive OR”.

0027<figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram of a chipset <b>100</b> employing a diplexer <b>114</b> according to an aspect of the present disclosure. The chipset <b>100</b> includes a power amplifier <b>102</b>, a duplexer/filter <b>104</b>, a radio frequency (RE) switch module <b>106</b>, a passive combiner <b>108</b>, a receiver <b>110</b>, a tuner circuitry <b>112</b> (e.g., a first tuner circuitry <b>112</b>A and a second tuner circuitry <b>112</b>B), a diplexer <b>114</b>, a capacitor <b>116</b>, an inductor <b>118</b>, a ground terminal <b>115</b> and an antenna <b>120</b>. The power amplifier <b>102</b> amplifies signal(s) to a certain power level for transmission. The duplexer/filter <b>104</b> filters the input/output signals according to a variety of different parameters, including frequency, insertion loss, rejection or other like parameters. The RF switch module <b>106</b> may select certain portions of the input signals to pass on to the rest of the chipset <b>100</b>. The passive combiner <b>108</b> combines the detected power from the first tuner circuitry <b>112</b>A and the second tuner circuitry <b>112</b>B. The receiver <b>110</b> processes the information from the passive combiner <b>108</b> and uses this information to further operate the chipset <b>100</b>. The tuner circuitry <b>112</b> (e.g., the first tuner circuitry <b>112</b>A and the second tuner circuitry <b>112</b>B) includes components such as a tuner, a portable data entry terminal (PDET), and a house keeping analog to digital converter (HKADC). The tuner circuitry <b>112</b> may perform impedance tuning (e.g., a voltage standing wave ratio (VSWR) optimization) for the antenna <b>120</b>.

0028As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the diplexer <b>114</b> is between the tuner component of the tuner circuitry <b>112</b> and the capacitor <b>116</b>, the inductor <b>118</b> and the antenna <b>120</b>. The diplexer <b>114</b> may be placed between the antenna <b>120</b> and the tuner circuitry <b>112</b> to provide high system performance for the chipset <b>100</b>. The diplexer <b>114</b> also performs frequency domain multiplexing on both high band frequencies and low band frequencies. After the diplexer <b>114</b> performs its frequency multiplexing functions on the input signals, the output of the diplexer <b>114</b> is fed to an optional LC (inductor/capacitor) network including the capacitor <b>116</b> and the inductor <b>118</b>. The LC network may provide extra impedance matching components for the antenna <b>120</b>, when desired. Then a signal with the particular frequency is transmitted or received by the antenna <b>120</b>.

0029<figref idref="DRAWINGS">FIG. 2A</figref> is a schematic diagram of a diplexer design <b>200</b> according to an aspect of the present disclosure. The diplexer design <b>200</b> includes a first input port <b>204</b>, a second input port <b>222</b>, a high pass filter match block <b>202</b>, a low pass filter match block <b>220</b>, a ground terminal <b>216</b>, and an antenna port <b>218</b>. The high pass filter match block <b>202</b> includes a first capacitor <b>210</b> (C₁₁), a second capacitor <b>212</b> (C₁₂), a first inductor <b>206</b> (L₁₁), and a third capacitor <b>214</b> (C₁₃). The low pass filter match block <b>220</b> includes a second inductor <b>224</b> (L₂₁), a fourth capacitor <b>230</b> (C₂₁), a third inductor <b>226</b> (L₂₂), and a fourth inductor <b>228</b> (L₂₃). In this configuration, a topology of the diplexer design <b>200</b> uses the high pass filter match block <b>202</b> to trap frequencies from the second input port <b>222</b>, and uses the low pass filter match block <b>220</b> to trap frequencies from the first input port <b>204</b>. In one implementation, the high pass filter match block <b>202</b> may operate as a low pass filter or a band pass filter. In another implementation, the low pass filter match block <b>220</b> may operate as a high pass filter or a hand pass filter. In a further implementation, the high pass filter match block <b>202</b> and the low pass filter match block <b>220</b> are different types of filters. The high pass fitter match block <b>202</b> and the low pass filter match block <b>220</b> may also be the same type of filter.

0030<figref idref="DRAWINGS">FIG. 2B</figref> is a top view of a layout of a diplexer design <b>240</b> according to an aspect of the present disclosure. The layout of the diplexer design <b>240</b> corresponds to the schematic diagram of the diplexer design <b>200</b> from <figref idref="DRAWINGS">FIG. 2A</figref>. Also, the components are implemented within (or on) semiconductor substrate <b>242</b>. As described herein, the term “semiconductor substrate” may refer to a substrate of a diced wafer or may refer to the substrate of a wafer that is not diced. In one configuration, the semiconductor substrate is comprised of glass, air, quartz, sapphire, high-resistivity silicon, or other like semiconductor materials.

0031As can be seen from <figref idref="DRAWINGS">FIG. 2B</figref>, the first input pad <b>204</b>, the second input pad <b>222</b>, the ground terminal pad <b>216</b>, and the antenna pad <b>218</b> may be implemented as, wafer level chip scale package (WLCSP) balls, for example. The capacitors (e.g., first capacitor <b>210</b> (C₁₁), the second capacitor <b>212</b> (C₁₂), the third capacitor <b>214</b> (C₁₃), and the fourth capacitor <b>230</b> (C₂₁)) may be implemented as a layered structure of conductive layers (e.g., a layered metal-insulator-metal structure), but are not limited to the structure shown in <figref idref="DRAWINGS">FIG. 2B</figref>. Furthermore, the geometry and arrangement of the various inductor and capacitor components in the diplexer design <b>240</b> reduce the electromagnetic coupling between the components.

0032In the depicted configuration, the inductors (e.g., the first inductor <b>206</b> (L₁₁), the second inductor <b>224</b> (L₂₁), the third inductor <b>226</b> (L₂₂), and the fourth inductor <b>228</b> (L₂₃)) are implemented as a series of traces and through substrate vias that are further illustrated in the 3D view of <figref idref="DRAWINGS">FIG. 2C</figref>. A more detailed explanation of the inductors will be provided below with respect to <figref idref="DRAWINGS">FIG. 2C</figref>. Again, the structures of the inductors (e.g., the first inductor <b>206</b> (L₁₁), the second inductor <b>224</b> (L₂₁), the third inductor <b>226</b> (L₂₂), and the fourth inductor <b>228</b> (L₂₃)) shown in <figref idref="DRAWINGS">FIG. 2B</figref> are not limited to the structures shown and can take on any structure. The layout of the diplexer design <b>240</b> is one implementation of the diplexer design <b>200</b> shown in <figref idref="DRAWINGS">FIG. 2A</figref>. Also, as shown in <figref idref="DRAWINGS">FIG. 2B</figref>, the high pass filter match block <b>202</b> and the low pass filler match block <b>220</b> are shown in the areas boxed in by the dotted-line borders.

0033<figref idref="DRAWINGS">FIG. 2C</figref> is a 3D view of a layout of a diplexer design <b>240</b> according to an aspect of the present disclosure <figref idref="DRAWINGS">FIG. 2C</figref> is a 3D view of the same diplexer design <b>240</b> in <figref idref="DRAWINGS">FIG. 2B</figref>, and therefore has the same components as shown in <figref idref="DRAWINGS">FIG. 2B</figref>. In <figref idref="DRAWINGS">FIG. 2C</figref>, the inductors (e.g., the first inductor <b>206</b> (L₁₁), the second inductor <b>224</b> (L₂₁), the third inductor <b>226</b> (L₂₂), and the fourth inductor <b>228</b> (L₂₃)) are shown as through substrate via inductors (e.g., through glass via inductors if the semiconductor substrate <b>242</b> is glass). Representatively, the inductors (e.g., the first inductor <b>206</b> (L₁₁), the second inductor <b>224</b> (L₂₁), the third inductor <b>226</b> (L₂₂), and the fourth inductor <b>228</b> (L₂₃)) are arranged from a first set of traces on a top surface of the semiconductor substrate <b>242</b>, and a second set of traces on a second surface of the semiconductor substrate <b>242</b> opposite the first surface. In this configuration, the sets of traces are on opposing first and second surfaces of the semiconductor substrate <b>242</b> and coupled together by the through substrate vias in a serpentine manner. In <figref idref="DRAWINGS">FIG. 2C</figref>, the semiconductor substrate <b>242</b>, is transparent to ease the viewing of both sets of traces and the through substrate vias of the first inductor <b>206</b> (L₁₁), the second inductor <b>224</b> (L₂₁), the third inductor <b>226</b> (L₂₂), and the fourth inductor <b>228</b> (L₂₃).

0034As shown in <figref idref="DRAWINGS">FIG. 2C</figref>, the capacitors (e.g., the first capacitor <b>210</b> (C₁₁), the second capacitor <b>212</b> (C₁₂), the third capacitor <b>214</b> (C₁₃), and the fourth capacitor <b>230</b> (C₂₁)) are deposited on the first surface of the semiconductor substrate <b>242</b>. Also, the first input pad <b>204</b>, the second input pad <b>222</b>, the ground terminal pad <b>216</b>, and the antenna pad <b>218</b> may be deposited on the first surface of the semiconductor substrate <b>242</b>. The first input pad <b>204</b>, the second input pad <b>222</b>, the ground terminal pad <b>216</b>, and the antenna pad <b>218</b> may also be accessed by a cylindrical via (or other connection) for electrically coupling to other sources of voltage/current. The high pass filter match block <b>202</b> and the low pass filter match block <b>220</b> are shown within the dotted-line borders. In one implementation, the size of the diplexer design <b>240</b> is smaller than a conventional diplexer size, for example, at least due to the use of through substrate via/through glass via inductors and metal-insulator-metal capacitors that conserve space.

0035<figref idref="DRAWINGS">FIG. 3</figref> is a graph <b>300</b> illustrating performance of a diplexer design according to an aspect of the present disclosure. The x-axis of the graph <b>300</b> reflects the frequency in gigahertz (GHz) and the y-axis of the graph <b>300</b> reflects a decibel (dB) rating. A high pass filter curve <b>302</b> is a frequency response (transmission in dB) of a high pass filter match block (e.g., the high pass filter match block <b>202</b>). A low pass filter curve <b>304</b> is a frequency response (transmission in dB) of a low pass filter match block (e.g., the low pass filter match block <b>220</b>) In the diplexer configuration of <figref idref="DRAWINGS">FIGS. 2A-2C</figref>, an antenna pad (e.g., the antenna pad <b>218</b>) is the output for both the high pass filter match block <b>202</b> and low pass filter match block <b>220</b>, whereas the input pads (e.g., the first input pad <b>204</b>, the second input pad <b>222</b>) are separate.

0036Referring again to <figref idref="DRAWINGS">FIG. 3</figref>, as seen by point m<b>15</b> on the high pass filter curve <b>302</b>, at a lower frequency of 710.0 MHz, the rejection is 47 dB (e.g., the high pass filter match block rejects signals at lower frequencies). As seen by point m<b>17</b> on the low pass filter curve <b>304</b>, the rejection is 50 dB at 2.13 GHz. By contrast, a conventional multi-layer ceramic chip (MLCC) diplexers may be limited to less than a 40 dB rejection, especially for high frequencies above 2 GHz. For both the low pass filter and high pass filter branches, the insertion loss may be in the 0.3 dB range, which is unavailable from conventional MLCC diplexers, especially for frequencies above 2 GHz.

0037Therefore, a through substrate via/through glass via diplexer (e.g., the diplexer configuration of <figref idref="DRAWINGS">FIGS. 2A-2C</figref>) delivers improved rejection compared to the rejection available from conventional MLCC diplexers, as well as a reduced insertion loss and a smaller size. For instance, the high pass filter curve <b>302</b> shows an insertion loss of less than 0.4 dB at frequencies such as 1.7 GHz, and a rejection of 47 dB at 710 MHz. Also, the low pass filter curve <b>304</b> shows an insertion loss of less than 0.4 dB at 1.04 GHz, and a rejection of 50 dB at 2.13 GHz.

0038<figref idref="DRAWINGS">FIG. 4A</figref> is a schematic diagram of a diplexer design <b>400</b> according to another aspect of the present disclosure. The diplexer design <b>400</b> includes a low pass filter match block <b>402</b>, a band pass filter match block <b>420</b>, an antenna port <b>418</b> and a ground terminal <b>416</b>. The low pass filter match block <b>402</b> includes a low pass input port <b>404</b>, a first inductor <b>406</b> (L₁₁), and a second inductor <b>408</b> (L₁₂). The low pass filter match block <b>402</b> also includes a first capacitor <b>410</b> (C₁₁), a second capacitor <b>412</b> (C₁₂), a third capacitor <b>414</b> (C₁₃), and a ground terminal <b>416</b>. The band pass filter match block <b>420</b> includes a band pass input port <b>422</b>, a third inductor <b>424</b> (L₂₁), and a fourth inductor <b>426</b> (L₂₂). The hand pass filter match block <b>420</b> also includes a fourth capacitor <b>430</b> (C₂₁), a fifth capacitor <b>432</b> (C₂₂), a sixth capacitor <b>434</b> (C₂₃), a seventh capacitor <b>436</b> (C₂₄), an eighth capacitor <b>438</b> (C₂₅), and the ground terminal <b>416</b>. The low pass filter match block <b>402</b> may be a high pass filter or a band pass filter. The band pass filter match block <b>420</b> may be a high pass filter or a low pass filter. The hand pass filter match block <b>420</b> and the low pass filter match block <b>402</b> may be different types of filters. The band pass filler match block <b>420</b> and the low pass filter match block <b>402</b> may also be the same type of filter.

0039In one implementation, the low pass input port <b>404</b> inputs low frequency signals. The band pass input port <b>422</b> may input signals at certain band frequencies. A topology of the diplexer design <b>400</b> may use the low pass filter match block <b>402</b> to trap frequencies from the band pass input port <b>422</b>. The diplexer design <b>400</b> may also use the band pass filter match block <b>420</b> to trap frequencies from the low pass input port <b>404</b>.

0040<figref idref="DRAWINGS">FIG. 4B</figref> is a top view of a layout of a diplexer design <b>440</b> according to an aspect of the present disclosure. The layout of the diplexer design <b>440</b> corresponds to the schematic diagram of the diplexer design <b>400</b> from <figref idref="DRAWINGS">FIG. 4A</figref>. Also, the components are implemented within (or on) a semiconductor substrate <b>442</b>. As shown in <figref idref="DRAWINGS">FIG. 48</figref>, a low pass input pad <b>404</b>, a band pass input pad <b>422</b>, a ground terminal pad <b>416</b>, and an antenna pad <b>418</b> are implemented as WLCSP balls although any suitable implementation could be used alternatively.

0041The capacitors (e.g., the first capacitor <b>410</b> (C₁₁), the second capacitor <b>412</b> (C₁₂), the third capacitor <b>414</b> (C₁₃), the fourth capacitor <b>430</b> (C₂₁), the fifth capacitor <b>432</b> (C₂₂), the sixth capacitor <b>434</b> (C₂₃), the seventh capacitor <b>436</b> (C₂₄), and the eighth capacitor <b>438</b> (C₂₅)) may be implemented as a layered structure (e.g., a layered metal-insulator-metal capacitor structure), but are not limited to the structure shown in <figref idref="DRAWINGS">FIG. 4B</figref>. In one implementation, the capacitor is disposed on only one side of the substrate, in order to conserve space and materials. Furthermore, the geometry and arrangement of the various inductor and capacitor components in the diplexer design <b>440</b> reduce the electromagnetic coupling between the components.

0042In this configuration, the inductors (cog., the first inductor <b>406</b> (L₁₁), the second inductor <b>408</b> (L₁₂), the third inductor <b>424</b> (L₂₁), and the fourth inductor <b>426</b> (L₂₂)) may be implemented as a series of traces and through substrate vias that are further illustrated in the 3D view of <figref idref="DRAWINGS">FIG. 4C</figref>. A more detailed explanation of the inductors is provided in <figref idref="DRAWINGS">FIG. 4C</figref>. Again, the structure of the inductors shown in <figref idref="DRAWINGS">FIG. 48</figref> is not limited to the structure shown and can take on any structure. The layout of the diplexer design <b>440</b> is one implementation of the diplexer design <b>400</b> shown in <figref idref="DRAWINGS">FIG. 4A</figref>. Also, as shown in <figref idref="DRAWINGS">FIG. 48</figref>, the low pass filter match block <b>402</b> and the band pass filter match block <b>420</b> are shown in the areas boxed in by the dotted-line borders.

0043<figref idref="DRAWINGS">FIG. 4C</figref> is a 3D view of a layout of a diplexer design <b>440</b> according to an aspect of the present disclosure. <figref idref="DRAWINGS">FIG. 4C</figref> is a 3D view of the same diplexer design <b>440</b> in <figref idref="DRAWINGS">FIG. 48</figref>, and therefore has the same components as shown in <figref idref="DRAWINGS">FIG. 4B</figref>. In <figref idref="DRAWINGS">FIG. 4C</figref>, the inductors (e.g., the first inductor <b>406</b> (L₁₁), the second inductor <b>408</b> (L₁₂), the third inductor <b>424</b> (L₂₁), and the fourth inductor <b>426</b> (L₂₂)) are shown as through substrate via inductors (e.g., through glass via inductors if the semiconductor substrate <b>442</b> is glass). Representatively, the inductors (e.g., the first inductor <b>406</b> (L₁₁), the second inductor <b>408</b> (L₁₂), the third inductor (L₂₁) <b>424</b>, and the fourth inductor <b>426</b> (L₂₂)) may have a first set of traces on a first surface of the semiconductor substrate <b>442</b>, and a second set of traces on a second surface of the semiconductor substrate <b>442</b>. In this configuration, the sets of traces are on opposing first and second surfaces of the semiconductor substrate <b>442</b> and coupled together by the through substrate vias in a serpentine manner. In <figref idref="DRAWINGS">FIG. 4C</figref>, the semiconductor substrate <b>442</b> is transparent to ease the viewing of both sets of traces and the through substrate vias of the inductors.

0044As shown in <figref idref="DRAWINGS">FIG. 4C</figref>, the capacitors (e.g., the first capacitor <b>410</b> (C₁₁), the second capacitor <b>412</b> (C₁₂), the third capacitor <b>414</b> (C₁₃), the fourth capacitor <b>430</b> (C₂₁), the fifth capacitor <b>432</b> (C₂₂), the sixth capacitor <b>434</b> (C₂₃), the seventh capacitor <b>436</b> (C₂₄), and the eighth capacitor <b>438</b> (C₂₅)) may be deposited on the first surface of the semiconductor substrate <b>442</b>. Also, the low pass input pad <b>404</b>, the band pass input pad <b>422</b>, the antenna pad <b>418</b>, and the ground terminal pad <b>416</b> may be deposited on the first surface of the semiconductor substrate <b>442</b>. The low pass input pad <b>404</b>, the hand pass input pad <b>422</b>, the antenna pad <b>418</b> and the ground terminal pad <b>416</b> may also be accessed by a cylindrical via (or other connection) for electrically coupling to other sources of voltage/current. The low pass filter match block <b>402</b> and the band pass filter match block <b>420</b> are shown within the dotted-line borders. In one implementation, the size of the diplexer design <b>440</b> is smaller than a conventional diplexer size, for example, at least due to the use of through substrate via/through glass via inductors for conserving space.

0045The diplexer design <b>440</b> may be a diplexer design for a different application (e.g., a small cell or a femto cell). This diplexer design (e.g., for a small cell application) is different from the one in <figref idref="DRAWINGS">FIG. 2A</figref> in that it has a low pass filter match branch and a band-pass filter match branch, while the design in <figref idref="DRAWINGS">FIG. 2A</figref> has a low pass filter branch and high pass filter branch. In this implementation, the fundamental difference is also more components added to combine the low pass filter and band pass filter into a single diplexer circuit.

0046<figref idref="DRAWINGS">FIG. 4D</figref> is a top view of a layout of a diplexer design <b>450</b> according to an aspect of the present disclosure. The layout of the diplexer design <b>450</b> corresponds to the schematic diagram of the diplexer design <b>400</b> from <figref idref="DRAWINGS">FIG. 4A</figref>. Also, the components are implemented within (or on) a semiconductor substrate <b>492</b>. As shown in <figref idref="DRAWINGS">FIG. 4D</figref>, a low pass input pad <b>454</b>, a band pass input pad <b>472</b>, a ground terminal pad <b>466</b>, and an antenna pad <b>468</b> are implemented as WLCSP balls, although any suitable implementation could be used alternatively. The components shown in <figref idref="DRAWINGS">FIG. 4D</figref> are also similar to the components shown in <figref idref="DRAWINGS">FIG. 4B</figref>, with some differences in terms of the arrangement and the capacitance/inductance values.

0047The capacitors (e.g., the first capacitor <b>460</b> (C₁₁), the second capacitor <b>462</b> (C₁₂), the third capacitor <b>464</b> (C₁₃), the fourth capacitor <b>480</b> (C₂₁), the fifth capacitor <b>482</b> (C₂₂), the sixth capacitor <b>484</b> (C₂₃), the seventh capacitor <b>486</b> (C₂₄), and the eighth capacitor <b>488</b> (C₂₅)) may be implemented as a layered structure (e.g., a layered metal-insulator-metal capacitor structure), but are not limited to the structure shown in <figref idref="DRAWINGS">FIG. 4D</figref>. In one implementation, the capacitor is disposed on only one side of the substrate, to conserve space and materials. Furthermore, the geometry and arrangement of the various inductor and capacitor components in the diplexer design <b>450</b> may reduce the electromagnetic coupling between the components. The capacitors in <figref idref="DRAWINGS">FIG. 4D</figref> may also have different capacitance values than their corresponding counterparts in <figref idref="DRAWINGS">FIG. 4B</figref>.

0048In this configuration, the inductors (e.g., the first inductor <b>456</b> (L₁₁), the second inductor <b>458</b> (L₁₂), the third inductor <b>474</b> (L₂₁), and the fourth inductor <b>476</b> (L₂₂)) may be implemented as a series of traces and through substrate vias that are further illustrated in the 3D view of <figref idref="DRAWINGS">FIG. 4E</figref>. A more detailed explanation of the inductors is provided in <figref idref="DRAWINGS">FIG. 4E</figref>. Again, the structure of the inductors shown in <figref idref="DRAWINGS">FIG. 4D</figref> is not limited to the structure shown and can take on any structure. The layout of the diplexer design <b>450</b> is one implementation of the diplexer design <b>400</b> shown in <figref idref="DRAWINGS">FIG. 4A</figref>.

0049As shown in <figref idref="DRAWINGS">FIG. 4D</figref>, the low pass filter match block <b>452</b> and the band pass filter match block <b>470</b> are shown in the areas boxed in by the dotted-line borders. Furthermore, the third inductor <b>474</b> (L₂₁) in <figref idref="DRAWINGS">FIG. 4D</figref> is arranged in a diagonal pattern different than the third inductor <b>424</b> (L₂₁) shown in <figref idref="DRAWINGS">FIG. 4B</figref>, which is arranged in a horizontal pattern. Also, the fourth inductor <b>476</b> (L₂₂) in <figref idref="DRAWINGS">FIG. 4D</figref> is arranged in a horizontal pattern different than the fourth inductor <b>426</b> (L₂₂) shown in <figref idref="DRAWINGS">FIG. 4B</figref>, which is arranged in a vertical pattern. In addition, the first inductor <b>456</b> (L₁₁) in <figref idref="DRAWINGS">FIG. 4D</figref> has five traces, which is different than the first inductor <b>406</b> (L₁₁) in <figref idref="DRAWINGS">FIG. 4B</figref>, which has four traces. Also, the second inductor <b>458</b> (L₁₂) in FIG. <b>4</b>D has six traces, which is different than the second inductor <b>408</b> (L₁₂) in <figref idref="DRAWINGS">FIG. 4B</figref>, which has five traces. All the inductors in <figref idref="DRAWINGS">FIG. 4D</figref> may also have different capacitance values than their corresponding counterparts in <figref idref="DRAWINGS">FIG. 4B</figref>.

0050<figref idref="DRAWINGS">FIG. 4E</figref> is a 3D view of a layout of a diplexer design <b>450</b> according to an aspect of the present disclosure. <figref idref="DRAWINGS">FIG. 4E</figref> is a 3D view of the same diplexer design <b>450</b> in <figref idref="DRAWINGS">FIG. 4D</figref>, and therefore has similar components to those shown in <figref idref="DRAWINGS">FIG. 4D</figref>. In <figref idref="DRAWINGS">FIG. 4E</figref>, the inductors (e.g., the first inductor <b>456</b> (L₁₁), the second inductor <b>458</b> (L₁₂), the third inductor <b>474</b> (L₂₁), and the fourth inductor <b>476</b> (L₂₂)) are shown as through substrate via inductors (e.g., through glass via inductors if the semiconductor substrate <b>492</b> is glass). Representatively, the inductors (e.g., the first inductor <b>456</b> (L₁₁), the second inductor <b>458</b> (L₁₂), the third inductor <b>474</b> (L₂₁), and the fourth inductor <b>476</b> (L₂₂)) may have a first set of traces on a first surface of the semiconductor substrate <b>492</b>, and a second set of traces on a second surface of the semiconductor substrate <b>492</b>. In this configuration, the sets of traces are on opposing first and second surfaces of the semiconductor substrate <b>492</b> and coupled together by the through substrate vias in a serpentine manner. In <figref idref="DRAWINGS">FIG. 4E</figref>, the semiconductor substrate <b>492</b> is transparent to ease the viewing of both sets of traces and the through substrate vias of the inductors.

0051As shown in <figref idref="DRAWINGS">FIG. 4E</figref>, the capacitors (e.g., the first capacitor <b>460</b> (C₁₁), the second capacitor <b>462</b> (C₁₂), the third capacitor <b>464</b> (C₁₃), the fourth capacitor <b>480</b> (C₃₁), the fifth capacitor <b>482</b> (C₂₂), the sixth capacitor <b>484</b> (C₂₃), the seventh capacitor <b>486</b> (C₂₄), and the eighth capacitor <b>488</b> (C₂₅)) may be deposited on the first surface of the semiconductor substrate <b>492</b>. Also, the low pass input pad <b>454</b>, the band pass input pad <b>472</b>, the antenna pad <b>468</b>, and the ground terminal pad <b>466</b> may be deposited on the first surface of the semiconductor substrate <b>492</b>. The low pass input pad <b>454</b>, the band pass input pad <b>472</b>, the antenna pad <b>468</b> and the ground terminal pad <b>466</b> may also be accessed by a cylindrical via or other connection) for electrically coupling to other sources of voltage/current. The low pass filter match block <b>452</b> and the band pass filter match block <b>470</b> are shown within the dotted-line borders. In one implementation, the size of the diplexer design <b>450</b> is smaller than a conventional diplexer size, for example, at least due to the use of through substrate via/through glass via inductors for conserving space.

0052The diplexer design <b>450</b> may be a diplexer design for a different application (e.g., a small cell or a femto cell and also having a WLAN 5 GHz trap). This diplexer design (e.g., for a small cell application) is different from the one in <figref idref="DRAWINGS">FIG. 2A</figref> in that it has an low pass filter match branch and a band-pass filter match branch, while the one in <figref idref="DRAWINGS">FIG. 2A</figref> has a low pass filter branch and high pass filter branch, in this implementation, the fundamental difference is also more components added to combine the low pass filter and band pass filter into a single diplexer circuit. The particular diplexer design <b>450</b> shown in <figref idref="DRAWINGS">FIGS. 4D and 4E</figref> (when compared to the diplexer design <b>440</b> shown in <figref idref="DRAWINGS">FIGS. 4B and 4C</figref>) may also have the layout configuration, capacitance values and inductance values to achieve greater than 30 dB rejection at 5.5 GHz. This particular diplexer design <b>450</b> may also have a band-pass filter and a WLAN 5 GHz trap as the band-reject component.

0053In one implementation, thick conductive films (e.g., metal) may be used on both sides of the capacitors to make the capacitors have a high Q (or quality) factor. In one example, the bottom plate may have conductive film with a thickness of up to 5 μm and the top plate may have conductive film with a thickness of up to 3 μm. This may be uncommon in traditional CMOS based capacitors, which often use thin metals (e.g., 100 to 200 nm). In this implementation, the semiconductor substrate (e.g., the semiconductor substrates <b>242</b>, <b>442</b>, <b>492</b>) may be fabricated from a low loss material that includes glass, air, quartz, sapphire, high-resistivity silicon, or other like semiconductor materials. In one implementation, the capacitor may also be disposed on only one side of the semiconductor substrate (e.g., the semiconductor substrates <b>242</b>, <b>442</b>, <b>492</b>). In one implementation, the inductors (e.g., when the semiconductor substrates <b>242</b>, <b>442</b>, <b>492</b> are glass) are through glass via inductors. Such a through glass via implementation may also give the inductors a high Q (or quality) factor.

0054<figref idref="DRAWINGS">FIG. 5</figref> is a graph <b>500</b> illustrating performance of a diplexer design according to an aspect of the present disclosure. The graph <b>500</b> is similar to the graph <b>300</b> of <figref idref="DRAWINGS">FIG. 3</figref>. That is, the x-axis of the graph <b>500</b> reflects the frequency in gigahertz (GHz), and the y-axis of the graph <b>500</b> reflects a decibel (dB) rating. The curve <b>502</b> is the frequency response for the low pass filter branch, and the curve <b>504</b> is the frequency response for the band pass filter branch.

0055Even though it is not shown on the graph, the diplexer of the present disclosure may also achieve greater than 30 dB rejection (for example, around 34 dB) at 5.5 GHz, to trap the WLAN 5 GHz band. In one implementation, the greater than 30 dB rejection at 5.5 GHz results may be achieved with a low pass filter (with a frequency range of 698 to 960 MHz) and a band pass filter (with a frequency range of 1710 to 2690 MHz) in the same diplexer.

0056<figref idref="DRAWINGS">FIG. 6</figref> is a process flow diagram illustrating a method <b>600</b> of making a diplexer design according to an aspect of the present disclosure. In block <b>602</b>, through substrate vias are formed in a substrate. In block <b>604</b>, a first set of traces are deposited on a first surface of the substrate and coupled to the through substrate vias. In block <b>606</b>, a second set of traces are deposited on a second surface of the substrate. The traces on the first surface are coupled to the traces on the second surface by the through substrate vias in a serpentine manner to create a 3D through substrate via/through glass via inductor. In one implementation, the second surface of the substrate is opposite to the first surface of the substrate. In block <b>608</b>, a capacitor is formed on the substrate. The capacitor may be formed on only one side of the substrate to conserve space and materials.

0057Although blocks are shown in a particular sequence, the present disclosure is not so limited. For example, block <b>608</b> (forming a capacitor on the substrate) may be performed prior to block <b>604</b> (depositing traces on a first surface of the substrate). In another example, block <b>608</b> (forming a capacitor on the substrate) may be performed prior to block <b>606</b> (depositing traces on a second surface of the substrate). The end result is a diplexer design, such as the diplexer design <b>240</b> of <figref idref="DRAWINGS">FIGS. 2B-2C</figref> or the diplexer designs <b>400</b>, <b>440</b> or <b>450</b> of <figref idref="DRAWINGS">FIGS. 4A-4E</figref>.

0058According to a further aspect of the present disclosure, circuitry for diplexer designs using through glass via or through substrate via technology is described. The diplexer includes a substrate having through substrate vias. The diplexer also includes a first means for coupling the through substrate vias on a first surface of the substrate. The diplexer further includes a second a means for coupling the opposite ends of the through substrate vias on a second surface of the substrate opposite the first surface. In this configuration, the through substrate vias and the first and second means for coupling operate as a 3D inductor. The first and second means for coupling may be the traces shown in <figref idref="DRAWINGS">FIGS. 2B</figref>, <b>2</b>C, <b>4</b>B, and <b>4</b>C.

0059In this configuration, the diplexer also includes a means for storing charge supported by the substrate. The charge storing means may be the a capacitors (e.g., the first capacitor <b>410</b> (C₁₁), the second capacitor <b>412</b> (C₁₂), the third capacitor <b>414</b> (C₁₃), fourth capacitor <b>430</b> (C₂₁), the fifth capacitor <b>432</b> (C₂₂), the sixth capacitor <b>434</b> (C₂₃), the seventh capacitor <b>436</b> (C₂₄), and the eighth capacitor <b>438</b> (C₂₅). In another aspect, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

0060<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram showing an exemplary wireless communication system <b>700</b> in which an aspect of the disclosure may be advantageously employed. For purposes of illustration, <figref idref="DRAWINGS">FIG. 7</figref> shows three remote units <b>720</b>, <b>730</b>, and <b>750</b> and two base stations <b>740</b>. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units <b>720</b>, <b>730</b>, and <b>750</b> include IC devices <b>725</b>A, <b>725</b>C, and <b>725</b>B that include the disclosed diplexer devices. It will be recognized that other devices may also include the disclosed diplexer devices, such as the base stations, switching devices, and network equipment. <figref idref="DRAWINGS">FIG. 7</figref> shows forward link signals <b>780</b> from the base station <b>740</b> to the remote units <b>720</b>, <b>730</b>, and <b>750</b> and reverse link signals <b>790</b> from the remote units <b>720</b>, <b>730</b>, and <b>750</b> to base stations <b>740</b>.

0061In <figref idref="DRAWINGS">FIG. 7</figref>, remote unit <b>720</b> is shown as a mobile telephone, remote unit <b>730</b> is shown as a portable computer, and remote unit <b>750</b> is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or other devices that store or retrieve data or computer instructions, or combinations thereof. Although <figref idref="DRAWINGS">FIG. 7</figref> illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed diplexer devices.

0062<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the diplexer devices disclosed above. A design workstation <b>800</b> includes a hard disk <b>801</b> containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation <b>800</b> also includes a display <b>802</b> to facilitate design of a circuit <b>810</b> or a semiconductor component <b>812</b> such as a diplexer device. A storage medium <b>804</b> is provided for tangibly storing the circuit design <b>810</b> Of the semiconductor component <b>812</b>. The circuit design <b>810</b> or the semiconductor component <b>812</b> may be stored on the storage medium <b>804</b> in a file format such as GDSH or GERBER. The storage medium <b>804</b> may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation <b>800</b> includes a drive apparatus <b>803</b> for accepting input from or writing output to the storage medium <b>804</b>.

0063Data recorded on the storage medium <b>804</b> may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium <b>804</b> facilitates the design of the circuit design <b>810</b> or the semiconductor component <b>812</b> by decreasing the number of processes for designing semiconductor wafers.

0064For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used herein, the term “memory” refers to types of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

0065If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

0066In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

0067Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. For example, relational terms, such as “above” and “below” are used with respect to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if oriented sideways, above and below may refer to sides of a substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function Of achieve substantially the same result as the corresponding configurations described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.