Power converter

CROSS-REFERENCE TO RELATED APPLICATION

0001This application is based on and claims the benefit of priority from earlier Japanese Patent Application No. 2012-240388 filed Oct. 31, 2012, the description of which is incorporated herein by reference.

BACKGROUND

00021. Technical Field

0003The present invention relates to a power converter including a plurality of semiconductor modules each formed of semiconductor elements.

00042. Related Art

0005A known power converter operable to convert direct-current (DC) power/alternating-current (AC) power into AC power/DC power, as disclosed in Japanese Patent Application Laid-Open Publication No. 2010-41809, includes a plurality of semiconductor modules each formed of semiconductor elements, such as insulated-gate bipolar transistors (IGBTs), and a control circuit board that controls the operation of each semiconductor element.

0006Each semiconductor module has a body including the semiconductor elements, from which control terminals, a pair of input terminals, and three output terminals protrude. A DC voltage is applied to the input terminals. The control terminals are connected to the control circuit board, which turns on and off the respective semiconductor elements of the respective semiconductor modules so as to convert a DC voltage applied to the input terminals into a three-phase AC voltage to be outputted from the output terminals.

0007The three output terminals of each semiconductor module are connected to an AC load, such as a three-phase AC motor, via bus bars or connectors or the like.

0008The three output terminals of each semiconductor module form one individual output terminal group, via which the three-phase AC voltage is outputted from the semiconductor module to the AC load. The power converter therefore includes a plurality of such output terminal groups for the respective semiconductor modules.

0009In the disclosed power converter, however, for each output terminal group, a combination of the three output terminals forming the output terminal group is predefined, that is, the three output terminals forming the output terminal group belong to a corresponding one of the plurality of semiconductor modules. This may require long bus bars to connect to the respective output terminals of each semiconductor module, which may cause the bus bars to interfere with each other. In addition, when connectors are directly connected to the respective output terminals of each semiconductor module, the connectors may be in close proximity to each other, which may cause the connectors to interfere with each other.

0010In consideration of the foregoing, it would therefore be desirable to have a power converter capable of preventing bus bars or connectors or the like connected to output terminals of respective output terminal groups from electrically interfering with each other.

SUMMARY

0011In accordance with an exemplary embodiment of the present invention, there is provided a power converter including: a plurality of semiconductor modules each having a body including semiconductor elements, the body being provided with control terminals, a pair of input terminals, and at least two output terminals protruding from the body, wherein the output terminals protruding from the bodies of the respective semiconductor modules are grouped into a plurality of output terminal groups each formed of three output terminals belonging to at least two different semiconductor modules; and a control circuit board electrically connected to the control terminals protruding from the bodies of the respective semiconductor modules and configured to turn on and off the respective semiconductor elements of the respective semiconductor modules so as to convert a DC voltage applied to the pair of input terminals of each semiconductor module into a three-phase AC voltage to be outputted from the three output terminals of each output terminal group.

0012In the power converter configured as above, for each of the plurality of output terminal groups, the three output terminals of the output terminal group belong to at least two different semiconductor modules. For example, two of the three output terminals of the output terminal group belong to a first semiconductor module, and one of the three output terminals of the output terminal group belongs to a second semiconductor module.

0013This can enhance the versatility of combinations of three output terminals to form one individual output terminal group. This may thus lead to an optimal combination of three output terminals depending on a shape and/or position of each bus bar such that the output terminals forming one individual output terminal group are in close proximity to each other so that long bus bars are not needed.

0014The present invention can therefor provide a power converter capable of preventing bus bars or connectors connected to the respective output terminals of the respective output terminal groups from interfering with each other.

BRIEF DESCRIPTION OF THE DRAWINGS

0015In the accompanying drawings:

0016<figref idref="DRAWINGS">FIG. 1</figref> is an enlarged perspective view showing a main portion of a power converter in accordance with a first embodiment of the present invention;

0017<figref idref="DRAWINGS">FIG. 2</figref> is a perspective view of the power converter of the first embodiment;

0018<figref idref="DRAWINGS">FIG. 3</figref> is a top view of each semiconductor module of the first embodiment;

0019<figref idref="DRAWINGS">FIG. 4</figref> is a top view of a boost module of the first embodiment;

0020<figref idref="DRAWINGS">FIG. 5</figref> is a perspective view of a reactor of the first embodiment;

0021<figref idref="DRAWINGS">FIG. 6</figref> is a top view of the power converter of the first embodiment having bus bars removed;

0022<figref idref="DRAWINGS">FIG. 7</figref> is a sectional view taken along line VII-VII of <figref idref="DRAWINGS">FIG. 6</figref>;

0023<figref idref="DRAWINGS">FIG. 8</figref> is a sectional view taken along line VIII-VIII of <figref idref="DRAWINGS">FIG. 6</figref>;

0024<figref idref="DRAWINGS">FIG. 9</figref> is a sectional view taken along line IX-IX of <figref idref="DRAWINGS">FIG. 6</figref>;

0025<figref idref="DRAWINGS">FIG. 10</figref> is a circuit diagram of the power converter of the first embodiment;

0026<figref idref="DRAWINGS">FIG. 11</figref> is a schematic diagram of a power converter in accordance with a second embodiment of the present invention;

0027<figref idref="DRAWINGS">FIG. 12</figref> is a schematic diagram of a power converter in accordance with a third embodiment of the present invention;

0028<figref idref="DRAWINGS">FIG. 13</figref> is a schematic diagram of a power converter in accordance with a fourth embodiment of the present invention;

0029<figref idref="DRAWINGS">FIG. 14</figref> is a schematic diagram of a power converter in accordance with a fifth embodiment of the present invention;

0030<figref idref="DRAWINGS">FIG. 15</figref> is a schematic diagram of a power converter in accordance with a sixth embodiment of the present invention; and

0031<figref idref="DRAWINGS">FIG. 16</figref> is a perspective view of an example of comparative power converter.

DESCRIPTION OF SPECIFIC EMBODIMENTS

0032The present invention will now be described more fully hereinafter with reference to the accompanying drawings. The terms “connecting” and “being connected” refer to electrically connecting and being electrically connected, respectively, except where specified otherwise.

First Embodiment

0033There will now be explained a power converter in accordance with a first embodiment of the present invention with reference to <figref idref="DRAWINGS">FIGS. 1 to 10</figref>. The power converter <b>1</b> of the present embodiment, as shown in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>, includes a plurality of semiconductor modules <b>2</b> (<b>2</b><i>a</i>, <b>2</b><i>b</i>) and a control circuit board <b>3</b>. Each semiconductor module <b>2</b> has a body <b>20</b> including semiconductor elements <b>29</b> (see <figref idref="DRAWINGS">FIG. 10</figref>), where control terminals <b>23</b>, a pair of input terminals <b>21</b> to which a DC voltage is applied, and three output terminals <b>22</b> (<b>22</b><i>a</i>, <b>22</b><i>b</i>) protrude from the body <b>20</b>. The control terminals <b>23</b> are connected to the control circuit board <b>3</b> that is configured to turn on and off the respective semiconductor elements <b>29</b> of the respective semiconductor modules <b>2</b> so as to convert a DC voltage applied to the input terminals <b>21</b> into a three-phase AC voltage to be outputted from the output terminals <b>22</b>.

0034A total of six output terminals are grouped into two groups <b>8</b>, where each group has three output terminals <b>22</b>, via which a three-phase AC voltage is outputted from the power converter <b>1</b>. Each group of output terminals <b>8</b> (<b>8</b><i>a</i>, <b>8</b><i>b</i>) are connected to a corresponding AC load <b>80</b> (see <figref idref="DRAWINGS">FIG. 10</figref>). A group of output terminals may hereinafter be referred to as an output terminal group.

0035Each semiconductor module <b>2</b> has three output terminals <b>22</b>. A first one of the two output terminal groups includes one output terminal <b>22</b><i>a </i>of the semiconductor module <b>2</b><i>a </i>and two output terminals <b>22</b><i>b </i>of the semiconductor module <b>2</b><i>b</i>. A second one of the two groups includes two output terminals <b>22</b><i>a </i>of the semiconductor module <b>2</b><i>a </i>and one output terminal <b>22</b><i>b </i>of the semiconductor module <b>2</b><i>b. </i>

0036The power converter <b>1</b> is a vehicle-mounted inverter, which is a stack <b>10</b> of the two semiconductor modules <b>2</b> (<b>2</b><i>a</i>, <b>2</b><i>b</i>), a boost module <b>6</b>, a reactor <b>7</b>, and a plurality of cooling elements <b>11</b>, as shown in <figref idref="DRAWINGS">FIG. 1</figref>. The cooling elements <b>11</b> are configured to cool the semiconductor modules <b>2</b>, the boost module <b>6</b>, and the reactor <b>7</b>.

0037As shown in <figref idref="DRAWINGS">FIG. 10</figref>, each semiconductor module <b>2</b> includes six semiconductor elements <b>29</b> (IGBTs). The semiconductor elements <b>29</b> form a three-phase bridge circuit. The boost module <b>6</b> includes two semiconductor elements <b>29</b>. In the present embodiment, a DC voltage of a DC power supply <b>81</b> is boosted by the boost module <b>6</b> and the reactor <b>7</b>. The boosted DC voltage is smoothed by a smoothing capacitor <b>4</b><i>a</i>. The smoothed boosted DC voltage is converted into a three-phase AC voltage by turning on and off the respective semiconductor elements <b>29</b> of the semiconductor module <b>2</b>.

0038In the present embodiment, a three-phase AC voltage for driving a first AC load <b>80</b><i>a</i>, e.g., a three-phase AC motor, is generated by four semiconductor elements <b>29</b><i>a </i>included in the semiconductor module <b>2</b><i>a </i>and two semiconductor elements <b>29</b><i>b </i>included in the semiconductor module <b>2</b><i>b</i>. A three-phase AC voltage for driving a second AC load <b>80</b><i>b </i>is generated by two semiconductor elements <b>29</b><i>a </i>included in the semiconductor module <b>2</b><i>a </i>and four semiconductor elements <b>29</b><i>b </i>included in the semiconductor module <b>2</b><i>b. </i>

0039As shown in <figref idref="DRAWINGS">FIG. 2</figref>, a capacitor <b>4</b> is provided on the side opposite the protruding output terminals <b>22</b>. The capacitor <b>4</b> includes the smoothing capacitor <b>4</b><i>a </i>and a noise subtraction filter capacitor <b>4</b><i>b </i>(see <figref idref="DRAWINGS">FIG. 10</figref>).

0040In addition, as shown in <figref idref="DRAWINGS">FIG. 2</figref>, the control circuit board <b>3</b> is provided adjacent the stack <b>10</b>. The control circuit board <b>3</b> includes a plurality of through-holes <b>30</b>, through which the respective output terminals <b>22</b> pass, and is connected to the control terminals <b>23</b>. The control circuit board <b>3</b> controls the switching operation of each semiconductor element <b>29</b>.

0041Current sensors <b>5</b> are attached to some of the output terminals <b>22</b> to detect current values. The detected current values are fed to the control circuit board <b>3</b>. The control circuit board <b>3</b> uses the detected current values to control the operations of the semiconductor modules <b>2</b>.

0042As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the body <b>20</b> of each semiconductor module <b>2</b> is rectangular plate-shaped. The control terminals <b>23</b> and the three output terminals <b>22</b> protrude in the same direction (Y-direction). A Y-directional length of the control terminals <b>23</b> is less than a Y-directional length of the output terminals <b>22</b>. The input terminals <b>21</b> protrude from the body <b>20</b> on the side opposite the output terminals <b>22</b> and control terminals <b>23</b>. The output terminals <b>22</b> protrude from a side surface <b>241</b> of the body <b>20</b> and the input terminals <b>21</b> protrude from the opposite side surface <b>242</b>, where the side surfaces <b>241</b>, <b>242</b> include longer edges of the body <b>20</b>. In addition, a heatsink <b>290</b> is exposed on a principal surface <b>200</b> of the body <b>20</b> for heat dissipation from the semiconductor modules <b>2</b>. The term “principal surface” of the body <b>20</b> means a surface having the greatest surface area among the six surfaces of the body <b>20</b>. The term “side surface” of the body <b>20</b> means a surface other than the principal surface.

0043As shown in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>3</b>, the three output terminals <b>22</b> are spaced apart from each other by a predetermined spacing along a direction (X-direction) perpendicular to both a normal direction of the principal surface <b>200</b> of the body <b>20</b> (Z-direction) and a protruding direction of the output terminals <b>22</b> (Y-direction). The three output terminals <b>22</b> are not bilaterally symmetric about the center <b>299</b> of the side surface <b>241</b> along the X-direction, but are slightly displaced in the X-direction. In addition, the pair of input terminals <b>21</b> are shifted toward one side of the side surface <b>242</b> along the X-direction.

0044As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the two semiconductor modules <b>2</b><i>a</i>, <b>2</b><i>b </i>are identically shaped. The semiconductor module <b>2</b><i>b </i>is turned upside down with respect to the semiconductor module <b>2</b><i>a</i>. As shown in <figref idref="DRAWINGS">FIG. 6</figref>, when viewed from the Z-direction, none of the three output terminals of the semiconductor module <b>2</b><i>a </i>overlap any of the three output terminals of the semiconductor module <b>2</b><i>b</i>. More specifically, when viewed from the Z-direction, the three output terminals of the semiconductor module <b>2</b><i>a </i>and the three output terminals of the semiconductor module <b>2</b><i>b </i>are alternately disposed along the X-direction without overlapping each other.

0045In addition, as shown in <figref idref="DRAWINGS">FIG. 2</figref>, the output terminals <b>22</b> are connected to bus bars <b>88</b>. Each bus bar <b>88</b> includes a first portion <b>881</b> being connected to a corresponding output terminal <b>22</b> and extending in the Y-direction, and a second portion <b>882</b> being connected to the first portion <b>881</b> and extending in the Z-direction. A leading end <b>889</b> of the second portion <b>882</b> is connected to a connector (not shown). Three such bus bars <b>88</b> connected to the respective output terminals <b>22</b> forming the first output terminal group <b>8</b><i>a </i>are bound together by a binder <b>84</b> to form a first bus bar group <b>885</b>. Similarly, three such bus bars <b>88</b> connected to the respective output terminals <b>22</b> forming the second output terminal group <b>8</b><i>b </i>are bound together by a binder <b>84</b> to form a second bus bar group <b>886</b>.

0046The boost module <b>6</b>, as shown in <figref idref="DRAWINGS">FIG. 4</figref>, includes a rectangular plate-shaped body <b>60</b>, a reactor connection terminal <b>63</b>, a positive terminal <b>61</b>, a negative terminal <b>62</b>, and control terminals <b>64</b>. The positive terminal <b>61</b> and the negative terminal <b>62</b> protrude from a first side surface <b>67</b> of the body <b>60</b>.

0047The control terminals <b>64</b> protrude from a second side surface <b>68</b> opposite the side surface <b>67</b>. The control terminals <b>64</b> are connected to the control circuit board <b>3</b>.

0048The reactor connection terminal <b>63</b> is provided on a third side surface <b>69</b> perpendicular to the first side surface <b>67</b>.

0049A shown in <figref idref="DRAWINGS">FIG. 5</figref>, the reactor <b>7</b> includes a rectangular plate-shaped body <b>73</b> and two terminals <b>70</b>, <b>71</b> protruding from a side surface <b>79</b> of the body <b>73</b> in the X-direction.

0050The terminals <b>70</b>, <b>71</b> of the reactor <b>7</b> and the reactor connection terminal <b>63</b> of the boost module <b>6</b> protrude from the respective side surfaces <b>79</b>, <b>69</b> in the same direction (X-direction). As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the reactor connection terminal <b>63</b> and one of the terminals (terminal <b>71</b>) of the reactor <b>7</b> are connected to each other via a connecting member <b>89</b>. The other one of the terminals (terminal <b>70</b>) of the reactor <b>7</b> is connected to a positive input terminal <b>47</b> of the capacitor <b>4</b>.

0051As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the power converter <b>1</b> includes the plurality of cooling elements <b>11</b>, each of which is a U-shaped tube and provides a coolant flow path <b>150</b> through which a coolant <b>15</b> flows in the cooling element. The cooling elements are connected in parallel with each other via links <b>14</b> at leading portions <b>111</b> of the respective cooling elements. The plurality of cooling elements <b>11</b> are provided with an inlet line <b>12</b> for introducing the coolant <b>15</b> into the cooling elements and an outlet line <b>13</b> for exhausting the coolant <b>15</b> from the cooling elements. The coolant <b>15</b> introduced via the inlet line <b>12</b> flows through the coolant flow paths <b>150</b> of the respective cooling elements and the links <b>14</b> connecting the cooling elements and is exhausted from the cooling elements via the outlet line <b>13</b>. With this configuration, the cooling elements <b>11</b> can efficiently cool the semiconductor modules <b>2</b>, the boost module <b>6</b>, and the reactor <b>7</b>.

0052As shown in <figref idref="DRAWINGS">FIGS. 6</figref>, <b>7</b>, the capacitor <b>4</b> includes a capacitor casing <b>49</b>, a plurality of capacitor elements <b>40</b> within the capacitor casing <b>49</b>, and a sealing member <b>480</b> for sealing the capacitor elements <b>40</b> in the capacitor casing <b>49</b>. Some of the capacitor elements <b>40</b> are the smoothing capacitors <b>4</b><i>a </i>(see <figref idref="DRAWINGS">FIG. 10</figref>). The others are the filter capacitors <b>4</b><i>b. </i>

0053As shown in <figref idref="DRAWINGS">FIG. 7</figref>, a casing bottom <b>491</b> side end face of the capacitor element <b>40</b> serves as a negative electrode <b>400</b>, and a casing opening <b>492</b> side end face <b>401</b> serves as a positive electrode <b>401</b>. The negative electrode <b>400</b> is connected to a negative electrode plate <b>470</b>, and the positive electrode <b>401</b> is connected to a positive electrode plate <b>471</b>. The negative electrode plate <b>470</b> is connected to the negative electrodes <b>400</b> of the respective capacitor elements <b>40</b>, while the positive electrode plate <b>471</b> is only connected to the capacitor elements <b>40</b> for the smoothing capacitors <b>4</b><i>a. </i>

0054Negative terminals <b>42</b>, <b>44</b>, <b>46</b> and a negative input terminal <b>48</b> (see <figref idref="DRAWINGS">FIG. 6</figref>) are connected to the negative electrode plate <b>470</b>. These terminals <b>42</b>, <b>44</b>, <b>46</b>, <b>48</b> extend from the inside to the outside of the casing <b>49</b> through the casing opening <b>492</b>. Positive terminals <b>41</b>, <b>43</b>, <b>45</b> (see <figref idref="DRAWINGS">FIG. 6</figref>) are connected to the positive electrode plate <b>471</b>. Meanwhile, the positive electrode <b>401</b> of the capacitor element <b>40</b> for the filter capacitor <b>4</b><i>b </i>is connected to another electrode plate <b>499</b> (see <figref idref="DRAWINGS">FIG. 9</figref>). A positive input terminal <b>47</b> (see <figref idref="DRAWINGS">FIG. 6</figref>) is connected to the electrode plate <b>499</b>.

0055As shown in <figref idref="DRAWINGS">FIGS. 6</figref>, <b>7</b>, the two terminals <b>41</b>, <b>42</b> of the six terminals <b>41</b> to <b>46</b> of the capacitor <b>4</b> disposed along the X-direction are connected to the input terminals <b>21</b><i>a </i>of the semiconductor module <b>2</b><i>a</i>, where the two terminals <b>41</b>, <b>42</b> are distant from the input terminals <b>47</b>, <b>48</b> in the X-direction.

0056As shown in <figref idref="DRAWINGS">FIGS. 6</figref>, <b>8</b>, the two intermediate terminals <b>43</b>, <b>44</b> of the six terminals <b>41</b> to <b>46</b> of the capacitor <b>4</b> disposed along the X-direction are connected to the terminals <b>61</b>, <b>62</b> of the boost module <b>6</b>.

0057As shown in <figref idref="DRAWINGS">FIGS. 6</figref>, <b>9</b>, the two terminals <b>45</b>, <b>46</b> of the six terminals <b>41</b> to <b>46</b> of the capacitor <b>4</b> disposed along the X-direction are connected to the input terminals <b>21</b><i>b </i>of the semiconductor module <b>2</b><i>b</i>, where the two terminals <b>45</b>, <b>46</b> are close to the input terminals <b>47</b>, <b>48</b> in the X-direction.

0058In addition, as shown in <figref idref="DRAWINGS">FIG. 6</figref>, the casing <b>19</b> includes output connector insertion holes <b>191</b>, <b>192</b>. Output connectors (not shown) are set in the output connector insertion holes <b>191</b>, <b>192</b> to be connected to the bus bars <b>88</b> (see <figref idref="DRAWINGS">FIG. 2</figref>) inside of the casing <b>19</b>. The output terminals <b>22</b> are connected to the respective AC loads <b>80</b> (see <figref idref="DRAWINGS">FIG. 10</figref>) via the output connectors.

0059There will now be explained some advantages of the present embodiment. As shown in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>, one of the three output terminals <b>22</b><i>a </i>of the semiconductor module <b>2</b><i>a </i>and two of the three output terminals <b>22</b><i>b </i>of the semiconductor module <b>2</b><i>b </i>form a first output terminal group <b>8</b><i>a</i>. Two of the three output terminals <b>22</b><i>a </i>of the semiconductor module <b>2</b><i>a </i>and one of the three output terminals <b>22</b><i>b </i>of the semiconductor module <b>2</b><i>b </i>form a second output terminal group <b>8</b><i>b. </i>

0060This configuration can enhance the versatility of combinations of three output terminals to form one individual output terminal group <b>8</b>. This may thus lead to an optimal combination of three output terminals <b>22</b> depending on a geometry and/or position of each bus bar <b>88</b> such that the three output terminals <b>22</b> forming one individual output terminal group <b>8</b> are in close proximity to each other so that long bus bars <b>88</b> are not needed.

0061One can imagine an embodiment such that the three output terminals of the semiconductor module <b>2</b><i>a </i>form a first output terminal group and the three output terminals of the semiconductor module <b>2</b><i>b </i>form a second output terminal group, as shown in <figref idref="DRAWINGS">FIG. 16</figref>. Such an embodiment may require long bus bars to connect the output terminals and the connectors depending on positions of the respective output terminals, which may cause some of the bus bars to be in contact with each other. The present embodiment, as shown in <figref idref="DRAWINGS">FIG. 2</figref>, leads to a combination of three output terminals that form one individual output terminal group <b>8</b> without use of long bus bars.

0062In the present embodiment, as shown in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>, the stack <b>10</b> of the plurality of semiconductor modules <b>2</b> and the plurality of cooling elements are provided. The plurality of output terminals <b>22</b> protrude in the same direction (Y-direction) from side surfaces <b>24</b> of the bodies <b>20</b> of the respective semiconductor modules <b>2</b>. In addition, three of the plurality of output terminals <b>22</b>, which are in close proximity to each other in the X-direction, form one individual output terminal group.

0063The plurality of output terminals <b>22</b> included in each semiconductor module <b>2</b> are distributed in the X-direction. Accordingly, in such an embodiment as shown in <figref idref="DRAWINGS">FIG. 16</figref> where the three output terminals of the semiconductor module <b>2</b><i>a </i>form one output terminal group <b>8</b><i>a </i>and the three output terminals of the semiconductor module <b>2</b><i>b </i>form another output terminal group <b>8</b><i>b</i>, the three output terminals in each output terminal group are distributed in the X-direction.

0064Given a stack of a plurality of semiconductor modules <b>2</b> (<b>2</b><i>a</i>, <b>2</b><i>b</i>) and a plurality of cooling elements as shown in <figref idref="DRAWINGS">FIG. 16</figref>, three output terminals of the semiconductor module <b>2</b><i>a </i>that are distributed in the X-direction and form one output terminal group <b>8</b><i>a </i>and three output terminals of the semiconductor module <b>2</b><i>b </i>(adjacent the semiconductor module <b>2</b><i>a </i>in the Z-direction) that are distributed in the X-direction and form another output terminal group <b>8</b><i>b </i>are in close proximity to each other in the Z-direction. Such a configuration requires bus bars to be long enough to connect to the three respective output terminals of each semiconductor module that are disposed in the X-direction. In addition, since the output terminals of the output terminal group <b>8</b><i>a </i>and the output terminals of the output terminal group <b>8</b><i>b </i>are disposed in close proximity to each other in the Z-direction, the bus bars <b>88</b> are more susceptible to interference with each other.

0065In the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 2</figref>, each output terminal group <b>8</b> is formed by three output terminals, some of which belong to the semiconductor module <b>2</b><i>a </i>and the others belong to the semiconductor module <b>2</b><i>b</i>, so that the three output terminals of each output terminal group <b>8</b> can be disposed in close proximity to each other in the X-direction. This can prevent three output terminals <b>22</b> of each output terminal group <b>8</b> from being distributed in the X-direction and the output terminals of different output terminal groups <b>8</b> from being disposed in close proximity to each other in the Z-direction, which can prevent the bus bars <b>88</b> connected to the respective output terminals <b>22</b> from electrically interfering with each other.

0066In the present embodiment, as shown in <figref idref="DRAWINGS">FIG. 6</figref>, none of the output terminals <b>22</b><i>a </i>protruding from the body <b>20</b> of the semiconductor module <b>2</b><i>a </i>overlap any of the output terminals <b>22</b><i>b </i>protruding from the body <b>20</b> of the semiconductor module <b>2</b><i>b </i>(adjacent the semiconductor module <b>2</b><i>a </i>in the Z-direction) when viewed from the Z-direction. Since each of the output terminals <b>22</b> (<b>22</b><i>a</i>, <b>22</b><i>b</i>) of each of the semiconductor modules <b>2</b><i>a</i>, <b>2</b><i>b </i>is welded to a corresponding bus bar <b>8</b> after overlapping leading portions of the output terminal and the bus bar in the Z-direction, this can facilitate connecting (e.g., welding) the output terminals and the bus bars.

0067In the present embodiment, the output terminals <b>22</b> are connected to the bus bars <b>88</b>. The bus bars <b>88</b> are connected to the connectors. Alternatively, the output terminals <b>22</b> may be connected directly to the connectors without using the bus bars <b>88</b>.

0068As described above, the present embodiment can provide a power converter capable of preventing bus bars and/or connectors or the like connected to the respective output terminal groups from interfering with each other.

Second Embodiment

0069There will now be explained a second embodiment of the present invention. Only differences of the second embodiment from the first embodiment will be explained. Elements having the same functions as in the first embodiment are assigned the same numbers and will not be described again for brevity.

0070In the present embodiment, the semiconductor modules <b>2</b> of a power converter <b>1</b> are modified in shape and arrangement. As shown in <figref idref="DRAWINGS">FIG. 14</figref>, each semiconductor module <b>2</b> of the present embodiment includes a quadrilateral plate-shaped body <b>20</b>, from which control terminals <b>23</b>, a pair of input terminals <b>21</b>, and three output terminals <b>22</b> protrude. In each semiconductor module <b>2</b>, two of the three output terminals <b>22</b> protrude from a first side surface <b>243</b> of the body <b>20</b>, and the other one protrudes from a second side surface <b>244</b> opposite and parallel to the first side surface <b>243</b>. The pair of input terminals <b>21</b> protrude from a third side surface <b>245</b> perpendicular to both the first and second side surfaces <b>243</b>, <b>244</b>.

0071The power converter <b>1</b> of the present embodiment includes two semiconductor modules <b>2</b> (<b>2</b><i>a</i>, <b>2</b><i>b</i>) having identical bodies and being disposed adjacent each other. The pair of input terminals <b>21</b> of the semiconductor module <b>2</b><i>a </i>and the pair of input terminals <b>21</b> of the semiconductor module <b>2</b><i>b </i>protrude in opposite directions from the respective bodies <b>20</b>. Two output terminals <b>22</b><i>a </i>on a first side surface <b>243</b> of the semiconductor module <b>2</b><i>a </i>and one output terminal <b>22</b><i>b </i>on a second side surface <b>244</b> of the semiconductor module <b>2</b><i>b </i>protrude from the respective bodies <b>20</b> in the same direction and form a first output terminal group <b>8</b><i>a </i>for outputting a three-phase AC voltage.

0072In addition, one output terminal <b>22</b><i>a </i>on a second side surface <b>244</b> of the semiconductor module <b>2</b><i>a </i>and two output terminals <b>22</b><i>b </i>on a first side surface <b>243</b> of the semiconductor module <b>2</b><i>b </i>protrude from the respective bodies <b>20</b> in the same direction and form a second output terminal group <b>8</b><i>b </i>for outputting a three-phase AC voltage.

0073Some advantages of the present embodiment will now be explained. In the above configuration, the three output terminals of the semiconductor module <b>2</b><i>a </i>and the three output terminals of the semiconductor module <b>2</b><i>a </i>lie opposite each other. This can prevent bus bars connected to the output terminals of the respective output terminal groups <b>8</b><i>a</i>, <b>8</b><i>b </i>from inferring with each other.

0074In addition, since at most two output terminals <b>22</b> protrude from one of side surfaces <b>24</b> of each semiconductor module <b>2</b><i>a</i>, <b>2</b><i>b</i>, an X-directional length of the body <b>20</b> of each semiconductor module <b>2</b><i>a</i>, <b>2</b><i>b </i>can be reduced as compared with the first embodiment where the three terminals protrude from one of the side surfaces <b>24</b> of each semiconductor module <b>2</b><i>a</i>, <b>2</b><i>b</i>. This can facilitate downsizing of the semiconductor modules <b>2</b>.

Third Embodiment

0075There will now be explained a third embodiment of the present invention. Only differences of the third embodiment from the first embodiment will be explained. Elements having the same functions as in the first embodiment are assigned the same numbers and will not be described again for brevity.

0076In the present embodiment, the semiconductor modules <b>2</b> of a power converter <b>1</b> of the present embodiment are modified in shape and arrangement. As shown in <figref idref="DRAWINGS">FIG. 12</figref>, the power converter <b>1</b> includes three semiconductor modules <b>2</b>, where each semiconductor module <b>2</b> has two input terminals <b>21</b> and two output terminals <b>22</b>. A body <b>20</b> of each semiconductor module <b>2</b> includes four semiconductor elements <b>29</b> (IGBTs) forming a bridge circuit.

0077In the present embodiment, the three semiconductor modules <b>2</b> are disposed in series along the X-direction. The output terminals of the three respective semiconductor modules <b>2</b> protrude in the same direction (e.g., in the Y-direction as shown in the <figref idref="DRAWINGS">FIG. 12</figref>). The two output terminals <b>22</b><i>a </i>of a first semiconductor module <b>2</b><i>a </i>and one of the two output terminals <b>22</b><i>b </i>of a second semiconductor module <b>2</b><i>b </i>form a first output terminal group <b>8</b><i>a</i>. The other one of the two output terminals <b>22</b><i>b </i>of the second semiconductor module <b>2</b><i>b </i>and the two output terminals <b>22</b><i>c </i>of a third semiconductor module <b>2</b><i>c </i>form a second output terminal group <b>8</b><i>b. </i>

0078Some advantages of the present embodiment will now be explained. In the above configuration, the first output terminal group <b>8</b><i>a </i>is disposed adjacent the second output terminal group <b>8</b><i>b </i>along the X-direction. This allows the two output terminal groups <b>8</b><i>a</i>, <b>8</b><i>b </i>to be spaced apart from each other by an adequate spacing, which can prevent bus bars connected to the output terminals of the respective output terminal groups <b>8</b><i>a</i>, <b>8</b><i>b </i>from inferring with each other.

0079In addition, in the present embodiment, each semiconductor module <b>2</b> includes only four semiconductor elements <b>29</b> (IGBTs). This can enhance fabrication yield in producing the semiconductor modules <b>2</b> as compared with embodiments where each semiconductor module <b>2</b> includes six or more semiconductor elements <b>29</b> (IGBTs).

Fourth Embodiment

0080There will now be explained a fourth embodiment of the present invention. Only differences of the fourth embodiment from the first embodiment will be explained. Elements having the same functions as in the first embodiment are assigned the same numbers and will not be described again for brevity.

0081In the present embodiment, the cooling elements <b>11</b> are modified in configuration. As shown in <figref idref="DRAWINGS">FIG. 13</figref>, the coolant <b>15</b> flows through the coolant flow path <b>150</b> in each cooling element <b>11</b> extending from the inlet line <b>12</b> to the outlet line <b>13</b> along the X-direction. As in the first embodiment, all the output terminals are grouped into two output terminal groups <b>8</b> (<b>8</b><i>c</i>, <b>8</b><i>d</i>), where the three output terminals of a first output terminal group <b>8</b><i>c </i>are connected to a first AC load <b>80</b> which has a relatively high power consumption and the three output terminals of a second output terminal groups <b>8</b><i>d </i>are connected to a second AC load <b>80</b> which has a relatively low power consumption (see <figref idref="DRAWINGS">FIG. 10</figref>). The output terminals of the output terminal group <b>8</b><i>c </i>are connected to an AC load <b>80</b>.

0082As in the first embodiment, the body <b>20</b> of each semiconductor module <b>2</b> includes six semiconductor elements <b>29</b> (IGBTs) (see <figref idref="DRAWINGS">FIG. 10</figref>). Some of the twelve semiconductor elements <b>29</b> (six elements of the semiconductor module <b>2</b><i>a </i>plus six elements of the semiconductor module <b>2</b><i>b</i>) are high power semiconductor elements <b>29</b><i>c </i>that output a three-phase. AC voltage to a high output terminal group <b>8</b><i>c</i>. The others of the twelve semiconductor elements <b>29</b> are low power semiconductor elements <b>29</b><i>d </i>that output a three-phase AC voltage to a low output terminal group <b>8</b><i>d</i>. The high power semiconductor elements <b>29</b><i>c </i>are disposed upstream of the low power semiconductor elements <b>29</b><i>d </i>along the coolant flow path <b>150</b>.

0083With this configuration, since the high power semiconductor elements <b>29</b><i>c </i>consume more power than the lower semiconductor element <b>29</b><i>d</i>, the coolant of lower temperature can be used to cool the high power semiconductor elements <b>29</b><i>c</i>. This can enhance efficiency of cooling the high power semiconductor elements <b>29</b><i>c. </i>

Fifth Embodiment

0084There will now be explained a fifth embodiment of the present invention. Only differences of the fifth embodiment from the first embodiment will be explained. Elements having the same functions as in the first embodiment are assigned the same numbers and will not be described again for brevity.

0085In the present embodiment, the current sensors <b>5</b> are modified in configuration. As shown in <figref idref="DRAWINGS">FIG. 14</figref>, the power converter <b>1</b> includes two current sensors <b>5</b>, i.e., first and second current sensor <b>5</b><i>a</i>, <b>5</b><i>b</i>. The first current sensor <b>5</b><i>a </i>measures a current flowing into the three output terminals <b>22</b> forming a first output terminal group <b>8</b><i>a</i>. The second current sensor <b>5</b><i>b </i>measures a current flowing into the three output terminals <b>22</b> forming a second output terminal group <b>8</b><i>b</i>. The two current sensors <b>5</b><i>a</i>, <b>5</b><i>b </i>are connected to a control circuit board (not shown). The control circuit board uses the current values measured by the current sensors <b>5</b><i>a</i>, <b>5</b><i>b </i>to control the operations of semiconductor modules <b>2</b>.

0086The output terminal <b>22</b> to which the first current sensor <b>5</b><i>a </i>is attached and the output terminal <b>22</b> to which the second current sensor <b>5</b><i>b </i>is attached protrude from the same body <b>20</b> of either one of the semiconductor modules <b>2</b> (e.g., the body <b>20</b> of the semiconductor modules <b>2</b><i>a </i>as shown in <figref idref="DRAWINGS">FIG. 14</figref>). The first and second current sensors <b>5</b><i>a</i>, <b>5</b><i>b </i>are integrated.

0087This can reduce the total number of components, which leads to reduction of manufacturing costs. In addition, the two output terminals to which the respective current sensors <b>5</b> are attached protrude from the same body <b>20</b> of either one of the semiconductor modules <b>2</b>. This allows the two output terminals to be disposed in close proximity to each other, which facilitates attachment of the current sensor <b>5</b><i>a</i>, <b>5</b><i>b </i>in an integrated manner.

Sixth Embodiment

0088There will now be explained a sixth embodiment of the present invention. Only differences of the sixth embodiment from the first embodiment will be explained. Elements having the same functions as in the first embodiment are assigned the same numbers and will not be described again for brevity.

0089In the present embodiment, the semiconductor modules <b>2</b> of a power converter <b>1</b> are modified in shape and arrangement. As shown in <figref idref="DRAWINGS">FIG. 15</figref>, the power converter <b>1</b> includes three semiconductor modules <b>2</b>. As in the third embodiment (see <figref idref="DRAWINGS">FIG. 12</figref>), each semiconductor module <b>2</b> has two output terminals <b>22</b>. In contrast to the third embodiment, the three semiconductor modules <b>2</b> and cooling elements form a stack <b>10</b> along the Z-direction.

0090The output terminals of the three respective semiconductor modules <b>2</b> all protrude in the same direction (e.g., in the Y-direction). One of the two output terminals <b>22</b><i>a </i>of a first semiconductor module <b>2</b><i>a</i>, one of the two output terminals <b>22</b><i>b </i>of a second semiconductor module <b>2</b><i>b</i>, and one of the two output terminals <b>22</b><i>c </i>of a third semiconductor module <b>2</b><i>c </i>form a first output terminal group <b>8</b><i>a</i>. The other one of the two output terminals <b>22</b><i>a </i>of the second semiconductor module <b>2</b><i>a</i>, the other one of the two output terminals <b>22</b><i>b </i>of the second semiconductor module <b>2</b><i>b</i>, and the other one of the two output terminals <b>22</b><i>c </i>of the second semiconductor module <b>2</b><i>c </i>form a second output terminal group <b>8</b><i>b. </i>

0091The first output terminal group <b>8</b><i>a </i>is disposed adjacent the second output terminal group <b>8</b><i>b </i>along the X-direction. More specifically, when viewed from the X-direction, the three terminals <b>22</b><i>a</i>-<b>22</b><i>c </i>of the first output terminal group <b>8</b><i>a </i>are disposed on the same side of the power converter <b>1</b>, and the three terminals <b>22</b><i>a</i>-<b>22</b><i>c </i>of the second output terminal group <b>8</b><i>b </i>are disposed on another same side.

0092Many modifications and other embodiments of the invention will come to mind to one skilled in the art to which this invention pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.