Epitaxial formation of source and drain regions

CROSS-REFERENCES TO RELATED APPLICATIONS

0001The present application is related to U.S. application Ser. No. 13/029,378, entitled “INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF” filed on Feb. 17, 2011, and U.S. application Ser. No. 13/114,910, entitled “Source/Drain Formation and Structure” filed on May 24, 2011 (Attorney Docket No. TSMC2011-1317), both of which are incorporated herein by reference in their entireties.

TECHNICAL FIELD

0002The present disclosure relates generally to the field of semiconductor devices and, more particularly, to integrated circuits and fabrication methods thereof.

BACKGROUND

0003The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.

0004In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.

BRIEF DESCRIPTION OF THE DRAWINGS

0005The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the numbers and dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

0006<figref idref="DRAWINGS">FIG. 1</figref> is a flowchart illustrating an exemplary method of forming an integrated circuit.

0007<figref idref="DRAWINGS">FIGS. 2A-2E</figref> are cross-sectional views of an integrated circuit during various fabrication stages, in accordance with some embodiments.

0008<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of dislocations in a source/drain region near a gate stack, in accordance with some embodiments.

0009<figref idref="DRAWINGS">FIG. 4A</figref> is a process sequence of a CDE process in a process chamber, in accordance with some embodiments.

0010<figref idref="DRAWINGS">FIG. 4B</figref> is a process flow of depositing a silicon-containing material in recesses of a substrate, in accordance with some embodiments.

0011<figref idref="DRAWINGS">FIGS. 5A-5C</figref> are cross-sectional views of a process sequence of forming a S/D region between a gate stack and an isolation structure, in accordance with some embodiments.

DETAILED DESCRIPTION

0012Generally, a plurality of ion implantations have been implemented for forming source/drain (S/D) regions, lightly-doped drain (LDD) regions, and pocket regions of transistors. For example, an N-type source/drain (NSD) process has a room-temperature phosphorus ion implantation that is provided to form a gradient dopant junction profile in a substrate. A room-temperature carbon ion implantation is then performed on the S/D regions to prevent over-diffusion of phosphorus dopants into the substrate. A room-temperature arsenic ion implantation and a room-temperature phosphorus ion implantation are performed to form S/D doped regions. After the multiple ion implantations, a rapid thermal anneal (RTA) is performed to activate dopants and to cure damage resulting from the ion implantations. Silicide is then formed at the top of the S/D doped regions.

0013As noted, the process described above uses the room-temperature phosphorus ion implantation to form the junction profile. When the sizes of transistors are scaled down, the S/D junction profiles may be too deep. The multiple ion implantations may also substantially damage the S/D regions. To cure the damage, an annealing process with a high thermal budget, e.g., a higher rapid thermal annealing (RTA) temperature of about 1050° C. and/or a longer RTA time, may be applied. The high thermal budget may aggravate a short-channel effect (SCE) of the transistors. If an anneal with a low thermal budget is applied, implantation damage may not be desirably cured. The low thermal budget may also result in a transient-enhanced diffusion (TED).

0014In order to address the issues related to implanting dopants in S/D regions, a silicon film with dopants is epitaxially grown in recessed regions near the gate electrodes. However, there are challenges in using epitaxially grown silicon film(s) with dopants to form S/D regions.

0015It is understood that the following descriptions provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one feature's relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

0016The embodiments will be described with respect to specific embodiments in a specific context, namely a source/drain region for a complementary metal-oxide semiconductor (CMOS) transistor. The embodiments may also be applied, however, to other doped regions within a semiconductor device.

0017Illustrated in <figref idref="DRAWINGS">FIG. 1</figref> is a flowchart of a method of forming an integrated circuit, in accordance with some embodiments. <figref idref="DRAWINGS">FIGS. 2A-2E</figref> are schematic cross-sectional views of an integrated circuit during various fabrication stages, in accordance with some embodiments. The integrated circuit may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high power MOS transistors, FinFET transistors, or other types of transistors. It is understood that <figref idref="DRAWINGS">FIGS. 2A-2E</figref> have been simplified for a better understanding of the concepts of the present disclosure. Accordingly, it should be noted that additional processes may be provided before, during, and after the method <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref>, and that some other processes may only be briefly described herein.

0018Referring now to <figref idref="DRAWINGS">FIG. 1</figref>, the method <b>100</b> can include forming a gate structure over a substrate (block <b>110</b>). The method <b>100</b> can include removing portions of the substrate to form recesses adjacent to the gate structure (block <b>120</b>). The method <b>100</b> can also include forming a silicon-containing material structure in each of the recesses (block <b>130</b>).

0019Referring now to <figref idref="DRAWINGS">FIGS. 2A-2E</figref> in conjunction with <figref idref="DRAWINGS">FIG. 1</figref>, an integrated circuit <b>200</b> can be fabricated in accordance with the method <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref>. In <figref idref="DRAWINGS">FIG. 2A</figref>, the integrated circuit <b>200</b> can have a substrate <b>201</b>. Substrate <b>201</b> may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. Substrate <b>201</b> may include an epitaxial layer (epi layer), and may be strained for performance enhancement.

0020In some embodiments forming N-type transistors, the substrate <b>201</b> can be a silicon substrate doped with a P-type dopant, such as boron (resulting in a P-type substrate). A metal gate structure can have a stack structure including a high dielectric constant gate layer, a diffusion barrier layer, a metal work function layer, a metallic layer, and/or other suitable layers. A dummy gate structure can have a stack structure including a dummy material layer, a hard mask layer, and/or other suitable layers.

0021In some embodiments, a gate stack <b>205</b> comprising a gate dielectric <b>207</b>, a gate electrode <b>209</b>, first spacers <b>211</b>, and second spacers <b>212</b> may be formed over the substrate <b>201</b>. The gate dielectric <b>207</b> may be a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, an oxide, a nitrogen-containing oxide, a combination thereof, or the like. The gate dielectric <b>207</b> may have a relative permittivity value greater than about 4. Other examples of such materials include aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, or combinations thereof.

0022The gate electrode <b>209</b> may comprise a conductive material, such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped poly-crystalline silicon, other conductive materials, combinations thereof, or the like.

0023Surrounding the gate stack <b>205</b> are the first spacers <b>211</b> and the second spacers <b>212</b>. The gate stack <b>205</b> and the surrounding spacers, such as spacers <b>211</b> and <b>212</b>, form a gate structure <b>206</b>. The spacer layers may comprise SiN, oxynitride, SiC, SiON, oxide, and the like. However, as one of ordinary skill in the art will recognize, the first spacers <b>211</b> and the second spacers <b>212</b> as illustrated in <figref idref="DRAWINGS">FIG. 2A</figref> are intended to be merely illustrative and are not intended to limit the embodiments to these descriptions. Rather, any suitable number and combination of spacer layers and shapes may be utilized in order to form spacers for the gate stack <b>205</b>, and any suitable combination of spacers may alternatively be utilized.

0024In some embodiments of forming an N-type transistor, N-type lightly-doped drains (LDDs) <b>219</b> can be formed in the substrate <b>201</b>. Portions of the N-type LDDs <b>219</b> can be formed under the gate structure <b>205</b>. The N-type LDDs <b>219</b> can be formed of n-type dopants (impurities). For example, the dopants can comprise phosphorous, arsenic, and/or other group V elements. In some embodiments, at least one thermal annealing process, e.g., a rapid thermal annealing (RTA) process, can be performed to activate the dopants of the N-type LDDs <b>219</b>. In some embodiments of forming an N-type transistor, P-type pocket doped regions (not shown) can be formed in the substrate <b>201</b>. The P-type pocket doped regions can be formed of P-type dopants (impurities). For example, the dopants can comprise boron and/or other group III elements.

0025<figref idref="DRAWINGS">FIG. 2A</figref> illustrates the formation of recesses <b>210</b> within the substrate <b>201</b>. The recesses <b>210</b> may be formed using, e.g., a wet etch process selective to the material of the substrate <b>201</b> and uses the gate stack <b>205</b>, the first spacers <b>211</b>, and the second spacers <b>212</b> as a hard mask in order to form the recesses <b>210</b>. For example, an etchant such as carbon tetrafluoride (CF₄) or tetramethylammonium hydroxide (THMA), combinations of these, or the like may be used to perform the wet etch and form the recesses <b>210</b>. The recesses <b>210</b> provide an opening in the substrate <b>201</b> into which source/drain regions (whose formation is described further below with respect to <figref idref="DRAWINGS">FIGS. 2B-2E</figref>) will subsequently be formed.

0026Recess <b>210</b>, formed below and between a spacer <b>212</b> surrounding gate structure <b>205</b> and a neighboring spacer <b>212</b> as shown in <figref idref="DRAWINGS">FIG. 2A</figref>, has a width W₁of between about 20 Å and about 100 Å, in accordance with some embodiments. Recesses <b>210</b> may additionally undercut the first spacers <b>211</b> and/or the second spacers <b>212</b>. Additionally, the wet etch process may be continued until the recesses <b>210</b> have a depth D₁from a surface of the substrate <b>201</b>. In some embodiments, D₁is in a range from about 200 Å and about 400 Å. However, these dimensions are not intended to limit the present embodiments, as any suitable dimensions for the recesses <b>210</b> may alternatively be utilized.

0027The recesses <b>210</b> may be formed to have either an angular or rounded shape. In an embodiment in which the recesses <b>210</b> have an angular shape, the recesses <b>210</b> may be formed to have a first angle α₁along with top of the recesses <b>210</b> and a second angle α₂along the bottom of the recesses <b>210</b>. In some embodiments, the first angle α₁is in a range from about 90° and about 180°. The second angle α₂is in a range from about 85° and about 170°, in accordance with some embodiments.

0028Referring to FIGS. <b>1</b> and <b>2</b>B-<b>2</b>E, the method <b>100</b> can include forming an epitaxial silicon-containing material structure in each of the recesses (block <b>130</b>). In some embodiments, the block <b>130</b> can include performing an epitaxial deposition/partial etch process and repeating the epitaxial deposition/partial etch process at least once. The block <b>130</b> may include epitaxially depositing a silicon-containing material (or layer) <b>215</b>, in recesses <b>210</b> as shown in <figref idref="DRAWINGS">FIGS. 2B-2D</figref>, in accordance with some embodiments. Block <b>130</b> also may include depositing a silicon-containing layer <b>216</b> over the silicon-containing material <b>215</b> in recesses <b>210</b>, as shown in <figref idref="DRAWINGS">FIG. 2E</figref>, in accordance with some embodiments.

0029The deposition of the silicon-containing material <b>215</b> includes in-situ doping the silicon-containing material <b>215</b>, in accordance with some embodiments. For example, forming an N-type transistor can use an N-type doping precursor, e.g., phosphine (PH₃) and/or other N-type doping precursor. By using the in-situ doping process, the dopant profile of the silicon-containing material <b>215</b> can be desirably achieved. In some embodiments, the silicon-containing material <b>215</b> can be an N-type doped silicon layer that is doped with phosphorus (SiP). In some embodiments, the silicon-containing material <b>215</b> can be an N-type doped silicon layer that is doped with both phosphorus and carbon (SiCP). Carbon could impede the out-diffusion of phosphorus from the silicon-containing material <b>215</b>. Other types of dopants may also be included. In some embodiments, the phosphorus dopant has a concentration in a range from about 0.3% to about 2% (atomic percent). In some embodiments, the carbon dopant has a concentration in a range from about 0.3% to about 2% (atomic percent).

0030In some embodiments, the silicon-containing material <b>215</b> can be formed by chemical vapor deposition (CVD), e.g., low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), any suitable CVD; molecular beam epitaxy (MBE) processes; any suitable epitaxial process; or any combinations thereof. In some embodiments, the deposition of the silicon-containing material <b>215</b> can have a deposition temperature of about 750° C. or less. In other embodiments, the deposition temperature ranges from about 500° C. to about 750° C. The pressure of the deposition process can range from about 50 Torr to about 500 Torr.

0031The deposition of the silicon-containing material <b>215</b> can use at least one silicon-containing precursor, such as silane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), Dichlorosilane (SiH₂Cl₂), another silicon-containing precursor, and/or any combinations thereof. In some embodiments, the silicon-containing precursor can have a flow rate ranging from about 20 standard cubic centimeters per minute (sccm) to about 500 sccm. In other embodiments forming a P-type transistor, the silicon-containing material <b>215</b> can be made of at least one material, such as silicon, silicon germanium, other semiconductor materials, and/or any combinations thereof.

0032As mentioned above, the deposition of the silicon-containing material <b>215</b> includes in-situ doping the silicon-containing material <b>215</b>, in accordance with some embodiments. For example, forming an N-type transistor can use an N-type doping precursor, e.g., phosphine (PH₃) and/or other N-type doping precursor. In some embodiments, the N-type doping precursor can have a flow rate ranging from about 20 sccm to about 500 sccm.

0033The silicon-containing material <b>215</b> in recesses <b>210</b> is epitaxial. However, dislocations <b>241</b> would form at gate corners <b>240</b> due to their proximity of spacers <b>211</b> or <b>212</b>, which are not made of crystalline silicon. As shown in <figref idref="DRAWINGS">FIG. 2B</figref>, gate corners <b>240</b> are located at the edge of gate structure <b>206</b> near the interface between the spacers, such as <b>211</b> and <b>212</b>, and substrate. If the dislocations <b>241</b> at gate corners <b>240</b> are not removed, they would accumulate with the epitaxial growth of silicon-containing material <b>215</b><i>a </i>in recesses <b>210</b> and would become gate corner defects (GCDs), which are in the path of carrier flow. The GCDs could degrade on current of transistors (I_on) and also increase the variation of threshold voltage (V_t). The deposition process leaves an amorphous silicon-containing material <b>215</b>* on non-silicon surfaces, such as over gate electrode <b>209</b>, in some embodiments.

0034Referring to <figref idref="DRAWINGS">FIG. 2C</figref>, an etching (or partial etching) process <b>220</b> removes the amorphous silicon-containing material <b>215</b>* and also a portion of the silicon-containing material <b>215</b><i>a </i>in recesses <b>210</b>. The remaining silicon-containing material <b>215</b> can be formed in each of the recesses <b>210</b>. In some embodiments, the etching process <b>220</b> can use an etching gas including at least one of hydrogen chloride (HCl), chlorine (Cl₂), germanium hydride (GeH₄), other suitable etching gases, and/or any combinations thereof. The flow rate of the etching gas can range from about 50 sccm to about 700 sccm, in accordance with some embodiments. In some embodiments, the pressure of the etching process <b>220</b> ranges from about 50 Torr to about 500 Torr. In some embodiments, the etching process <b>220</b> can have an etching temperature of about 750° C. or less. In other embodiments, the etching temperature can range from about 500° C. to about 750° C.

0035The etching process <b>220</b> would remove the amorphous silicon-containing material <b>215</b>* over non-crystalline surface at a rate higher than the removal rate of epitaxial silicon-containing material <b>215</b>. In addition, the etching process would remove a portion of epitaxial silicon-containing material <b>215</b> including the dislocations <b>241</b> near the gate corners <b>240</b>. As mentioned above, the dislocations <b>241</b> need to be removed as completely as possible. Otherwise, dislocations <b>241</b> would accumulate and grow with the epitaxial deposition of films, such as film <b>215</b>, in recesses <b>210</b> and would become GCDs.

0036The epitaxial deposition/partial etch process is repeated a number of times until a desired thickness D₂is reached, as shown in <figref idref="DRAWINGS">FIG. 2D</figref> in accordance with some embodiments. Such repeated deposition/partial etch process is also called a cyclic deposition/etch (CDE) process. In some embodiments, D₂is in a range from about 70 Å and about 300 Å. The dotted lines in recesses <b>210</b> are used to illustrate the multiple sub-layers formed by the epitaxial CDE process. With proper tuning of the partial etch process, the silicon-containing layer <b>215</b> near gate corners <b>240</b> would not have dislocations.

0037As mentioned above, the silicon-containing material <b>215</b> can be an N-type doped silicon layer that is doped with both phosphorus and carbon, in accordance with some embodiments. Carbon could impede the out-diffusion of phosphorus from the silicon-containing material <b>215</b>. The phosphorus- and carbon-doped silicon layer can be referred to as an SiCP layer. The dopants in the silicon-containing material <b>215</b> deposited by CDE have higher level of activation than implanted dopants. In some embodiments, the dopant activation level is in a range from about 2E20 atoms/cm³to about 6E20 atoms/cm³. In contrast, the activation of implanted dopant at S/D is typically at about 1E20 to 2E20 atoms/cm³level. The higher activation level makes formation of in-situ doping of epitaxial grown silicon-containing desirable.

0038Following the CDE process, a selective epitaxial growth (SEG) process may be used to deposit additional silicon-containing film to fill the remaining recesses <b>210</b>. The SEG process has a higher growth rate than the CDE process, in accordance with some embodiments. The SEG process is a selective deposition process and the silicon-containing film formed by this process deposits on epitaxial silicon-containing film, such as layer <b>215</b>. SEG processes utilize simultaneous deposition and etch. The silicon-containing layer <b>216</b> deposited by SEG may be formed beyond the silicon substrate surface <b>230</b>, as shown in <figref idref="DRAWINGS">FIG. 2E</figref> in accordance with some embodiments. In some embodiments, the surface <b>216</b> of the silicon-containing layer <b>216</b> is leveled with silicon substrate surface <b>230</b>. The thickness D₃of the silicon-containing layer <b>216</b> is in a range from about 30 Å to about 400 Å, in some embodiments. In some embodiments, the silicon-containing layer is doped with phosphorus (SiP).

0039When the epitaxially grown silicon-containing layer <b>216</b> is formed next to spacers <b>212</b>, dislocations <b>218</b> would be formed and accumulate, as shown in <figref idref="DRAWINGS">FIG. 2E</figref>. However, since dislocations <b>218</b> are not in the paths of carriers, they do not degrade device performance. Layer <b>215</b> and layer <b>216</b> form the S/D regions <b>250</b>. In some embodiments, the material and/or method of forming the silicon-containing layer <b>216</b> can be as same as or similar to those of the silicon-containing material <b>215</b>. In some embodiments, the silicon-containing layer <b>216</b> may have a dopant concentration different from that of the silicon-containing material <b>215</b>.

0040If dislocations <b>241</b> near gate corners <b>240</b> are allowed to remain on some regions of wafers, as shown in <figref idref="DRAWINGS">FIG. 3</figref> in accordance with some embodiments, the dislocations <b>241</b> near gate corners <b>240</b> in layer <b>215</b> could initiate the growth of dislocations <b>218</b> in layer <b>216</b> to form continuous dislocation regions <b>255</b>. The dislocations in continuous regions <b>255</b> that are in carrier paths would degrade device performance. Therefore, there is a need to improve the process of forming the S/D regions <b>250</b> to remove dislocations <b>241</b> on all parts of wafers. As mentioned above, the dislocations <b>241</b> at gate corners <b>240</b> start with the formation of the silicon-containing material <b>215</b> in recess <b>210</b>. Dislocations <b>241</b> would accumulate and grow with the epitaxial deposition of the silicon-containing material <b>215</b>.

0041To ensure dislocations <b>241</b> of material <b>215</b> do not grow to merge with dislocations <b>218</b> in layer <b>216</b> to form continuous dislocation regions <b>255</b>, the thickness D₂of silicon-containing material <b>215</b> should be kept relatively low to keep the growth of dislocations <b>241</b> to a minimum. However, since the carbon in the silicon-containing material <b>215</b> (SiCP) could impede the out diffusion of phosphorus (P), D₂cannot be too thin either. As mentioned above in <figref idref="DRAWINGS">FIG. 2D</figref>, D₂is in a range from about 70 Å and about 300 Å, in accordance with some embodiments. In addition to controlling the thickness D₂of the silicon-containing material <b>215</b> to limit the growth of dislocations <b>241</b>, the growth of dislocations <b>241</b> can also be controlled by the CDE process.

0042<figref idref="DRAWINGS">FIG. 4A</figref> shows the process sequence of a CDE process <b>400</b> in a process chamber, in accordance with some embodiments. The process <b>400</b> include a deposition operation <b>401</b>, a post-deposition purge operation <b>402</b>, a partial-etch operation <b>403</b>, and a post-etch purge operation <b>404</b>, in accordance with some embodiments. The CDE process occurs in a process chamber. In some embodiments, the deposition operation <b>401</b> employs a silicon-containing gas, such astrisilane (Si₃H₈), di-silane (Si₂H₆), etc., as silicon source. A dopant gas, such as PH₃, is also used to provide a dopant, in accordance with some embodiments. In some embodiments, the deposition time is in a range from about 3 seconds to about 20 seconds. In some embodiments, the amount of the silicon-containing material <b>215</b> deposited in operation <b>401</b> is in a range from about 15 Å to about 80 Å during each CDE cycle, in accordance with some embodiments.

0043After deposition operation <b>401</b>, a purge gas is introduced into the process chamber to purge out the deposition gas at operation <b>402</b>. The purge gas may be any non-reactive gas with the deposition gas, such as N₂, or any inert gas (H₂, Ne, Ar, Kr, etc.) In some embodiments, an absorbing gas, such as HCl, is used to remove any residual deposition gas(es) in the process chamber during operation <b>402</b>. Once the chamber is cleaned, the etch operation <b>403</b> follows. In some embodiments, the etch operation <b>403</b> employs HCl gas and GeH₄gas. HCl and GeH₄react with silicon to etch silicon. For example, GeH₄reacts with silicon to form SiGe, which is then removed by HCl. In some embodiments, the etch time is in a range from about 40 seconds to about 200 seconds. In some embodiments, the amount of the silicon-containing material <b>215</b> removed in operation <b>403</b> is in a range from about 5 Å and about 30 Å during each CDE cycle, in accordance with some embodiments.

0044After the etching operation <b>403</b>, the purge operation <b>404</b> follows to remove the etching gases used in operation <b>403</b> from the chamber. The purge gas may be any non-reactive gas with the deposition gas, such as N₂, or any inert gas (H₂, Ne, Ar, Kr, etc.). As mentioned above, an absorbing gas, such as HCl, is used to remove any residual deposition gas(es) in the process chamber during operation <b>402</b>, in some embodiments. In each individual deposition/partial-etch cycle, a net thickness in a range from about 10 Å and about 40 Å is formed in an individual cycle in accordance with some embodiments. CDE process <b>400</b> is repeated a number of times until the desired thickness D₂is reached.

0045As described above, the CDE process <b>400</b> requires switching gases in the processing chamber. During manufacturing of semiconductor devices, multiple chambers of processing systems are used to process substrates. Chamber matching could become an issue, especially for a process operation with a short operation period, such as the deposition operation <b>401</b>. For example, if operation <b>401</b> has a processing time of 10 seconds, a gas flow switching with a delay of about 1 second could cause a 10% process variation. Such variation could result in thicker deposition on some wafers or portions of wafers. As a result, some dislocations <b>241</b> are not completely removed in the etching operation <b>403</b> due to gas flow switching delay in some chambers.

0046In order to prevent such occurrence, a post-CDE etch can be added. <figref idref="DRAWINGS">FIG. 4B</figref> shows a process flow <b>450</b> of depositing the silicon-containing material <b>215</b> in recesses <b>210</b>, in accordance with some embodiments. At operation <b>451</b> of process flow <b>450</b>, a CDE process is performed to deposit silicon-containing material (or layer) <b>215</b> recesses <b>210</b>. The CDE process deposits a thickness D₂of material <b>215</b>, in accordance with some embodiments. The CDE process includes a number of deposition/partial-etch cycles. After thickness D₂is reached, a post-deposition etch process is performed at operation <b>452</b> to remove residual dislocations <b>241</b> accumulated near gate corners <b>240</b>. The post-deposition etch at operation <b>452</b> also utilizes HCl and GeH₄, which are also used in the etch operation <b>403</b> of CDE, in accordance with some embodiments. However, the process parameter(s) may be similar to or different from operation <b>403</b> of CDE. The HCl/GeH₄flow ratio for etch operation <b>452</b> is significantly higher than the HCl/GeH₄flow ratio of etch operation <b>403</b>, in accordance with some embodiments. However, using an HCl/GeH₄flow ratio similar to etch operation <b>403</b> may also remove residual dislocations <b>241</b>.

0047In some embodiments, the process duration is in a range from about 30 seconds to about 80 seconds. The extended etch removes dislocations <b>241</b> in substrate processes in different chambers to ensure a chamber mismatch does not result in the growth of dislocations <b>241</b>, which could lead to GCDs.

0048With the additional post-deposition etch as described in operation <b>452</b> above, the S/D regions <b>250</b> are formed free of GCDs for wafers processed by various chambers, as shown in <figref idref="DRAWINGS">FIG. 2E</figref> in accordance with some embodiments. Transistors next to isolation devices usually experience more challenges associated with dislocations due to the neighboring isolation structure. <figref idref="DRAWINGS">FIGS. 5A-5C</figref> are cross-sectional views of a process sequence of forming a S/D region between a gate stack and an isolation structure, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 5A</figref> shows one of the gate stacks <b>205</b> with spacers <b>211</b> and <b>212</b> next to a shallow trench isolation (STI) <b>260</b>, in accordance with some embodiments. The STI <b>260</b> is filled with one or more dielectric materials, such as dielectric layer <b>261</b>. In some embodiments, dielectric layer <b>261</b> is made of SiO₂. A recess <b>210</b>* is formed between the gate stack <b>205</b> and the STI <b>260</b>. In an embodiment in which the recess <b>210</b>* has an angular shape, the recess <b>210</b>* may be formed to have a first angle α₁along with top of the recess <b>210</b>* and a second angle α₂along the bottom of the recess <b>210</b>* next to the gate stack <b>205</b>, as shown in <figref idref="DRAWINGS">FIG. 5A</figref>. In some embodiments, the first angle α₁is in a range from about 90° to about 180°. The second angle α₂is in a range from about 85° to about 170°, in accordance with some embodiments. The recess <b>210</b>* also forms a third angle α₃along the bottom of recess <b>210</b>* next to STI <b>260</b>. The third angle α₃is in a range from about 85° to about 170°, in accordance with some embodiments.

0049<figref idref="DRAWINGS">FIG. 5B</figref> shows the structure of <figref idref="DRAWINGS">FIG. 5A</figref> after a CDE process <b>451</b> and the post-deposition etching <b>452</b> described in <figref idref="DRAWINGS">FIGS. 4A and 4B</figref> have been performed to form the silicon-containing material <b>215</b>* in recess <b>210</b>*, in accordance with some embodiments. <figref idref="DRAWINGS">FIG. 5B</figref> shows that after processes <b>451</b> and <b>452</b>, the silicon-containing material <b>215</b>* does not have dislocations <b>241</b> on gate corner <b>240</b>. However, due to being next to dielectric layer <b>261</b>, dislocations <b>242</b> remains near the interface between the silicon-containing material <b>215</b>* and STI <b>260</b>. The number of dislocations <b>242</b> needs to be controlled so that their existence would not degrade device performance involving gate stack <b>205</b> next to STI <b>260</b>. <figref idref="DRAWINGS">FIG. 5C</figref> shows the S/D region <b>250</b>* after a silicon-containing layer <b>216</b>* by the SEG process is formed over silicon-containing material <b>215</b>*, in accordance with some embodiments. There are dislocations <b>218</b> in layer <b>216</b>* and dislocations <b>229</b> in layer <b>216</b>* near STI <b>260</b>. However, the dislocations <b>229</b> and <b>242</b> are far away from the S/D region <b>250</b>* near gate stack <b>205</b>, which is free of dislocations. Thus, dislocations <b>229</b> and <b>242</b> do not impact the device performance of the transistor involving gate stack <b>205</b>.

0050As noted, the processes of the method <b>100</b> described above in conjunction with <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>A-<b>2</b>E, and <b>4</b>A-<b>4</b>B are merely exemplary. The method <b>100</b> can include different steps according to different process flows. For example, the gate structure <b>205</b> can be formed by a gate-first process or a gate-last process. In some embodiments using a gate-last process, the method <b>100</b> can include a gate replacing process. The gate structure <b>205</b> can be a dummy gate structure. The dummy gate structure <b>205</b> can each include a dummy gate material and a hard mask material formed thereover. The dummy gate material can be made of at least one material such as polysilicon, amorphous silicon, silicon oxide, silicon nitride, a material having an etching rate that is substantially different from the spacers (shown in <figref idref="DRAWINGS">FIG. 2A</figref>).

0051For the gate-last process, the hard mask materials and the dummy gate materials can be removed, for example, by a wet etch process, a dry etch process, or any combinations thereof. After removing the dummy gate materials, the method <b>100</b> can include forming gate electrode material within openings in which the dummy gate materials are disposed. In some embodiments, the gate electrode material can be a stack structure including a diffusion barrier layer, a metallic work function layer, a metallic conductive layer, and/or other suitable material layers.

0052In some embodiments, at least one high dielectric constant (high-k) layer (not shown) can be formed under the gate electrode material. The high-k dielectric layer can include high-k dielectric materials such as HfO₂, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, other suitable high-k dielectric materials, or any combinations thereof. In some embodiments, the high-k material may further be selected from metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina alloy, other suitable materials, or any combinations thereof.

0053In some embodiments, the diffusion barrier can be configured to prevent metallic ions of the work function metal material from diffusing into the gate dielectric material. The diffusion barrier may comprise at least one material such as aluminum oxide, aluminum, aluminum nitride, titanium, titanium nitride, tantalum, tantalum nitride, other suitable material, and/or combinations thereof.

0054In some embodiments, the metallic work function layer can include at least one P-metal work function layer and/or at least one N-metal work function layer. The P-type work function materials can include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, and/or other suitable materials. The N-type metal materials can include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, and/or other suitable materials. In some embodiments, the metallic conductive layer can be made of at least one material, such as aluminum, copper, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, MoON, RuO₂, and/or other suitable materials.

0055In some embodiments, dielectric materials, contact plugs, via plugs, metallic regions, and/or metallic lines (not shown) can be formed over the gate electrode portions for interconnection. The dielectric layers may include materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, ultra low-k dielectric material, or any combinations thereof. The via plugs, metallic regions, and/or metallic lines can include materials such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other conductive materials, and/or combinations thereof. The via plugs, metallic regions, and/or metallic lines can be formed by any suitable processes, such as deposition, photolithography, and etching processes, and/or combinations thereof.

0056The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described eliminate dislocations near gate corners and gate corner defects (GCDs), and maintain transistor performance. The mechanisms described involve using a post-deposition etch to remove residual dislocations near gate corners after a cyclic deposition and etching (CDE) process is used to fill a portion of the recess regions with an epitaxially grown silicon-containing material. The mechanisms described also involve keeping the thickness of the portion of recess regions filled by the CDE process in a low range to minimize the growth of dislocations near gate corners. The remaining recess regions may be filled by another silicon-containing layer deposited by an epitaxial process without dislocations near gate corners. The embodiments described enable gate corners to be free of dislocation defects and prevent device performance degradation. The mechanisms described also widen the process window of forming S/D regions without gate corner defects and reduce chamber matching issues.

0057In a first exemplary embodiment, a method of forming an integrated circuit is provided. The method includes forming a plurality of gate structures over a substrate, and removing portions of the substrate to form recesses adjacent to the plurality of gate structures. The method also includes depositing a first epitaxial silicon-containing layer in the recesses, and depositing the first epitaxial silicon-containing layer using a cyclic deposition etching (CDE) process. The method further includes performing an etching process after depositing the first epitaxial silicon-containing layer to remove dislocations near gate corners. In addition, the method includes depositing a second epitaxial silicon-containing layer over the first epitaxial silicon-containing layer to form source and drain regions next to the plurality of gate structures.

0058In a second exemplary embodiment, a method of forming an integrated circuit is provided. The method includes forming a plurality of gate structures over a substrate, and removing portions of the substrate to form recesses adjacent to the plurality of gate structures. The method also includes depositing a first epitaxial silicon-containing layer in the recesses, and depositing the first epitaxial silicon-containing layer using a cyclic deposition etching (CDE) process. The method further includes performing an etching process after depositing the first epitaxial silicon-containing layer to remove dislocations near gate corners. In addition, the method includes depositing a second epitaxial silicon-containing layer over the first epitaxial silicon-containing layer to form source and drain regions next to the plurality of gate structures. The etching process after depositing the first epitaxial silicon-containing layer enables the source and drain regions formed to be free of dislocation defects near gate corners of the plurality of gate structures.

0059In a third exemplary embodiment, an integrated circuit is provided. The integrated circuit includes a gate structure disposed over a substrate, and a silicon-containing material structure disposed over a recess adjacent to the gate structure. The silicon-containing material structure includes a first epitaxial layer and a second epitaxial layer, and a gate corner of the gate structure is free of dislocation. A corner of the second epitaxial layer away from a surface of the substrate and next to a spacer of the gate structure includes dislocations, and the dislocations are away from the gate corner.

0060The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.