Single-ended volatile memory access

CROSS REFERENCE TO RELATED PATENT APPLICATIONS

0001This patent application relates to the U.S. patent application entitled “Volatile Memory Access Via Shared Bitlines”, inventors Michael Lee and Bao Truong, Attorney Docket No. AUS920110398US1 (Ser. No. to be assigned, filed on the same day as the subject patent application, and assigned to the same assignee), the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

0002The disclosures herein relate generally to volatile memory, and more specifically, to writing information to and reading information from static random access memory (SRAM). Writing to and reading information from SRAM expends valuable energy. Reduction of such energy expenditures by SRAM is desirable. One use of SRAM is in an information handling system (IHS) to store information in an SRAM array.

BRIEF SUMMARY

0003In one embodiment, a memory method is disclosed that includes selecting by a wordline enable signal a particular memory cell of a memory cell pair in an array of memory cells arranged in rows and columns. The particular memory cell of the memory cell pair is an addressed memory cell. The remaining memory cell of the memory cell pair is an unaddressed memory cell. The method also includes transmitting, in response to the wordline enable signal, data from the addressed memory cell to an evaluation gate by activating a pass gate in the addressed memory cell that couples the addressed memory cell to the evaluation gate via a first complement bitline therebetween. The method further includes activating, in response to the wordline enable signal, a pass gate in the unaddressed memory cell to couple the unaddressed memory cell to a true bitline that terminates without an evaluation gate.

0004In another embodiment, a memory is disclosed. The memory includes a plurality of memory cells configured in an array including rows and columns of memory cells, wherein the rows of memory cells include memory cell pairs. Each memory cell of a memory cell pair may include a cross-coupled inverter pair and two pass-devices that couple to alternate sides of the cross-coupled inverter pair. Each memory cell of a memory cell pair may be coupled to an associated respective pair of bitlines, each pair of bitlines including a true bitline and a complement bitline. The memory also includes a wordline drive circuit, coupled to the rows of memory cells, that generates a wordline enable signal to select a particular memory cell of a memory cell pair in a row of the array of memory cells. The particular memory cell of the memory cell pair is an addressed memory cell. The remaining memory cell of the memory cell pair is an unaddressed memory cell. The addressed memory cell may include a first pass gate. In response to the wordline enable signal, the addressed memory cell transmits data to an evaluation gate by activating the first pass gate to couple the addressed memory cell to the evaluation gate via a first complement bitline therebetween. The unaddressed memory cell includes a second pass gate that activates in response to the wordline enable signal to couple the unaddressed memory cell to a true bitline that terminates without an evaluation gate.

0005In yet another embodiment, an information handling system (IHS) is disclosed. The IHS includes a processor and a memory coupled to the processor. The memory includes a plurality of memory cells configured in an array including rows and columns of memory cells, wherein the rows of memory cells include memory cell pairs. Each memory cell of a memory cell pair may include a cross-coupled inverter pair and two pass-devices that couple to alternate sides of the cross-coupled inverter pair. Each memory cell of a memory cell pair may be coupled to an associated respective pair of bitlines, each pair of bitlines including a true bitline and a complement bitline. The memory also includes a wordline drive circuit, coupled to the rows of memory cells, that generates a wordline enable signal to select a particular memory cell of a memory cell pair in a row of the array of memory cells. The particular memory cell of the memory cell pair is an addressed memory cell. The remaining memory cell of the memory cell pair is an unaddressed memory cell. The addressed memory cell may include a first pass gate. In response to the wordline enable signal, the addressed memory cell transmits data to an evaluation gate by activating the first pass gate to couple the addressed memory cell to the evaluation gate via a first complement bitline therebetween. The unaddressed memory cell includes a second pass gate that activates in response to the wordline enable signal to couple the unaddressed memory cell to a true bitline that terminates without an evaluation gate.

BRIEF DESCRIPTION OF THE DRAWINGS

0006The appended drawings illustrate only exemplary embodiments of the invention and therefore do not limit its scope because the inventive concepts lend themselves to other equally effective embodiments.

0007<figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram of one embodiment of the disclosed memory circuit including a pair of SRAM memory cells.

0008<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of one embodiment of the disclosed array of memory cells.

0009<figref idref="DRAWINGS">FIG. 3A</figref> is a flow chart that depicts one method for reading the contents of a memory cell.

0010<figref idref="DRAWINGS">FIG. 3B</figref> is a flow chart that depicts one method for reading the contents of another memory cell.

0011<figref idref="DRAWINGS">FIG. 4</figref> is an information handling system (IHS) that includes the disclosed array of memory cells.

0012<figref idref="DRAWINGS">FIG. 5</figref> is a schematic diagram of another embodiment of a the disclosed memory circuit including a pair of SRAM memory cells.

0013<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of another embodiment of the disclosed array of memory cells.

0014<figref idref="DRAWINGS">FIG. 7</figref> is a schematic diagram of a read/write head used included in the disclosed memory array.

0015<figref idref="DRAWINGS">FIG. 8A</figref> is a is a flow chart that depicts a method for reading from the contents a memory cell.

0016<figref idref="DRAWINGS">FIG. 8B</figref> is a is a flow chart that depicts a method for writing to a memory cell.

0017<figref idref="DRAWINGS">FIG. 9</figref> illustrates a representative portion of a memory cell layout pattern that practices the disclosed methodology.

DETAILED DESCRIPTION

0018In one embodiment, the disclosed memory circuit includes a wordline drive circuit that addresses a particular cell of a pair of memory cells in a row of a memory cell array. That particular memory cell is the addressed memory cell and the remaining memory cell is the unaddressed memory cell of the memory cell pair. The addressed memory cell couples to a pair of true and complement bitlines. The unaddressed memory cell couples to another pair of true and complement bitlines. The complement bitline of the addressed memory cell conveys the data of the addressed memory cell to an evaluation gate for resolution. The remaining bitline of the addressed memory cell, namely the true bitline of the addressed memory cell remains in the precharge state. The complement bitline of the unaddressed memory also remain in the precharge state. In this manner, both cells of the pair of memory cells conserve valuable energy. While the true bitline of the unaddressed memory cell may change state depending on the data value it stores, the true bitline terminates without an evaluation gate. In this manner, the memory circuit does not waste energy propagating data downstream of the termination. A bitline drive circuit and the wordline drive circuit cooperate to select a particular a memory cell for a robust differential write operation.

0019<figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram of one embodiment of the disclosed memory circuit <b>100</b>. In this particular embodiment, memory circuit <b>100</b> includes at least static random access memory (SRAM) cells <b>101</b> and <b>102</b> arranged in at least two columns. For simplicity, <figref idref="DRAWINGS">FIG. 1</figref> shows only the memory cells <b>101</b> and <b>102</b> that may form the top-most cells of respective columns in a memory array. Other like memory cells may populate a memory array of columns and rows, such as the memory array that <figref idref="DRAWINGS">FIG. 2</figref> shows. Memory cell <b>101</b> includes a cross-coupled inverter pair <b>105</b>, <b>110</b> for storing a data bit. As seen in <figref idref="DRAWINGS">FIG. 1</figref>, memory cell <b>101</b> also includes pass-devices <b>115</b> and <b>120</b> that couple to inverters <b>105</b> and <b>110</b> to facilitate the reading and writing of information for that memory cell. Memory cell <b>102</b> includes a cross-coupled inverter pair <b>145</b>, <b>150</b> for storing another data bit. Memory cell <b>102</b> also includes pass-devices <b>155</b> and <b>160</b> that couple to inverters <b>145</b> and <b>150</b> to facilitate the reading and writing of information for that memory cell. Memory cells <b>101</b> and <b>102</b> may each store a logic value of the cross-coupled inverter pairs <b>145</b>, <b>150</b> and <b>155</b>, <b>160</b> respectively that may be accessed as either a true (T) data bit or a complement (C) bit.

0020Bitlines bl <b>125</b> and blb <b>130</b>, and also wordlines wl_A <b>190</b> and wl_B <b>195</b>, couple to memory cell <b>101</b>. The designations “bl” and “blb” indicate that these bitlines are differential bitlines that complement one another. In one embodiment, bitline bl <b>125</b> is a true bitline and bitline blb <b>130</b> is a complement bitline. In other embodiments, the roles of bitlines <b>125</b> and <b>130</b> may reverse. Bitlines bl <b>165</b> and blb <b>170</b>, and also wordlines wl_A <b>190</b> and wl_B <b>195</b>, couple to memory cell <b>102</b>. Bitlines blb <b>130</b> and blb <b>170</b> couple to the respective downstream output gates <b>103</b> and <b>103</b>′. In one embodiment, data output gates <b>103</b> and <b>103</b>′ function as evaluation gates for data content of memory cells <b>101</b> and <b>102</b>. In actual practice, gate <b>103</b> and gate <b>103</b>′ may be implemented as two inverters, wherein one inverter couples to bitline <b>130</b> and the other inverter couples to bitline <b>170</b>. Bitlines blb <b>130</b> and blb <b>170</b> are corresponding bitlines of SRAM memory cells <b>101</b> and <b>102</b> because they each exhibit the same logic convention in their respective SRAM cells. Data output gate <b>103</b> senses bitlines blb <b>130</b> and data output gate <b>103</b>′ senses blb <b>170</b> in a single-ended read operation of the complement of the logic value that cell <b>101</b> or <b>102</b> stores depending on which wordline, wl_A <b>190</b> or wl_B <b>195</b>, activates during the read operation. Gate <b>103</b> or gate <b>103</b>′ thus acts as an evaluation gate for the data contents of the selected memory cell and outputs the data content of the addressed memory cell on output data_out <b>104</b> or data_out <b>104</b>′ respectively in one embodiment.

0021More particularly, the output data bit at data_out <b>104</b> corresponds to the stored bit in memory cell <b>101</b> when the wordline wl_A <b>190</b> activates for a single-ended read operation. Alternatively, the output data bit at data_out <b>104</b>′ corresponds to the stored bit in memory cell <b>102</b> when wordline wl_B <b>195</b> activates for a single-ended read operation. Bitline drive circuit (<b>230</b> in <figref idref="DRAWINGS">FIG. 2</figref>) couples to bitlines bl <b>125</b> and blb <b>130</b>, or to bl <b>165</b> and blb <b>170</b> to select a particular one of memory cells <b>101</b> and <b>102</b>, i.e. a particular column, for a write operation. Wordline drive circuit (<b>240</b> in <figref idref="DRAWINGS">FIG. 2</figref>) couples to wordlines wl_A <b>190</b> and wl_B <b>195</b> to select a particular row of a memory array that multiple rows and columns of memory cells <b>101</b> and <b>102</b> may form.

0022To store a data bit in memory cell <b>101</b> during a differential write operation, wordline drive circuit (<b>240</b> in <figref idref="DRAWINGS">FIG. 2</figref>) selects and activates both wordlines wl_A <b>190</b> and wl_B <b>195</b>. Returning to <figref idref="DRAWINGS">FIG. 1</figref>, this action effectively connects pass-device <b>115</b> to bitline bl <b>125</b> and also connects pass device <b>120</b> to bitline blb <b>130</b>. Differentially activating bitlines bl <b>125</b> and blb <b>130</b> in this manner writes a data bit into memory cell <b>101</b> by forcing the inverter pair <b>105</b>, <b>110</b> to assume a state corresponding to the state of bitlines <b>125</b> and <b>130</b>. In this differential write operation to memory cell <b>101</b>, bitline drive circuit (<b>230</b> in <figref idref="DRAWINGS">FIG. 2</figref>) forces the desired logic state onto bitline <b>125</b> while also forcing the complement of the desired logic value onto bitline <b>130</b>. For write operations to memory cell <b>101</b>, the bitline drive circuit (<b>230</b> in <figref idref="DRAWINGS">FIG. 2</figref>) need not drive bitlines bl <b>165</b> and blb <b>170</b> that associate with memory cell <b>102</b>.

0023When wordline drive circuit (<b>240</b> in <figref idref="DRAWINGS">FIG. 2</figref>) activates both wordlines wl_A <b>190</b> and wl_B <b>195</b> to write information to memory cell <b>101</b>, this action also activates pass devices <b>155</b> and <b>160</b> of memory cell <b>102</b>. However, this action does not affect the contents of memory cell <b>102</b> because bitline drive circuitry (not shown) does not activate bitlines blb <b>165</b> and blb <b>170</b> when performing a write operation to memory cell <b>101</b>.

0024Memory cell arrays may include a single row or multiple rows with multiple columns. The particular aspect ratio of the rows and columns may depend on the application for the memory cell array and other considerations such as the energy needed to pre-charge bitlines and timing considerations. At least two columns of memory cells form the exemplary embodiment of the disclosed memory circuit.

0025<figref idref="DRAWINGS">FIG. 2</figref> shows the disclosed memory array <b>200</b> of memory cells <b>101</b>, <b>102</b> arranged in columns and rows. The columns are arranged in pairs of cells according to the teachings of <figref idref="DRAWINGS">FIG. 1</figref> with representative memory cell pairs <b>101</b>,<b>102</b> being identified in particular in row 1. This particular embodiment includes four (4) rows of cells, namely rows 1, 2, 3 and 4. Other embodiments may include a larger or smaller number of rows of cells depending on the particular application. For example, eight or sixteen columns may be included in the memory array to accommodate bytes of data. Similarly, nine or eighteen columns may be included in the memory array to accommodate bytes of data with a parity check bit. While memory array <b>200</b> may include fewer or more columns than the six (6) representative columns that <figref idref="DRAWINGS">FIG. 2</figref> shows, for discussion purposes <figref idref="DRAWINGS">FIG. 2</figref> identifies the two center columns of array <b>200</b> as column A (COL A) and column B (COL B). Memory array <b>200</b> may include more columns than the center columns identified as column A and column B. <figref idref="DRAWINGS">FIG. 2</figref> uses prime designators to differentiate the memory cell pairs <b>101</b>, <b>102</b> in the different rows of memory array <b>200</b>. For example, row 1 includes memory cells <b>101</b>, <b>102</b> in COL A and COL B, respectively. Row 2 includes memory cells <b>101</b>′, <b>102</b>′ in COL A and COL B, respectively. Row 3 includes memory cells <b>101</b>″, <b>102</b>″ in COL A and COL B, respectively. Row 4 includes memory cells <b>101</b>′″, <b>102</b>″ in COL A and COL B, respectively.

0026In memory array <b>200</b> of <figref idref="DRAWINGS">FIG. 2</figref>, bitlines bl <b>125</b> and blb <b>130</b> of COL A extend vertically through each of memory cells <b>101</b>, <b>101</b>′, <b>101</b>″ and <b>101</b>′″. Bitline blb <b>130</b> of COL A also couples to the input of gate <b>103</b>. In memory array <b>200</b>, bitlines bl <b>165</b> and blb <b>170</b> of COL B extend vertically through each of memory cells <b>102</b>, <b>102</b>′, <b>102</b>″ and <b>102</b>′″. Bitline blb <b>170</b> of COL B also couples to the input of gate <b>103</b>′. Bitlines bl <b>125</b> and <b>165</b> extend vertically through each of the memory cells in COL A and COL B, and terminate in ends <b>125</b>A and <b>165</b>A as also shown in <figref idref="DRAWINGS">FIG. 1</figref>. In one embodiment, the terminations at ends <b>125</b>A and <b>165</b>A may be open circuits.

0027Returning to <figref idref="DRAWINGS">FIG. 2</figref>, the following example describes a write operation to one of memory cells <b>101</b>, <b>102</b> in ROW 1 of memory array <b>200</b>, namely the particular memory cells <b>101</b>, <b>102</b> in COL A and COL B, respectively. In general, differential bitline drive circuit <b>230</b> selects the appropriate bitlines to designate a particular column for differential write operations to a memory cell in memory array <b>200</b>. Wordline drive circuit <b>240</b> further selects a particular row of memory array <b>200</b> by activating appropriate wordlines <b>220</b> corresponding to that row. In particular, the differential pair of bitlines <b>125</b> and <b>130</b> along with wordlines wl_A <b>190</b> and wl_B <b>195</b> in row 1 uniquely select memory cell <b>101</b> of COL A for data bit storage. Alternatively, the differential pair of bitlines <b>165</b> and <b>170</b> along with wordlines wl_A <b>190</b> and wl_B <b>195</b> of row 1 may uniquely select memory cell <b>102</b> of COL B for data bit storage.

0028In one embodiment, bitline drive circuit <b>230</b> precharges all of the bitlines <b>210</b> to the supply voltage (not specifically shown) when memory array <b>200</b> is in the quiescent or inactive state. The pre-charge voltage level corresponds to a logic 1. A memory that needlessly causes a memory cell bitline to discharge carries a penalty in wasted energy in the memory array. The disclosed memory array <b>200</b> may avoid wasting energy by arranging memory cells in pairs, as exemplified by memory cell pair <b>101</b> and <b>102</b> of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>. In one embodiment, wordline drive circuit <b>240</b> activates only wordline wl_A <b>190</b> of row 1 to read the contents of memory cell <b>101</b> of COL A in row 1. Bitline <b>130</b> then reflects the state of memory cell <b>101</b>. Bitline <b>125</b> associated with memory cell <b>101</b> of COL A, and bitlines <b>165</b> and <b>170</b> associated memory cell <b>102</b> of COL B, may remain in the pre-charged state and hence do not waste energy. Leaving the bitlines in the pre-charged state may conserve energy.

0029Gate <b>103</b> or gate <b>103</b>′ senses the state of memory cell <b>101</b> or memory cell <b>102</b> respectively by passing the data bit from the selected memory cell to the data output line data_out <b>104</b> or <b>104</b>′ via either bitline <b>130</b> or <b>170</b>. The output data reflects the state of the memory cell uniquely appearing on one bitlines <b>130</b> or <b>170</b>, and addressed on one corresponding wordlines wl_A <b>190</b> or wl_B <b>195</b>. The non-selected bitline remains at logic level 1. More specifically, gate <b>103</b> and <b>103</b>′ couple to input bitlines <b>130</b> and <b>170</b> respectively. When wordline wl_A <b>190</b> activates pass gate <b>120</b> of memory cell <b>101</b>, the complement of the logic state of memory cell <b>101</b> appears on bitline <b>130</b>, while bitline <b>170</b> remains in a pre-charged logical 1 state. Alternatively, when wordline wl_B<b>195</b> activates pass gate <b>160</b>, the complement of the state of memory cell <b>102</b> appears on bitline <b>170</b> while bitline <b>130</b> remains in a pre-charged logical 1 state.

0030TABLE 1 shows the logic states or “truth table” of gate <b>103</b> when gate <b>103</b> is an inverter.

0000<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="77pt" align="center" /><colspec colname="2" colwidth="35pt" align="center" /><colspec colname="3" colwidth="105pt" align="center" /><thead><row><entry namest="1" nameend="3" rowsep="1">TABLE 1</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>bitline 130</entry><entry>bitline 170</entry><entry>data output 104</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>0</entry><entry>1</entry><entry>1</entry></row><row><entry>1</entry><entry>1</entry><entry>0</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0031In reading the contents of memory cell <b>101</b> of row 1, bitline <b>170</b> is in its pre-charged state (logical 1), which corresponds to the TABLE 1 entries having a logic 1 in the bitline <b>170</b> column. Wordline wl_A <b>190</b> activates pass device <b>120</b> which reflects the complement of the memory contents of memory cell <b>101</b> to bitline <b>130</b>. If the memory cell contains a logic 1, then the complement 0 appears on bitline <b>130</b>. From TABLE 1, a logic level 1 then appears at the data output data_out <b>104</b>. Similarly, if memory cell <b>101</b> contained a logic level 0, then the complement logic value 1 appears on bitline <b>130</b>, which results in a logic level 0 appearing at the data output data_out <b>104</b>.

0032In a similar manner, to read the contents of memory cell <b>102</b>, the data bit stored in memory cell <b>102</b> reflects in the data output data_out ′<b>104</b> when wordline wl_B <b>195</b> activates pass device <b>160</b> of memory cell <b>102</b>. In this case, bitline blb <b>130</b> stays at a logic 1 level. Memory cell <b>102</b> content of logic level 1 appears as the complement 0 on bitline blb <b>170</b> which appears as a logic level 1 at data output data_out′ <b>104</b>. Similarly, memory cell <b>102</b> content of logic level 0 appears as the complement 1 on bitline blb <b>170</b> which appears as a logic level 0 at data output data_out <b>104</b>.

0033In one embodiment, since one of the two wordlines wl_A <b>190</b> and wl_B <b>195</b> uniquely activates only one of the single-ended bitlines blb <b>130</b> and blb <b>170</b> of the pair of memory cells <b>101</b>, <b>102</b>, this action effectively uniquely addresses one of memory cells <b>101</b>, <b>102</b> in the addressed row. This approach may avoid the use of multiplexer circuitry otherwise needed to distinguish which bitline is addressed in other methods of reading cells. Thus, the disclosed memory array <b>200</b> may reduce the discharge of energy on unneeded bitlines. In this embodiment, gates <b>103</b> and <b>103</b>′ act as evaluation gates that senses respective single-ended read bitlines of a pair of cells, and pass the data from the memory cell selected by the wordline. In a preferred embodiment, gate <b>103</b> is a inverter gate.

0034Exemplary memory cells <b>101</b> and <b>102</b> each include a true memory bitline bl and a complement memory bitline blb. Although the read operation of one embodiment operates on complement memory bit lines, a memory read operation may be configured to sense the true bitlines with substantially equal results to the scenario wherein a memory read operation senses the complement bit lines blb. Sensing true bitlines produces the complement of the memory cell logic state at the data output.

0035In summary, for one embodiment of the disclosed methodology, Table 2 below shows the state changes of the bitlines of SRAM cells <b>101</b> and <b>102</b> in row 1 of memory array <b>200</b> when wordline drive circuit <b>240</b> addresses one of cells <b>101</b> and <b>102</b>. Bitline state changes consume energy. The disclosed methodology may reduce bitline state changes. For discussion purposes, assume that wordline circuit <b>240</b> addresses memory cell <b>101</b> to read the data contents of that SRAM cell. In this scenario, memory cell <b>101</b> is the addressed cell and SRAM cell <b>102</b> is the unaddressed cell of an memory cell pair.

0000<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="63pt" align="left" /><colspec colname="2" colwidth="154pt" align="left" /><thead><row><entry namest="1" nameend="2" rowsep="1">TABLE 2</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>Addressed memory</entry><entry /></row><row><entry>cell</entry></row><row><entry>bl</entry><entry>remains in precharge state (no state change)</entry></row><row><entry>blb</entry><entry>may change state according to the memory contents</entry></row><row><entry /><entry>of the memory cell (may expend energy)</entry></row><row><entry>Unaddressed</entry></row><row><entry>memory cell</entry></row><row><entry>bl</entry><entry>may change state, state change does not propagate</entry></row><row><entry /><entry>beyond this cell</entry></row><row><entry>blb</entry><entry>remains in precharge state (no state change)</entry></row><row><entry namest="1" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables><br /> When wordline circuit <b>240</b> addresses memory cell <b>101</b> for a read operation by activating the blb bitline <b>130</b> of memory cell <b>101</b>, the blb bitline <b>130</b> of addressed SRAM cell <b>101</b> may change state depending on the memory content of the memory cell and drives evaluation gate <b>103</b>. This state change on the blb bitline of addressed SRAM cell <b>101</b> and also the possible state change on the bl line of the unaddressed may consume energy. However, in one embodiment, by virtue of the effective termination of bitline <b>165</b> at <b>165</b>A for read operations (<figref idref="DRAWINGS">FIG. 1</figref> and <figref idref="DRAWINGS">FIG. 2</figref>), when memory cell <b>101</b> is the addressed memory cell, a state change occurring on the bitline bl <b>165</b> of the unaddressed memory cell <b>102</b> does not propagate further downstream beyond termination <b>165</b>A to circuitry that might otherwise load down the bitline bl <b>165</b> and consume more energy. In this manner, the memory circuit may conserve energy during a read operation by avoiding the need for bitline bl <b>165</b> to drive logic gates downstream of termination <b>165</b>A in the column (e.g. COL B) that includes the unaddressed memory cell <b>102</b>. The remaining bitline bl of addressed SRAM cell <b>101</b> and the bitline blb of unaddressed memory cell <b>102</b> remain in the precharge state, thus conserving energy during a read operation. Whereas bitline bl <b>165</b> of memory cell <b>102</b> includes an effective termination for read operations at <b>165</b>A, bitline bl <b>125</b> of memory cell <b>101</b> includes an effective termination for read operations at <b>125</b>A. In one embodiment, these terminations are effective terminations with respect to read operations and do not affect write operations. The teachings above apply in a similar manner when memory cells <b>101</b> and <b>102</b> reverse roles such that memory cell <b>102</b> is the addressed memory cell and memory cell <b>101</b> is the unaddressed memory cell. In that case, when memory cell <b>102</b> becomes the addressed memory cell and memory cell <b>101</b> is the unaddressed memory cell, then termination <b>125</b>A prevents the propagation of data signals further downstream beyond termination <b>125</b>A to circuitry that might otherwise load down bitline bl <b>125</b> and consume more energy.

0036<figref idref="DRAWINGS">FIG. 3A</figref> is a flow chart describing one embodiment of the disclosed method of reading from a column A (COL A) of the SRAM memory cells <b>101</b> and <b>102</b>. Process flow commences at start block <b>305</b>. Wordline drive circuit <b>240</b> selects wordline wl_A, as per block <b>310</b>. More particularly, wordline drive circuit <b>240</b> transmits the wordline activate signal to the column A memory cell, as per block <b>315</b>. The wordline activate signal turns on pass devices (<b>120</b> and <b>155</b> in <figref idref="DRAWINGS">FIG. 1</figref>), as per block <b>320</b>. In response, the complement of the data bit stored in memory cell <b>101</b> appears on the complement bit line blb <b>130</b>. The evaluation gates <b>103</b>, such as inverters in one embodiment, evaluate the complement operation of bitline blb <b>130</b> of COLA, as per block <b>325</b>. Evaluation gate <b>103</b> outputs a bit corresponding to the data bit stored in column A memory cell <b>101</b> at data_out <b>104</b>, as per block <b>330</b>. Process flow ends at end block <b>335</b> or restarts at start block <b>305</b> to read another memory cell.

0037<figref idref="DRAWINGS">FIG. 3B</figref> is a flow chart describing one embodiment of the disclosed method of reading from a column B (COL B) of the SRAM memory cells <b>101</b> and <b>102</b>. Process flow commences at start block <b>345</b>. Wordline drive circuit <b>240</b> selects wordline wl_B, as per block <b>350</b>. More particularly, wordline drive circuit <b>240</b> transmits the wordline activate signal to the column B memory cell, as per block <b>355</b>. The wordline activate signal turns on pass devices (<b>115</b> and <b>160</b> in <figref idref="DRAWINGS">FIG. 1</figref>), as per block <b>360</b>. In response, the complement of the data bit stored in memory cell <b>101</b> appears on the complement bit line blb <b>170</b>. The evaluation gate <b>103</b>′ (inverter) evaluates the complement of bitline blb <b>130</b> of COL B, as per block <b>365</b>. Evaluation gate <b>103</b>′ outputs a bit corresponding to the data bit stored in column B memory cell <b>102</b> at data_out <b>104</b>′, as per block <b>370</b>. Process flow ends at end block <b>375</b> or restarts at start block <b>345</b> to read another memory cell.

0038In summary, the choice of activating either wordline wl_A or wordline wl_B selects which one of memory cells of column A or column B respectively outputs data to its respective complement bitline blb. The evaluation gates processes complement the respective bitlines blb, evaluating and outputting the data from the selected memory cell to the respective data_out line.

0039<figref idref="DRAWINGS">FIG. 4</figref> shows an information handling system (IHS) <b>400</b> that is configured to employ the disclosed SRAM memory circuit technology and is described in more detail below.

0040<figref idref="DRAWINGS">FIG. 5</figref> shows another embodiment of the disclosed memory circuit as memory circuit <b>500</b>. Memory circuitry <b>500</b> includes of a pair of SRAM memory cells <b>501</b> and <b>502</b> that operate in an energy efficient manner. SRAM memory cells <b>501</b> and <b>502</b> are arranged in at least two columns of which <figref idref="DRAWINGS">FIG. 5</figref> depicts the two top-most cells. Memory cell <b>501</b> includes a cross-coupled inverter pair <b>505</b> and <b>510</b>, and pass devices <b>515</b> and <b>520</b>. Memory cell <b>501</b> couples to bitlines bl <b>525</b> and bl′ <b>530</b>, and to wordline wl_a <b>595</b>, via pass devices <b>515</b> and <b>520</b> as shown. Memory cell <b>502</b> includes cross-coupled inverter pair <b>545</b> and <b>550</b>, and pass devices <b>555</b> and <b>560</b>. Memory cell <b>502</b> couples to bitlines bl′ <b>530</b> and bl <b>565</b>, and to wordline wl_b <b>590</b>, via pass devices <b>555</b> and <b>560</b> as shown. SRAM memory cells <b>501</b> and <b>502</b> share bitline bl′ <b>530</b> as discussed in more detail below. Pass devices <b>515</b> and <b>520</b> couple to wordline wl_a <b>595</b> at nodes <b>910</b> and <b>915</b>, respectively. Pass devices <b>555</b> and <b>560</b> couple to wordline wl_b <b>590</b> at nodes <b>920</b> and <b>925</b>, respectively.

0041<figref idref="DRAWINGS">FIG. 6</figref> shows a memory array <b>600</b> including SRAM memory cells <b>501</b> and <b>502</b> embedded in the array. Memory array <b>600</b> arranges the SRAM memory cells in columns and rows as shown. In <figref idref="DRAWINGS">FIG. 6</figref>, bitlines are shown generally as bitlines <b>605</b> and wordlines are shown generally as wordlines <b>610</b>, although specific bitlines and specific wordlines will have other numbers. Memory array <b>600</b> further includes read/write heads <b>700</b>, <b>700</b>′ and <b>700</b>″. Memory cells <b>501</b> and <b>502</b> share bitline bl′ <b>530</b> at node <b>517</b>. Moreover, memory cell <b>501</b> shares bitline bl <b>525</b> with adjacent memory cell <b>502</b>′ at node <b>507</b>, while memory cell <b>502</b> shares bitline bl <b>565</b> with adjacent memory cell <b>501</b>″ at node <b>527</b>. In general, in memory array <b>600</b>, columns of memory cells share a common bitline located between the cell columns.

0042Returning now to <figref idref="DRAWINGS">FIG. 5</figref>, activating wordline wl_a <b>595</b> during a single-ended read operation causes the complement of the data contents of memory cell <b>501</b> to appear on bitline bl′ <b>530</b>. Similarly, activating wordline wl_b <b>590</b> causes the complement of the data contents of memory cell <b>502</b> to appear on bitline bl′ <b>530</b>. Data contents of either memory cell <b>501</b> or <b>502</b> appear on the same bitline bl′ <b>530</b>, thus providing sharing of this bitline bl′ <b>530</b>. Activation of wordline wl_a <b>595</b> or wl_b <b>590</b> uniquely selects either SRAM memory cell <b>501</b> or <b>502</b>, respectively, to place its data on shared bitline bl′ <b>530</b>. As will be described below, bitlines bl <b>525</b> and bl <b>565</b> remain at the pre-charge logic level 1 during read operations even though pass devices <b>515</b> or <b>560</b> may be active. Thus, bitlines bl <b>525</b> and bl <b>565</b> do not needlessly discharge and waste energy during read operations of cells <b>501</b> and <b>502</b>.

0043During a differential write operation to memory cell <b>501</b> of SRAM cell pair <b>501</b>, <b>502</b>, wordline wl_a <b>595</b> activates pass devices <b>515</b> and <b>520</b> via nodes <b>910</b> and <b>915</b>, respectively. More particularly, a read/write head <b>700</b> (discussed below with reference to <figref idref="DRAWINGS">FIG. 7</figref>) acts as a driver that forces a desired data bit onto bitline bl <b>525</b> and simultaneously forces the complement of the data bit value onto bitline bl′ <b>530</b> to write the data bit value to memory cell <b>501</b>. Similarly, when selecting wordline wl_b <b>590</b> for a differential write operation to memory cell <b>502</b> of SRAM cell pair <b>501</b>, <b>502</b>, read/write head <b>700</b> forces a desired data bit value onto bitline bl <b>565</b> and forces the complement of that data bit value onto the shared bitline bl′ 530. Bitlines bl <b>525</b> and <b>565</b> form an opposed pair of intra-cell bitlines in that they are on opposites sides of a cell pair. Intra-cell bitlines may be shared by adjacent columns within memory cell pairs.

0044<figref idref="DRAWINGS">FIG. 7</figref> shows a representative read/write head <b>700</b> configured to perform single-ended reading of, and robust differential writing to, a selected memory cell in memory array <b>600</b>. Read/write head <b>700</b> couples to bitlines bl <b>525</b>, bl′ <b>530</b>, and bl <b>565</b> to drive data onto, and to receive data from, those bitlines during write and read operations, respectively. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, read/write head <b>700</b> shares bitline bl <b>525</b> with the partially shown read/write head <b>700</b>′ to its left (i.e. read/write head <b>700</b>′ in <figref idref="DRAWINGS">FIG. 6</figref>). Returning to <figref idref="DRAWINGS">FIG. 7</figref>, read/write head <b>700</b>′ includes gate <b>730</b>′ further including write enable and wl_b enable inputs, which may enable driver <b>735</b> to drive data0 data to inter-pair bitline bl <b>525</b> during a write data operation to a column B col_B memory cell exemplified by memory cell <b>502</b>′. Read/write head <b>700</b> also shares bitline bl <b>565</b> with the partially shown read/write head to its right (read/write head <b>701</b>″ in <figref idref="DRAWINGS">FIG. 6</figref>). Read/write head <b>700</b>″ includes gate <b>710</b>′ further including write enable and wl_a enable inputs, which may enable driver <b>705</b> to drive data2 data to inter-pair bitline bl <b>565</b> during a write data operation to a column A col_A memory cell exemplified by memory cell <b>501</b>″.

0045During a differential write operation to memory cell <b>501</b> of an SRAM memory cell pair <b>501</b> and <b>502</b>, addressing circuitry (not shown) transmits an enable signal on write enable input <b>710</b>A of AND gate <b>710</b> to enable driver <b>705</b>, while input <b>702</b> enables driver <b>720</b>. For this write operation to memory cell <b>501</b> to proceed, the addressing circuitry (not shown) also transmits an enable signal to the remaining input <b>710</b>B of gate <b>710</b> (and also to wordline wl_a <b>595</b>), thus enabling gate <b>710</b>. Driver <b>705</b> sends a data bit on input <b>701</b> to bitline bl <b>525</b>. Simultaneously, the inverter <b>725</b> complements (inverts) the data bit and drives the complement of the data bit through the write enabled driver <b>720</b> onto bitline bl′ <b>530</b> for a robust write operation to memory cell <b>501</b> through the enabled pass devices <b>515</b> and <b>520</b>.

0046For a differential write operation to memory cell <b>502</b> of <figref idref="DRAWINGS">FIG. 5</figref>, addressing circuitry (not shown) signals wordline wl_b <b>590</b> to enable memory cell <b>502</b> and also enable gate <b>730</b> on input <b>730</b>B of <figref idref="DRAWINGS">FIG. 7</figref>. More specifically, a driver <b>735</b> sends a data bit from input <b>701</b> to bitline bl <b>565</b> through driver <b>735</b>. Simultaneously, the inverter <b>725</b> complements (inverts) the data bit and drives the complement of the data bit onto bitline bl′ <b>530</b> through driver <b>720</b> for a robust write operation to memory cell <b>502</b> through the enabled pass devices <b>555</b> and <b>560</b>. From the discussion above, it can be seen that read/write head <b>700</b> differentially writes to SRAM memory cell <b>501</b> via bitlines <b>525</b> and <b>530</b>, whereas read/write head <b>700</b> differentially writes to SRAM memory cell <b>502</b> via bitlines <b>530</b> and <b>565</b>. Bitline <b>530</b> is a shared bitline because memory circuit <b>500</b> employs this bitline for both write operations to memory cell <b>501</b> and write operations to memory cell <b>502</b> via the common node <b>517</b>. Since shared bitline <b>530</b> is between memory cells <b>501</b> and <b>502</b> of a particular memory cell pair, bitline <b>530</b> is an “intra-pair” shared bitline for that memory cell pair.

0047During a singled-ended read operation, the wordline wl_a <b>595</b> or wl_b <b>590</b> activates pass device <b>520</b> or pass device <b>555</b>, respectively of <figref idref="DRAWINGS">FIG. 5</figref>. Output data driver <b>715</b> of read/write head <b>700</b> of <figref idref="DRAWINGS">FIG. 7</figref> is also enabled with read enable input <b>706</b>. The complement of the data contents of the selected memory cell reflects to the common shared bitline bl′ <b>530</b> and transmits through driver <b>715</b> to data output <b>704</b>. In this embodiment bitline bl′ <b>530</b> reflects the complement of the data stored in the enabled memory cell, so output data driver may be configured as an inverter, so that data output <b>704</b> reflects the contents of the memory cell rather than the complement of the content of the memory cell.

0048Returning to <figref idref="DRAWINGS">FIG. 6</figref>, the disclosed memory circuit topology includes two different types of bitline sharing, exemplified by intra-pair bitlines <b>530</b>′, <b>530</b>, and <b>530</b>″ and by inter-pair bitlines <b>525</b> and <b>565</b>. As discussed above, using memory cell pair <b>501</b>, <b>502</b> in row 1 as a representative memory cell pair, <figref idref="DRAWINGS">FIG. 6</figref> shows that within the memory cell pair <b>501</b>, <b>502</b> the two memory cells share a common “intra-pair” bitline bl′ <b>530</b> and share a common node <b>517</b> for differential memory write operations to either of cells <b>501</b> and <b>502</b>. Likewise, in row 2 the memory cell pairs <b>901</b> and <b>902</b> below memory cell pair <b>501</b>, <b>502</b> also couple to the intra-pair shared bitline bl′ <b>530</b>. In this particular embodiment, intra-pair shared bitline <b>530</b> is a bl′ bitline that passes through and couples to all of the cell pairs in the cell pair column of which memory cell pair <b>501</b>, <b>502</b> are the uppermost cells. Intra-pair bitline bl′ <b>530</b> couples as well to read/write head <b>700</b>, as <figref idref="DRAWINGS">FIG. 7</figref> depicts. Memory array <b>600</b> also uses intra-pair bitline bl′ <b>530</b> for single-ended read operations.

0049Returning again to <figref idref="DRAWINGS">FIG. 6</figref>, the disclosed memory circuit topology also employs “inter-pair” bitline sharing that is a type of bitline sharing different from the “intra-pair” bitline sharing discussed above. Whereas “intra-pair” bitline sharing refers to sharing of a bitline by two cells within a cell pair in a particular row, “inter-pair” bitline sharing refers to sharing of a bitline between two adjacent cell pairs in the same row of the memory array, such as memory array <b>600</b>. For example, cell pair <b>501</b>, <b>502</b> and cell pair <b>501</b>′, <b>502</b>′ share inter-pair bitline bl <b>525</b> that runs between these two cell pairs, as illustrated in <figref idref="DRAWINGS">FIG. 6</figref>. Likewise, cell pair <b>501</b>, <b>502</b> and cell pair <b>501</b>″, <b>502</b>″ share inter-pair bitline bl <b>565</b> that runs between these two cell pairs. Memory array <b>600</b> replicates the topology of the three cell pairs of row 1 in the remaining square boxes of memory array <b>600</b> in rows 2, 3 and 4 below row 1. The read/write heads <b>700</b>′, <b>700</b> and <b>700</b>″ cooperate with the intra-pair bitline sharing and inter-pair bitline sharing arrangement above to efficiently write data to, and read data from, the memory cells of memory array <b>600</b>. Since bitline bl <b>525</b>′ and bitline bl <b>565</b>″ are situated on the peripheral edge or border of the memory array, the memory array does not implement inter-pair bitline sharing for these particular bitlines.

0000<tables id="TABLE-US-00003" num="00003"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="63pt" align="left" /><colspec colname="2" colwidth="77pt" align="left" /><colspec colname="3" colwidth="77pt" align="left" /><thead><row><entry namest="1" nameend="3" rowsep="1">TABLE 3</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>Write Operations</entry><entry>intra-pair bitline sharing</entry><entry>inter-pair bitline sharing</entry></row><row><entry>Read Operations</entry><entry>intra-pair bitline sharing</entry></row><row><entry /><entry>(singled-ended)</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables><br /> Table 3 summarizes the different types of bitline sharing that memory array <b>600</b> employs to efficiently write data to, and read data from, the memory array. As seen in Table 3, write operations employ both the disclosed intra-pair bitline sharing and inter-pair bitline sharing, while read operations employ the disclosed single-ended intra-pair bitline sharing.

0050<figref idref="DRAWINGS">FIG. 8A</figref> is a flow chart describing a representative read memory operation from a memory cell in the disclosed SRAM array <b>600</b>. The read memory operation to memory cell <b>501</b> or memory cell <b>502</b> starts at start block <b>805</b>. Read/write head <b>700</b> transmits a wordline select signal to select wordline wl_a <b>595</b> or wordline wl_b <b>590</b> of wordline drive circuit <b>620</b>, as per block <b>810</b>, corresponding to memory cell <b>501</b> or memory cell <b>502</b> respectively. The memory read circuit of read/write head <b>700</b> transmits a wordline enable signal to the wordline drive circuit <b>620</b> driving the selected wordline wl_a <b>595</b> or wordline wl_b <b>590</b> corresponding to memory cell <b>501</b> or <b>502</b> respectively, as per block <b>815</b>. The wordline drive circuit <b>620</b> transmits an on signal to pass device <b>520</b> in memory cell <b>501</b> on wordline wl_a <b>595</b>, or to pass device <b>555</b> on wordline wl_b <b>590</b> which turns on the memory cell pass device <b>520</b> of memory cell <b>501</b> or turns on the memory cell pass device <b>555</b> of memory cell <b>502</b> respectively, as per block <b>820</b>. The memory read circuit of read/write head <b>700</b> also transmits a read enable signal <b>706</b> to gate <b>715</b> coupling the shared complement bitline bl′ <b>530</b> in the read/write head to data out1 <b>704</b>, as per block <b>825</b>. Gate <b>715</b> evaluates the complement bitline bl′ <b>530</b>, as per block <b>830</b>. Gate <b>715</b> outputs the data corresponding to the contents of the selected memory cell <b>501</b> or memory cell <b>502</b> from complement bitline bl′ <b>530</b> on the data out1 line at <b>704</b>, as per block <b>835</b>. The read memory operation terminates according to block <b>840</b>. In actual practice, the disclosed memory circuit may commence another memory read or write operation immediately after the read operation discussed above.

0051<figref idref="DRAWINGS">FIG. 8B</figref> shows a flow chart describing a representative write operation to a memory cell of the disclosed SRAM array. The write memory operation begins at start block <b>850</b>. The write memory circuit of read/write head <b>700</b> selects either wordline wl_a <b>595</b> to write data to memory cell <b>501</b>, or wordline wl_b <b>590</b> to write data to memory cell <b>502</b>, according to block <b>855</b>. The write memory circuit transmits a wordline enable signal as per block <b>860</b> to the wordline drive circuit <b>620</b> (which enables both pass devices <b>515</b> and <b>520</b> or both pass devices <b>555</b> and <b>560</b> of memory cell <b>501</b> or <b>502</b> respectively), and to enable either gate <b>710</b> or gate <b>730</b> in the read/write head controlling driver of the bitline corresponding to a write operation to memory cell <b>501</b> or <b>502</b> respectively. The write memory circuit transmits a write enable signal <b>710</b>A or <b>730</b>A to gate <b>710</b> or <b>730</b> controlling the driver <b>705</b> or <b>735</b> of the selected bitline bl <b>525</b> or bitline bl <b>565</b> respectively, and to driver of the shared complement bitline <b>530</b> in the read/write head <b>700</b> as per block <b>865</b>. The read/write head <b>700</b> receives data from data input (write data1) <b>701</b>, as per block <b>870</b>. The read/write head <b>700</b> writes data to the selected memory cell as per block <b>875</b> by driving the data through the bitline driver <b>705</b> or <b>735</b> to bitline <b>525</b> or <b>565</b>, and by driving the data complemented by inverter <b>725</b> through driver <b>720</b> to the shared complement bitline bl′ <b>530</b> for a differential write memory operation of the memory cell <b>501</b> or <b>502</b> respectively. The write memory operation terminates according to block <b>880</b>. In actual practice, the disclosed memory circuit may commence another memory read or write operation immediately after the write operation discussed above.

0052<figref idref="DRAWINGS">FIG. 9</figref> shows a representative portion of an integrated circuit layout pattern that practices the disclosed methodology. Memory array <b>900</b> includes memory cell pair <b>501</b>, <b>502</b>, and memory cell pair <b>901</b>, <b>902</b>. Memory cells <b>501</b>, <b>502</b>, <b>901</b>, <b>902</b> occupy areas bounded by borders <b>935</b>, <b>940</b>, <b>945</b> and <b>950</b>, respectively. Memory cells physically overlap slightly to conserve space in array <b>900</b>. For example, cell area borders <b>935</b> and <b>945</b> overlap by a width <b>905</b>. The entire ROW 1 of memory cells slightly overlaps ROW 2 of memory cells by width <b>905</b>. Similarly, columns of memory cells overlap slightly to conserve space. By example, memory cell borders <b>935</b> and <b>945</b> of column A (col_A) overlap memory cell borders <b>940</b> and <b>950</b> of column B (col_B) respectively overlap by a width <b>907</b>. More generally, adjacent rows of memory cells overlap by width <b>905</b>, and adjacent columns of cells overlap by width <b>907</b>.

0053Returning to <figref idref="DRAWINGS">FIG. 5</figref>, memory cells <b>501</b> and <b>502</b> exhibit a particular layout symmetry. Specifically, in this particular embodiment, the orientation of the circuitry of memory cell <b>502</b> is “upside down and reversed” with respect to the orientation of the circuitry of memory cell <b>501</b>, such that memory cells <b>501</b> and <b>502</b> exhibit quadrilateral symmetry. In other words with such quadrilateral symmetry, memory cell <b>501</b> couples to a bl bitline on its left edge, and bl′ bitline on its right edge, and a wordline along the lower edge. In contrast, memory cell <b>502</b> couples to a bl bitline on its right edge, a bl′ bitline on its left edge and a wordline along the upper edge.

0054Returning to <figref idref="DRAWINGS">FIG. 9</figref>, cells in a column have the same symmetry, while memory cells in a particular row alternate in symmetry. Column B (col_B) memory cells exhibit “upside down and reversed” symmetry (quadrilateral symmetry) with respect to the column A (col_A) memory cells. This arrangement of symmetries facilitates sharing of bitlines between memory cells in adjacent columns. For example, the columns of memory cells adjacent to bitlines bl <b>525</b> and <b>565</b> as well as bitlines bl′ <b>530</b> and <b>530</b>″ (also depicted in <figref idref="DRAWINGS">FIG. 6</figref>) share those bitline, respectively. Memory cells <b>502</b>′ and <b>501</b> share node <b>507</b> of bitline bl <b>525</b>. Memory cells <b>501</b> and <b>502</b> share node <b>517</b> of bitline bl′ <b>530</b>. Memory cells <b>502</b> and <b>501</b>″ share node <b>527</b> of bitline bl <b>565</b>. The “upside down and reversed” (quadrilateral) symmetry in alternating columns of memory cells facilitates pairing of cells, exemplified by memory cells <b>501</b> and <b>502</b>, into column A (col_A) and column B (col_B) memory cells. Wordlines <b>610</b> alternate between wordlines that service column A (col_A) exemplified by wordline wl_a <b>595</b>, and wordlines that service column B (col_B) exemplified by wordline wl_b <b>590</b>. Specifically, wordline wl_a <b>595</b> connects to memory cell <b>501</b> at nodes <b>910</b> and <b>915</b>, while wordline wl_b <b>590</b> connects to memory cell <b>502</b> via nodes <b>920</b> and <b>925</b>. Nodes <b>910</b>′ and <b>915</b>′, and nodes <b>920</b>′ and <b>925</b>′ connect wl_a and wl_b wordlines to memory cells <b>901</b> and <b>902</b> respectively. More generally, wordlines <b>610</b> serve alternate columns of memory cells, with wl_a wordlines coupled to col_A memory cells and wl_b wordlines coupled to col_B memory cells. By pairs of memory cells exhibiting quadrilateral symmetry, it is meant that the topology of the memory cell pairs is such that pairs of memory cells are reflected in both the horizontal and vertical axes, e.g. column B (col_B) memory cells are upside-down and reversed with column A (col_A) memory cells. In summary, the arrangement of symmetries in memory cells facilitates straight paths for wordlines <b>610</b> which in turn facilitates compact arrangement of memory cells along columns. Sharing bitlines facilitates compact arrangement of memory cells in the along rows. The symmetries and pairing of memory cells according to the embodiment facilitates a more compact memory array than in other arrangements, and sharing of bitlines results in energy efficiency of reading SRAM.

0055Sharing of the bitlines as provided by the exemplary embodiments has the benefit that the memory read operation does not needlessly discharge bitlines associated with memory cells for which the data would be discarded. Practicing the disclosed technology may achieve significant energy savings.

0056Returning now to <figref idref="DRAWINGS">FIG. 4</figref>, information handling system (IHS) <b>400</b> employs the disclosed SRAM memory array <b>200</b> and/or <b>600</b> as SRAM cache <b>450</b> and/or SRAM system memory <b>420</b>. IHS <b>400</b> includes a processor <b>410</b> that may include multiple cores and SRAM cache <b>450</b>. IHS <b>400</b> processes, transfers, communicates, modifies, stores or otherwise handles information in digital form, analog form or other form. IHS <b>400</b> includes a bus <b>415</b> that couples processor <b>410</b> to system memory <b>420</b> via a memory controller <b>425</b> and memory bus <b>430</b>. In one embodiment, system memory <b>420</b> is external to processor <b>410</b>. System memory <b>420</b> may be a static random access memory (SRAM) array of <figref idref="DRAWINGS">FIG. 2</figref> or <figref idref="DRAWINGS">FIG. 6</figref> and/or a dynamic random access memory (DRAM) array. A video graphics controller <b>435</b> couples display <b>440</b> to bus <b>415</b>. Nonvolatile storage <b>445</b>, such as a hard disk drive, CD drive, DVD drive, or other nonvolatile storage couples to bus <b>415</b> to provide IHS <b>400</b> with permanent storage of information. I/O devices <b>490</b>, such as a keyboard and a mouse pointing device, couple to bus <b>415</b> via I/O controller <b>455</b> and I/O bus <b>460</b>. One or more expansion busses <b>465</b>, such as USB, IEEE 1394 bus, ATA, SATA, PCI, PCIE, DVI, HDMI and other busses, couple to bus <b>415</b> to facilitate the connection of peripherals and devices to IHS <b>400</b>. A network interface adapter <b>405</b> couples to bus <b>415</b> to enable IHS <b>400</b> to connect by wires or wirelessly to a network and other information handling systems. IHS <b>400</b> may take the form of a desktop, server, portable, laptop, notebook, or other form factor computer or data processing system. IHS <b>400</b> may take other form factors such as a gaming device, a personal digital assistant (PDA), a portable telephone device, a communication device or other devices that include a processor and memory. IHS <b>400</b> is especially sensitive to energy consumption in the form of a portable, laptop, notebook, gaming device, PDA or any battery-powered device.

0057IHS <b>400</b> may include a computer program product on digital media <b>475</b> such as a CD, DVD or other media. In one embodiment, digital media <b>475</b> includes an application <b>482</b>. A user may load application <b>482</b> on nonvolatile storage <b>445</b> as application <b>482</b>′. Nonvolatile storage <b>445</b> may store an operating system <b>481</b>. When IHS <b>400</b> initializes, the IHS loads operating system <b>481</b> and application <b>485</b>′ into system memory <b>420</b> for execution as operating system <b>481</b>′ and application <b>482</b>″. Operating system <b>481</b>′ governs the operation of IHS <b>400</b>.

0058The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, blocks, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, blocks, operations, elements, components, and/or groups thereof.

0059The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. For example, those skilled in the art will appreciate that the logic sense (logic high (1), logic low (0)) of the apparatus and methods described herein may be reversed and still achieve equivalent results. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.