US20120249276A1

Integrated inductor device with high inductance, for example for use as an antenna in a radiofrequency identification system

Claim Score by NHIP

Abstract

An embodiment of integrated inductor device, comprising a plurality of modules overlaid to each other, each module including at least one coil of conducting material. The directly overlaid pairs of coils are coiled in opposite directions. The directly overlaid modules are mechanically coupled through first adhesive conductive regions and the coils of the directly overlaid modules are electrically coupled to each other through second adhesive conductive regions. The first and the second adhesive conductive regions coupling directly overlaid modules are formed in the same step of the process, are of the same material and are arranged at a same level.

US20120249276A1, drawing sheet 1 — Sheet 1 of 11

Term

5.6 yearsto projected expiry

Projected expiry 16 April 2032, counted from filing; an application has no term until it is granted.

31 claims: 5 independent, 26 dependent

20
An article, comprising:a first conductive coil that has an outer end and an inner end and that spirals in a direction from the outer end to the inner end;and a second conductive coil that is disposed over the first coil, has an outer end and an inner end, and spirals in the direction from the inner end to the outer end, one of the outer and inner ends of the second coil electrically coupled to a respective one of the outer and inner ends of the first coil.
32
A system, comprising:a first conductive coil that has an outer end and an inner end and that spirals in a direction from the outer end to the inner end;a second conductive coil that is disposed over the first coil, has an outer end and an inner end, and spirals in the direction from the inner end to the outer end, one of the outer and inner ends of the second coil electrically coupled to a respective one of the outer and inner ends of the first coil;and a circuit that is coupled to the ends of the first and second coils that are not electrically coupled to one another.
37
Broadest claimClaim Score 80, broad(NHIP)A method, comprising:causing a current to flow in a direction from one of an inner end and an outer end of a first winding to the other of the inner end and the outer end;causing the current to flow from the other of the inner end and outer end of the first winding to a respective one of an inner end and an outer end of a second winding;and causing the current to flow in the direction from the respective one of the inner end and the outer end of the second winding to the other of the inner end and the outer end of the second winding.
44
An article, comprising:a first group of at least one coil, each coil having an outer portion and an inner portion and spiraling in a first direction from the outer portion to the inner portion;and a second group of at least one coil interleaved with the at least one coil of the first group to form a stack of coils that is configured to allow a current to flow serially through the coils of the first and second groups in a same one of the first direction and a second direction, each coil of the second group having an outer portion and an inner portion and spiraling in the second direction from the outer portion to the inner portion.

Independent claims4

80 paragraphs in 6 sections, as filed

PRIORITY CLAIM

0001The instant application claims priority to Italian Patent Application No. TO2011A000295, filed Apr. 1, 2011, which application is incorporated herein by reference in its entirety.

TECHNICAL FIELD

0002An embodiment relates to an integrated inductor device with high inductance, for example for use as an antenna in a radiofrequency identification system.

BACKGROUND

0003The medical field sees an increasingly widespread use of devices based on MEMS resonators that can withstand difficult conditions and operate as radio frequency identification (RFID) memories, in which the resonators are activated by the magnetic field generated by the current flowing in an antenna.

0004For this purpose, the antenna should meet some requirements, such as having an inductance value on the order of microHenries (pH), a small size, and a low cost. It has already been suggested to make the antenna on a BGA/LGA (Ball Grid Array/Land Grid Array) substrate. These substrates are formed by a plurality of overlaid conductive tracks (generally of copper, each formed in a conductive layer), and insulated from each other by insulating material layers. Holes, referred to as “vias”, allow electric contact through different insulating layers of the substrate. The electric contact in the holes is obtained by the metallization of the inner surface of the holes, obtained by a process of electrochemical plating or by applying a conductive material layer and by screening and a subsequent high temperature baking. Another method to produce the electric contact through the holes consists in totally filling the latter with an adhesive charged with conductive particles by screening and baking, or by injection and baking and baking the conductive adhesive. The holes mutually couple the conductive tracks so as to form a plurality of conductive paths. In this case, the antenna for the memories or other RFID device may be produced on one of the main surfaces of the BGA/LGA substrate, for example as a miniaturized loop antenna, formed by a track of copper or other conducting material.

0005This implementation, however, allows achieving only low values of inductance (a few nanoHenries), while, as indicated above, the application as an antenna for a RFID system may require values of about three orders of magnitude higher.

SUMMARY

0006An embodiment is an integrated inductor device that overcomes the drawbacks of the prior art.

0007In an embodiment, an inductor device is formed by superimposing a plurality of substrates or modules having the same structure.

0008Furthermore, in an embodiment, for each substrate or module, each coil is associated to at least one first adhesive conductive region that achieves the mechanical connection with an adjacent substrate (module) and to at least one second adhesive conductive region that achieves the electric connection with the coil formed in the adjacent substrate (module) and the first and second adhesive conductive regions are made of the same material and are arranged at a same level.

0009In an embodiment, each module is made as a BGA/LGA substrate, including at most four metallization levels. In particular, by superimposing six modules of four metallization layers each, an overall inductance on the order of one μH can be obtained with a simple layout and a reduced area (for example, about 3.6 mm2). Adhesive conductive regions formed by conductive glue or solder paste formed on the mutually facing surfaces of the overlaid modules allow mechanical and electric coupling among the various modules, in a simple and effective manner.

0010As an alternative, each module is formed by a substrate carrying a coil made by applying conductive material. The same conductive layer forming the coil also forms electric contact regions and mechanical connection regions. After stacking a plurality of modules, the latter are glued by using the mechanical connection regions.

0011The stacking can occur at a board level, each board integrating a plurality of identical modules and the single devices being obtained by cutting overlaid boards, or at a single-module level, by gluing to a first board single devices formed in a second board, which has been previously cut, and then also cutting the first board.

BRIEF DESCRIPTION OF THE DRAWINGS

0012For a better understanding of the present disclosure, one or more embodiments thereof will now be disclosed as a non-limitative example only and with reference to the accompanying drawings, wherein:

0013<figref idref="DRAWINGS">FIG. 1</figref> is a cross-section of an embodiment of the present integrated inductor;

0014<figref idref="DRAWINGS">FIG. 2</figref> is an exploded perspective view of a part of the integrated inductor of <figref idref="DRAWINGS">FIG. 1</figref>;

0015<figref idref="DRAWINGS">FIGS. 3</figref>a-3d show the layout of the four layers forming an upper module of the integrated inductor of <figref idref="DRAWINGS">FIG. 1</figref>;

0016<figref idref="DRAWINGS">FIGS. 4</figref>a-4d show the layout of the four layers forming a first intermediate module of the integrated inductor of <figref idref="DRAWINGS">FIG. 1</figref>;

0017<figref idref="DRAWINGS">FIGS. 5</figref>a-5d show the layout of the four layers of a second intermediate module of the integrated inductor of <figref idref="DRAWINGS">FIG. 1</figref>;

0018<figref idref="DRAWINGS">FIGS. 6</figref>a-6d show the layout of the four layers of the bottom module of the integrated inductor of <figref idref="DRAWINGS">FIG. 1</figref>;

0019<figref idref="DRAWINGS">FIG. 7</figref> shows a board integrating a plurality of identical modules for the formation of a plurality of integrated inductors of the type shown in <figref idref="DRAWINGS">FIG. 1</figref>;

0020<figref idref="DRAWINGS">FIGS. 8 and 9</figref> are perspective views in two subsequent manufacturing steps of a first substrate, usable in a different embodiment of the present integrated inductor;

0021<figref idref="DRAWINGS">FIGS. 10 and 11</figref> are perspective views in two subsequent manufacturing steps of a second substrate, usable with the substrate of <figref idref="DRAWINGS">FIGS. 8 and 9</figref>;

0022<figref idref="DRAWINGS">FIG. 12</figref> shows an integrated inductor which can be obtained by alternately superimposing a plurality of substrates according to <figref idref="DRAWINGS">FIGS. 9 and 11</figref>;

0023<figref idref="DRAWINGS">FIG. 13</figref> shows a board integrating a plurality of substrates of the type shown in <figref idref="DRAWINGS">FIG. 8</figref>;

0024<figref idref="DRAWINGS">FIG. 14</figref> shows subsequent manufacturing steps of integrated inductors, according to an embodiment; and

0025<figref idref="DRAWINGS">FIG. 15</figref> shows the cross-section of a detail of a variant of the inductor of <figref idref="DRAWINGS">FIG. 12</figref>.

DETAILED DESCRIPTION

0026<figref idref="DRAWINGS">FIG. 1</figref> shows a first embodiment of an integrated inductor 1 formed by a plurality of overlaid modules 2-5 having a similar structure, each incorporating four coils 25 which are overlaid so as to have the center aligned along a single central axis A and to be mutually coupled. The directly overlaid coils are wound in opposite directions so that the current always flows in a single direction (clockwise or counterclockwise).

0027Hereinafter, for the sake of clarity, the current is assumed to flow counterclockwise in all coils and the connections are accordingly defined as “input” and “output” connections. But the direction of the current could be opposite, therefore reversing the role of the connections.

0028The plurality of modules 2-5 includes in this case six modules, including a first end module, typically an upper module 2, a second end module, typically a bottom module 5, two first intermediate modules 3 and two second intermediate modules 4, the first and the second intermediate modules 3, 4 being alternated. Modules 2-5 are manufactured according to the BGA technique, each having four metal layers, one for each coil, and differ only slightly in the layout.

0029In detail, each of the modules 2-5 is formed by a first insulating layer 10, a first metal layer 11, a second insulating layer 12, a second metal layer 13, a core layer 15, a third metal layer 17, a third insulating layer 18, a fourth metal layer 19, and a fourth insulating layer 20.

0030The first and the fourth insulating layer 10, 20 respectively forming the upper layer and the bottom layer of each module 2-5, are typically made as solder masks, i.e. of a non-conductive material that may be shaped by screening, for example of polymer material, such as, among others, AUS 308 material of Taiyo America, Inc.

0031The second and the third insulating layers 12 and 18 are so-called “prepreg” layers i.e. each formed by, for example, a BT laminate containing crossed glass fibres therein, which ensure rigidity and a reduced temperature expansion.

0032Core layer 15 is of an insulating material, typically plastic, for example a BT (Bismaleimide Triazine) or FR-4 or other material of printed circuits.

0033Metal layers 11, 13, 17, 19 are, for example, of copper with an upper, corrosion protecting layer, typically of nickel-gold, and are shaped so as to each form a respective coil 25 as well as pads for the connections, including at least, for each metal layer, an input pad 26 and an output pad 27 (in which the indication “input” and “output” refer to the current direction shown, as explained above, and are not limitative). Furthermore, first and fourth metal layers 11, 19 of all modules 2-4 also each form a connection pad 28 and the first metal layer 11 of upper module 2 forms an output terminal 29 (<figref idref="DRAWINGS">FIG. 3</figref>a). The electric connections, together with the conductive vias passing through different modules 2-4, are configured and arranged so as to allow current to flow in coils 25 always in the same direction, as disclosed hereinafter.

0034Coils 25 of metal layers 11, 13, 17 and 19 are each formed by a spiral, and the spirals of two overlaid layers are wound in opposite directions, but input pads 26A-26P are arranged alternatively near the edge and near the center of the integrated inductor 1. Therefore, coil 25 of first metal layer 11 of all modules 2-5 is wound in a counterclockwise direction from the outside and from its own input pad (input pad 26A, 26E, 26I and 26M, <figref idref="DRAWINGS">FIGS. 3</figref>a, 4a, 5a and 6a), coil 25 of second metal layer 13 is wound from the outside in a clockwise direction (corresponding to a counterclockwise direction from its own input pad 26B, 26F, 26J and 26N, <figref idref="DRAWINGS">FIGS. 3</figref>b, 4b, 5b and 6b), coil 25 of third metal layer 17 is wound in a counterclockwise direction from the outside and from its own input pad (input pad 26C, 26G, 26K and 26O, <figref idref="DRAWINGS">FIGS. 3</figref>c, 4c, 5c and 6c), and coil 25 of fourth metal layer 19 is wound from the outside in a clockwise direction (corresponding to a counterclockwise direction from its own input pad 26D, 26H, 26L and 26P, <figref idref="DRAWINGS">FIGS. 3</figref>d, 4d, 5d and 6d).

0035Output pads 27A-27P of modules 2-4 are arranged vertically aligned to input pads 26B-26P of the metal level immediately below, as may be noted easily from <figref idref="DRAWINGS">FIGS. 3</figref>a-5d. Accordingly, output pads 27A-27P are also arranged alternatively near the edge or near the center of integrated inductor 1.

0036Vice versa, connection pads 28 of all the metal layers 2-5 are overlaid. Furthermore, connection pad 28 of fourth metal layer 19 of bottom module 5 also forms an output pad of the bottom module 5.

0037Conductive vias 30-33 completely pass through each module 2-4, but vias 30-32 each couple reciprocally, in each module, a single output pad with the immediately underlying input pad, whereas vias 33 couple all the connection pads 28 to each other. Here, vias 30, 31 are arranged near the center of integrated inductor 1; vias 32-33 are arranged near the edge. In particular, as may be seen in <figref idref="DRAWINGS">FIG. 1</figref>, in upper module 2, conductive via 30 passes through and electrically couples output pad 27A to input pad 26B (both in a central position); conductive via 31 passes through and electrically couples output pad 27C to input pad 26D. As may be seen in <figref idref="DRAWINGS">FIGS. 3</figref>b, 3c, via 32 (not visible in <figref idref="DRAWINGS">FIG. 1</figref> because hidden by via 33) passes through output pad 27B of second metal level 13 of upper module 2 and couples the latter to input pad 26C of underlying metal level 17; similarly, vias 30-32 of modules 5-4 respectively couple the output pads to the directly underlying input pads, as may be seen in <figref idref="DRAWINGS">FIGS. 4</figref>a-6d.

0038Output pads 27D, 27H and 27L of fourth metal level 19 of modules 2-4 are instead coupled to input pads 26E, 26I and 26M of an underlying level (first metal level 13 of modules 3-5) by first electric connection regions 35, represented by a shaded line in <figref idref="DRAWINGS">FIGS. 3</figref>a-6d.

0039Similarly, vias 33 of modules 2-5 are reciprocally coupled to each other by second electric connection regions 36; mechanical connection regions 37 mechanically couple modules 2-5 to each other. Mechanical connection regions 37 extend peripherally near the edges of relative modules 2-5 on both sides thereof, except for the sides intended to form the upper surface and the lower surface of integrated inductor 1.

0040First and second electric connection regions 35, 36 and mechanical connection regions 37 form adhesive conductive regions extending, for each upper and lower surface of modules 2-5, horizontally aligned (on a same level) in corresponding openings 39 of the first and fourth insulating layers 10, 20 of modules 2-5, except for, as indicated, mechanical connection regions 37 of the upper and lower surfaces of inductor 1 and are formed by the same material, applied approximately simultaneously, for example, a conductive glue (containing, for example, an Ag filler) or a tin-silver, tin-silver-copper, or other lead-free metal welding alloy.

0041Integrated inductor 1 is manufactured as follows according to an embodiment.

0042First, a plurality of boards 40 is manufactured (<figref idref="DRAWINGS">FIG. 7</figref> shows a part thereof). Each board is formed by a plurality of approximately identical modules 2, 3, 4, or 5. For example, <figref idref="DRAWINGS">FIG. 7</figref> shows a plurality of upper modules 2. Boards 40 are manufactured according to known technologies, so that each module 2-5 has the disclosed configuration. Therefore, a conductive adhesive or a lead-free paste is applied by screening or dispensing on the side areas of first and fourth insulating layers 10, 20 and over output pads 27 and vias 33 to form regions 35-37; therefore, boards 40 relative to the various modules are overlaid and reciprocally glued. In particular, if the adhesive conductive vias 35-37 are made by conductive glues, before superimposition, boards 40 are subjected to a thermal treatment at a polymerization-initiation temperature lower than the glass-transition temperature of the glue (depending on the type of glue), in order to obtain a sufficient adhesion of adhesive conductive regions 35-37 and to maintain the overlaid modules in position. Once the boards are overlaid, the polymerization of the adhesive is completed in a static oven or a tunnel depending on the features of the adhesive. Vice versa, if adhesive conductive regions 35-37 are made by a solder paste, a reflow process is performed in standard conditions for lead-free solder pastes with a peak temperature of 260° C.

0043Therefore, if provided by the application, electronic components are bonded at each upper module; finally the composite boards obtained thereby are cut to obtain the single integrated switches 1.

0044The alignment in the plane of the boards is performed by optical positioning machines, which take the first board as a reference using references (designated “fiducials”) made on the first board for metal plating, screening, marking, cutting, or boring. Thus, the effect of the sum of tolerances is avoided, thereby making the positioning tolerance independent of the number of stacked boards. In cases where the inductances are high enough and the number of overlaid boards is low, and thus the alignment error has a reduced influence on the overall inductance of the module, the superimposition may be performed by a support with metal plugs that pass through centering holes made on the boards. The supports are then used for baking in static or tunnel ovens of the stacked boards and then removed before cutting.

0045In an embodiment, core layer 15 can have a thickness in the range approximately between 60 and 110 μm, for example approximately 100 μm, first and fourth insulating layers 10, 20, of solder mask, can have a thickness of about 20 μm, second and third insulating layers 12 and 18, of prepreg, can have an overall thickness in the range approximately between 30 and 40 μm, and metal layers 11, 13, 17 and 19 can have a thickness of about 17 μm for an overall thickness of each module 2-5 generally variable approximately between 220 (in case of thin device) and 300 μm (in case of standard device).

0046<figref idref="DRAWINGS">FIGS. 8-13</figref>, 15 relate to a different embodiment of the present integrated inductor, wherein each module includes a single substrate (drilled to make the connections), on which a conductive track that forms a coil is made (for example by screening, dispensing, or printing).

0047Also in this case, the processing occurs typically at a board level, each board forming a plurality of substrates that, after being superimposed and glued, are cut in a final step, to obtain the single inductors. However, for the sake of simplicity, the manufacturing steps are disclosed at a single substrate level.

0048<figref idref="DRAWINGS">FIG. 8</figref> shows a first substrate 50 provided with a first and a second surface 50A, 50B. As indicated above, the first substrate 50 may be one of a plurality of modules forming a board 75, as shown in <figref idref="DRAWINGS">FIG. 13</figref>.

0049The first substrate 50 can be of any insulating material such as BT (Bismaleidetriazine) or epoxy resin charged with glass fibers, injected plastic, PET, polycarbonate, or other types of plastic material, ceramics, glass, paper, cardboard, and the like. As an alternative, the first substrate 50 can be of a ferromagnetic material with the two opposite faces coated with a dielectric material layer as disclosed more in detail hereinafter. Furthermore, biocompatible or medical materials can be selected.

0050Initially, the first substrate 50 is drilled to form two through holes 51 and 52 extending between surfaces 50A, 50B. In <figref idref="DRAWINGS">FIG. 8</figref>, first through hole 51 is central and second through hole 52 is arranged near the edge of first substrate 50. Furthermore, in the example shown, through holes 51 and 52 are metallized. For a ferromagnetic substrate, the holes are at first coated with a dielectric layer, typically an epoxy or glass paste, for example by screening and then baking, and then filled with an adhesive conductive material or with a solder paste.

0051Hereinafter, in <figref idref="DRAWINGS">FIG. 9</figref>, a conductive material is printed or dispensed on first surface 50A of first substrate 50 so as to approximately simultaneously form a coil 55 and adhesive conductive regions forming both electric and mechanical connections. In an embodiment, a conductive glue or a solder paste is applied, for example by screening, on the upper surface of first substrate 50. The conductive material fills holes 51 and 52 (where it forms a first and a second via 53 and 54), forms a spiral (forming coil 55), a first contact region 56 and a peripheral region 59. Coil 55 extends between first via 53 (and therefore first through hole 51) and first contact region 56. First contact region 56 is made near the edge of first substrate 50, near but distinct from the second via 54 and the peripheral region 59 surrounds, for example completely, the first substrate 50.

0052Peripheral region 59 is similar to mechanical connection regions 37 of the embodiments of <figref idref="DRAWINGS">FIGS. 1-7</figref> and has the aim of allowing the mechanical connection between first substrate 50 and a second overlaid substrate, as explained hereinafter.

0053The conductive material may be an adhesive material charged with conductive particles, or a lead-free solder paste formed by microparticles amalgamated with fluxes so as to obtain a pasty consistency, or a conductive ink. The adhesive materials are subjected to partial capture to control the extension thereof, thus avoiding short-circuiting between the coils and maintaining the adhesiveness thereof. For this purpose, spacers can be used. For example, when the inductance is dispensed, the spacers may be formed on the substrate, by previously dispensing adhesive cylinders of the same kind used for the manufacture of the inductance, or of a different kind, and by baking (for about an hour at a temperature of about 150° C.) so as to ensure a rigid support.

0054A second substrate 60 (shown in <figref idref="DRAWINGS">FIG. 10</figref>) is manufactured independently. Second substrate 60 is similar to first substrate 50, except for the position of the through-holes. Accordingly, the material of second substrate 60 may be any, possibly even another material with respect to first substrate 50, and second substrate 60 has first and second surfaces 60A, 60B.

0055In a processing step which occurs approximately simultaneously, before or after the processing steps of first substrate 50, second substrate 60 is drilled so as to form a third through hole 61 and a fourth through hole 62. Here, both through holes 61, 62 are formed near the edge of second substrate 60, with third through hole 61 in a position such as to be aligned, after the superimposition of substrates 50, 60, to first conductive region 56 of first substrate 50, and fourth through hole 62 aligned (after the superimposition of the substrates) to the second through hole 52. Also in this case, through holes 61, 62 can be metallized. Furthermore (not shown), second substrate 60 can be part of a respective board (not shown), similar to board 75 of <figref idref="DRAWINGS">FIG. 13</figref>.

0056Subsequently (<figref idref="DRAWINGS">FIG. 11</figref>), second substrate 60 is printed to form a respective coil 65, a second contact region 66, and an own peripheral region 59. This step is carried out as already disclosed for first substrate 50 by applying a conductive glue or a solder paste, and also leads to the filling of fourth and fifth hole 61, 62. Thereby, a third and fourth via 63 and 64 form in through holes 61, 62, and coil 65 extends between third via 63 and second contact region 66.

0057Even in this case, coil 65 of second substrate 60 is wound in an opposite direction with respect to coil 55 of first substrate 50. Indeed, in the embodiment which is shown, coil 55 of first substrate 50 extends counterclockwise from the outside (first connection region 56) inwards (first via 53), while coil 65 of second substrate 60 extends clockwise from the outside (third through via 63) inwards (third connection region 66), so that the current always flows in the same direction, as explained hereinafter.

0058Therefore, second substrate 60 is superimposed over first substrate 50, with surface 60B in contact with surface 50A, so that third via 63 is overlaid and electrically contacts first contact region 56 and fourth via 64 is overlaid and electrically contacts second via 54. Subsequently, another first substrate 50 is superimposed over second substrate 60 so that first via 53 is overlaid vertically to third connection region 66 and second via 54 is overlaid vertically to fourth via 64. Also in this case, the process of superimposition may be performed using fiducials (not shown), always referring each substrate 50, 60 added on top, to the bottom substrate.

0059The process continues with the alternated superimposition of first and second substrates 50, 60, to obtain an integrated inductor 70, shown in <figref idref="DRAWINGS">FIG. 12</figref> and formed by a stack of substrates 50, 60, for example 10.

0060During superimposition, the bottom substrate of the stack, having the configuration of second substrate 60 of <figref idref="DRAWINGS">FIG. 11</figref>, may not be preventively drilled and have, instead of third and fourth vias 63, 64, corresponding contact regions 67, 68 (<figref idref="DRAWINGS">FIG. 12</figref>) coupled to one another. Furthermore, the top substrate in the stack has the configuration of first substrate 50 of <figref idref="DRAWINGS">FIG. 9</figref>, and may not have peripheral region 59. In this case, during the application of the conductive glue or solder paste, first connection region 56 and the top portion of third via 54 can be shaped so as to form connection pads for the outer connection.

0061Optionally, before being stacked, substrates 50 and 60 can be subjected to a heating step in an oven, so as to increase the consistency of the adhesive conductive regions, in particular of peripheral regions 59. For this purpose, the heating is performed at a temperature lower than the polymerization temperature, for example lower than about 100° C. for a time of about 10 minutes.

0062Finally, at the end of the alternated superimposition of substrates 50 and 60, these are reciprocally glued, arranging the stack of substrates 50, 60 in an oven at a temperature in the range approximately between 120-170° C., typically about 150° C., for about 1-2 hours, so as to obtain the polymerization of the conductive glue or solder paste and, therefore, the gluing of peripheral regions 59 of each substrate 50, 60 to the overlaying substrate 60, 50, as well as of first and second contact regions 56, 66 to the respective overlaying and underlying metallized vias 63, 53.

0063When substrates 50, 60 are each part of a respective board including a plurality of substrates 50 or 60, after gluing the stack is singulated to form single inductors 70.

0064Thereby, in the integrated inductor 70 of <figref idref="DRAWINGS">FIG. 12</figref>, in which first contact region 56 represents a current input and the end of second via 54 represents a current output, the current always flows in a counterclockwise direction, entering the first contact region 56 of upper substrate 50 and flowing through first coil 55 up to first via 53, which is in electrical contact with the second contact region 66 of second coil 65 (<figref idref="DRAWINGS">FIG. 11</figref>) of underlying substrate 60. Therefore the current also flows through second coil 65 in a counterclockwise direction up to third contact via 63 and from here reaches first contact region 56 of a first underlying substrate 50. After flowing through all the coils in a counterclockwise direction, the current reaches contact regions 66, 67 and then passes through second and fourth vias 54, 64, which are overlaid to one another, up to second via 54 of the overlaid substrate, which represents an output terminal of integrated inductor 70.

0065<figref idref="DRAWINGS">FIG. 15</figref> shows a detail of a variant of the integrated inductor of <figref idref="DRAWINGS">FIG. 12</figref>, using substrates 150, 160 of a ferromagnetic material, covered by insulating layers 170 on the two faces. A coil 165 is formed on one of the faces (for example the top one) of substrates 150, 160. As already indicated, vias 161 (corresponding to vias 53-54, 63-64) are insulated from corresponding substrate 150, 160 by an insulation 162. Insulating layers 170 can be screened and peripheral regions 159 (made approximately simultaneously to coils 165 and to contact regions which are not shown and are similar to contact regions 56, 66) allow mutual gluing of substrates 150, 160. In this case, a further increase of the overall value of the inductance, as well as an increase in the mechanical resistance of the module, may be obtained.

0066<figref idref="DRAWINGS">FIG. 14</figref> shows a different manufacturing process. In this case, a first board 80 and a second board 81 each integrating coils in an opposite direction are manufactured independently. Boards 80, 81 may be subjected to the same manufacturing steps disclosed above to obtain modules 2-5 of <figref idref="DRAWINGS">FIGS. 1-7</figref>, for example modules 2 and 5, or substrates 50, 60 of <figref idref="DRAWINGS">FIGS. 9 and 11</figref>. Therefore, according to the known technique of “pick and place”, first panel 80 is cut, so as to form a plurality of single elements 83 which are singularly taken and arranged over corresponding elements of second board 81, on which (by dispensing or screening) a conductive adhesive or a solder paste has been preventively applied and which has been prebaked (in the case of conductive adhesive). After all single elements 83 have been arranged, these are glued to board 81, for example by polymerization of peripheral region 59.

0067Before gluing single elements 83, different boards can also be superimposed; or different modules 83 can be superimposed to each other on board 81.

0068An embodiment of the integrated inductor and an embodiment of the corresponding manufacturing process, as disclosed herein, have several advantages.

0069In particular, an embodiment of the present integrated inductor can be made of the desired value, even having a magnitude on the order of one pH, with a simple layout of the single layers and with limited manufacturing costs. The layers of the dielectric can be made thin, therefore helping the coupling effect among the various overlaid coils.

0070The manufacture of the substrates of ferromagnetic material insulated by dielectrics allows to further increase the value of the overall inductance of the module.

0071The adhesive conductive regions among different overlaid modules may be formed in the same manufacturing step and therefore may be of the same material and may be arranged on the same level (horizontal alignment). This provides a high mechanical and electrical resistance of the connections, as well as a simple manufacturing that requires limited costs.

0072An embodiment of <figref idref="DRAWINGS">FIGS. 8-13</figref> is advantageously usable in case the substrate is made of a non-conventional material, such as glass or plastic, if there are particular requirements, such as light mechanical flexibility.

0073It is finally apparent that changes and variations can be made to the devices and manufacturing processes disclosed and shown herein without departing from the scope of the disclosure.

0074For example, as indicated, substrates 50, 60 of the embodiment of <figref idref="DRAWINGS">FIGS. 8-13</figref> can be made of paper or cardboard. In this case the coils and the adhesive regions can be made of conductive ink, such as for example an ink made by charging an appropriate solvent with carbon or silver microparticles to an extent as to obtain a viscosity suitable for deposition by dispensing or screening.

0075The through holes 51, 52 and 61, 62 may also be preventively metallized when vias 53, 54, 63, 64, 161 are made.

0076In case both the input connection and the output connection are not to be on the same upper side of the integrated inductor, vias 33 or 54, 64 of the output connection of the current can be avoided.

0077The application of the conductive adhesive or of the solder paste in the through holes for forming the electrical connections through the substrates can take place approximately simultaneously to or before the manufacture of the inductance, and as a function of the ratio between the diameter of the hole and the thickness of the substrate (“aspect ratio”).

0078The metal layers 11, 13, 17, 19 of the embodiment of <figref idref="DRAWINGS">FIGS. 1-7</figref> can be replaced by conductive layers, for example layers of an organic compound.

0079Furthermore, contact regions 35, 36; 56, 66 can be formed by portions of respective coils 55, 65, 165, without being distinct therefrom.

0080From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.

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Citations
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2 members in 1 office

This recordMember, by publication datePriority claim

Priority claims2

Priority claims
Document	Office	Kind	Date
TO2011A000295	Italy	–	2011-04-01
TO20110295	Italy	A	2011-04-01

Members2

Family members, oldest first
Document	Office	Kind
US2012249276A1	United States of America	A1	2012-10-04
US9460841B2	United States of America	B2	2016-10-04

90 transactions on the USPTO file

Allowed after 3 non-final rejections, 2 final rejections and 2 RCEs.

Non-final rejections: 3
Final rejections: 2
RCEs: 2
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2024-03-21	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2020-03-17	Payment of Maintenance Fee, 4th Year, Large EntityM1551	M1551
2016-10-04	Recordation of Patent Grant MailedPGM/	PGM/
2016-10-04	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2016-09-15	Email NotificationEML_NTR	EML_NTR
2016-09-14	Issue Notification MailedAllowedWPIR	WPIR
2016-08-31	Dispatch to FDCD1935	D1935
2016-08-31	Application Is Considered Ready for IssuePILS	PILS
2016-08-30	Response to Reasons for AllowanceREAS	REAS
2016-08-30	Issue Fee Payment VerifiedN084	N084
2016-08-30	Issue Fee Payment ReceivedIFEE	IFEE
2016-07-18	Filing Receipt - CorrectedFLRCPT.C	FLRCPT.C
2016-07-08	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2016-07-07	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2016-06-27	Reasons for AllowanceEX.R	EX.R
2016-04-01	Date Forwarded to ExaminerFWDX	FWDX
2016-03-30	Response after Non-Final ActionA...	A...
2015-12-30	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2015-12-27	Non-Final RejectionNon-final rejectionCTNF	CTNF
2015-11-17	Date Forwarded to ExaminerFWDX	FWDX
2015-11-17	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2015-11-16	Request for Continued Examination (RCE)RCEX	RCEX
2015-11-16	Request for Extension of Time - GrantedXT/G	XT/G
2015-11-16	Request for Extension of Time - GrantedXT/G	XT/G
2015-11-16	Workflow - Request for RCE - BeginBRCE	BRCE
2015-10-06	Mail Advisory Action (PTOL - 303)MCTAV	MCTAV
2015-10-01	After Final Consideration Program Additional Consideration and/or updated searchAFAC	AFAC
2015-10-01	Advisory Action (PTOL-303)CTAV	CTAV
2015-09-29	Interview Summary - Examiner Initiated - TelephonicEXET	EXET
2015-09-20	Date Forwarded to ExaminerFWDX	FWDX
2015-09-16	PILOT- Request for After Final Consideration ProgramRAFC	RAFC
2015-09-16	Response after Final ActionA.NE	A.NE
2015-07-16	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2015-06-24	Final RejectionFinal rejectionCTFR	CTFR
2015-02-25	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2015-02-20	Date Forwarded to ExaminerFWDX	FWDX
2015-02-17	Response after Non-Final ActionA...	A...
2015-02-17	Request for Extension of Time - GrantedXT/G	XT/G
2014-10-15	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2014-10-10	Non-Final RejectionNon-final rejectionCTNF	CTNF
2014-08-11	Correspondence Address ChangeC.ADB	C.ADB
2014-04-26	Date Forwarded to ExaminerFWDX	FWDX
2014-04-26	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2014-04-24	Request for Continued Examination (RCE)RCEX	RCEX
2014-04-24	Workflow - Request for RCE - BeginBRCE	BRCE
2014-04-17	Email NotificationEML_NTR	EML_NTR
2014-04-17	Mail Advisory Action (PTOL - 303)MCTAV	MCTAV
2014-04-11	Advisory Action (PTOL-303)CTAV	CTAV
2014-04-10	Interview Summary - Applicant Initiated - TelephonicEXAT	EXAT
2014-04-10	Interview Summary- Applicant InitiatedEXIA	EXIA
2014-04-03	Date Forwarded to ExaminerFWDX	FWDX
2014-03-31	PILOT- Request for After Final Consideration ProgramRAFC	RAFC
2014-03-31	Response after Final ActionA.NE	A.NE
2014-01-29	Electronic ReviewELC_RVW	ELC_RVW
2014-01-29	Email NotificationEML_NTF	EML_NTF
2014-01-29	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2014-01-23	Final RejectionFinal rejectionCTFR	CTFR
2013-10-30	Correspondence Address ChangeC.ADB	C.ADB
2013-10-23	Date Forwarded to ExaminerFWDX	FWDX
2013-10-21	Response after Non-Final ActionA...	A...
2013-10-21	Request for Extension of Time - GrantedXT/G	XT/G
2013-07-19	Electronic ReviewELC_RVW	ELC_RVW
2013-07-18	Email NotificationEML_NTF	EML_NTF
2013-07-18	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2013-07-12	Non-Final RejectionNon-final rejectionCTNF	CTNF
2013-05-10	Date Forwarded to ExaminerFWDX	FWDX
2013-05-09	Response to Election / Restriction FiledELC.	ELC.
2013-05-08	Electronic ReviewELC_RVW	ELC_RVW
2013-05-08	Email NotificationEML_NTF	EML_NTF
2013-05-08	Mail Restriction RequirementMCTRS	MCTRS
2013-05-03	Restriction/Election RequirementCTRS	CTRS
2012-10-11	Case Docketed to Examiner in GAUDOCK	DOCK
2012-10-04	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2012-08-31	Request for Foreign Priority (Priority Papers May Be Included)RQPR	RQPR
2012-08-06	Case Docketed to Examiner in GAUDOCK	DOCK
2012-07-26	Application Dispatched from OIPEOIPE	OIPE
2012-06-28	Application Is Now CompleteCOMP	COMP
2012-06-28	Sent to Classification ContractorPGPC	PGPC
2012-06-28	Filing Receipt - UpdatedFLRCPT.U	FLRCPT.U
2012-06-22	Payment of additional filing fee/PreexamFLFEE	FLFEE
2012-06-22	A statement by one or more inventors satisfying the requirement under 35 USC 115, Oath of the ApplicOATHDECL	OATHDECL
2012-04-23	Filing ReceiptFLRCPT.O	FLRCPT.O
2012-04-23	Notice Mailed--Application Incomplete--Filing Date AssignedINCD	INCD
2012-04-06	Cleared by OIPE CSRL194	L194
2012-04-02	Information Disclosure Statement consideredIDSC	IDSC
2012-04-02	Electronic Information Disclosure StatementEIDS.	EIDS.
2012-04-02	Preliminary AmendmentA.PE	A.PE
2012-04-02	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-04-02	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2012-04-02	Initial Exam Team nnIEXX	IEXX

4 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2024-03-21	Maintenance fee paymentMAFP	MAFP
2020-03-17	Maintenance fee paymentMAFP	MAFP
2016-09-14	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2012-06-22	AssignmentAS	AS