Differential output buffer having mixing and output stages

0001This application claims benefit of Japanese Application No. JP-A-2011-65733. The disclosure of the prior application is hereby incorporated by reference in its entirety.

BACKGROUND

0002This disclosure relates to differential output buffers that output emphasized differential output signal in which transitions in the differential data signal are emphasized.

0003Communication systems that transmit and receive differential data signals are widely used. A pre-emphasis technique is used in transmitting and receiving differential data signals in order to compensate attenuations of high-frequency signals during the transmission in wirings or the like. The pre-emphasis is a technique to emphasize the amplitude of signals at rising and falling edges at the transmitting side in order to compensate attenuation of high-frequency signals at the receiving side.

0004In the pre-emphasis technique, it is required to variably adjust the emphasis amount at the rising and falling edges depending on the characteristics of the transmission paths. It is also required to emphasize the signal in multiple steps in time with varying levels. For example, the emphasis amount may be maximized immediately after the rising and falling edges, slightly decreased thereafter, and then further decreased. For example, 10G-K specification for transmitting up to 1 meter length on printed circuit boards, which is one of IEEE 802.3 communication specifications, requires the emphasis in up to three steps.

0005US Patent Application No. 2008-0218222 (Patent document 1) proposes a technique to vary the emphasis level in multiple steps and to continue the emphasis in multiple steps in time with varying levels. Patent document 1 discloses a differential output buffer including a pre-driver stage and an output driver stage. The pre-driver stage includes a first differential pair that performs a current subtraction. The output driver stage includes a second differential pair and receives a second differential data signal from the pre-driver stage and outputs an output signal to a transmission line.

0006The pre-driver stage can generate signals that accurately represent the emphasis levels. The output driver stage receives differential signals generated by the pre-driver stage at the gates of transistors of the second differential pair. However, the output driver stage cannot always generate accurately emphasized output signals. That is, the output driver stage has a relatively high gain when the amplitude of the differential signal input to the gates of the transistors in the second differential pair is small. When the amplitude of the input differential signal increases, however, the output driver stage saturates and its gain decreases. As a result, the amplitude of the output signal cannot be accurately controlled by the amplitude of the signal input from the pre-driver stage. Accordingly, it is impossible to realize emphasis levels represented by the signals generated by the pre-driver stage.

0007As explained above, the emphasis technique requires a function to control the emphasis amounts in multiple levels and also requires an accurate control of the emphasis levels.

SUMMARY

0008It would be advantageous to provide differential output drivers that can accurately control the emphasis amounts in multiple steps without increasing output capacitance and chip area.

0009Aspects of this disclosure provide a differential output buffer that includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal, which is the differential data signal delayed by a delay period and inverted, to generate a mixed differential data signal. The output stage includes a first and a second output stage current source and a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled and supplied with an output stage operating current from corresponding one of the output stage current sources. Gates of the transistors in the first output stage differential pair are supplied with the differential data signal and gates of the transistors in the second output stage differential pair are supplied with the mixed differential data signal. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes from which an emphasized differential data signal is output. Further, the mixing stage includes a mixing ratio setting circuit that sets a mixing ratio between the differential data signal and the inverted delayed differential data signal to one of 1:0, 1:1, and 0:1.

0010In an example, the mixing circuit may include a first and a second mixing stage current source and a first and a second mixing stage differential pair of transistors. Sources of the transistors in each of the mixing stage differential pairs may be commonly coupled and supplied with a mixing stage operating current from corresponding one of the mixing stage current sources. Gates of the transistors in the first mixing stage differential pair may be supplied with the differential data signal and gates of the transistors in the second mixing stage differential pair may be supplied with the inverted delayed differential data signal. Drains of corresponding ones of the transistors in the first and second mixing stage differential pairs may be commonly connected to respective mixing stage load resistors to form mixing stage output nodes from which the mixed differential data signal is output. Further, the mixing ratio setting circuit may set the mixing ratio by one of (1) enabling or disabling to supply the mixing stage operating current to each of the first and second mixing stage differential pairs; and (2) enabling or disabling to supply one of the differential data signal and the inverted delayed differential data signal to the gates of the transistors in each of the first and second mixing stage differential pairs.

0011Further, each of the first and second mixing stage current sources may supply a first mixing stage operating current and a second mixing stage operating current, which is twice the first mixing stage operating current, and the mixing ratio setting circuit may set the mixing ratio to (1) 1:1 by enabling each of the first and second mixing stage current sources to supply the first mixing stage operating current to corresponding one of the first and second mixing stage differential pairs; and (2) one of 1:0 and 0:1 by enabling one of, and disabling the other of, the first and second mixing stage current sources to supply the second mixing stage operating current to corresponding one of the first and second mixing stage differential pairs.

0012In an embodiment, the mixing circuit includes a first mixing circuit that generates a first mixed differential data signal by mixing the differential data signal and the inverted delayed differential data signal with a first mixing ratio and a second mixing circuit that generates a second mixed differential data signal by mixing the differential data signal and the inverted delayed differential data signal with a second mixing ratio. The second output stage current source may include a first and a second emphasizing current source, and the second output stage differential pair may include a first and a second emphasizing differential pair of transistors. Sources of the transistors in each of the emphasizing differential pairs may be commonly coupled and supplied with an emphasizing current from corresponding one of the emphasizing current sources, the emphasizing currents supplied from the first and second emphasizing current sources are different with each other. Gates of the transistors in the first emphasizing differential pair may be supplied with the first mixed differential data signal and gates of the transistors in the second emphasizing differential pair may be supplied with the second mixed differential data signal. Further, the mixing ratio setting circuit may set the mixing ratio of each of the first and second mixing ratios to one of 1:0, 1:1, and 0:1.

0013In another embodiment, the inverted delayed differential data signal may include an inverted first-tap delayed differential data signal, which is the differential data signal delayed by a first delay period and inverted, and an inverted second-tap delayed differential signal, which is the differential data signal delayed by a second delay period, different from the first delay period, and inverted. The mixing circuit may include a first mixing circuit that generates a first mixed differential data signal by mixing the differential data signal and the inverted first-tap delayed differential data signal with a first mixing ratio, and a second mixing circuit that generates a second mixed differential data signal by mixing the differential data signal and the inverted second-tap delayed differential data signal with a second mixing ratio. The second output stage current source may include a first and a second emphasizing current source, and the second output stage differential pair may include a first and a second emphasizing differential pair of transistors. Sources of the transistors in each of the emphasizing differential pairs may be commonly coupled and supplied with an emphasizing current from corresponding one of the emphasizing current sources. Gates of the transistors in the first emphasizing differential pair may be supplied with the first mixed differential data signal and gates of the transistors in the second emphasizing differential pair may be supplied with the second mixed differential data signal. Further, the mixing ratio setting circuit may set each of the first and second mixing ratios to one of 1:0, 1:1, and 0:1.

0014In an example, the inverted delayed differential data signal may include an inverted first-tap delayed differential data signal, which is the differential data signal delayed by a first delay period and inverted, and an inverted second-tap delayed differential signal, which is the differential data signal delayed by a second delay period, different from the first delay period, and inverted. The mixing circuit may generate the mixed differential data signal by mixing the differential data signal, the inverted first-tap delayed differential data signal, and the inverted second-tap delayed differential data signal. Further, the mixing ratio setting circuit may set a mixing ratio between the differential data signal, the inverted first-tap delayed differential data signal, and the inverted second-tap delayed differential data signal to one of 1:0:0, 1:1:0, 1:0:1, 0:1:0, 0:0:1, and 0:1:1.

0015Another aspect of this disclosure provides a method of controlling an emphasis level of an emphasized differential data signal. The method includes providing an output stage including a first and a second output stage current source and a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled and supplied with an output stage operating current from corresponding one of the output stage current sources, and drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes. The method further includes mixing a differential data signal and an inverted delayed differential data signal with a mixing ratio to generate a mixed differential data signal, inputting the differential data signal to gates of the transistors in the first output stage differential pair and the mixed differential data signal to gates of the transistors in the second output stage differential pair, and outputting the emphasized differential data signal from the output nodes. Furthermore, the method includes controlling the emphasis level of the emphasized differential data signal by setting the mixing ratio to one of 1:0, 1:1, and 0:1.

0016Still another aspect of this disclosure provides a method of designing a differential output buffer that includes designing a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal with a mixing ratio to generate a mixed differential data signal. The output stage includes a first and a second output stage current source and a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled and supplied with an output stage operating current from corresponding one of the output stage current sources, gates of the transistors in the first output stage differential pair are supplied with the differential data signal and gates of the transistors in the second output stage differential pair are supplied with the mixed differential data signal, and drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes from which an emphasized differential data signal is output. The designing of the output stage includes determining dimensions of the transistors in the first and second output stage differential pairs such that (1) a sum of the dimensions of the transistors in the first and second output stage differential pairs is capable of transmitting the emphasized differential data signal through a transmission line, and (2) a combination of the dimensions of the transistors in the first and second output stage differential pairs enables to realize required emphasis levels of the emphasized differential data signal by setting the mixing ratio to 1:0, 1:1, and 0:1.

BRIEF DESCRIPTION OF THE DRAWINGS

0017Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

0018<figref idref="DRAWINGS">FIG. 1</figref> shows a circuit diagram of a first exemplary differential output buffer;

0019<figref idref="DRAWINGS">FIG. 2</figref> shows a circuit diagram of an exemplary mixing circuit in the first exemplary differential output buffer shown in <figref idref="DRAWINGS">FIG. 1</figref>;

0020<figref idref="DRAWINGS">FIG. 3</figref> shows a circuit diagram of a second exemplary differential output buffer;

0021<figref idref="DRAWINGS">FIG. 4</figref> shows a circuit diagram of a third exemplary differential output buffer;

0022<figref idref="DRAWINGS">FIG. 5</figref> shows a circuit diagram of a fourth exemplary differential output buffer; and

0023<figref idref="DRAWINGS">FIG. 6</figref> shows a circuit diagram of a second exemplary mixing circuit in the fourth exemplary differential output buffer shown in <figref idref="DRAWINGS">FIG. 5</figref>.

DETAILED DESCRIPTION OF EMBODIMENTS

0024<figref idref="DRAWINGS">FIG. 1</figref> is a circuit diagram of a first exemplary differential output buffer according to this disclosure. The exemplary differential output buffer <b>100</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref> outputs emphasized differential signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bin which transitions in the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bare emphasized.

0025The differential output buffer <b>100</b>A includes a mixing stage <b>10</b>A and an output stage <b>20</b>A. The mixing stage <b>10</b>A generates mixed differential data signal by mixing differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band inverted delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_B. The inverted delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_Bis the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bthat is delayed by one tap and inverted. Here, “tap” is a unit of delay period. The differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bmay be delayed by using, for example, flip-flops that hold and output the signal in synchronous with a clock signal.

0026The mixing stage <b>10</b>A includes a first buffer <b>11</b> and a mixing circuit <b>12</b>. The buffer <b>11</b> receives the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band output differential data signal V_A1and V_A2, which has the same logic as the differential data signal V_INand V_IN_{<sub2>—</sub2>}_B. The buffer <b>11</b> may be omitted but preferably be provided to adjust the timing of the differential data signal V_A1and V_A2with the timing of the mixed differential data signal V_B1and V_B2, which is output from the mixing circuit <b>12</b>.

0027The mixing circuit <b>12</b> further includes a second buffer <b>12</b><i>a </i>and a third buffer <b>12</b><i>b. </i>The second buffer <b>12</b><i>a </i>receives the differential data signals V_INand V_IN_{<sub2>—</sub2>}_Band the third buffer <b>12</b><i>b </i>receives delayed differential data signals EV_INand EV_IN_{<sub2>—</sub2>}_B, which is the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bdelayed by one tap. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the inverting output terminal, which is marked by a circuit, of the third buffer <b>12</b><i>b </i>and the non-inverting output terminal, which is not marked by a circle, of the second buffer <b>12</b><i>a </i>are coupled to form a first output terminal that outputs the output signal V_B1. While, the inverting output terminal, which is marked by a circuit, of the second buffer <b>12</b><i>a </i>and the non-inverting output terminal, which is not marked by a circle, of the third buffer <b>12</b><i>b </i>are coupled to form a second output terminal that outputs the output signal V_B2.

0028Accordingly, the mixing circuit <b>12</b> mixes the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band inverted signal of the delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_Bby inputting the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bto the second buffer <b>12</b><i>a </i>and the delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_Bto the third buffer <b>12</b><i>b. </i>That is, the mixing circuit <b>12</b> mixes the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INto generate the mixed differential data signal V_B1and V_B2. Here, using differential buffers <b>12</b><i>a </i>and <b>12</b><i>b </i>having output terminals coupled with each other as described above and selecting appropriate input terminals of these differential buffers to input the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_Benable to mix the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band inverted delayed differential data signal EV_{IN B}and EV_INwithout using an inverting circuit.

0029Specifically, the mixing circuit <b>12</b> mixes the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_IN_{<sub2>—</sub2>}_B, which is an inverted signal of the delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_B, with mixing ratios of 1:0, 1:1, and 0:1 and generates the mixed differential data signal V_B1and V_B2with respective mixing ratios. The mixing ratio is set by a mixing ratio setting circuit, which is not shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0030The output stage <b>20</b>A has a first output differential pair <b>21</b> including a first transistor <b>21</b><i>a </i>and a second transistor <b>21</b><i>b </i>and a second output differential pair <b>22</b> including a third transistor <b>22</b><i>a </i>and a fourth transistor <b>22</b><i>b. </i>

0031Sources of the first and the second transistors <b>21</b><i>a </i>and <b>21</b><i>b </i>are commonly connected to the drain of a transistor <b>23</b>. The source of the transistor <b>23</b>, which operates as a constant current source, is connected to the ground. The first and the second transistors <b>21</b><i>a </i>and <b>21</b><i>b </i>have mutually the same dimension. Similarly, sources of the third and the fourth transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>are commonly connected to the drain of a transistor <b>24</b>. The source of the transistor <b>24</b>, which operates as a constant current source, is connected to the ground. The third and the fourth transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>have mutually the same dimension.

0032The drain of the first transistor <b>21</b><i>a </i>in the first output differential pair <b>21</b>, which receives the differential data signal V_A1to the gate, and the drain of the third transistor <b>22</b><i>a </i>in the second output differential transistor pair <b>22</b>, which receives the mixed differential data signal V_B1at the gate, are commonly connected to form a first output node. The first output node is connected to a terminal of a first output stage load resistor <b>25</b><i>a, </i>and the other terminal of the first output stage load resistor <b>25</b><i>a </i>is connected to the power supply V_DC. Similarly, the drain of the second transistor <b>21</b><i>b </i>in the first output differential transistor pair <b>21</b>, which receives the differential data signal V_A2to the gate, and the drain of the fourth transistor <b>22</b><i>b </i>in the second output differential transistor pair <b>22</b>, which receives the mixed differential data signal V_B2at the gate, are commonly connected to form a second output node. The second output node is connected to a terminal of a second output stage load resistor <b>25</b><i>b, </i>and the other terminal of the second output stage load resistor <b>25</b><i>b </i>is connected to the power supply V_DD.

0033Accordingly, the output stage <b>20</b>A generates an output signal V_OUTand V_{OUT B}by summing the differential data signal V_A1and V_A2and the mixed differential data signal V_B1and V_B2, and further by inverting the result of summation. The output stage <b>20</b>A outputs the differential output signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bbetween the output node, i.e., between the drains of the first and the third transistors <b>21</b><i>a </i>and <b>22</b><i>a </i>commonly connected to the first output stage load resistor <b>25</b><i>a </i>and the drains of the second and the fourth transistors <b>21</b><i>b </i>and <b>22</b><i>b </i>commonly connected to the second output stage load resistor <b>25</b><i>b. </i>

0034Thus, the entire differential output buffer <b>100</b>A generates the differential output signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bby mixing the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_IN.

0035If no pre-emphasis function is required, a differential output buffer may be constructed without the mixing circuit <b>12</b> and the second output stage differential pair <b>22</b>. That is, a differential output buffer may be constructed only with the buffer <b>11</b>, the first output stage differential pair <b>21</b> and the transistor <b>23</b> that constitutes the constant current source. Assume that a relative dimension of each of transistors <b>21</b><i>a, </i><b>21</b><i>b </i>and <b>23</b> of such imaginary differential output buffer, which has a capability of transmitting signals through a transmission line, is 100%. Then, the exemplary differential output buffer <b>100</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref> has the same capability of transmitting signals through the transmission line if a sum of the relative dimensions of the transistors in the first and second output stage differential pairs <b>21</b> and <b>22</b> is 100%.

0036For example, relative dimensions of the first and second transistors <b>21</b><i>a </i>and <b>21</b><i>b </i>in the first output stage differential pair <b>21</b> and the third and fourth transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>in the second output stage differential pair <b>22</b> in the exemplary differential output buffer <b>100</b>A may be 60% and 40%, respectively. The transistors <b>23</b> and <b>24</b> for the constant current sources may have the same relative dimensions as the relative dimensions of the transistors in the corresponding one of the output stage differential pair. Accordingly, a sum of the relative dimensions of the transistors for the constant current sources may also be 100%.

0037Accordingly, the total area of the output stage <b>20</b>A of the exemplary differential output buffer <b>100</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref> may be made approximately the same as the area of the imaginary differential output buffer. It should be noted that the exemplary differential output buffer <b>100</b>A has the pre-emphasis function while the imaginary differential output buffer does not have the function. In other words, the exemplary differential output buffer <b>100</b>A provides the pre-emphasis function without significantly increasing the area.

0038Furthermore, an output load capacitance of the exemplary differential output buffer <b>100</b>A, which is determined by the total dimension of the transistors in the output stage differential pairs, may also be made approximately the same as the load capacitance of the imaginary differential output buffer. In other words, the exemplary differential output buffer <b>100</b>A provides the pre-emphasis function without significantly increasing the output load capacitance.

0039Note that the relative dimensions of the transistors in the first and second output stage differential pairs are not limited to 60% and 40%, respectively. The relative dimensions may be set to, 70% and 30%, 50% and 50%, and so on, depending on required emphasis levels.

0040<figref idref="DRAWINGS">FIG. 2</figref> is a circuit diagram of an exemplary mixing circuit that constitutes the mixing stage <b>10</b>A of the first exemplary differential output buffer <b>100</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0041The exemplary mixing circuit <b>12</b> has a similar construction as the output stage <b>20</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref>. That is, the exemplary mixing circuit <b>12</b> has a first mixing stage differential pair <b>121</b> including first and second transistors <b>121</b><i>a </i>and <b>121</b><i>b, </i>and a second mixing stage differential pair <b>122</b> including third and fourth transistors <b>122</b><i>a </i>and <b>122</b><i>b. </i>Transistors in each of the differential pairs <b>121</b> and <b>122</b> have mutually the same dimension. Further, different from the output stage <b>20</b>A, a dimension of the transistors in the first mixing stage differential pair <b>121</b> and a dimension of the transistors in the second mixing stage differential pair are the same.

0042Sources of the first and second transistors <b>121</b><i>a </i>and <b>121</b><i>b, </i>which constitute the first mixing stage differential pair <b>121</b>, are commonly coupled to constant current sources <b>123</b><i>a </i>and <b>123</b><i>b, </i>which constitute the first mixing stage current source <b>123</b>. Similar to the constant current sources in the output stage shown in <figref idref="DRAWINGS">FIG. 1</figref>, each of these constant current sources <b>123</b><i>a </i>and <b>123</b><i>b </i>may be constructed with, for example, a transistor. Similarly, sources of the third and fourth transistors <b>122</b><i>a </i>and <b>122</b><i>b, </i>which constitute the second mixing stage differential pair <b>122</b>, are commonly coupled to constant current sources <b>124</b><i>a </i>and <b>124</b><i>b</i>, which constitute the second mixing stage current source <b>124</b>. Each of these four constant current sources <b>123</b><i>a, </i><b>123</b><i>b, </i><b>124</b><i>a, </i>and <b>124</b><i>b </i>supplies the same current.

0043Drains of the first transistor <b>121</b><i>a </i>in the first mixing stage differential pair <b>121</b> and the third transistor <b>122</b><i>a </i>in the second mixing stage differential pair <b>122</b> are commonly connected to one of the terminals of a first mixing stage load resistor <b>125</b><i>a. </i>The other terminal of the first mixing stage load resistor <b>125</b><i>a </i>is connected to the power supply V_DD. Similarly, drains of the second transistor <b>121</b><i>b </i>in the first mixing stage differential pair <b>121</b> and the fourth transistor <b>122</b><i>b </i>in the second mixing stage differential pair <b>122</b> are commonly connected to one of the terminals of a second mixing stage load resistor <b>125</b><i>b. </i>The other terminal of the second mixing stage load resistor <b>125</b><i>b </i>is connected to the power supply V_DD.

0044The first mixing stage differential pair <b>121</b> receives the differential data signal V_INand V_IN_{<sub2>—</sub2>}_B, and the second mixing stage differential pair <b>122</b> receives the delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_B. Specifically, gates of the first and second transistors <b>121</b><i>a </i>and <b>121</b><i>b </i>in the first mixing stage differential pair <b>121</b> receive the differential data signal V_INand V_IN_{<sub2>—</sub2>}_B, and gates of the third and fourth transistors <b>122</b><i>a </i>and <b>122</b><i>b </i>in the second mixing stage differential pair <b>122</b> receive the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_IN.

0045That is, the gate of the first transistor <b>121</b><i>a </i>receives the positive phase differential data signal V_INand the gate of the third transistor <b>122</b><i>a, </i>whose drain is coupled to the drain of the first transistor <b>121</b><i>a, </i>receives the negative phase delayed differential data signal EV_IN_{<sub2>—</sub2>}_B. Further, the gate of the second transistor <b>121</b><i>b </i>receives the negative phase differential data signal V_IN_{<sub2>—</sub2>}_Band the gate of the fourth transistor <b>122</b><i>b, </i>whose drain is coupled to the drain of the second transistor <b>121</b><i>b, </i>receives the positive phase delayed differential data signal EV_IN. This construction enable to mix the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_IN.

0046<figref idref="DRAWINGS">FIG. 2</figref> further shows a mixing ratio setting circuit <b>14</b>. The mixing ratio setting circuit <b>14</b> controls each of four constant current sources <b>123</b><i>a, </i><b>123</b><i>b, </i><b>124</b><i>a, </i>and <b>124</b><i>b </i>in accordance with the control signal CS. Specifically, the mixing ratio setting circuit <b>14</b> enable/disable each of the constant current sources to supply the source current to each of the first mixing stage differential pair <b>121</b> including transistors <b>121</b><i>a </i>and <b>121</b><i>b </i>and the second mixing stage differential pair <b>122</b> including transistors <b>122</b><i>a </i>and <b>122</b><i>b. </i>Here, the mixing ratio setting circuit <b>14</b> can only make one of following three modes;

0047Mode 1: enable both of two constant current sources <b>123</b><i>a </i>and <b>123</b><i>b </i>that constitute the first mixing stage current source <b>123</b> to supply the source currents to the first mixing stage differential pair <b>121</b> and disable both of two constant current sources <b>124</b><i>a </i>and <b>124</b><i>b </i>that constitutes the second mixing stage current source <b>124</b> to supply the sources current to the second mixing stage differential pair <b>122</b>;

0048Mode 2: enable one of, and disable the other one of, two constant current sources <b>123</b><i>a </i>and <b>123</b><i>b </i>that constitute the first mixing stage current source <b>123</b> to supply the source current to the first mixing stage differential pair <b>121</b> and enable one of, and disable the other one of, two constant current sources <b>124</b><i>a </i>and <b>124</b><i>b </i>that constitutes the second mixing stage current source <b>124</b> to supply the source current to the second mixing stage differential pair <b>122</b>; and

0049Mode 3: disable both of two constant current sources <b>123</b><i>a </i>and <b>123</b><i>b </i>that constitute the first mixing stage current source <b>123</b> to supply the source currents to the first mixing stage differential pair <b>121</b> and enable both of two constant current sources <b>124</b><i>a </i>and <b>124</b><i>b </i>that constitutes the second mixing stage current source <b>124</b> to supply the source currents to the second mixing stage differential pair <b>122</b>.

0050The mixing stage mixes the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INwith mixing ratios of 1:0, 1:1, and 0:1 in the modes 1, 2, and 3, respectively, and outputs the mixed differential data signal V_B1and V_B2with respective mixing ratios.

0051The mixed differential data signal V_B1and V_B2are input to gates of the transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>in the second output stage differential pair <b>22</b> of the output stage <b>20</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref>. Here the mixed differential data signal has the mixing ratio between the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INof one of 1:0, 1:1, and 0:1. Accordingly, gates of both transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>that constitute the second output stage differential pair <b>22</b> receive signals with the same level, or gate of one of the transistors receive a signal having a logical level of 1 and gate of the other one of the transistors receives a signal having a logical level of 0. In either case, the state of the second output stage differential pair <b>22</b> is determined without being affected by the change of gain of the differential pair.

0052That is, in the former case, each of the transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>flows a half of the current that the current source <b>24</b> supplies. In the latter case, one of the transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>flows the entire current that the current source <b>24</b> supplies, and the other of the transistors flows no current. Accordingly, in either case, the output stage <b>20</b>A mixes the differential data signal VI_Nand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INwith intended ratios. As a result, the exemplary differential output buffer <b>100</b>A can generate differential output signals V_OUTand V_OUT_{<sub2>—</sub2>}_Bwith intended emphasis levels.

0053As explained above, the differential output drivers according to the exemplary output buffer can accurately control the amount of emphasis in multiple levels without increasing output capacitance and chip area.

0054The mixing circuit used in the differential output buffer disclosed in Patent document 1, on the other hand, mixes the differential data signal and the inverted delayed differential data signal with various mixing ratios C2:C3 shown in TABLE 3 thereof. As a result, the intended emphasis level may not be realized due to the change of gain of the output stage.

0055For example, the mixing ratio of C2:C3=100%:0% shown in the first row of TABLE 3 provides the intended emphasis level of 0%. However, the mixing ratio of C2:C3=60%:40% shown on the third row of TABLE 3 does not provide the intended emphasis level. That is, the amplitude of the mixed differential data signal changes depending on the combination of logical levels of the differential data signal and the inverted delayed differential data signal, and the gain of the second output stage differential pair changed depending on the amplitude of the mixed differential data signal. Specifically, when the logical levels of the differential data signal and the inverted delayed differential data signal are the same and the amplitude of the mixed differential data signal is large, the gain of the second output stage differential pair decreases.

0056As a result, the intended emphasis level of 16% cannot be realized by mixing the inverted delayed differential data signal with a ratio of C3=40%. The actually realized emphasis level is smaller than the intended level due to the decrease of the gain.

0057TABLE 1 shows mixing ratios of the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INin the output signal, or the emphasized differential signal V_OUTand V_{OUT B}, that the first exemplary differential output buffer <b>100</b>A shown in <figref idref="DRAWINGS">FIGS. 1 and 2</figref> generates in each of the modes. Specifically, TABLE 1 shows percentages of the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bin the column of “VIN” and percentages of the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INin the column of “EV”, respectively. TABLE 1 further shows contributions of the first and second output stage differential pairs <b>21</b> and <b>22</b>, which constitute the output stage <b>20</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref>, to the percentages. Note that the first output stage differential pair <b>21</b> contributes to the percentage of “EV”, while the second output stage differential pair <b>22</b> contributes to percentages of both of “VIN” and “EV”.

0000<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="offset" colwidth="56pt" align="left" /><colspec colname="1" colwidth="70pt" align="center" /><colspec colname="2" colwidth="14pt" align="left" /><colspec colname="3" colwidth="56pt" align="center" /><colspec colname="4" colwidth="21pt" align="left" /><thead><row><entry /><entry namest="offset" nameend="4" rowsep="1">TABLE 1</entry></row></thead><tbody valign="top"><row><entry /><entry namest="offset" nameend="4" align="center" rowsep="1" /></row><row><entry /><entry>VIN</entry><entry /><entry>EV</entry><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="1" colwidth="56pt" align="center" /><colspec colname="2" colwidth="35pt" align="center" /><colspec colname="3" colwidth="49pt" align="center" /><colspec colname="4" colwidth="21pt" align="center" /><colspec colname="5" colwidth="56pt" align="center" /><tbody valign="top"><row><entry>mode</entry><entry>1st + 2nd</entry><entry>%</entry><entry>2nd</entry><entry>%</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="1" colwidth="56pt" align="char" char="." /><colspec colname="2" colwidth="35pt" align="center" /><colspec colname="3" colwidth="49pt" align="char" char="." /><colspec colname="4" colwidth="21pt" align="char" char="." /><colspec colname="5" colwidth="56pt" align="char" char="." /><tbody valign="top"><row><entry>1</entry><entry>60 + 40</entry><entry>100</entry><entry>0</entry><entry>0</entry></row><row><entry>2</entry><entry>60 + 20</entry><entry>80</entry><entry>20</entry><entry>20</entry></row><row><entry>3</entry><entry>60 + 0 </entry><entry>60</entry><entry>40</entry><entry>40</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0058The first row of TABLE 1 shows the percentages in the first mode where the mixing ratio at the mixing circuit <b>12</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> is 1:0. In the first mode, the second output stage differential pair <b>22</b> only receives a signal originated from the differential data signal V_INand V_IN_{<sub2>—</sub2>}_B. The first and second output stage differential pairs contribute to the output signal, or the emphasized differential signal V_OUTand V_OUT_{<sub2>—</sub2>}_B, from the output stage <b>20</b>A with the percentages of 60% and 40%, respectively, Accordingly, the percentages of “VN” and “EV” in the emphasized differential signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bin the first mode are 100% and 0%, respectively.

0059The second row of TABLE 1 shows the percentages in the second mode where the mixing ratio at the mixing circuit <b>12</b> is 1:1. In the second mode, the second output stage differential pair <b>22</b> receives signals originated from the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INmixed with a ratio of 1:1. Accordingly, contributions of the second output stage differential pair <b>22</b> to “VIN” and “EV” in the emphasized differential data signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bare 20% and 20%, respectively. While, the first output stage differential pair <b>21</b> exclusively contributes to “VIN” with the percentage of 60%. Accordingly, in total, the percentages of “YIN” and “EV” in the emphasized differential signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bare 80% and 20%, respectively.

0060The third row of TABLE 1 shows the percentages in the third mode where the mixing ratio at the mixing circuit <b>12</b> is 0:1. In the third mode, the second output stage differential pair <b>22</b> only receives a signal originated from the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_IN. Accordingly, contributions of the second output stage differential pair <b>22</b> to “VIN” and “EV” in the emphasized differential data signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bare 0% and 40%, respectively. Accordingly, in total, the percentages of “VIN” and “EV” in the emphasized differential signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bare 60% and 40%, respectively.

0061In the first exemplary differential output buffer <b>100</b>A, a total dimension of the transistors in the first and second output stage differential pairs <b>21</b> and <b>22</b> is capable of transmitting output signals through a transmission line. Further, a combination of dimensions of the transistors in the first and second output stage differential pairs <b>21</b> and <b>22</b> enables to realize required emphasis levels shown in TABLE 1 by setting the mixing ratio at the mixing circuit <b>12</b> to 1:0, 1:1, and 0:1. That is, the first exemplary differential output buffer <b>100</b>A is designed such that i) a sum of dimensions of the transistors in the first and second output stage differential pairs <b>21</b> and <b>22</b> is capable of transmitting output signals through a transmission line, and ii) a combination of dimensions of the transistors in the first and second output stage differential pairs <b>21</b> and <b>22</b> enables to realize required emphasis levels by setting the mixing ratio to 1:0, 1:1, and 0:1.

0062The design of the exemplary differential output buffer may be performed using a CAD (Computer-aided-design) system to generate a layout data. The layout data is used to generate a mask data, and masks formed using the mask data are used to fabricate a semiconductor integrated circuit that includes the exemplary differential output butter.

0063In the first exemplary embodiment, dimensions of transistors in the first and second output stage differential pairs <b>21</b> and <b>22</b>, or contributions of the first and second output stage differential pairs <b>21</b> and <b>22</b> shown in <figref idref="DRAWINGS">FIG. 1</figref> are set to 60% and 40%, respectively. The contributions may be adjusted in accordance with required emphasis levels.

0064In the first exemplary embodiment, the mixing circuit <b>12</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> includes two mixing stage differential pairs <b>121</b> and <b>122</b>, four constant current sources <b>123</b><i>a, </i><b>123</b><i>b, </i><b>124</b><i>a, </i>and <b>124</b><i>b </i>each supplies the same current, and the mixing ratio setting circuit <b>13</b>. The mixing circuit <b>12</b> has a construction that two of four constant current sources are provided for each of the first and second mixing stage differential pairs, and that the mixing ratio setting circuit controls ON and OFF of the constant current sources.

0065The mixing circuit may have various other constructions. For example, because only two of the four constant current sources in the exemplary mixing circuit are ON in any of the modes, the mixing circuit may be constructed with only two constant current sources. The mixing circuit may have switches to connect (i) both of the two constant current sources to the first mixing stage differential pair <b>121</b>, (ii) one of the two constant current sources to each of the first and second mixing stage differential pairs <b>121</b> and <b>122</b>, or (iii) both of the two constant current sources to the second mixing stage differential pair <b>122</b>.

0066It is also possible to provide one constant current source, which is controlled to be ON and OFF, to each of the first and second mixing stage differential pairs <b>121</b> and <b>122</b>. In this case, when one of the constant current sources is ON and the other is OFF, the current flows in the mixing circuit <b>12</b> becomes a half of the current that flows in the mixing circuit when both of the constant current sources are ON. As a result, the common mode voltage of the mixed differential data signal increases and the amplitude of the mixed differential data signal becomes a half of the amplitude compared with the case that both of the constant current sources are ON.

0067However, it is possible to design the output stage <b>20</b>A that accept the mixed differential data signal with the reduced amplitude at least when the power supply voltage V_DDis relatively high. Specifically, the output stage <b>20</b>A may be designed such that (i) one of the transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>in the second output stage differential pair <b>22</b> flows the entire current of the current source <b>24</b> and the other flows no current, and (ii) the amplitude of the output signal is maintained, even when the amplitude of the mixed differential data signal is reduced.

0068It is also possible to enable/disable the supply of input signals including the differential data signal VIN and VIN_B and the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INto the first and second mixing stage differential pairs <b>121</b> and <b>122</b>. In this case, the constant current sources provided for each of the first and second mixing stage differential pairs <b>121</b> and <b>122</b> may be kept ON in all of the modes.

0069The sprit of the first exemplary embodiment and various modifications thereof may also be applied to the second and following exemplary embodiments.

0070<figref idref="DRAWINGS">FIG. 3</figref> is a circuit diagram of a second exemplary differential output buffer according to this disclosure.

0071The second exemplary differential output buffer <b>100</b>B shown in <figref idref="DRAWINGS">FIG. 3</figref> has a mixing stage <b>10</b>B and an output stage <b>20</b>B. The mixing stage <b>10</b>B includes a buffer <b>11</b> and a mixing circuit <b>12</b>, same as the mixing stage <b>10</b>A of the first exemplary differential output buffer <b>100</b>A. The mixing stage <b>10</b>B in the second exemplary differential output buffer further includes another mixing circuit <b>13</b>. The mixing circuit <b>13</b> includes, similar to the mixing circuit <b>12</b>, two buffers including a fourth buffer <b>13</b><i>a </i>and a fifth buffer <b>13</b><i>b. </i>The fourth buffer <b>13</b><i>a </i>receives the differential data signal V_INand V_IN_{<sub2>—</sub2>}_B, and the fifth buffer <b>13</b><i>b </i>receives the delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_B. Same as the mixing circuit <b>12</b> shown in <figref idref="DRAWINGS">FIG. 2</figref>, the mixing circuit <b>13</b> also mixes the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INwith a mixing ratio of one of 1:0, 1:1, and 0:1.

0072The output stage <b>20</b>B of the second exemplary differential output buffer <b>100</b>B shown in <figref idref="DRAWINGS">FIG. 3</figref> includes, similar to the output stage <b>20</b>A of the first exemplary differential output buffer <b>100</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref>, a first and a second output stage differential pair <b>21</b> and <b>22</b>. In addition, the output stage <b>20</b>B of the second exemplary differential output buffer <b>100</b>B includes a third output stage differential pair <b>26</b>. Further, the dimension of the third and fourth transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>that constitute the second output stage differential pair <b>22</b><i>b </i>in the second exemplary differential output buffer <b>100</b>B is different from the dimension of the same transistors in the first exemplary differential buffer <b>100</b>A shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0073That is, the third and fourth transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>in the first exemplary differential output buffer <b>100</b>A has the relative dimension of 40%. On the other hand, the third and fourth transistors <b>22</b><i>a </i>and <b>22</b><i>b </i>in the second exemplary differential output buffer <b>100</b>B has the relative dimension 30%. Accordingly, the transistor <b>24</b> also has the relative dimension of 30% and the constant current source formed by the transistor <b>24</b> supplies 30% of the total current that flows in the output stage <b>20</b>B of the second exemplary differential output buffer <b>100</b>B.

0074The third output stage differential pair <b>26</b> includes a fifth transistor <b>26</b><i>a </i>and a sixth transistor <b>26</b><i>b. </i>Sources of the fifth and sixth transistors are commonly coupled to the drain of a transistor <b>27</b>, which is used as a constant current source. The drain of the fifth transistor <b>26</b><i>a </i>is commonly coupled with drains of the first and third transistors <b>21</b><i>a </i>and <b>22</b><i>a. </i>The drain of the sixth transistor <b>26</b><i>b </i>is commonly coupled with drains of the second and fourth transistors <b>21</b><i>b </i>and <b>22</b><i>b. </i>

0075The fifth and sixth transistors <b>26</b><i>a </i>and <b>26</b><i>b </i>that constitute the third output stage differential pair <b>26</b> have the relative dimension of 10%. The transistor <b>27</b> that constitute the constant current source also has the relative dimension of 10% and supplies 10% of the total current of the output stage <b>20</b>B. That is, in the second exemplary differential output buffer <b>100</b>B, the total dimension of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b>, and <b>23</b> is 100%.

0076The output signal, or the second mixed differential data signal, V_C1and V_C2of the second mixing circuit <b>13</b> is supplied to respective gates of the fifth and sixth transistors <b>26</b><i>a </i>and <b>26</b><i>b </i>that constitute the third output stage differential pair <b>23</b>. Accordingly, the output stage <b>20</b>B generates an output signal V_OUTand V_OUT_{<sub2>—</sub2>}_Bby summing the differential data signal V_A1and V_A2, the mixed differential data signal V_B1and V_B2, and the second mixed differential data signal V_C1and V_C2with ratios of 60%, 30%, and 10%, respectively.

0077TABLE 2 shows mixing ratios of the differential data signal V_{IN and V}_IN_{<sub2>—</sub2>}_Band the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INin the output signal, or the emphasized differential signal V_OUTand V_OUT_{<sub2>—</sub2>}_B, that the second exemplary differential output buffer <b>100</b>B shown in <figref idref="DRAWINGS">FIG. 3</figref> generates. Same as TABLE 1, TABLE 2 shows percentages of the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bin the column of “VIN” and the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INin the column of “EV”, respectively, depending on the mixing ratios in the two mixing circuits <b>12</b> and <b>13</b>. TABLE 2 further shows contributions of the first, second, and third output stage differential pairs <b>21</b>, <b>22</b> and <b>26</b>, which constitute the output stage <b>20</b>B, to the percentages.

0000<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="91pt" align="center" /><colspec colname="2" colwidth="21pt" align="left" /><colspec colname="3" colwidth="70pt" align="center" /><colspec colname="4" colwidth="21pt" align="left" /><thead><row><entry /><entry namest="offset" nameend="4" rowsep="1">TABLE 2</entry></row></thead><tbody valign="top"><row><entry /><entry namest="offset" nameend="4" align="center" rowsep="1" /></row><row><entry /><entry>VIN</entry><entry /><entry>EV</entry><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="63pt" align="center" /><colspec colname="3" colwidth="35pt" align="center" /><colspec colname="4" colwidth="56pt" align="center" /><tbody valign="top"><row><entry /><entry>1st + 2nd + 3rd</entry><entry>%</entry><entry>2nd + 3rd</entry><entry>%</entry></row><row><entry /><entry namest="offset" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="63pt" align="char" char="." /><colspec colname="3" colwidth="35pt" align="center" /><colspec colname="4" colwidth="56pt" align="char" char="." /><tbody valign="top"><row><entry /><entry>60 + 30 + 10</entry><entry>100</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry /><entry>60 + 30 + 5</entry><entry>95</entry><entry>0 + 5</entry><entry>5</entry></row><row><entry /><entry>60 + 30 + 0</entry><entry>90</entry><entry> 0 + 10</entry><entry>10</entry></row><row><entry /><entry>60 + 15 + 10</entry><entry>85</entry><entry>15 + 0 </entry><entry>15</entry></row><row><entry /><entry>60 + 15 + 5</entry><entry>80</entry><entry>15 + 5 </entry><entry>20</entry></row><row><entry /><entry>60 + 15 + 0</entry><entry>75</entry><entry>15 + 10</entry><entry>25</entry></row><row><entry /><entry>60 + 0 + 0</entry><entry>70</entry><entry>30 + 0 </entry><entry>30</entry></row><row><entry /><entry>60 + 0 + 5</entry><entry>65</entry><entry>30 + 5 </entry><entry>35</entry></row><row><entry /><entry>60 + 0 + 0</entry><entry>60</entry><entry>30 + 10</entry><entry>40</entry></row><row><entry /><entry namest="offset" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0078As shown in TABLE 2, the second exemplary differential output buffer <b>100</b>B shown in <figref idref="DRAWINGS">FIG. 3</figref> can vary the percentage of “EV” from 0% to 40% with a step of 5%. That is, a combination of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b> and <b>26</b> enables to realize required emphasis levels shown in TABLE 2 by setting the mixing ratio in each of the mixing circuits <b>12</b> and <b>13</b> to 1:0, 1:1, and 0:1. Further, a total dimension of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b> and <b>26</b> is capable of transmitting output signals through a transmission line.

0079Accordingly, the second exemplary differential output buffer <b>100</b>B is designed such that i) a sum of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b>, and <b>26</b> is capable of transmitting output signals through a transmission line, and ii) a combination of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b>, and <b>26</b> enables to realize required emphasis levels by setting the mixing ratio in each of the mixing circuits <b>12</b> and <b>13</b> to 1:0, 1:1, and 0:1.

0080<figref idref="DRAWINGS">FIG. 4</figref> is a circuit diagram of a third exemplary differential output buffer according to this disclosure.

0081The differential output buffer <b>100</b>C shown in <figref idref="DRAWINGS">FIG. 4</figref> includes a mixing stage <b>10</b>C and an output stage <b>20</b>C. The mixing stage <b>20</b>C has the same construction as the mixing stage <b>20</b>B in the second exemplary differential output buffer <b>100</b>B shown in <figref idref="DRAWINGS">FIG. 3</figref>. However, the sixth buffer <b>13</b><i>b </i>that constitute the mixing circuit <b>13</b> of the third exemplary differential output buffer <b>100</b>C receives a different input signal.

0082That is, the sixth buffer <b>13</b><i>b </i>in the mixing stage <b>10</b>B of the second exemplary differential output buffer <b>100</b>B shown in <figref idref="DRAWINGS">FIG. 3</figref> receives the delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_B, while the sixth buffer <b>13</b><i>b </i>in the mixing stage <b>10</b>C of the third exemplary differential output buffer <b>100</b>C shown in <figref idref="DRAWINGS">FIG. 4</figref> receives a second delayed differential data signal EV<b>2</b>_INand EV<b>2</b>_IN_{<sub2>—</sub2>}_B. Here, the delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_Bis a signal that delayed the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bby a delay period of one tap. While the second delayed differential data signal EV<b>2</b>_INand EV<b>2</b>_IN_{<sub2>—</sub2>}_Bis a signal that delayed the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bby a second delay period of, for example, two taps. Accordingly, the third exemplary differential output buffer <b>100</b>C shown in <figref idref="DRAWINGS">FIG. 4</figref> can continue the emphasis during a period of two taps with varying levels.

0083TABLE 3 shows mixing ratios of the differential data signal V_INand V_IN_{<sub2>—</sub2>}_B, the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_IN, and the inverted second delayed differential data signal EV<b>2</b>_IN_{<sub2>—</sub2>}_Band EV<b>2</b>_INin the output signal, or the emphasized differential signal V_OUTand V_OUT_B, that the third exemplary differential output buffer <b>100</b>C shown in <figref idref="DRAWINGS">FIG. 4</figref> generates. Same as TABLEs 1 and 2, TABLE 3 shows percentages of the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bin the column of “VIN” and percentages of inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_INin the column of “EV”, respectively. TABLE 3 additionally shows percentages of the inverted second delayed differential data signal EV<b>2</b>_IN_{<sub2>—</sub2>}_Band EV<b>2</b>_INin the column of “EV<b>2</b>. TABLE 3 further shows contributions of the first, second, and third output stage differential pairs <b>21</b>, <b>22</b> and <b>26</b>, which constitute the output stage <b>20</b>C of the third exemplary differential output buffer <b>100</b>C, to the percentages.

0000<tables id="TABLE-US-00003" num="00003"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="7"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="77pt" align="center" /><colspec colname="2" colwidth="7pt" align="left" /><colspec colname="3" colwidth="49pt" align="center" /><colspec colname="4" colwidth="14pt" align="left" /><colspec colname="5" colwidth="42pt" align="center" /><colspec colname="6" colwidth="14pt" align="left" /><thead><row><entry /><entry namest="offset" nameend="6" rowsep="1">TABLE 3</entry></row></thead><tbody valign="top"><row><entry /><entry namest="offset" nameend="6" align="center" rowsep="1" /></row><row><entry /><entry>VIN</entry><entry /><entry>EV</entry><entry /><entry>EV2</entry><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="7"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="35pt" align="center" /><colspec colname="3" colwidth="21pt" align="center" /><colspec colname="4" colwidth="42pt" align="center" /><colspec colname="5" colwidth="14pt" align="center" /><colspec colname="6" colwidth="42pt" align="center" /><tbody valign="top"><row><entry /><entry>1st + 2nd + 3rd</entry><entry>%</entry><entry>2nd</entry><entry>%</entry><entry>3rd</entry><entry>%</entry></row><row><entry /><entry namest="offset" nameend="6" align="center" rowsep="1" /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="7"><colspec colname="offset" colwidth="14pt" align="left" /><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="35pt" align="char" char="." /><colspec colname="3" colwidth="21pt" align="char" char="." /><colspec colname="4" colwidth="42pt" align="char" char="." /><colspec colname="5" colwidth="14pt" align="char" char="." /><colspec colname="6" colwidth="42pt" align="char" char="." /><tbody valign="top"><row><entry /><entry>60 + 30 + 10</entry><entry>100</entry><entry>0</entry><entry>0</entry><entry>0</entry><entry>0</entry></row><row><entry /><entry>60 + 30 + 5</entry><entry>95</entry><entry>0</entry><entry>0</entry><entry>5</entry><entry>5</entry></row><row><entry /><entry>60 + 30 + 0</entry><entry>90</entry><entry>0</entry><entry>0</entry><entry>10</entry><entry>10</entry></row><row><entry /><entry>60 + 15 + 10</entry><entry>85</entry><entry>15</entry><entry>15</entry><entry>0</entry><entry>0</entry></row><row><entry /><entry>60 + 15 + 5</entry><entry>80</entry><entry>15</entry><entry>15</entry><entry>5</entry><entry>5</entry></row><row><entry /><entry>60 + 15 + 0</entry><entry>75</entry><entry>15</entry><entry>15</entry><entry>10</entry><entry>10</entry></row><row><entry /><entry>60 + 0 + 10</entry><entry>70</entry><entry>30</entry><entry>30</entry><entry>0</entry><entry>0</entry></row><row><entry /><entry>60 + 0 + 5</entry><entry>65</entry><entry>30</entry><entry>30</entry><entry>5</entry><entry>5</entry></row><row><entry /><entry>60 + 0 + 0</entry><entry>60</entry><entry>30</entry><entry>30</entry><entry>10</entry><entry>10</entry></row><row><entry /><entry namest="offset" nameend="6" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0084As shown in TABLE 3, the third exemplary differential output buffer <b>100</b>C can continue the emphasis during a delay period of two taps with varying levels. Further, similar to the second exemplary differential output buffer <b>100</b><i>b </i>shown in <figref idref="DRAWINGS">FIG. 3</figref>, a combination of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b> and <b>26</b> enables to realize required emphasis levels shown in TABLE 3 by setting the mixing ratio in each of the mixing circuits <b>12</b> and <b>13</b> to 1:0, 1:1, and 0:1. In addition, similar to the second exemplary differential output buffer <b>100</b>B shown in <figref idref="DRAWINGS">FIG. 3</figref>, a total dimension of the transistors in the first, second and third output stage differential pairs <b>21</b>, <b>22</b> and <b>26</b> is capable of transmitting output signals through a transmission line.

0085Accordingly, similar to the second exemplary differential output buffer <b>100</b>B, the third exemplary differential output buffer <b>100</b>C is designed such that i) a sum of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b>, and <b>26</b> is capable of transmitting output signals through a transmission line, and ii) a combination of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b>, and <b>26</b> enables to realize required emphasis levels by setting the mixing ratio in each of the mixing circuits <b>12</b> and <b>13</b> to 1:0, 1:1, and 0:1.

0086<figref idref="DRAWINGS">FIG. 5</figref> is a circuit diagram of a fourth exemplary differential output buffer according to this disclosure.

0087The fourth exemplary differential output buffer <b>100</b>D shown in <figref idref="DRAWINGS">FIG. 5</figref> includes a mixing stage <b>10</b>D and an output stage <b>20</b>D. The output stage <b>20</b>D has the same construction as the output stages <b>20</b>B in the second exemplary differential output buffer <b>100</b>B shown in <figref idref="DRAWINGS">FIG. 3 and 20C</figref> in the third exemplary differential output buffer <b>100</b>C shown in <figref idref="DRAWINGS">FIG. 4</figref>. Different from the second and third exemplary differential output buffers <b>100</b>B and <b>100</b>C, however, the mixing circuits <b>12</b>D and <b>13</b>D of the fourth exemplary differential buffer <b>100</b>D have respective three buffers <b>12</b><i>a, </i><b>12</b><i>b, </i>and <b>12</b><i>c, </i>and <b>13</b><i>a, </i><b>13</b><i>b, </i>and <b>13</b><i>c. </i>

0088These three buffers <b>12</b><i>a, </i><b>12</b><i>b, </i>and <b>12</b><i>c, </i>and <b>13</b><i>a, </i><b>13</b><i>b, </i>and <b>13</b><i>c </i>that constitute each of the mixing circuits <b>12</b>D and <b>13</b>D receives the differential data signal V_INand V_IN_{<sub2>—</sub2>}_B, the delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_B, and the second delayed differential data signal EV<b>2</b>_INand EV<b>2</b>_IN_{<sub2>—</sub2>}_B, respectively. The delayed differential data signal EV_INand EV_IN_{<sub2>—</sub2>}_Band the second delayed differential data signal EV<b>2</b>_INand EV<b>2</b>_IN_{<sub2>—</sub2>}_Bare signals that delayed the differential data signal V_INand V_IN_{<sub2>—</sub2>}_Bby periods of one tap and two taps, respectively.

0089<figref idref="DRAWINGS">FIG. 6</figref> is a circuit diagram of an exemplary mixing circuit <b>12</b>D in the fourth exemplary differential output buffer <b>100</b>D shown in <figref idref="DRAWINGS">FIG. 5</figref>. The other mixing circuit <b>13</b>D in the fourth exemplary differential output buffer <b>100</b>D has the same construction as the mixing circuit <b>12</b>D.

0090Similar to the first exemplary mixing circuit <b>12</b> shown in <figref idref="DRAWINGS">FIG. 2</figref>, the second exemplary mixing circuit <b>12</b>D shown in <figref idref="DRAWINGS">FIG. 6</figref> includes the first and second mixing stage differential pairs <b>121</b> and <b>122</b>. In addition, the second exemplary mixing circuit <b>12</b>D includes a third mixing stage differential pair <b>126</b>. Sources of transistors <b>126</b><i>a </i>and <b>126</b><i>b </i>of the third mixing stage differential pair <b>126</b> are commonly coupled to the third mixing stage current source <b>127</b>.

0091The third mixing stage current source <b>127</b> includes two constant current sources <b>127</b><i>a </i>and <b>127</b><i>b. </i>Each of these constant current sources <b>127</b><i>a </i>and <b>127</b><i>b </i>supplies the same current as each of other constant current sources <b>123</b><i>a, </i><b>123</b><i>b, </i><b>124</b><i>a, </i>and <b>124</b><i>b </i>supplies. The drain of one of the transistors <b>126</b><i>a </i>in the third mixing stage differential pair <b>126</b> is commonly coupled to drains of the transistors <b>121</b><i>a </i>and <b>122</b><i>b. </i>The drain of the other one of the transistors <b>126</b><i>b </i>in the third mixing stage differential pair <b>126</b> is commonly coupled to drains of the transistor <b>121</b><i>b </i>and <b>122</b><i>b. </i>

0092The third mixing stage differential pair <b>126</b> receives the second delayed differential data signal EV<b>2</b>_INand EV<b>2</b>_IN_{<sub2>—</sub2>}_B. Specifically, gates of the transistor <b>126</b><i>a </i>and <b>126</b><i>b </i>in the third mixing stage differential pair <b>126</b> received inverted second delayed differential data signal EV<b>2</b>_IN_{<sub2>—</sub2>}_Band EV<b>2</b>_IN. Accordingly, the second exemplary mixing circuit <b>12</b>D can mix the differential data signal V_INand V_IN_{<sub2>—</sub2>}_B, the inverted delayed differential data signal EV_IN_{<sub2>—</sub2>}_Band EV_IN, and the inverted second delayed differential data signal EV<b>2</b>_IN_{<sub2>—</sub2>}_Band EV<b>2</b>_IN.

0093The second exemplary mixing circuit <b>12</b>D shown in <figref idref="DRAWINGS">FIG. 6</figref> includes a second mixing ratio setting circuit <b>14</b>D that controls, in accordance with the control signal CS, ON and OFF of each of six constant current sources <b>123</b><i>a, </i><b>123</b><i>b, </i><b>124</b><i>a, </i><b>124</b><i>b, </i><b>127</b><i>a, </i>and <b>127</b><i>b </i>in the first, second, and third mixing stage current sources <b>123</b>, <b>124</b>, and <b>127</b>. Note that, however, the second mixing ratio setting circuit <b>14</b>D keeps one of these mixing stage current sources OFF and controls the other two of the mixing stage current sources in the same manner as the mixing ratio setting circuit <b>14</b> shown in <figref idref="DRAWINGS">FIG. 2</figref>.

0094For example, the second mixing ratio setting circuit <b>14</b>D may keep two constant current sources <b>127</b><i>a </i>and <b>127</b><i>b </i>in the third mixing stage current source <b>127</b> OFF and control ON and OFF of the constant current sources <b>123</b><i>a, </i><b>123</b><i>b, </i><b>124</b><i>a, </i>and <b>124</b><i>b </i>in the first and second mixing stage current sources <b>123</b> and <b>124</b> in the same manner as the first mixing ratio setting circuit <b>14</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> controls. Thereby, the second mixing ratio setting circuit <b>14</b>D realizes the first to third modes same as the first mixing ratio setting circuit <b>14</b>. Further, the second mixing ratio setting circuit <b>14</b>D may keep two constant current sources <b>124</b><i>a </i>and <b>124</b><i>b </i>in the second mixing stage current source <b>124</b> OFF and control ON and OFF of the constant current sources in the first and third mixing stage current sources <b>123</b> and <b>127</b> to realize following fourth to sixth modes;

0095Mode 4: turn ON both of two constant current sources <b>123</b><i>a </i>and <b>123</b><i>b </i>that constitute the first mixing stage current source <b>123</b> and turn OFF both of two constant current sources <b>127</b><i>a </i>and <b>127</b><i>b </i>that constitutes the third mixing stage current source <b>127</b>;

0096Mode 5: turn ON one of, and turn OFF the other one of, two constant current sources <b>123</b><i>a </i>and <b>123</b><i>b </i>that constitute the first mixing stage current source <b>123</b> and turn ON one of, and turn OFF the other one of, two constant current sources <b>127</b><i>a </i>and <b>127</b><i>b </i>that constitute the third mixing stage current source <b>127</b>; and

0097Mode 6: turn OFF both of two constant current sources <b>123</b><i>a </i>and <b>123</b><i>b </i>that constitute the first mixing stage current source <b>123</b> and turn ON both of two constant current sources <b>127</b><i>a </i>and <b>127</b><i>b </i>that constitutes the third mixing stage current source <b>127</b>.

0098Furthermore, the second mixing ratio setting circuit <b>14</b>D may keep two constant current sources <b>123</b><i>a </i>and <b>123</b><i>b </i>that constitute the first mixing stage current source <b>123</b> OFF and control ON and OFF of the constant current sources in the second and third mixing stage current sources <b>124</b> and <b>127</b> to realize following seventh to ninth modes;

0099Mode 7: turn ON both of two constant current sources <b>124</b><i>a </i>and <b>124</b><i>b </i>that constitute the second mixing stage current source <b>124</b> and turn OFF both of two constant current sources <b>127</b><i>a </i>and <b>127</b><i>b </i>that constitutes the third mixing stage current source <b>127</b>;

0100Mode 8: turn ON one of, and turn OFF the other one of, two constant current sources <b>124</b><i>a </i>and <b>124</b><i>b </i>that constitute the second mixing stage current source <b>124</b> and turn ON one of, and turn OFF the other one of, two constant current sources <b>127</b><i>a </i>and <b>127</b><i>b </i>that constitutes the third mixing stage current source <b>127</b>; and

0101Mode 9: turn OFF both of two constant current sources <b>124</b><i>a </i>and <b>124</b><i>b </i>that constitute the second mixing stage current source <b>124</b> and turn ON both of two constant current sources <b>127</b><i>a </i>and <b>127</b><i>b </i>that constitutes the third mixing stage current source <b>127</b>.

0102Note that, however, the fourth mode is equivalent to the first mode, the seventh mode is equivalent to the third mode, and the ninth mode is equivalent to the sixth mode. Accordingly, the second mixing ratio setting circuit <b>14</b>D actually selects one of six modes. The other mixing circuit <b>13</b>D included in the fourth exemplary differential output buffer <b>100</b>D shown in <figref idref="DRAWINGS">FIG. 5</figref> also includes a mixing ratio setting circuit having the same function.

0103TABLE 4 is a list of emphasis that the fourth exemplary differential output buffer <b>100</b>D can realize.

0000<tables id="TABLE-US-00004" num="00004"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="6"><colspec colname="1" colwidth="77pt" align="center" /><colspec colname="2" colwidth="7pt" align="left" /><colspec colname="3" colwidth="63pt" align="center" /><colspec colname="4" colwidth="7pt" align="left" /><colspec colname="5" colwidth="56pt" align="center" /><colspec colname="6" colwidth="7pt" align="left" /><thead><row><entry namest="1" nameend="6" rowsep="1">TABLE 4</entry></row></thead><tbody valign="top"><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row><row><entry>VIN</entry><entry /><entry>EV</entry><entry /><entry>EV2</entry><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="6"><colspec colname="1" colwidth="56pt" align="left" /><colspec colname="2" colwidth="35pt" align="center" /><colspec colname="3" colwidth="35pt" align="center" /><colspec colname="4" colwidth="28pt" align="center" /><colspec colname="5" colwidth="35pt" align="center" /><colspec colname="6" colwidth="28pt" align="center" /><tbody valign="top"><row><entry>1st + 2nd + 3rd</entry><entry>%</entry><entry>2nd + 3rd</entry><entry>%</entry><entry>2nd + 3rd</entry><entry>%</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="6"><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="35pt" align="char" char="." /><colspec colname="3" colwidth="35pt" align="center" /><colspec colname="4" colwidth="35pt" align="char" char="." /><colspec colname="5" colwidth="35pt" align="center" /><colspec colname="6" colwidth="28pt" align="char" char="." /><tbody valign="top"><row><entry>60 + 30 + 10</entry><entry>100</entry><entry>0 + 0</entry><entry>0</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 30 + 5</entry><entry>95</entry><entry>0 + 5</entry><entry>5</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 30 + 5</entry><entry>95</entry><entry>0 + 0</entry><entry>0</entry><entry>0 + 5</entry><entry>5</entry></row><row><entry>60 + 30 + 0</entry><entry>90</entry><entry> 0 + 10</entry><entry>10</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 30 + 0</entry><entry>90</entry><entry>0 + 5</entry><entry>5</entry><entry>0 + 5</entry><entry>5</entry></row><row><entry>60 + 30 + 0</entry><entry>90</entry><entry>0 + 0</entry><entry>0</entry><entry> 0 + 10</entry><entry>10</entry></row><row><entry>60 + 15 + 10</entry><entry>85</entry><entry>15 + 0 </entry><entry>15</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 15 + 10</entry><entry>85</entry><entry>0 + 0</entry><entry>0</entry><entry>15 + 0 </entry><entry>15</entry></row><row><entry>60 + 15 + 5</entry><entry>80</entry><entry>15 + 5 </entry><entry>20</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 15 + 5</entry><entry>80</entry><entry>15 + 0 </entry><entry>15</entry><entry>0 + 5</entry><entry>5</entry></row><row><entry>60 + 15 + 5</entry><entry>80</entry><entry>0 + 5</entry><entry>5</entry><entry>15 + 0 </entry><entry>15</entry></row><row><entry>60 + 15 + 5</entry><entry>80</entry><entry>0 + 0</entry><entry>0</entry><entry>15 + 5 </entry><entry>20</entry></row><row><entry>60 + 15 + 0</entry><entry>75</entry><entry>15 + 10</entry><entry>25</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 15 + 0</entry><entry>75</entry><entry>15 + 5 </entry><entry>20</entry><entry>0 + 5</entry><entry>5</entry></row><row><entry>60 + 15 + 0</entry><entry>75</entry><entry>15 + 0 </entry><entry>15</entry><entry> 0 + 10</entry><entry>10</entry></row><row><entry>60 + 15 + 0</entry><entry>75</entry><entry> 0 + 10</entry><entry>10</entry><entry>15 + 0 </entry><entry>15</entry></row><row><entry>60 + 15 + 0</entry><entry>75</entry><entry>0 + 5</entry><entry>5</entry><entry>15 + 5 </entry><entry>20</entry></row><row><entry>60 + 15 + 0</entry><entry>75</entry><entry>0 + 0</entry><entry>0</entry><entry>15 + 10</entry><entry>25</entry></row><row><entry>60 + 0 + 10</entry><entry>70</entry><entry>30 + 0 </entry><entry>30</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 0 + 10</entry><entry>70</entry><entry>15 + 0 </entry><entry>15</entry><entry>15 + 0 </entry><entry>15</entry></row><row><entry>60 + 0 + 10</entry><entry>70</entry><entry>0 + 0</entry><entry>0</entry><entry>30 + 0 </entry><entry>30</entry></row><row><entry>60 + 0 + 5</entry><entry>65</entry><entry>30 + 5 </entry><entry>35</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 0 + 5</entry><entry>65</entry><entry>30 + 0 </entry><entry>30</entry><entry>0 + 5</entry><entry>5</entry></row><row><entry>60 + 0 + 5</entry><entry>65</entry><entry>15 + 5 </entry><entry>20</entry><entry>15 + 0 </entry><entry>15</entry></row><row><entry>60 + 0 + 5</entry><entry>65</entry><entry>15 + 0 </entry><entry>15</entry><entry>15 + 5 </entry><entry>20</entry></row><row><entry>60 + 0 + 5</entry><entry>65</entry><entry>0 + 5</entry><entry>5</entry><entry>30 + 0 </entry><entry>30</entry></row><row><entry>60 + 0 + 5</entry><entry>65</entry><entry>0 + 0</entry><entry>0</entry><entry>30 + 5 </entry><entry>35</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry>30 + 10</entry><entry>40</entry><entry>0 + 0</entry><entry>0</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry>30 + 5 </entry><entry>35</entry><entry>0 + 5</entry><entry>5</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry>30 + 0 </entry><entry>30</entry><entry> 0 + 10</entry><entry>10</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry>15 + 10</entry><entry>25</entry><entry>15 + 0 </entry><entry>15</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry>15 + 5 </entry><entry>20</entry><entry>15 + 5 </entry><entry>20</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry>15 + 0 </entry><entry>15</entry><entry>15 + 10</entry><entry>25</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry> 0 + 10</entry><entry>10</entry><entry>30 + 0 </entry><entry>30</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry>0 + 5</entry><entry>5</entry><entry>30 + 5 </entry><entry>35</entry></row><row><entry>60 + 0 + 0</entry><entry>60</entry><entry>0 + 0</entry><entry>0</entry><entry>30 + 10</entry><entry>40</entry></row><row><entry namest="1" nameend="6" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0104As shown in TABLE 4, the fourth exemplary differential output buffer <b>100</b>D shown in <figref idref="DRAWINGS">FIG. 4</figref> can continue the emphasis during a period of two taps with varying levels. Further, a combination of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b> and <b>26</b> enables to realize required emphasis levels shown in TABLE 4 by setting the mixing ratio in each of the mixing circuits <b>12</b>D and <b>13</b>D to 1:0:0, 1:1:0, 1:0:1, 0:1:0, 0:0:1, and 0:1:1. In addition, a total dimension of the transistors in the first, second and third output stage differential pairs <b>21</b>, <b>22</b> and <b>26</b> is capable of transmitting output signals through a transmission line.

0105Accordingly, the third exemplary differential output buffer <b>100</b>D is designed such that i) a sum of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b>, and <b>26</b> is capable of transmitting output signals through a transmission line, and ii) a combination of dimensions of the transistors in the first, second, and third output stage differential pairs <b>21</b>, <b>22</b>, and <b>26</b> enables to realize required emphasis levels by setting the mixing ratio in each of the mixing circuits <b>12</b>D and <b>13</b>D to 1:0:0, 1:1:0, 1:0:1, 0:1:0, 0:0:1, and 0:1:1.

0106It is also possible to provide differential output buffers that can continue the emphasis during periods of three or more taps.