Single-to-differential conversion circuit

CROSS-REFERENCE TO RELATED APPLICATION

0001This application claims priority to Taiwanese Patent Application No. 100111572, filed on Apr. 1, 2011, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The invention relates to a single-to-differential conversion circuit, more particularly to a single-to-differential conversion circuit with gain compensation.

00042. Description of the Related Art

0005In a telecommunication system, the receiver usually needs to use a single-to-differential conversion circuit to convert a received radio frequency (RF) signal into a differential signal having a first differential voltage and a second differential voltage. Under ideal conditions, the first and second differential voltages should be the same in magnitude, and 180° out of phase.

0006Looking at the current technology of the related circuit and the small signal model for a single-to-differential conversion circuit as shown in <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, a simple description is provided as follows:

0007After a first transistor M₁receives a RF signal, under ideal conditions and when the equivalent impedances Z_gs1, Z_gs2, Z₃(where Z_gs1is the equivalent impedance between the gate and source of the first transistor M₁, Z_gs2is the equivalent impedance between the gate and source of a second transistor M₂, and Z₃is a third equivalent impedance) are sufficiently large in magnitude (or the equivalent impedances Z_gs1, Z_gs2, and Z₃approach positive infinity), and when the load equivalent impedance Z_Lis sufficiently small in magnitude, the single-to-differential conversion circuit can output a first differential voltage V_o1and a second differential voltage V_o2as follows:

0000<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mrow><msub><mi>V</mi><mrow><mi>o</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><mo>=</mo><mrow><mrow><mo>-</mo><mrow><msub><mi>g</mi><mi>m</mi></msub><mo></mo><mrow><mo>(</mo><mfrac><msub><mi>V</mi><mn>1</mn></msub><mn>2</mn></mfrac><mo>)</mo></mrow></mrow></mrow><mo></mo><msub><mi>Z</mi><mn>1</mn></msub></mrow></mrow></math></maths><maths id="MATH-US-00001-2" num="00001.2"><math overflow="scroll"><mrow><msub><mi>V</mi><mrow><mi>o</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><mo>=</mo><mrow><mrow><msub><mi>g</mi><mi>m</mi></msub><mo></mo><mrow><mo>(</mo><mfrac><msub><mi>V</mi><mn>1</mn></msub><mn>2</mn></mfrac><mo>)</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mn>2</mn></msub></mrow></mrow></math></maths>

0008Where Z₁is a first equivalent impedance, Z₂is a second equivalent impedance, V₁is an input voltage, and g_mis a transconductance coefficient of the first transistor M₁(or the second transistor M₂). In the implementations of the current technology, the first and second equivalent impedances Z₁, Z₂are implemented by resistors, and the third equivalent impedance Z₃is implemented by resistors or transistors.

0009Therefore, under ideal conditions, when the first equivalent impedance Z₁is equal to the second equivalent impedance Z₂, the single-to-differential conversion circuit will output a group of differential voltages including the first differential voltage V_o1and the second differential voltage V_o2. When the first differential voltage V_o1and the second differential voltage V_o2are equal, the phase difference is 180°.

0010However, during the operation of the single-to-differential conversion circuit described above, the input voltage V₁is usually attenuated when transmitted to a node X because the equivalent impedance Z_gs1between the gate and the source of the first transistor M₁, the equivalent impedance Z_gs2between the gate and the source of the second transistor M₂, and/or the third equivalent impedance Z₃are not large enough. The magnitude of the voltage V_xat the node X is thus smaller than half the input voltage V₁, and the gate-source voltage V_gs1of the first transistor M₁is therefore not equal to the gate-source voltage V_gs2of the second transistor M₂. The gain mismatch of the first and second differential voltages V_o1, V_o2in the set of differential signals will result in unbalanced set of differential signals. Therefore, it is worth looking into efficiently solving the gain mismatch problem when designing the receiver circuit of a telecommunication system.

SUMMARY OF THE INVENTION

0011Therefore, an object of the present invention is to provide a single-to-differential conversion circuit with gain compensation.

0012According to one embodiment of the present invention, a single-to-differential conversion circuit of the present invention comprises a first transistor, a second transistor, and a transforming unit. Both of the first and second transistors has a first terminal, a second terminal, and a third terminal. The third terminal of the first transistor receives an input signal.

0013The transforming unit has a first induction element, a second induction element, and a third induction element. The first induction element has a first inductive terminal coupled to the second terminal of the first transistor, and a second inductive terminal to be coupled to a voltage source. The second induction element has a first inductive terminal to be coupled to the voltage source, and a second inductive terminal coupled to the second terminal of the second transistor. The third induction element has a first inductive terminal coupled to the first terminal of the first transistor and the first terminal of the second transistor, and a second inductive terminal to be coupled to ground.

0014The first induction element and the third induction element undergo a first electrical coupling according to a first coupling parameter. The second induction element and the third induction element undergo a second electrical coupling according to a second coupling parameter.

BRIEF DESCRIPTION OF THE DRAWINGS

0015Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which:

0016<figref idref="DRAWINGS">FIG. 1</figref> is a circuit diagram of a conventional single-to-differential conversion circuit;

0017<figref idref="DRAWINGS">FIG. 2</figref> is a small signal model diagram of the conventional single-to-differential conversion circuit;

0018<figref idref="DRAWINGS">FIG. 3</figref> is a circuit diagram of the preferred embodiment of the single-to-differential conversion circuit of the present invention;

0019<figref idref="DRAWINGS">FIG. 4</figref> is an equivalent circuit diagram of the preferred embodiment;

0020<figref idref="DRAWINGS">FIG. 5</figref> is an alternative implementation of a transforming unit of the preferred embodiment;

0021<figref idref="DRAWINGS">FIG. 6</figref> is another alternative implementation of the transforming unit of the preferred embodiment; and

0022<figref idref="DRAWINGS">FIG. 7</figref> is yet another alternative implementation of the transforming unit of the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0023<figref idref="DRAWINGS">FIG. 3</figref> shows the preferred embodiment of a single-to-differential conversion circuit of the present invention that comprises a first transistor <b>11</b>, a second transistor <b>12</b>, and a transforming unit <b>13</b>.

0024The first transistor <b>11</b> has a first terminal, a second terminal, and a third terminal which receives an input signal. The second transistor <b>12</b> has a first terminal, a second terminal and a third terminal. In the present embodiment, the first and second transistors <b>11</b>, <b>12</b> are both N-type metal oxide semiconductor-field effect transistors. The first terminals of both first and second transistors <b>11</b>, <b>12</b> are source terminals. The second terminals of both first and second transistors <b>11</b>, <b>12</b> are drain terminals. The third terminals of both first and second transistors <b>11</b>, <b>12</b> are gate terminals.

0025The transforming unit <b>13</b> has a first induction element <b>131</b>, a second induction element <b>132</b> and a third induction element <b>133</b>. The first induction element <b>131</b> has a first inductive terminal electrically coupled to the second terminal of the first transistor <b>11</b>, and a second inductive terminal electrically coupled to a voltage source V_DD. The second induction element <b>132</b> has a first inductive terminal electrically coupled to the voltage source V_DD, and a second inductive terminal electrically coupled the second terminal of the second transistor <b>12</b>. The third induction element <b>133</b> has a first inductive terminal electrically coupled to the first terminal of the first transistor <b>11</b> and the first terminal of the second transistor <b>12</b> (this connection node is referred to as node X), and a second inductive terminal electrically coupled to a ground terminal. The first induction element <b>131</b> and the third induction element <b>133</b> undergo a first electrical coupling according to a coupling parameter. The second induction element <b>132</b> and the third induction element <b>133</b> undergo a second electrical coupling according to the coupling parameter.

0026For simplicity, <figref idref="DRAWINGS">FIG. 4</figref> is the equivalent circuit diagram of <figref idref="DRAWINGS">FIG. 3</figref>. Two fourth induction elements <b>134</b> are the equivalence of the third induction element <b>133</b> and the two fourth induction elements <b>134</b> are electrically coupled in series. Every fourth induction element <b>134</b> has an inductance value L₄twice that of the inductance value L₃of the third induction element <b>133</b> (L₄=2×L₃).

0027The following description refers to <figref idref="DRAWINGS">FIG. 4</figref> and describes the relevant theoretical foundation of the preferred embodiment of the present invention.

0028With the preferred embodiment operating at a first cycle (the positive half cycle of the input signal), because an alternating current flows via the fourth induction elements <b>134</b>, according to the coupling relationship of the transforming unit <b>13</b>, there is created a first induction current I_kat the first and second induction elements <b>131</b>, <b>132</b>, and the current direction is flowing out of the first induction element <b>131</b>, calculated by:

0000<maths id="MATH-US-00002" num="00002"><math overflow="scroll"><mrow><msub><mi>I</mi><mi>k</mi></msub><mo>=</mo><mrow><msub><mi>I</mi><mn>4</mn></msub><mo>·</mo><mi>K</mi><mo>·</mo><msqrt><mfrac><mrow><mn>2</mn><mo></mo><msub><mi>L</mi><mn>3</mn></msub></mrow><msub><mi>L</mi><mn>0</mn></msub></mfrac></msqrt></mrow></mrow></math></maths>

0029wherein I₄is the current flowing through the fourth induction elements <b>134</b>, K is the coupling coefficient, and L₀=L₁=L₂, which means the first and second induction elements <b>131</b>, <b>132</b> have the inductance values L₁, L₂respectively, that are equal to each other.

0030When the preferred embodiment is operating at a second cycle (the negative half cycle of the input signal), there is created a second induction current I_k′ at the first and second induction elements <b>131</b>, <b>132</b>, where the second induction current I_k′ is equal to the first induction current I_k. The current direction of the second induction current I_k′ is flowing into the second induction element <b>132</b>.

0031From the above, assuming the first transistor <b>11</b> has the third terminal voltage V₁=V_IN, and the second transistor <b>12</b> has the third terminal voltage V₂=0, a first differential voltage V_o1(from the first terminal of the first induction element) and a second differential voltage V_o2(from the second terminal of the second induction element) can be calculated as follows:

0000<maths id="MATH-US-00003" num="00003"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>V</mi><mrow><mi>o</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><mo>=</mo><mi /><mo></mo><mrow><mrow><mo>-</mo><mrow><mo>(</mo><mrow><mrow><msub><mi>g</mi><mrow><mi>m</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><mo></mo><msub><mi>V</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow><mo>-</mo><msub><mi>I</mi><mi>k</mi></msub></mrow><mo>)</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo></mo><mrow><mrow><mo>-</mo><mrow><mo>(</mo><mrow><mrow><msub><mi>g</mi><mrow><mi>m</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><mo></mo><msub><mi>V</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow><mo>-</mo><mrow><msub><mi>I</mi><mn>4</mn></msub><mo>·</mo><mi>K</mi><mo>·</mo><msqrt><mfrac><mrow><mn>2</mn><mo></mo><msub><mi>L</mi><mn>3</mn></msub></mrow><msub><mi>L</mi><mn>0</mn></msub></mfrac></msqrt></mrow></mrow><mo>)</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>0</mn></mrow></msub></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo></mo><mrow><mrow><mo>-</mo><mrow><mo>[</mo><mrow><mrow><msub><mi>g</mi><mrow><mi>m</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><mo></mo><mrow><mo>(</mo><mrow><msub><mi>V</mi><mi>IN</mi></msub><mo>-</mo><msub><mi>V</mi><mi>X</mi></msub></mrow><mo>)</mo></mrow></mrow><mo>-</mo><mrow><msub><mi>I</mi><mn>4</mn></msub><mo>·</mo><mi>K</mi><mo>·</mo><msqrt><mfrac><mrow><mn>2</mn><mo></mo><msub><mi>L</mi><mn>3</mn></msub></mrow><msub><mi>L</mi><mn>0</mn></msub></mfrac></msqrt></mrow></mrow><mo>]</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>0</mn></mrow></msub></mrow></mrow></mtd></mtr></mtable></math></maths><maths id="MATH-US-00003-2" num="00003.2"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>V</mi><mrow><mi>o</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub><mo>=</mo><mi /><mo></mo><mrow><mrow><mo>-</mo><mrow><mo>(</mo><mrow><mrow><msub><mi>g</mi><mrow><mi>m</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub><mo></mo><msub><mi>V</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow><mo>+</mo><msub><mi>I</mi><mi>k</mi></msub></mrow><mo>)</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo></mo><mrow><mrow><mo>-</mo><mrow><mo>(</mo><mrow><mrow><msub><mi>g</mi><mrow><mi>m</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub><mo></mo><msub><mi>V</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow><mo>-</mo><mrow><msub><mi>I</mi><mn>4</mn></msub><mo>·</mo><mi>K</mi><mo>·</mo><msqrt><mfrac><mrow><mn>2</mn><mo></mo><msub><mi>L</mi><mn>3</mn></msub></mrow><msub><mi>L</mi><mn>0</mn></msub></mfrac></msqrt></mrow></mrow><mo>)</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>0</mn></mrow></msub></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo></mo><mrow><mrow><mo>-</mo><mrow><mo>[</mo><mrow><mrow><msub><mi>g</mi><mrow><mi>m</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub><mo></mo><mrow><mo>(</mo><mrow><mo>-</mo><msub><mi>V</mi><mi>X</mi></msub></mrow><mo>)</mo></mrow></mrow><mo>+</mo><mrow><msub><mi>I</mi><mn>4</mn></msub><mo>·</mo><mi>K</mi><mo>·</mo><msqrt><mfrac><mrow><mn>2</mn><mo></mo><msub><mi>L</mi><mn>3</mn></msub></mrow><msub><mi>L</mi><mn>0</mn></msub></mfrac></msqrt></mrow></mrow><mo>]</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>0</mn></mrow></msub></mrow></mrow></mtd></mtr></mtable></math></maths>

0032where g_m1, g_m2are the transconductance coefficients of the first and second transistors <b>11</b>, <b>12</b>, respectively. V_gs1is the voltage between the third and first terminals of the first transistor <b>11</b>. V_gs2is the voltage between the third and first terminals of the second transistor <b>12</b>. I_kis the first inductive current. Z_L1/Z_L2are the equivalent impedances of the first and second induction elements <b>131</b>, <b>132</b>, and Z_L1=Z_L2=Z_L0. V_Xis the voltage at the node X.

0033Assuming g_m1=g_m2=g_m, then the voltage V_Xat the node X is as follows:

0000<maths id="MATH-US-00004" num="00004"><math overflow="scroll"><mrow><msub><mi>V</mi><mi>X</mi></msub><mo>=</mo><mrow><mrow><mfrac><mrow><mrow><mo>(</mo><mrow><msub><mi>g</mi><mi>m</mi></msub><mo>+</mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow><mo>)</mo></mrow><mo>·</mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>3</mn></mrow></msub></mrow><mrow><mn>1</mn><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mrow><mn>2</mn><mo></mo><msub><mi>g</mi><mi>m</mi></msub></mrow><mo>+</mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><mo>+</mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow><mo>)</mo></mrow><mo>·</mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>3</mn></mrow></msub></mrow></mrow></mfrac><mo>·</mo><msub><mi>V</mi><mi>IN</mi></msub></mrow><mo>=</mo><mrow><mi>A</mi><mo>·</mo><msub><mi>V</mi><mi>IN</mi></msub></mrow></mrow></mrow></math></maths>

0034and the current I₄flowing through the fourth induction elements <b>134</b> is as follows:

0000<maths id="MATH-US-00005" num="00005"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>I</mi><mn>4</mn></msub><mo>=</mo><mi /><mo></mo><mrow><mrow><msub><mi>g</mi><mi>m</mi></msub><mo></mo><mrow><mo>(</mo><msub><mi>V</mi><mi>IN</mi></msub><mo>)</mo></mrow></mrow><mo>+</mo><mrow><mrow><mo>(</mo><mrow><msub><mi>V</mi><mi>IN</mi></msub><mo>-</mo><msub><mi>AV</mi><mi>IN</mi></msub></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mo>-</mo><msub><mi>AV</mi><mi>IN</mi></msub></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo></mo><mrow><mrow><mo>[</mo><mrow><msub><mi>g</mi><mi>m</mi></msub><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow></mrow><mo>]</mo></mrow><mo></mo><msub><mi>V</mi><mi>IN</mi></msub></mrow></mrow></mtd></mtr></mtable></math></maths>

0035where Y_gs1is the equivalent reactance between the third terminal and the first terminal of the first transistor <b>11</b>. Y_gs2is the equivalent reactance between the third terminal and the first terminal of the second transistor <b>12</b>. Z_L3is the equivalent impedance of the third induction element <b>133</b>. A is a matching coefficient.

0036Therefore, according to the above equations, the relationship of the first and second differential voltages V_o1, V_o2to the input voltage V_INcan be obtained as follows:

0000<maths id="MATH-US-00006" num="00006"><math overflow="scroll"><mrow><mfrac><msub><mi>V</mi><mrow><mi>o</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><msub><mi>V</mi><mi>IN</mi></msub></mfrac><mo>=</mo><mrow><mrow><mo>-</mo><mrow><mo>{</mo><mrow><mrow><msub><mi>g</mi><mi>m</mi></msub><mo></mo><mrow><mo>(</mo><mrow><mn>1</mn><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow></mrow><mo>-</mo><mrow><mrow><mo>[</mo><mrow><msub><mi>g</mi><mi>m</mi></msub><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow></mrow><mo>]</mo></mrow><mo>·</mo><mi>K</mi><mo>·</mo><msqrt><mfrac><mrow><mn>2</mn><mo></mo><msub><mi>L</mi><mn>3</mn></msub></mrow><msub><mi>L</mi><mn>0</mn></msub></mfrac></msqrt></mrow></mrow><mo>}</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>0</mn></mrow></msub></mrow></mrow></math></maths><maths id="MATH-US-00006-2" num="00006.2"><math overflow="scroll"><mrow><mfrac><msub><mi>V</mi><mrow><mi>o</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub><msub><mi>V</mi><mi>IN</mi></msub></mfrac><mo>=</mo><mrow><mrow><mo>-</mo><mrow><mo>{</mo><mrow><mrow><msub><mi>g</mi><mi>m</mi></msub><mo></mo><mrow><mo>(</mo><mrow><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow></mrow><mo>+</mo><mrow><mrow><mo>[</mo><mrow><msub><mi>g</mi><mi>m</mi></msub><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow></mrow><mo>]</mo></mrow><mo>·</mo><mi>K</mi><mo>·</mo><msqrt><mfrac><mrow><mn>2</mn><mo></mo><msub><mi>L</mi><mn>3</mn></msub></mrow><msub><mi>L</mi><mn>0</mn></msub></mfrac></msqrt></mrow></mrow><mo>}</mo></mrow></mrow><mo></mo><msub><mi>Z</mi><mrow><mi>L</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>0</mn></mrow></msub></mrow></mrow></math></maths>

0037According to the above description, when there is a gain mismatch in the single-to-differential conversion circuit of the preferred embodiment (i.e., the equivalent impedance Z_gs1between the third and first terminals of the first transistor <b>11</b>, the equivalent impedance Z_gs2between the third and first terminals of the second transistors <b>12</b>, and/or the equivalent impedance Z_L3of the third induction element <b>133</b> are not big enough in magnitude), the matching coefficient A will have a value less than 0.5. If the first to third induction elements <b>131</b>-<b>133</b> do not electrically couple (i.e., the coupling coefficient K is 0), then

0000<maths id="MATH-US-00007" num="00007"><math overflow="scroll"><mrow><mrow><mo></mo><mfrac><msub><mi>V</mi><mrow><mi>o</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub><msub><mi>V</mi><mi>IN</mi></msub></mfrac><mo></mo></mrow><mo>></mo><mrow><mo></mo><mfrac><msub><mi>V</mi><mrow><mi>o</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub><msub><mi>V</mi><mi>IN</mi></msub></mfrac><mo></mo></mrow></mrow></math></maths>

0038Therefore, the first differential voltage V_o1and the second differential voltage V_o2will not balance.

0039If during the design, the coupling coefficient K of the transforming unit <b>13</b> is

0000<maths id="MATH-US-00008" num="00008"><math overflow="scroll"><mrow><mrow><mi>K</mi><mo>=</mo><mfrac><msub><mi>g</mi><mi>m</mi></msub><mrow><mrow><mn>2</mn><mo></mo><mrow><mo>[</mo><mrow><msub><mi>g</mi><mi>m</mi></msub><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mn>1</mn><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>1</mn></mrow></msub></mrow><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mo>-</mo><mi>A</mi></mrow><mo>)</mo></mrow><mo></mo><msub><mi>Y</mi><mrow><mi>gs</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn></mrow></msub></mrow></mrow><mo>]</mo></mrow></mrow><mo>·</mo><msqrt><mfrac><mrow><mn>2</mn><mo></mo><msub><mi>L</mi><mn>3</mn></msub></mrow><msub><mi>L</mi><mn>0</mn></msub></mfrac></msqrt></mrow></mfrac></mrow><mo>,</mo></mrow></math></maths>

0040the first electrical coupling can decrease the absolute value of the first differential voltage V_o1, and the second electrical coupling can increase the absolute value of the second differential voltage V_o2. The first differential voltage V_o1and the second differential voltage V_o2are then equal in magnitude (i.e., the absolute value of both first and second differential voltages V_o1, V_o2are equal), and 180° out of phase.

0041Therefore, the coupling coefficient K of the transforming unit <b>13</b> can be used to compensate the gain mismatch of the single-to-differential conversion circuit. There may be some variance during circuit operations and differences in the circuit components. The transconductance coefficient g_m1of the first transistor <b>11</b> may not be equal to the transconductance coefficient g_m2of the second transistor <b>12</b>, the inductance L₁of the first induction element <b>131</b> may not be equal to the inductance L₂of the second induction element <b>132</b>, and the first and second coupling parameters between the first and second induction elements <b>131</b>, <b>132</b> and the third induction element <b>133</b> and the related electrical couplings may be different. However, the present embodiment discloses the method to compensate the gain mismatch problem in the single-to-differential conversion circuit.

0042According to the foundation of the above description, if the present embodiment is to be applied to a high frequency situation, for example, anti-collision radar for cars (approximately operating at 77 GHz), an embodiment of the transforming unit <b>13</b> of the single-to-differential conversion circuit is shown in <figref idref="DRAWINGS">FIG. 5</figref>, which uses a transmission line model.

0043Referring to both <figref idref="DRAWINGS">FIGS. 3 and 5</figref>, a first transmission line section <b>91</b> replaces the first induction element <b>131</b>, a second transmission line section <b>92</b> replaces the second induction element <b>132</b>, and a third transmission line section <b>93</b> replaces the third induction element <b>133</b>. The lengths of the first and second transmission line sections <b>91</b>, <b>92</b> are one eight of the wavelength of the input signal (λ/8). The length of the third transmission line section <b>93</b> is one quarter of the wavelength of the input frequency (λ/4). The coupling effect of the first, second and third transmission line sections <b>91</b>, <b>92</b> and <b>93</b> can compensate the gain mismatching problem in the single-to-differential conversion circuit.

0044If the present embodiment is to be applied to a mid-to-low frequency situation, an embodiment of the transforming unit <b>13</b> of the single-to-differential conversion circuit is shown in <figref idref="DRAWINGS">FIG. 6</figref>, which uses a transformer model.

0045Referring to both <figref idref="DRAWINGS">FIGS. 3 and 6</figref>, a first loop unit <b>81</b> replaces the first induction unit <b>131</b> and the second induction unit <b>132</b>. A second loop unit <b>82</b> replaces the third induction unit <b>133</b>. The first loop unit <b>81</b> is disposed to surround the second loop unit <b>82</b> in a co-planar manner. The second loop unit <b>82</b> is spaced apart from the first loop unit <b>81</b> by a first distance d. The distance d influences the coupling parameter K, and the shorter the distance d, the bigger will be the coupling parameter K. Therefore, during the design, the adjustment of the first distance d changes the coupling parameter K to compensate the gain mismatching problem of the single-to-differential conversion circuit.

0046Referring to both <figref idref="DRAWINGS">FIG. 3</figref> and <figref idref="DRAWINGS">FIG. 7</figref>, which is similar to the implementation of <figref idref="DRAWINGS">FIG. 6</figref>, but where the first loop unit <b>81</b> is disposed to surround the second loop unit <b>82</b> in a non-coplanar manner, the second loop unit <b>82</b> is spaced apart from the first loop unit <b>81</b> by a second distance b. The distance b influences the coupling parameter K. The shorter the distance b, the bigger will be the coupling parameter K. Therefore, during the design, the adjustment of the second distance b can change the coupling parameter K to compensate the gain mismatching problem of the single-to-differential conversion circuit.

0047On an extra note, <figref idref="DRAWINGS">FIG. 5</figref> to <figref idref="DRAWINGS">FIG. 7</figref> are three derivations of the transforming unit <b>13</b> in the single-to-differential conversion circuit when used in different products. The invention is not limited to these embodiments.

0048Worth noting is that the first induction unit <b>131</b> and the third induction unit <b>133</b> can also undergo a first electrical coupling according to a first coupling parameter, and the second induction unit <b>132</b> and the third induction unit <b>133</b> can also undergo a second electrical coupling according to a second coupling parameter. When designing, the first and second coupling parameters can be changed to compensate for the gain mismatching problem of the single-to-differential conversion circuit.

0049According to the above description, the embodiments can use electrical coupling to compensate a gain mismatching problem in a single-to-differential conversion circuit, thereby achieving the goal of the present invention.

0050While the present invention has been described in connection with what are considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.