US20120249181A1

Latch circuit and clock control circuit

Claim Score by NHIP

Abstract

A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.

US20120249181A1, drawing sheet 1 — Sheet 1 of 25

Term

Projected expiry 30 March 2030.

13 claims: 4 independent, 9 dependent

1
Broadest claimClaim Score 78, broad(NHIP)A latch circuit comprising:a latch unit that holds and output input data of 0 or 1;and a clock propagation suppressing unit that compares input data input to the latch unit with output data output from the latch unit, and prevent a clock signal externally input from propagating to the latch unit when it is detected that the data match at 0, or prevent a clock signal externally input from propagating to the latch unit when it is detected that the data match at 1.
4
A latch circuit comprising:a latch unit that holds and output input data of 0 or 1;a data matching detection unit that compares input data input to the latch unit with output data output from the latch unit, and detecting either that the data match at 0 or that the data match at 1;and a clock propagation suppressing unit that prevents a clock signal externally input from propagating to the latch unit when data matching in the case that the data match at 0 or the case that the data match at 1 is detected by the data matching detection unit.
8
A clock control circuit connected to a latch circuit which holds and outputs input data of 0 or 1, the clock control circuit comprising:a clock propagation suppressing unit that compares input data input to the latch circuit with output data output from the latch circuit, and prevent a clock signal externally input from propagating to the latch circuit when it is detected that the data match at 0, or prevent a clock signal externally input from propagating to the latch circuit when it is detected that the data match at 1.
10
A clock control circuit connected to a latch circuit which holds and outputs input data of 0 or 1, the clock control circuit comprising:a data matching detection unit that compares input data input to the latch unit with output data output from the latch unit, and detect either that the data match at 0 or that the data match at 1;a clock propagation suppressing unit that prevents an clock signal externally input from propagating to the latch unit when data matching in the case that the data match at 0 or the case that the data match at 1 is detected by the data matching detection unit.

Independent claims4

160 paragraphs in 11 sections, as filed

0001This application is a continuation application of International PCT Application No. PCT/JP2009/007039, filed on Dec. 18, 2009, the entire contents of which are incorporated herein by reference.

FIELD

0002The present invention relates to a latch circuit and a clock control circuit.

BACKGROUND

0003Conventionally, clock gating has been performed on an unused latch circuit to reduce the power consumption of an electric circuit. The clock gating refers to stopping the supply of a clock to a portion where and when it is known in advance that an input is not changed. However, in a latch circuit to be used, the supply of a clock cannot be stopped, thereby failing in reducing the power consumption.

0004Then, input/output data signals of the latch circuit are compared with each other, and when they match, the propagation of an input clock into the inner portion of the latch circuit is suppressed. <figref idref="DRAWINGS">FIG. 1</figref> illustrates an example of a latch circuit having the function of suppressing the clock propagation into the internal portion.

0005A latch circuit 10 illustrated in <figref idref="DRAWINGS">FIG. 1</figref> includes a data input terminal 11, a data output terminal 12, a clock input terminal 13 for input of a inverted clock, and an IH (inhibit) pin 14 for input of a control signal for suppressing the clock propagation in a latch. The latch circuit provided with an IH pin in <figref idref="DRAWINGS">FIG. 1</figref> is referred to as the IH latch circuit 10.

0006<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of the circuit in <figref idref="DRAWINGS">FIG. 1</figref>. The clock input terminal 13 and the IH pin 14 are connected to a clock internal propagation suppressing unit 21, and an internal clock signal XCLK for which the propagation control of a clock has been performed by the clock internal propagation suppressing unit 21 is input to a latch unit 22. The latch unit 22 holds an input value outputs it. The internal clock signal XCLK and the data signal from the data input terminal 11 are input to the latch unit 22, and the latch unit 22 outputs the data signal to the data output terminal 12.

0007<figref idref="DRAWINGS">FIG. 3</figref> is an example of a detailed configuration of the IH latch circuit 10 illustrated in <figref idref="DRAWINGS">FIGS. 1 and 2</figref>. The circuit includes P-channel MOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistors) P1, P2, P3, P4, P5, P6, P7, and P8, and N-channel MOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistors) N1, N2, n3, N4, N5, N6, N7, and N8. In the descriptions below, the P-channel MOSFET is described as a PMOS transistor, and the N-channel MOSFET is described as an NMOS transistor.

0008The source terminal of the PMOS transistor P1 is connected to a high-voltage side power supply terminal (VDD), and the gate terminal is connected to the IH pin 14. The source terminal of the PMOS transistor P2 is connected to the drain terminal of the PMOS transistor P1, and the gate terminal is connected to the clock input terminal 13. The source terminal of the NMOS transistor N1 is connected to the low-voltage side power supply terminal (VSS), the gate terminal is connected to the clock input terminal 13, and the drain terminal is connected to the drain terminal of the PMOS transistor P2. The source terminal of the NMOS transistor N2 is connected to the low-voltage side power supply terminal, the gate terminal is connected to the IH pin 14, and the drain terminal is connected to the drain terminals of the PMOS transistor P2 and the NMOS transistor N1.

0009The portion (enclosed by the dotted lines in <figref idref="DRAWINGS">FIG. 3</figref>) configured by the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 corresponds to the clock internal propagation suppressing unit 21 in <figref idref="DRAWINGS">FIG. 2</figref>. That is, this portion controls the internal propagation of a clock signal. When the control signal for suppression of the internal propagation of the clock signal (hereafter referred to as an IH signal) indicates a high level (hereafter described by H), the PMOS transistor P1 is placed in the OFF state, the NMOS transistor N2 is placed in the ON state, and the internal clock signal XCLK is constantly placed at the low level (hereafter described by L). That is, when the IH signal indicates H, the propagation of the clock signal from the clock input terminal 13 is suppressed. On the other hand, when the IH signal indicates L, and the inverted clock input from the clock input terminal 13 indicates L, the PMOS transistors P1 and P2 are placed in the ON state, the NMOS transistors N1 and N2 are placed in the OFF state, and the internal clock signal XCLK indicates H. Furthermore, if the IH signal indicates H and the inverted clock input from the clock input terminal 13 indicates H, then the PMOS transistors P1 and P2 are placed in the OFF state, the NMOS transistors N1 and N2 are placed in the ON state, and the internal clock signal XCLK indicates L. Thus, when the IH signal indicates L, the inverted result (signal) of the inverted clock input from the clock input terminal 13 is propagated as the internal clock signal XCLK to the latch unit 22.

0010The portion corresponding to the latch unit 22 in <figref idref="DRAWINGS">FIG. 2</figref> is described below.

0011The source terminal of the PMOS transistor P3 is connected to the high-voltage side power supply terminal, and the internal clock signal XCLK is input to the gate terminal. The source terminal of the NMOS transistor N3 is connected to the low-voltage side power supply terminal, the internal clock signal XCLK is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P3. The PMOS transistor P3 and the NMOS transistor N3 configure an inverter (negation circuit).

0012The source terminal of the PMOS transistor P4 is connected to the high-voltage side power supply terminal, and the gate terminal is connected to the data input terminal 11. The source terminal of the NMOS transistor N4 is connected to the low-voltage side power supply terminal, the gate terminal is connected to the data input terminal 11, and the drain terminal is connected to the drain terminal of the PMOS transistor P4. The PMOS transistor P4 and the NMOS transistor N4 configure an inverter.

0013The source terminal of the PMOS transistor P5 is connected to the drain terminals of the PMOS transistor P4 and the NMOS transistor N4, and the gate terminal is connected to the drain terminals of the PMOS transistor P3 and the NMOS transistor N3. The source terminal of the NMOS transistor N5 is connected to the drain terminals of the PMOS transistor P4 and the NMOS transistor N4, and the internal clock signal XCLK is input to the gate terminal. The PMOS transistor P5 and the NMOS transistor N5 as pass transistors configure a transfer gate 20. When the gate terminal of the PMOS transistor P5 indicates N, and the gate terminal of the NMOS transistor N5 indicates H, a signal obtained by inverting the input data signal input from the data output terminal 12 is output as the data signal PCM1.

0014The source terminal of the PMOS transistor P6 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N6 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P6. The PMOS transistor P6 and the NMOS transistor N6 configure an inverter, invert the data signal PCM1, and outputs the data signal PAM1.

0015The source terminal of the PMOS transistor P7 is connected to the high-voltage side power supply terminal, and the data signal PAM1 is input to the gate terminal. The source terminal of the NMOS transistor N7 is connected to the low-voltage side power supply terminal, the data signal PAM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P7. The PMOS transistor P7 and the NMOS transistor N7 configure an inverter, invert the data signal PAM1, and output the data signal PCM1.

0016The loop portion by two inverter circuits configured by the PMOS transistors P6 and P7 and the NMOS transistors N6 and N7 has the function of holding the latch data.

0017The source terminal of the PMOS transistor P8 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N8 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P8. The PMOS transistor P8 and the NMOS transistor N8 configure an inverter, invert the data signal PCM1, and output it to the data output terminal 12.

0018The portion configured by the PMOS transistors P3, P4, P5, P6, P7, and P8 and the NMOS transistors N3, N4, N5, N6, and N7 corresponds to the latch unit 22 in <figref idref="DRAWINGS">FIG. 2</figref>.

0019In the IH latch circuit 10 as illustrated in <figref idref="DRAWINGS">FIGS. 1 through 3</figref>, it is necessary to compare input/output data signals, and input the result to the IH pin 14 as a control signal. In the comparing operation, an ENOR circuit (Exclusive-NOR circuit) and an exclusive-OR circuit (Exclusive-OR circuit)) are used. <figref idref="DRAWINGS">FIG. 4</figref> is an example of using the ENOR circuit 41 in comparing the input/output data signals.

0020As illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, the data signal input from the data input terminal 11 of the IH latch circuit 10 illustrated in <figref idref="DRAWINGS">FIG. 1</figref> and the data signal output to the data output terminal 12 are input to an ENOR circuit 41 for comparison. The result of the data comparison is output to the IH pin 14. The ENOR circuit 41 outputs H if the two input signals match each other, and outputs L if they do not match each other. That is, if the input/output data signals match each other, the H is input to the IH pin 14, and if the input/output data signals do not match each other, the L is input to the IH pin 14. Thus, if the input/output data signals match each other, the internal propagation of the clock of the IH latch circuit 10 is suppressed, and if the input/output data signals do not match each other, the clock is propagated in the IH latch circuit 10.

0021<figref idref="DRAWINGS">FIG. 5</figref> is a timing chart of the case in which the IH pin 14 is clipped (pulled down) to L (connected to the low-voltage side power supply terminal), that is, a timing chart indicating the state in which there is no IH pin. <figref idref="DRAWINGS">FIG. 6</figref> is a timing chart of the case in which the result of inputting the input/output data signals of the IH latch circuit 10 to the ENOR circuit 41 is input to the IH pin 14 as with the circuit illustrated in <figref idref="DRAWINGS">FIG. 4</figref>.

0022When the IH pin 14 is clipped to L, the clock propagation in the IH latch circuit 10 is not controlled. Therefore, the internal clock signal XCLK is a inverted signal of the signal input to the clock input terminal 13 as illustrated in the timing chart in <figref idref="DRAWINGS">FIG. 5</figref>. On the other hand, when the IH pin 14 is connected to the output of the ENOR circuit 41, the clock propagation in the IH latch circuit 10 is controlled depending on whether or not the input/output data signals of the IH latch circuit 10 match each other. As illustrated in the timing chart in <figref idref="DRAWINGS">FIG. 6</figref>, when the input data signal D and the output data signal M indicate L (in the case of timing 1), and when the input data signal D and the output data signal M indicate H (in the case of timing 3), the IH1 as an output signal from the ENOR circuit 41 indicates H. Thus, the internal clock signal XCLK in the IH latch circuit 10 indicates L. As described above, since the internal propagation of the clock signal can be suppressed when the input/output data signals match in the circuit illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, the power consumption of the IH latch circuit 10 can be reduced.

0023However, the ENOR circuit 41 for comparison of the input/output data signals requires at least 10 transistors as illustrated in <figref idref="DRAWINGS">FIG. 7</figref>. This implies the problem of a large number of transistors configuring the circuit. In addition, as illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, the input data signal input from the input terminal A2 requires driving two transistors, that is, a PMOS transistor P71 and an NMOS transistor N71. However, the input data signal input from the input terminal Al requires driving four transistors, that is, PMOS transistors P74 and P75, and NMOS transistors N73 and N74. Thus, the input capacitance (fan in capacitance) driven by an input data signal is approximately double that of the normal circuit, and the corresponding power consumption increases.

DOCUMENTS OF PRIOR ART

0024Patent Documents

0025Patent Document 1: Japanese Laid-open Patent Publication No. 10-290143

0026Patent Document 2: Japanese Laid-open Patent Publication No. 4-86116

0027Patent Document 3: Japanese Laid-open Patent Publication No. 11-340795

0028Patent Document 4: Japanese Laid-open Patent Publication No. 2000-77983

0029Patent Document 5: Japanese Laid-open Patent Publication No. 2006-229745

0030Patent Document 6: Japanese Laid-open Patent Publication No. 9-214297

SUMMARY

0031According to an aspect of the invention, a latch circuit includes a latch unit, a data matching detection unit, and a clock propagation suppressing unit. The latch unit holds and outputs input data. The data matching detection unit compares the input data input to the latch unit with the output data output from the latch unit, and detects only that they match at L (0) or that they match at H (1). The clock propagation suppressing unit prevents the clock signal input externally from being propagated to the latch device when data matching is detected as matching the input data and the output data at L (0) or at H (1).

0032According to the aspect above, by configuring the data matching detection device, which has been conventionally configured by an EOR circuit and an ENOR circuit, by a negative logical sum (NOR) circuit or a logical product (AND) circuit, the number of transistors configuring a circuit can be minimized. Thus, the power consumption can be reduced.

0033According to an aspect of the invention, a latch circuit includes a latch unit, a data matching detection and clock propagation suppressing unit. The latch unit holds and outputs an input value. The data matching detection and clock propagation suppressing unit compares the input data input to the latch unit with the output data output from the latch unit, and prevents the clock signal externally input only when the matching of the data at L (0) is detected from propagating to the latch unit, or prevents the clock signal externally input only when the matching of the data at H (1) is detected from propagating to the latch unit.

0034According to the aspect above, the configuration of the circuits of the data matching detection and clock propagation suppressing unit can be optimized, and the number of transistors configuring the circuit can be reduced. Thus, the power consumption can be reduced.

0035The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

0036It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

0037<figref idref="DRAWINGS">FIG. 1</figref> illustrates an IH latch circuit having an IH pin;

0038<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of the IH latch circuit;

0039<figref idref="DRAWINGS">FIG. 3</figref> illustrates an example of the configuration of the IH latch circuit;

0040<figref idref="DRAWINGS">FIG. 4</figref> illustrates a circuit configured by an IH latch circuit and an ENOR circuit;

0041<figref idref="DRAWINGS">FIG. 5</figref> is a timing chart of the IH latch circuit when the IH pin is clipped to L;

0042<figref idref="DRAWINGS">FIG. 6</figref> is a timing chart of the IH latch circuit when the output from the ENOR circuit is input to the IH pin

0043<figref idref="DRAWINGS">FIG. 7</figref> is an example of the configuration of the ENOR circuit;

0044<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram of the embodiment 1 of the present invention;

0045<figref idref="DRAWINGS">FIG. 9</figref> is an example of the circuit of a clock internal propagation suppressing unit 82 and a latch unit 83 in <figref idref="DRAWINGS">FIG. 8</figref>;

0046<figref idref="DRAWINGS">FIG. 10</figref> is a circuit example 1;

0047<figref idref="DRAWINGS">FIG. 11</figref> is a timing chart of the circuit example 1;

0048<figref idref="DRAWINGS">FIG. 12</figref> is an example of the detailed configuration of a NOR circuit;

0049<figref idref="DRAWINGS">FIG. 13</figref> is a circuit example 2;

0050<figref idref="DRAWINGS">FIG. 14</figref> is a timing chart of the circuit example 2;

0051<figref idref="DRAWINGS">FIG. 15</figref> is an example of the detailed configuration of an AND circuit;

0052<figref idref="DRAWINGS">FIG. 16</figref> is a block diagram of the embodiment 2 of the present invention;

0053<figref idref="DRAWINGS">FIG. 17</figref> is a circuit example 3;

0054<figref idref="DRAWINGS">FIG. 18</figref> is an example of the detailed configuration of the circuit example 3;

0055<figref idref="DRAWINGS">FIG. 19</figref> is a circuit example 4;

0056<figref idref="DRAWINGS">FIG. 20</figref> is an example of the detailed configuration of the circuit example 4;

0057<figref idref="DRAWINGS">FIG. 21</figref> is a table of the power measured by each operation pattern on the circuit examples 1 through 4 and an example using an ENOR circuit;

0058<figref idref="DRAWINGS">FIG. 22</figref> illustrates an example of obtaining average power etc. from the measurement result in <figref idref="DRAWINGS">FIG. 20</figref>; and

0059<figref idref="DRAWINGS">FIG. 23</figref> is a table of the leakage power measured by each operation pattern on the circuit examples 1 through 4 and an example using an ENOR circuit.

DESCRIPTION OF EMBODIMENTS

0060The embodiments of the latch circuit and the clock control circuit are described below with reference to the attached drawings. First, the embodiment 1 is described with reference to <figref idref="DRAWINGS">FIGS. 8 through 15</figref>, and then the embodiment 2 is described with reference to <figref idref="DRAWINGS">FIGS. 16 through 20</figref>. Finally, the power consumption of the circuit example disclosed below is studied with reference to <figref idref="DRAWINGS">FIGS. 21</figref>, 22, and 23.

0061Embodiment 1

0062<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram of the latch circuit and the clock control circuit according to the embodiment 1.

0063The latch circuit according to the embodiment 1 includes a data matching detection unit 81, a clock internal propagation suppressing unit 82, and a latch unit 83. The clock control circuit includes the clock internal propagation suppressing unit 82.

0064The clock internal propagation suppressing unit 82 and the latch unit 83 have the same operations as the clock internal propagation suppressing unit 21 and the latch unit 22 in <figref idref="DRAWINGS">FIG. 2</figref>, respectively. That is, the clock internal propagation suppressing unit 82 controls the propagation of the clock depending on the output result of the data matching detection unit 81, and the latch unit 83 holds and outputs an input value.

0065<figref idref="DRAWINGS">FIG. 9</figref> is an example of the configuration of the circuit of the clock internal propagation suppressing unit 82 and the latch unit 83.

0066The circuit includes PMOS transistors P201, P202, P203, P204, P205, P206, P207, and P208, and NMOS transistors N201, N202, N203, N204, N205, N206, N207, and N208.

0067The source terminal of the PMOS transistor P201 is connected to the high-voltage side power supply terminal, the gate terminal is connected to an IH pin 87. The source terminal of the PMOS transistor P202 is connected to the drain terminal of the PMOS transistor P201, and the gate terminal is connected to a clock input terminal 84. The source terminal of the NMOS transistor N201 is connected to the low-voltage side power supply terminal, the gate terminal is connected to the clock input terminal 84, and the drain terminal is connected to the drain terminal of the PMOS transistor P202. The source terminal of the NMOS transistor N202 is connected to the low-voltage side power supply terminal, the gate terminal is connected to the IH pin 87, and the drain terminal is connected to the drain terminals of the PMOS transistor P202 and the NMOS transistor N201.

0068The portion (enclosed by the dotted lines in <figref idref="DRAWINGS">FIG. 9</figref>) configured by the PMOS transistors P201 and P202 and the NMOS transistors N201 and N202 corresponds to the clock internal propagation suppressing unit 82 in <figref idref="DRAWINGS">FIG. 8</figref>. That is, the portion controls the internal propagation of the clock signal. When the IH signal as a control signal for suppression of the internal propagation of a clock signal indicates H, the PMOS transistor P201 is placed in the OFF state, the NMOS transistor N202 is placed in the ON state, and the internal clock signal XCLK constantly indicates L. That is, when the IH signal indicates H, the propagation of the clock signal from the clock input terminal 84 is suppressed. On the other hand, if the IH signal indicates L, and the inverted clock input from the clock input terminal 84 indicates L, then the PMOS transistors P201 and P202 are placed in the ON state, the NMOS transistors N201 and N202 are placed in the OFF state, and the internal clock signal XCLK indicates H. If the IH signal indicates H, and the inverted clock input from the clock input terminal 84 indicates H, then the PMOS transistors P201 and P202 are placed in the OFF state, the NMOS transistors N201 and N202 are placed in the ON state, and the internal clock signal XCLK indicates L. Thus, when the IH signal indicates L, the inverted result (signal) of the inverted clock input from the clock input terminal 84 propagates as the internal clock signal XCLK to the latch unit 83.

0069The portion corresponding to the latch unit 83 in <figref idref="DRAWINGS">FIG. 8</figref> is described below.

0070The source terminal of the PMOS transistor P203 is connected to the high-voltage side power supply terminal, the internal clock signal XCLK is input to the gate terminal. The source terminal of the NMOS transistor N203 is connected to the low-voltage side power supply terminal, the internal clock signal XCLK is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P203. The PMOS transistor P203 and the NMOS transistor N203 configure an inverter.

0071The source terminal of the p204 is connected to the high-voltage side power supply terminal, and the gate is connected to a data input terminal 85. The source terminal of the NMOS transistor N204 is connected to the low-voltage side power supply terminal, the gate terminal is connected to the data input terminal 85, and the drain terminal is connected to the drain terminal of the PMOS transistor P204. The PMOS transistor P204 and the NMOS transistor N204 configure an inverter.

0072The source terminal of the PMOS transistor P205 is connected to the drain terminals of the PMOS transistor P204 and the NMOS transistor N204, the gate terminal is connected to the drain terminals of the PMOS transistor P203 and the NMOS transistor N203. The source terminal of the NMOS transistor N205 is connected to the drain terminals of the PMOS transistor P204 and the NMOS transistor N204, and the internal clock signal XCLK is input to the gate terminal. The PMOS transistor P205 and the NMOS transistor N205 which are pass transistors configure a transfer gate 200. The signal obtained by inverting the input data signal input from the data input terminal 85 when the gate terminal of the PMOS transistor P205 indicates L and the gate terminal of the NMOS transistor N205 indicates H is output as the data signal PCM1.

0073The source terminal of the PMOS transistor P206 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N206 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P206. The PMOS transistor P206 and the NMOS transistor N206 configure an inverter, invert the data signal PCM1, and output the data signal PAM1.

0074The source terminal of the PMOS transistor P207 is connected to the high-voltage side power supply terminal, and the data signal PAM1 is input to the gate terminal. The source terminal of the NMOS transistor N207 is connected to the low-voltage side power supply terminal, the data signal PAM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P207. The PMOS transistor P207 and the NMOS transistor N207 configure an inverter, invert the data signal PAM1, and output the data signal PCM1.

0075The loop portion by two inverter circuits configured by the PMOS transistors P206 and P207 and the NMOS transistors N206 and N207 has the function of holding latch data.

0076The source terminal of the PMOS transistor P208 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N208 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P208. The PMOS transistor P208 and the NMOS transistor N208 configure an inverter, invert the data signal PCM1, and output the resultant signal to the data output terminal 86.

0077The portion configured by the PMOS transistors P203, P204, P205, P206, P207, and P208 and the NMOS transistor N203, N204, N205, N206, and N207 corresponds to the latch unit 83 in <figref idref="DRAWINGS">FIG. 8</figref>.

0078Back in <figref idref="DRAWINGS">FIG. 8</figref>, the input data is input from the data input terminal 85 to the data matching detection unit 81, the output data signal is input from the data output terminal 86, and the IH signal for control of the clock propagation in the latch circuit is output to the clock internal propagation suppressing unit 82. The IH signal and the signal from the clock input terminal 84 are input to the clock internal propagation suppressing unit 82, and the clock internal propagation suppressing unit 82 outputs the internal clock signal XCLK to the latch unit 83.

0079The data matching detection unit 81 compares the input data signal with the output data signal, and outputs an IH signal at H when the data signals match at L or H.

0080Thus, the embodiment 1 replaces the ENOR circuit which conventionally compares the input/output data of the latch unit as illustrated in <figref idref="DRAWINGS">FIG. 4</figref> with the data matching detection unit 81.

0081<figref idref="DRAWINGS">FIG. 10</figref> (circuit example 1) and <figref idref="DRAWINGS">FIG. 13</figref> (circuit example 2) illustrate the circuit example of the embodiment 1.

CIRCUIT EXAMPLE 1

0082First, the circuit example 1 is described below.

0083As illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, in the circuit example 1, the input data signal D input to a data input terminal 92 of the IH latch circuit 10 (which is the same as illustrated in <figref idref="DRAWINGS">FIG. 1</figref>) and the output data signal M output to a data output terminal 93 are input to a NOR (negative logical sum) circuit 91 for comparison. A result of the data comparison (that is, IH2) is output to an IH pin 94. The NOR circuit 91 outputs H as the IH2 signal when the two input signals match at L. That is, only when the latched data indicates L (that is, 0) and the input data indicates L (that is, 0), the internal clock XCLK in the IH latch circuit 10 stops.

0084<figref idref="DRAWINGS">FIG. 11</figref> is a timing chart of the circuit example 1. When the input data signal D and the output data signal M indicate L (in the case of timing 1), the IH2 as an output signal from the NOR circuit 91 indicates H. Thus, the internal clock signal XCLK in the IH latch circuit 10 indicates L. In the circuit example 1, when the input/output data signals match at L (that is, 0), the internal propagation of the clock signal can be suppressed.

0085<figref idref="DRAWINGS">FIG. 12</figref> is an example of the detailed configuration of the NOR circuit 91. As illustrated in <figref idref="DRAWINGS">FIG. 12</figref>, the NOR circuit can be configured by four transistors. Six transistors can be saved as compared with the case in which the input/output data comparison circuit of the latch circuit is configured by ENOR circuits. The input data signal input from the input terminal Al only have to drive two transistors of a PMOS transistor P112 and an NMOS transistor N111, and the input data signal input from the input terminal A2 only have to drive two transistors of a PMOS transistor P111 and an NMOS transistor N112. That is, the input capacitance is lower than the input capacitance (fan-in capacitance) of the ENOR circuit.

CIRCUIT EXAMPLE 2

0087The circuit example 2 is described next with reference to <figref idref="DRAWINGS">FIG. 13</figref>.

0088In the circuit example 2, the input data signal D input to a data input terminal 122 of the IH latch circuit 10 (which is the same as illustrated in <figref idref="DRAWINGS">FIG. 1</figref>) and the output data signal M output to the data output terminal 123 are input to an AND (logical product) circuit 121 for comparison. A result of the data comparison (that is, IH3) is output to an IH pin 124. The AND circuit 121 outputs H when the two input signals match at L. That is, only when the latched data indicates H (that is, 1) and the input data indicates H (that is, 1), the internal clock XCLK stops.

0089<figref idref="DRAWINGS">FIG. 14</figref> is a timing chart of the circuit example 2. When the input data signal D and the output data signal M indicate H (in the case of timing 3), the IH3 as an output signal from the AND circuit 121 indicates H. Thus, the internal clock signal XCLK in the IH latch circuit 10 indicates L. In the circuit example 2, when the input/output data signals match at H (that is, 1), the internal propagation of the clock signal can be suppressed.

0090<figref idref="DRAWINGS">FIG. 15</figref> is an example of the detailed configuration of the AND circuit 112. As illustrated in <figref idref="DRAWINGS">FIG. 15</figref>, the AND circuit can be configured by six transistors. Four transistors can be saved as compared with the case in which the input/output data comparison circuit of the latch circuit is configured by ENOR circuits. The input data signal input from the input terminal A1 only have to drive two transistors of a PMOS transistor P142 and an NMOS transistor N141, and the input data signal input from the input terminal A2 only have to drive two transistors of a PMOS transistor P141 and an NMOS transistor N142. That is, the input capacitance is lower than the input capacitance (fan-in capacitance) of the ENOR circuit.

0091Thus, the embodiment 1 is described above with reference to the circuit examples 1 and 2.

0092In the embodiment 1, the function of detecting the matching of input/output data, which has been conventionally configured by an ENOR circuit, is configured using the NOR circuit or the AND circuit. That is, it has conventionally been detected in both cases in which the input/output data match at L (0) and H (1). However, in the present embodiment, it is detected in one case in which the data match at H (1) or L (0). Thus, in the present embodiment, the data matching at L (0) or H (1) can be detected. However, by configuring the data matching detection unit 81 using the NOR circuit or the AND circuit, the number of transistors required for the circuit of the portion for control of the internal clock propagation of the latch circuit can be smaller than in the conventional circuit. That is, in the case of the NOR circuit, the propagation of the internal clock can be suppressed only when the input data and the output data match at L, and in the case of the AND circuit, the propagation of the internal clock can be suppressed only when the input data and the output data match at H. By replacing the ENOR circuit with the NOR circuit or the AND circuit, the number of transistors configuring the circuit can be reduced. Whether the NOR circuit is used or the AND circuit is used can be determined by considering whether it is probable that the latch value is L (0) or H (1), thereby effectively reducing the power consumption. The study of the power consumption is described later with reference to <figref idref="DRAWINGS">FIGS. 21</figref>, 22, and 23.

0093The embodiment 2 is described below.

Embodiment 2

0094The embodiment 2 realizes the effect equivalent to the circuit according to the embodiment 1 by using the smaller number of transistors. <figref idref="DRAWINGS">FIG. 16</figref> is a block diagram of the latch circuit and the clock control circuit according to the embodiment 2.

0095The latch circuit according to the embodiment 2 includes a data matching detection and clock internal propagation suppression unit 151 and a latch unit 152. The clock control circuit includes the clock internal propagation suppression unit 151.

0096An input data signal from a data input terminal 154 is input to the data matching detection and clock internal propagation suppression unit 151, an output data signal from a data output terminal 155 is input, and a clock signal from a clock input terminal 153 is input. The data matching detection and clock internal propagation suppression unit 151 compares the input data signal with the output data signal, and stops the internal clock signal XCLK only when both data signals match at L or at H. Thus, the data matching detection and clock internal propagation suppression unit 151 outputs the internal clock signal XCLK to the latch unit 152. The latch unit 152 holds and outputs an input value, and corresponds to the latch unit 83 in <figref idref="DRAWINGS">FIG. 8</figref>. Therefore, the detailed descriptions of the latch unit 152 are omitted here.

0097Described below is a circuit example of the embodiment 2.

CIRCUIT EXAMPLE 3

0098A latch circuit 160 of the circuit example 3 in <figref idref="DRAWINGS">FIG. 17</figref> realizes the effect equivalent to the latch circuit using the NOR circuit illustrated in <figref idref="DRAWINGS">FIG. 10</figref>. It is hereafter referred to as a latch 0 circuit.

0099The latch circuit 160 of the circuit example 3 includes a data input terminal 161 to which the input data signal D is input, a data output terminal 162 from which the output data signal M is output, and a clock input terminal 163 to which a inverted clock signal is input.

0100<figref idref="DRAWINGS">FIG. 18</figref> illustrates an example of a detailed circuit of the latch circuit 160.

0101The circuit includes PMOS transistors P171, P172, P173, P174, P175, P176, P177, P178, and P179, and NMOS transistors N171, N172, N173, N174, N175, N176, N177, N178, and N179.

0102In <figref idref="DRAWINGS">FIG. 18</figref>, the wiring from the PCM1 to the PMOS transistor P173 and the NMOS transistor N173 can be started from the inverter provided after M which corresponds to the same logic as the data signal PCM1.

0103The portion other than the enclosure by the dotted lines in <figref idref="DRAWINGS">FIG. 18</figref> corresponds to the latch unit 152, and corresponds to the portion configured by the PMOS transistors P3, P4, P5, P6, P7, and P8, and NMOS transistors N3, N4, N5, N6, and N7. It is described in detail below.

0104The source terminal of the PMOS transistor P175 is connected to the high-voltage side power supply terminal, and the internal clock signal XCLK is input to the gate terminal. The source terminal of the NMOS transistor N175 is connected to the low-voltage side power supply terminal, the internal clock signal XCLK is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P175. The PMOS transistor P175 and the NMOS transistor N175 configure an inverter.

0105The source terminal of the PMOS transistor P174 is connected to the high-voltage side power supply terminal, and the gate terminal is connected to the data input terminal 161. The source terminal of the NMOS transistor N174 is connected to the low-voltage side power supply terminal, and the gate terminal is connected to the data input terminal 161. The PMOS transistor P174 and the NMOS transistor N174 configure an inverter.

0106The source terminal of the PMOS transistor P176 is connected to the drain terminals of the PMOS transistor P174 and the NMOS transistor N174, and the gate terminal is connected to the drain terminals of the PMOS transistor P175 and the NMOS transistor N175. The source terminal of the NMOS transistor N176 is connected to the drain terminals of the PMOS transistor P174 and the NMOS transistor N174, and the internal clock signal XCLK is input to the gate terminal. The PMOS transistor P176 and the NMOS transistor N176 configure a transfer gate terminal, and output as the data signal PCM1 the signal obtained by inverting the input data signal input from the data input terminal 161 when the gate terminal of the PMOS transistor P176 indicates L and the gate terminal of the NMOS transistor N176 indicates H.

0107The source terminal of the PMOS transistor P177 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N177 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P177. The PMOS transistor P177 and the NMOS transistor N177 configure an inverter, invert the data signal PCM1, and output the data signal PAM1.

0108The source terminal of the PMOS transistor P178 is connected to the high-voltage side power supply terminal, and the data signal PAM1 is input to the gate terminal. The source terminal of the NMOS transistor N178 is connected to the low-voltage side power supply terminal, the data signal PAM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P178. The PMOS transistor P178 and the NMOS transistor N178 configure an inverter, invert the data signal PAM1, and output the data signal PCM1.

0109The portion configured by the PMOS transistors P177 and P178 and the NMOS transistors N177 and N178 has the function of holding latch data.

0110The source terminal of the PMOS transistor P179 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N179 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P179. The PMOS transistor P179 and the NMOS transistor N179 configure an inverter, invert the data signal PCM1, and output the obtained signal to the data output terminal 162.

0111Thus, the portion configured by the PMOS transistors P174, P175, P176, P177, P178, and P179, and the NMOS transistors N174, N175, N176, N177, N178, and N179 corresponds to the latch unit explained with reference to <figref idref="DRAWINGS">FIG. 3</figref>.

0112The portion other than the enclosure by the dotted lines in <figref idref="DRAWINGS">FIG. 18</figref>, that is, the configuration of the latch unit can be otherwise configured.

0113The portion enclosed by the dotted lines in <figref idref="DRAWINGS">FIG. 18</figref> corresponds to the data matching detection and clock internal propagation suppression unit 151, and operates as follows.

0114When the input data signal D indicates L and the output data signal M indicates L, the data signal PCM1 indicates H, and the circuit operates as follows. By the inverter formed by the PMOS transistor P174 and the NMOS transistor N174, the input data signal D is inverted. Thus, the NMOS transistor N172 is placed in the ON state. Since the data signal PCM1 indicates H, the NMOS transistor N172 is placed in the ON state. Thus, the internal clock signal XCLK indicates L regardless of state of L or H of the signal input from the clock input terminal 163, and the clock propagation is suppressed.

0115When the input data signal D indicates H and the output data signal M indicates H, the data signal PCM1 indicates L, the PMOS transistors P171 and P173 are placed in the ON state, and the NMOS transistors N172 and N173 are placed in the OFF state. Thus, the inverted clock <o ostyle="single">CK</o> input from the clock input terminal 163 is inverted by the inverter configured by the PMOS transistor P172 and the NMOS transistor N171, and output as the internal clock signal XCLK.

0116When the input data signal D indicates H and the output data signal M indicates L, the data signal PCM1 indicates H, the PMOS transistors P171 is placed in the ON state, the PMOS transistor P173 is placed in the OFF state, the NMOS transistors

0117N172 is placed in the OFF state, and the NMOS transistor N173 is placed in the ON state. Thus, the inverted clock <o ostyle="single">CK</o> input from the clock input terminal 163 is inverted by the inverter configured by the PMOS transistor P172 and the NMOS transistor N171, and is output as the internal clock signal XCLK.

0118When the input data signal D indicates L and the output data signal M indicates H, the data signal PCM1 indicates L, the PMOS transistor P171 is placed in the OFF state, the PMOS transistor P173 is placed in the ON state, the NMOS transistor N172 is placed in the ON state, and the NMOS transistor N173 is placed in the OFF state. Thus, the inverted clock input from the clock input terminal 163 is inverted by the inverter configured by the PMOS transistor P172 and the NMOS transistor N171, and is output as the internal clock signal XCLK.

0119As described above, like the latch circuit using the NOR circuit, it is obvious that the latch circuit 160 of the circuit example 3 has a similar effect of suppressing the propagation of the internal clock signal XCLK in the latch unit when the input data signal D and the output data signal M match at L. That is, the timing chart of the circuit example 3 is similar to D, M, and XCLK in <figref idref="DRAWINGS">FIG. 11</figref>.

0120In addition, the number of transistors of the circuit example 3 is compared with the number of transistors of the circuit example 1 (<figref idref="DRAWINGS">FIG. 10</figref>) as follows. The number of the transistors in the circuit example 1 is a total of 20, that is, four in the NOR circuit 91 (<figref idref="DRAWINGS">FIG. 12</figref>), and 16 in the IH latch circuit 10 (<figref idref="DRAWINGS">FIG. 3</figref>). The number of transistors in the circuit example 3 is 18 as illustrated in <figref idref="DRAWINGS">FIG. 18</figref>. Thus, the number of transistors in the circuit example 3 is smaller by two than the number of transistors in the circuit example 1.

CIRCUIT EXAMPLE 4

0121Described next is a circuit example according to the embodiment 2.

0122A latch circuit 180 in the circuit example 4 realizes the effect equivalent to the latch circuit using an AND circuit illustrated in <figref idref="DRAWINGS">FIG. 13</figref>. It is hereafter referred to as a latch 1 circuit.

0123The latch circuit 180 of the circuit example 4 includes a data input terminal 181 for inputting the input data signal D, a data output terminal 182 from which the output data signal M is output, and a clock input terminal 183 to which the inverted clock signal is input.

0124<figref idref="DRAWINGS">FIG. 20</figref> illustrates an example of the detailed circuit.

0125The circuit includes PMOS transistors P191, P192, P193, P194, P195, P196, P197, P198, and P199, and NMOS transistors N191, N192, N193, N194, N195, N196, N197, N198, and N199.

0126In <figref idref="DRAWINGS">FIG. 20</figref>, the wiring from the data signal PAM1 to the PMOS transistor P193 and the NMOS transistor N193 can be arranged from M indicating an equivalent logic of the data signal PAM1.

0127The portion other than the enclosure by the dotted lines in <figref idref="DRAWINGS">FIG. 20</figref> corresponds to the latch unit 152, and corresponds to the portion configured by the PMOS transistors P3, P4, P5, P6, P7, and P8, and the NMOS transistors N3, N4, N5, N6, and N7. The details are described as follows.

0128The source terminal of the PMOS transistor P195 is connected to the high-voltage side power supply terminal, and the internal clock signal XCLK is input to the gate terminal. The source terminal of the NMOS transistor N195 is connected to the low-voltage side power supply terminal, the internal clock signal XCLK is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P195. The PMOS transistor P195 and the NMOS transistor N195 configure an inverter.

0129The source terminal of the PMOS transistor P194 is connected to the high-voltage side power supply terminal, and the gate terminal is connected to the data input terminal 161. The source terminal of the NMOS transistor N194 is connected to the low-voltage side power supply terminal, and the gate terminal is connected to the data input terminal 181. The PMOS transistor P194 and the NMOS transistor N194 configure an inverter.

0130The source terminal of the PMOS transistor P196 is connected to the drain terminals of the PMOS transistor P194 and the NMOS transistor N194, and the gate terminal is connected to the drain terminals of the PMOS transistor P195 and the NMOS transistor N195. The source terminal of the NMOS transistor N196 is connected to the drain terminals of the PMOS transistor P194 and the NMOS transistor N194, and the internal clock signal XCLK is input to the gate terminal. The PMOS transistor P196 and the NMOS transistor N196 configure a transfer gate terminal, and the signal obtained by inverting the input data signal input from the data input terminal 181 when the gate terminal of the PMOS transistor P196 indicates L and the gate terminal of the NMOS transistor N196 indicates H is output as the data signal PCM1.

0131The source terminal of the PMOS transistor P197 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N197 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P197. The PMOS transistor P197 and the NMOS transistor N197 configure an inverter, invert the data signal PCM1, and output the data signal PAM1.

0132The source terminal of the PMOS transistor P198 is connected to the high-voltage side power supply terminal, and the data signal PAM1 is input to the gate terminal. The source terminal of the NMOS transistor N198 is connected to the low-voltage side power supply terminal, the data signal PAM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P198. The PMOS transistor P198 and the NMOS transistor N198 configure an inverter, inverts the data signal PAM1, and outputs the data signal PCM1.

0133The portion configured by the PMOS transistors P197 and P198, and the NMOS transistors N197 and N198 has the function of holding latch data.

0134The source terminal of the PMOS transistor P199 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N199 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P199. The PMOS transistor P199 and the NMOS transistor N199 configure an inverter, invert the data signal PCM1, and output the resultant signal to the data output terminal 162.

0135Thus, the portion configured by the PMOS transistors P194, P195, P196, P197, P198, and P199, and the NMOS transistors N194, N195, N196, N197, N198, and N199 corresponds to the latch unit explained with reference to <figref idref="DRAWINGS">FIG. 3</figref>.

0136The configuration of the portion other than the enclosure by the dotted lines in <figref idref="DRAWINGS">FIG. 20</figref>, that is, the latch unit, can be another configuration.

0137The portion enclosed by the dotted lines in <figref idref="DRAWINGS">FIG. 20</figref> corresponds to the data matching detection and clock internal propagation suppression unit 151, and operates as follows.

0138When the input data signal D indicates H, and the output data signal M indicates H, the data signal PAM1 indicates H, the PMOS transistors P191 and P193 are placed in the OFF state, the NMOS transistors N192 and N193 are placed in the ON state. Thus, whether the signal input from the clock input terminal 183 indicates L or H, the internal clock signal XCLK signal indicates L, thereby suppressing the clock propagation.

0139When the input data signal D indicates L and the output data signal M indicates L, the data signal PAM1 indicates L, the PMOS transistors P191 and P193 are placed in the ON state, and the NMOS transistors N192 and N193 are placed in the OFF state. Thus, the inverted clock <o ostyle="single">CK</o> input from the clock input terminal 183 is inverted by the inverter configured by the PMOS transistor P192 and the NMOS transistor N191, and is output as the internal clock signal XCLK.

0140When the input data signal D indicates H and the output data signal M indicates L, the data signal PAM1 indicates L, the PMOS transistors P191 is placed in the OFF state, the PMOS transistor P193 is placed in the ON state, the NMOS transistors N192 is placed in the OFF state, and the NMOS transistor N193 is placed in the ON state. Thus, the inverted clock <o ostyle="single">CK</o> input from the clock input terminal 163 is inverted by the inverter configured by the PMOS transistor P172 and the NMOS transistor N171, and is output as the internal clock signal XCLK.

0141When the input data signal D indicates L and the output data signal M indicates H, the data signal PAM1 indicates H, the PMOS transistor P191 is placed in the ON state, the PMOS transistor P193 is placed in the OFF state, the NMOS transistor N192 is placed in the OFF state, and the NMOS transistor N193 is placed in the ON state. Thus, the inverted clock input from the clock input terminal 163 is inverted by the inverter configured by the PMOS transistor P192 and the NMOS transistor N191, and is output as the internal clock signal XCL.

0142As described above, it is obvious that the latch circuit 180 of the circuit example 4 has a similar effect of suppressing the propagation of the internal clock signal XCLK in the latch unit when the input data signal D and the output data signal M match at H. That is, the timing chart of the circuit example 4 is similar to D, M, and XCLK in <figref idref="DRAWINGS">FIG. 14</figref>.

0143The number of transistors of the circuit example 4 is compared with the number of transistors of the circuit example 2 (<figref idref="DRAWINGS">FIG. 13</figref>) as follows. The number of the transistors in the circuit example 2 is a total of 22, that is, six in the AND circuit (<figref idref="DRAWINGS">FIG. 15</figref>), and 16 in the IH latch circuit 10 (<figref idref="DRAWINGS">FIG. 3</figref>). The number of transistors in the circuit example 4 is 18 as illustrated in <figref idref="DRAWINGS">FIG. 20</figref>. Thus, the number of transistors in the circuit example 4 is smaller by four than the number of transistors in the circuit example 2.

0144As described above, the embodiment 2 can further reduce the number of transistors required to configure a latch circuit as compared with the embodiment 1. In the embodiment 2, as in the embodiment 1, the propagation of the internal clock can be suppressed only when the input/output data of the latch circuit match at L (0) in the circuit example 3. In the circuit example 4, the propagation of the internal clock can be suppressed only when the input/output data of the latch circuit match at H (1). Therefore, the power consumption can be effectively reduced by using the circuit example 3 or 4 by considering whether or not it is probable that the latch value is L (0) or H (1). The study of the power consumption is described later with reference to <figref idref="DRAWINGS">FIGS. 21</figref>, 22, and 23.

0145The embodiments of the present invention are described above in detail with reference to the circuit examples 1 through 4. As described above, the disclosed latch circuit can reduce the number of transistors as compared with the conventional circuit.

0146Relating to the disclosed circuit example, the power consumption of each circuit is actually measured to verify that the power consumption is reduced. The measurement result is illustrated in <figref idref="DRAWINGS">FIGS. 21</figref>, 22, and 23.

0147<figref idref="DRAWINGS">FIG. 21</figref> illustrates a result of measuring the average power on the circuit examples 1 through 4, the circuit illustrated in <figref idref="DRAWINGS">FIG. 1</figref> (the IH terminal clipped at L), and the circuit illustrated in <figref idref="DRAWINGS">FIG. 4</figref> (using an ENOR circuit) in each operation pattern, and setting the resultant data based on the circuit in <figref idref="DRAWINGS">FIG. 4</figref>. Each operation pattern of (1) through (4) refers to the pattern corresponding to the timing 1 through 4 illustrated in <figref idref="DRAWINGS">FIGS. 5</figref>, 6, 11, 14, and etc.

0148In <figref idref="DRAWINGS">FIG. 21</figref>, “(1) 0→0” refers to the average power of the circuit when the data of the data output terminal does not change as 0, “(2) 0→1” refers to the average power of the circuit when the data of the data output terminal changes from 0 to 1, “(3) 1→1” refers to the average power of the circuit when the data of the data output terminal does not change as 1, and “(4) 1→0” refers to the average power of the circuit when the data of the data output terminal changes from 1 to 0.

0149<figref idref="DRAWINGS">FIG. 22</figref> illustrates the result of obtaining the average power etc. from the measurement result in <figref idref="DRAWINGS">FIG. 21</figref>. In <figref idref="DRAWINGS">FIG. 22</figref>, the “average (=operation rate of 50%)” refers to the average obtained as the case (operation rate or 50%) in which each of (1) through (4) accounts for 25%. Furthermore, “0→0 97%” in <figref idref="DRAWINGS">FIG. 22</figref> is obtained as power consumption of (0→0)×0.97+ power consumption of (0→1)×0.01+ power consumption of (1→1)×0.01+ power consumption of (1→0)×0.01. “1→1 97%” in <figref idref="DRAWINGS">FIG. 22</figref> is obtained as power consumption of (0→0)×0.01+ power consumption of (0→1)×0.01+ power consumption of (1→1)×0.97+ power consumption of (1→0)×0.01. That is, the former refers to the power consumption when the pattern of 0→0 is 97%, and the latter refers to the power consumption when the pattern of 1→1 is 97%.

0150Referring to <figref idref="DRAWINGS">FIG. 21</figref>, in the circuit example 1, each power consumption becomes 70.1%, 67.3%, and 71.5% in the case of 0→0, 0→1, and 1→0 as compared with the case in which the ENOR circuit in <figref idref="DRAWINGS">FIG. 4</figref> is used, which is lower than the case in which the ENOR circuit is used (100%). However, in the case of 1→1, it increases to 453.3%. As a result, as illustrated in <figref idref="DRAWINGS">FIG. 22</figref>, when each accounts for 25% (operation rate of 50%), the average is 77.2%, which is lower than the circuit using the ENOR circuit. In addition, when the case in which the change of data is hardly detected as 0→0 is 97%, the value is lower at 72.7%. However, when the case in which the change of data is hardly detected as 1→1 is 97%, the value increases to 327.5%.

0151The circuit example 2 indicates the opposite feature with respect to the case of the circuit example 1. That is, with reference to <figref idref="DRAWINGS">FIG. 21</figref>, in the case of 1→1, 1→0, 0→1, the respective values indicate the power consumption of 78.8%, 74.5%, and 78.9% as compared with the ENOR circuit, which indicates lower consumption than in the case of the ENOR circuit (100%) . However, in the case of 0→0, the value increases to 526.6%. As a result, as illustrated in <figref idref="DRAWINGS">FIG. 22</figref>, the average obtained when each case accounts for 25% (operation rate of 50%) is 85.3%, which is lower than the circuit using the ENOR circuit. In addition, when the case in which the change of data is hardly detected as 1→1 is 97%, the value is lower at 81.0%. However, when the case in which the change of data is hardly detected as 0→0 is 97%, the value increases to 368.5%. In addition, since the number of transistors has increased by 2 as compared with the circuit example 1, the power consumption is higher than in the case of the circuit example 1 (NOR).

0152Similarly, in the circuit example 3, with reference to <figref idref="DRAWINGS">FIG. 21</figref>, in the case of 0→0, 0→1, 1→0, the respective values indicate the power consumption of 76.5%, 60.6%, and 72.3% as compared with the ENOR circuit in <figref idref="DRAWINGS">FIG. 4</figref>, which indicates lower consumption than in the case of the ENOR circuit (100%). However, in the case of 1→1, the value increases to 435.3%. As a result, as illustrated in <figref idref="DRAWINGS">FIG. 22</figref>, the average obtained when each case accounts for 25% (operation rate of 50%) is 73.9%, which is lower than the circuit using the ENOR circuit. In addition, when the case in which the change of data is hardly detected as 0→0 or 1→1 is 97%, the respective values are 75.6% and 314.3.

0153In the circuit example 4, with reference to <figref idref="DRAWINGS">FIG. 21</figref>, in the case of 1→1, 1→0, 0→1, the respective values indicate the power consumption of 80.0%, 60.4%, and 63.0% as compared with the ENOR circuit, which indicates lower consumption than in the case of the ENOR circuit (100%). However, in the case of 0→0, the value increases to 499.5%. As a result, as illustrated in <figref idref="DRAWINGS">FIG. 22</figref>, the average obtained when each case accounts for 25% (operation rate of 50%) is 70.3%, which is lower than in the case in which the ENOR circuit is used. In addition, when the case in which the change of data is hardly detected as 0→0 or 1→1 is 97%, the respective values are 745.8% and 76.8.

0154Thus, in the circuit examples 3 and 4, the tendency is similar to that in the circuit example 1 or 2 basically. However, since the number of transistors is smaller, the power consumption is lower than in the circuit examples 1 and 2. In addition, when there is hardly any change of data, the power consumption can be almost the same as in the circuit example 1 in the case of 0→0 in the circuit example 3, and can be almost the same or lower than in the case of the circuit example 2 in the case of 1→1in the circuit example 4.

0155<figref idref="DRAWINGS">FIG. 23</figref> is a set of the measurement results of the leakage power of the circuit examples 1 through 4 and the circuits in <figref idref="DRAWINGS">FIGS. 1 and 4</figref>. The leakage power refers to the power consumption when a clock and data do not change. That is, for example, “<1> D=0, M=0” in <figref idref="DRAWINGS">FIG. 23</figref> refers to the power measured immediately before the signal of L is input to the clock input terminal when the input data is 0 and the output data is 0 in the circuit. (“Immediately before” refers to the timing before a signal is input.) Similarly, “<2> D=1, M=0” refers to the power measured immediately before the signal of L is input to the clock input terminal when the input data is 1 and the output data is 0 in the circuit. The same holds true with <3> and <4>.

0156The averaged power of the measurement power of each circuit in the cases of <1> through <4> is described in the rightmost column in <figref idref="DRAWINGS">FIG. 23</figref>. In this case, when the leakage power of the circuit illustrated in <figref idref="DRAWINGS">FIG. 4</figref> (the case in which the ENOR circuit is used) is 100%, the average leakage power of the circuit examples 1 through 4 is respectively 69.6%, 90.5%, 67.4%, and 72.6%. Since the leakage power is subject to the influences of the topology of a circuit and the number of transistors, it is not generally described, but the leakage power in the case in which the ENOR circuit is used is 100% as the highest value. Thus, the circuit examples 1 through 4 can minimize the leakage power as compared with the case in which the ENOR circuit is used.

0157As described above, according to the disclosed circuit examples 1 through 4, the power consumption during the operation and the leakage power can be lower than that by the conventional circuit. For more detail, from the power measurement result in <figref idref="DRAWINGS">FIG. 21</figref>, the circuit according to the circuit example 1 or 3 is used in the circuit having a higher probability that the latch value indicates L (0), and the circuit according to the circuit example 2 or 4 is used in the circuit having a higher probability that the latch value indicates H (1), thereby reducing the power consumption. In many cases, since the number of transistors to be used is smaller in the circuit examples 3 and 4 than in the circuit examples 1 and 2, it can be said that they excel in downsizing and power-saving. However, the circuit examples 1 and 2 has the feature that the circuit size and the power consumption can be reduced more than the case in which a conventional ENOR circuit is used (<figref idref="DRAWINGS">FIG. 4</figref>) by using a external circuit such as the NOR circuit and the AND circuit without changing the configuration of the conventional latch circuit such as an IH latch circuit illustrated in <figref idref="DRAWINGS">FIG. 1</figref> etc. That is, when the circuit size and the power consumption are to be reduced using the conventional latch circuit, it is effective to use the embodiment 1, and the embodiment 2 is to be used when the size of a circuit is further reduced and the power consumption is further decreased.

0158Although the embodiments of the present invention have been described above in detail, the circuit of the portion for controlling the internal clock propagation can be simplified and the circuit size can be minimized according to the disclosed latch circuit.

0159It is obvious that the present invention is not limited to the descriptions of the above-mentioned embodiments, and a number of variations and modifications can be made within the range of the gist of the present invention.

0160That is, all examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.

Every citation, both ways

Citations
Document	Relation	Office	Cited during
US9577635B2	Cited by	United States of America	Applicant
US10135425B1	Cited by	United States of America	Search report
US2008028343A1	Cites	United States of America	Pre-grant
US5656962A	Cites	United States of America	Pre-grant
US6831496B2	Cites	United States of America	Pre-grant
US8143919B2	Cites	United States of America	Pre-grant

10 members in 5 offices

This recordMember, by publication datePriority claim

Priority claims4

Priority claims
Document	Office	Kind	Date
2009007039	Japan	W	2009-12-18
2009007039	Japan	W	2009-12-18
PCTJP2009007039	–	–	–
WO2009JP07039	–	–	–

Members10

Family members, oldest first
Document	Office	Kind
WO2011074050A1	World Intellectual Property Organization (WIPO)	A1	2011-06-23
KR20120101105A	Republic of Korea	A	2012-09-12
US2012249181A1	United States of America	A1	2012-10-04
EP2515437A1	European Patent Office (EPO)	A1	2012-10-24
JPWO2011074050A1	Japan	A1	2013-04-25
KR101354286B1	Republic of Korea	B1	2014-01-23
JP5423809B2	Japan	B2	2014-02-19
EP2515437A4	European Patent Office (EPO)	A4	2014-02-26
US9018981B2	United States of America	B2	2015-04-28
EP3244534A1	European Patent Office (EPO)	A1	2017-11-15

58 transactions on the USPTO file

Allowed after 1 non-final rejection and 1 final rejection.

Non-final rejections: 1
Final rejections: 1
RCEs: 0
Appeals: 0

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	Event	Code
2019-06-03	Expire PatentEXP.	EXP.
2018-12-17	Maintenance Fee Reminder MailedREM.	REM.
2015-04-28	Recordation of Patent Grant MailedPGM/	PGM/
2015-04-28	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2015-04-09	Email NotificationEML_NTR	EML_NTR
2015-04-08	Issue Notification MailedAllowedWPIR	WPIR
2015-03-31	Dispatch to FDCD1935	D1935
2015-03-31	Application Is Considered Ready for IssuePILS	PILS
2015-03-30	Response to Reasons for AllowanceREAS	REAS
2015-03-30	Issue Fee Payment VerifiedN084	N084
2015-03-30	Issue Fee Payment ReceivedIFEE	IFEE
2015-01-02	Electronic ReviewELC_RVW	ELC_RVW
2015-01-02	Email NotificationEML_NTF	EML_NTF
2015-01-02	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2014-12-03	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2014-11-30	Reasons for AllowanceEX.R	EX.R
2014-11-30	Information Disclosure Statement consideredIDSC	IDSC
2014-11-20	Date Forwarded to ExaminerFWDX	FWDX
2014-11-17	Response after Final ActionA.NE	A.NE
2014-11-17	Request for Extension of Time - GrantedXT/G	XT/G
2014-08-14	Information Disclosure Statement (IDS) FiledM844	M844
2014-08-14	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2014-07-18	Electronic ReviewELC_RVW	ELC_RVW
2014-07-18	Email NotificationEML_NTF	EML_NTF
2014-07-18	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2014-07-13	Final RejectionFinal rejectionCTFR	CTFR
2014-07-13	Information Disclosure Statement consideredIDSC	IDSC
2014-03-30	Date Forwarded to ExaminerFWDX	FWDX
2014-03-20	Response after Non-Final ActionA...	A...
2014-02-10	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2014-02-10	Information Disclosure Statement (IDS) FiledM844	M844
2014-02-10	Reference capture on IDSRCAP	RCAP
2014-02-10	Request for Foreign Priority (Priority Papers May Be Included)RQPR	RQPR
2013-12-20	Electronic ReviewELC_RVW	ELC_RVW
2013-12-20	Email NotificationEML_NTF	EML_NTF
2013-12-20	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2013-12-13	Non-Final RejectionNon-final rejectionCTNF	CTNF
2013-11-05	Case Docketed to Examiner in GAUDOCK	DOCK
2013-10-07	Case Docketed to Examiner in GAUDOCK	DOCK
2013-08-14	Information Disclosure Statement consideredIDSC	IDSC
2013-08-14	Information Disclosure Statement (IDS) FiledM844	M844
2013-08-14	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-06-05	Information Disclosure Statement consideredIDSC	IDSC
2013-06-05	Reference capture on IDSRCAP	RCAP
2013-06-05	Information Disclosure Statement (IDS) FiledM844	M844
2013-06-05	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-10-04	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2012-08-28	Information Disclosure Statement consideredIDSC	IDSC
2012-08-28	Information Disclosure Statement (IDS) FiledM844	M844
2012-08-28	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-08-28	Case Docketed to Examiner in GAUDOCK	DOCK
2012-07-10	Application Dispatched from OIPEOIPE	OIPE
2012-06-22	Application Is Now CompleteCOMP	COMP
2012-06-22	Sent to Classification ContractorPGPC	PGPC
2012-06-22	Filing ReceiptFLRCPT.O	FLRCPT.O
2012-06-13	Cleared by OIPE CSRL194	L194
2012-06-12	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2012-06-12	Initial Exam Team nnIEXX	IEXX

6 legal events, as the office reported them to INPADOC

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	Event	Code
2019-06-18	Lapsed due to failure to pay maintenance feeLapsedFP	FP
2019-06-03	Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYLAPS	LAPS
2019-06-03	Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH	STCH
2018-12-17	Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2015-04-08	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2012-06-22	AssignmentAS	AS

Latch circuit and clock control circuit

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Abstract

Term

FIELD

BACKGROUND

DOCUMENTS OF PRIOR ART

SUMMARY

BRIEF DESCRIPTION OF DRAWINGS

DESCRIPTION OF EMBODIMENTS

CIRCUIT EXAMPLE 1

CIRCUIT EXAMPLE 2

CIRCUIT EXAMPLE 3

CIRCUIT EXAMPLE 4

Priority claims4

Members10

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Abstract

Term

CROSS-REFERENCE TO RELATED APPLICATIONS

FIELD

BACKGROUND

DOCUMENTS OF PRIOR ART

SUMMARY

BRIEF DESCRIPTION OF DRAWINGS

DESCRIPTION OF EMBODIMENTS

CIRCUIT EXAMPLE 1

CIRCUIT EXAMPLE 2

CIRCUIT EXAMPLE 3

CIRCUIT EXAMPLE 4

Priority claims4

Members10

Over time

Transactions

Over the term

Events

Numbers

Titles

Patent term adjustment

Classification