Circuit Arrangement with a Plurality of On-Chip Monitor Circuits and a Control Circuit and Corresponding Methods

TECHNICAL FIELD

0001Various embodiments relate to a circuit arrangement with a plurality of on-chip monitor circuits and a control circuit, and corresponding methods.

BACKGROUND

0002Modern electronic systems, for example, mobile phones, digital cameras and personal digital assistants, have an ever increasing demand for highly-integrated and energy-efficient semiconductor circuits. In order to meet these requirements, the physical size of field effect transistors (FETs) within the semiconductor circuits is reduced. Due to the shrinking size, the FETs become more susceptible to variations of parameters of the semiconductor circuits, like process, supply voltage, aging of the devices, and temperature. Traditionally, these variations are modeled by guard-banding, i.e., safety margins may be added to allow for a robust operation of the semiconductor circuits. However, safety margins are expensive in terms of area and power dissipation.

0003On-chip monitor circuits may be implemented to measure the actual status of the semiconductor circuits with respect to certain variations. Countermeasures or adaptive techniques may be initiated on a circuit level or a system level responsive to the measurement results of the on-chip monitor circuits. A specific on-chip monitor circuit is typically designed to measure one specific effect, such as the process performance class with high measurement accuracy. Further variations such as process or supply voltage are acting as disturbing effects during the measurement and will reduce the measurement accuracy of a specific on-chip monitor circuit.

0000A sensitivity of the on-chip monitor circuit to disturbing effects should be as small as possible to avoid a corruption of the measurement results. A thorough design of the on-chip monitor may decrease the sensitivity to disturbing effects. If the sensitivity of the on-chip monitor circuit to disturbing effects cannot completely eliminated, a calibration of the on-chip monitor circuit may be required to compensate for the disturbing effects. The calibration may be performed during fabrication, after fabrication or during operation of the on-chip monitor circuit. The calibration of an on-chip monitor may be implemented by providing a circuitry that modifies the electrical behavior of the monitor, i.e. the monitor operation can be switched between several, predefined configuration settings. During calibration, one specific predefined configuration setting may be selected that provides the best measurement accuracy and stored for later use of the monitor in a measurement mode. The selected configuration setting may be stored in a register, a volatile memory, a nonvolatile memory, or an electrical fuse. The register, the volatile memory, the nonvolatile memory, or the electrical fuse may be implemented on the same semiconductor substrate as the on-chip monitor or implemented on a separate semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

0004The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit of a reference number identifies the figure in which the reference number first appears. The use of similar reference numbers in different instances in the description and the figures may indicate similar or identical items.

0005<figref idref="DRAWINGS">FIG. 1</figref> illustrates an exemplary circuit arrangement with a plurality of on-chip monitor circuits and a controller.

0006<figref idref="DRAWINGS">FIG. 2</figref> illustrates a graph showing a supply voltage of an on-chip monitor circuit to be calibrated during a calibration.

0007<figref idref="DRAWINGS">FIG. 3</figref> illustrates a further graph showing a supply voltage of an on-chip monitor circuit to be calibrated during a calibration.

0008<figref idref="DRAWINGS">FIG. 4</figref> illustrates a further exemplary circuit arrangement with a plurality of on-chip monitor circuits and a controller.

0009<figref idref="DRAWINGS">FIG. 5</figref> illustrates an exemplary self-calibrating on-chip monitor circuit.

0010<figref idref="DRAWINGS">FIG. 6</figref> illustrates an exemplary on-chip monitor circuit with external calibration.

0011<figref idref="DRAWINGS">FIG. 7</figref> illustrates an exemplary circuit arrangement with a plurality of on-chip monitor circuits, a controller and a plurality of post-processors.

0012<figref idref="DRAWINGS">FIG. 8</figref> illustrates an exemplary system with a circuit arrangement, a functional circuit and a regulator circuit.

0013<figref idref="DRAWINGS">FIG. 9</figref> illustrates a flow diagram that includes a number of operations supervising an on-chip monitor circuit.

0014<figref idref="DRAWINGS">FIG. 10</figref> illustrates a flow diagram that includes a number of operations calibrating an on-chip monitor circuit.

DETAILED DESCRIPTION

0015Disclosed herein are techniques for monitoring a parameter of a semiconductor chip. According to one implementation, a circuit arrangement includes a plurality of on-chip monitor circuits. Each of the plurality of on-chip monitor circuits is configured to measure a parameter of a semiconductor chip. The circuit arrangement further includes a controller that is coupled to the plurality of on-chip monitor circuits. The controller is configured to receive a measurement result from at least one of the plurality of on-chip monitor circuits and to control a calibration of another one of the plurality of on-chip monitor circuits in accordance with the measurement result.

0016In various embodiments, a controller may be implemented by any kind of logic, e.g. digital logic such as e.g. a hardwired logic and/or programmable logic. In various embodiments, a controller may be implemented by e.g. as a processor, e.g. a microprocessor (e.g. a CISC microprocessor or a RISC microprocessor), as a programmable gate array (PGA) or a field programmable gate array (FPGA), or the like.

0017According to another implementation, a circuit arrangement includes a plurality of on-chip monitor circuits that are arranged in a network. Each of the plurality of on-chip monitor circuits configured to measure at least one parameter of a semiconductor chip. The circuit arrangement further includes a controller that is coupled to the network of on-chip monitor circuits. The controller is configured to receive measurement results from the plurality of on-chip monitor circuits and to generate an output in accordance with an evaluation of the measurement results. The circuit arrangement further includes at least one feedback loop that is coupled to the controller and the network. The at least one feedback loop is configured to control a calibration of at least one of the plurality of on-chip monitor circuits in accordance with the output.

0018According to another embodiment, a method is provided for supervising an on-chip monitor circuit. A measurement of at least one of a plurality of on-chip monitor circuits is started and each of the plurality of on-chip monitor circuits is configured to measure a parameter of a semiconductor chip. Further, a measurement of an on-chip monitor circuit to be supervised is started and the on-chip monitor circuit to be supervised is configured to measure a parameter of the semiconductor chip. Further, at least one measurement result from the at least one of the plurality of on-chip monitor circuits is processed. A measurement result of the on-chip monitor circuit to be supervised is denoted as invalid if the at least one measurement result from the at least one of the plurality of on-chip monitor circuits deviates from a predetermined range.

0019According to another embodiment, a method is provided for calibrating an on-chip monitor circuit. A plurality of on-chip monitor circuits configured to measure at least one parameter of a semiconductor chip is activated. Further, an on-chip monitor circuit to be calibrated is activated. Measurement results from the plurality of on-chip monitor circuits are combined. Further, a calibration of the on-chip monitor circuit to be calibrated is controlled in accordance with the combination of the measurement results.

0020Implementations as illustrated and described hereby may allow for an accurate calibration of on-chip monitor circuits and an accurate measurement of chip parameters. Variations of operating conditions may be detected during a calibration phase or a measurement phase and a calibration or a measurement may be repeated in case of significant variations of operating conditions. In addition, the implementations as illustrated and described hereby may only require a small area and may only have a low power consumption.

0021The techniques described herein may be implemented in a number of ways. Examples and context are provided below with reference to the included figures and ongoing discussion.

Exemplary Devices

0022<figref idref="DRAWINGS">FIG. 1</figref> shows a schematic diagram of an exemplary circuit arrangement <b>100</b> that includes a plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and a controller <b>106</b>. Each of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> is configured to measure a parameter of a semiconductor chip. The controller <b>106</b> is coupled to the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and is configured to receive a measurement result from at least one <b>104</b> of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b>. The controller <b>106</b> is further configured to control a calibration of another one <b>102</b> of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> in accordance with the measurement result.

0023As illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> may include two on-chip monitor circuits <b>102</b> and <b>104</b>, i.e., a first on-chip monitor circuit <b>102</b> and a second on-chip monitor circuit <b>104</b>. Alternatively, the plurality of on-chip monitor circuits may include more than two on-chip monitor circuits. Each of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> may be configured to measure one or several parameters of the semiconductor chip. A measurement result provided by one of the on-chip monitor circuits <b>102</b> and <b>104</b> may correspond to a current state of a parameter of the semiconductor chip. An on-chip monitor circuit may be configured to measure a parameter, such as a temperature, a supply voltage, a circuit delay, a frequency, an aging state, a process variation, a dynamic power dissipation or a leakage current. Additionally or alternatively, an on-chip monitor circuit may be configured to measure CMOS device parameters, such as drive current and threshold voltage, or a resistance and coupling capacitances of on-chip interconnects. An on-chip monitor circuit may include, e.g., a ring oscillator, a line of delay elements and/or a time-to-digital converter to measure the one or several parameters. Additionally or alternatively, the on-chip monitor circuit may include a sensor, e.g. a thermal sensor, to measure the one or several parameters. The on-chip monitor circuit may include all-digital logic, all-analog logic or both, digital and analog logic.

0024The controller <b>106</b> may control a calibration of the first on-chip monitor circuit <b>102</b> by receiving a measurement result from the second on-chip monitor circuit <b>104</b> and by checking if the measurement result falls within a predetermined range. If the measurement result deviates from the predetermined range, the calibration of the first on-chip monitor circuit <b>102</b> may be invalid and the calibration may be repeated. For example, the controller <b>106</b> may interrupt the calibration and initiate a re-start of the calibration of the first on-chip monitor circuit <b>102</b>. If the measurement result does not deviate from the predetermined range, the calibration of the first on-chip monitor circuit <b>102</b> may be valid and finished.

0025In one implementation, the first on-chip monitor circuit <b>102</b> may be an on-chip monitor circuit to be calibrated and the second on-chip monitor circuit <b>104</b> may be an on-chip monitor circuit that supervises a calibration of the on-chip monitor circuit to be calibrated <b>102</b>. For example, the supervising on-chip monitor circuit <b>104</b> may measure a supply voltage VDD of the on-chip monitor circuit to be calibrated <b>102</b> during the calibration of the on-chip monitor circuit to be calibrated <b>102</b>. The controller <b>106</b> may receive a plurality of measurement results of the supply voltage VDD from the supervising on-chip monitor circuit <b>104</b> within a predetermined period. The controller <b>106</b> may control the calibration of the on-chip monitor circuit to be calibrated <b>102</b> in accordance with a combination of the plurality of measurement results received. Additionally or alternatively, the controller <b>106</b> may detect if at least one of the plurality of measurement results deviates from a predetermined range.

0026<figref idref="DRAWINGS">FIG. 2</figref> illustrates a graph showing a supply voltage VDD of the on-chip monitor circuit to be calibrated <b>102</b> during a calibration. The calibration of the on-chip monitor circuit to be calibrated <b>102</b> may take a predetermined time period t<b>1</b>, herein called calibration phase t<b>1</b>. During the calibration phase t<b>1</b>, the supervising on-chip monitor circuit <b>104</b> may perform ten measurements of the supply voltage VDD and may provide ten measurement results 1, 2, 3 . . . 10 to the controller <b>106</b>. The controller <b>106</b> may check for each of the ten measurement results 1, 2, 3 . . . 10 if it deviates from a predetermined voltage range that is defined by a lower voltage level VDDmin and an upper voltage level VDDmax. For example, as illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, measurement results number 4 and number 5 exceed the upper voltage level VDDmax and measurement result number 8 falls below the lower voltage level VDDmin. As at least one of the measurement results deviates from the predetermined range, the controller <b>106</b> may denote the calibration of the on-chip monitor circuit to be calibrated <b>102</b> as invalid. In addition, the controller <b>106</b> may control the calibration of the on-chip monitor circuit <b>102</b> by initiating a repeat of the calibration.

0027Generally, substantial variations of operating conditions may prevent an accurate calibration of the on-chip monitor circuit to be calibrated <b>102</b>. For example, significant variations of the supply voltage VDD may prevent an accurate calibration of the on-chip monitor circuit to be calibrated <b>102</b>. By continuously monitoring the supply voltage VDD during the calibration phase t<b>1</b> of the on-chip monitor circuit to be calibrated <b>102</b>, a distortion of the calibration by temporal variations of the supply voltage VDD may be detected. The calibration of the on-chip monitor circuit to be calibrated <b>102</b> may be denoted as invalid and may be discarded if the supply voltage VDD varies widely during the calibration phase t<b>1</b>, i.e., if the supply voltage VDD is not stable. The calibration of the on-chip monitor circuit to be calibrated <b>102</b> may be interrupted and re-started.

0028<figref idref="DRAWINGS">FIG. 3</figref> illustrates a further graph showing the supply voltage VDD of the on-chip monitor circuit to be calibrated <b>102</b> during a calibration. The calibration of the on-chip monitor circuit to be calibrated <b>102</b> may take a predetermined time period t<b>2</b>, herein called calibration phase t<b>2</b>. During the calibration phase t<b>2</b>, the supervising on-chip monitor circuit <b>104</b> may perform ten measurements of the supply voltage VDD and may provide ten measurement results 1, 2, 3 . . . 10 to the controller <b>106</b>. Each of the ten measurement results 1, 2, 3 . . . 10 may fall within the predetermined voltage range that is defined by the lower voltage level VDDmin and the upper voltage level VDDmax. Therefore, the controller <b>106</b> may denote the calibration of the on-chip monitor circuit to be calibrated <b>102</b> as valid and the calibration of the on-chip monitor circuit to be calibrated <b>102</b> may be finished.

0029During the calibration phase t<b>2</b> of the on-chip monitor circuit to be calibrated <b>102</b>, no significant variation of the supply voltage VDD may occur and the calibration of the on-chip monitor circuit to be calibrated <b>102</b> may not be disturbed. An accurate calibration of the on-chip monitor circuit to be calibrated <b>102</b> may be performed with the supply voltage VDD being stable during the calibration phase t<b>2</b>.

0030<figref idref="DRAWINGS">FIG. 4</figref> shows a schematic circuit diagram of a further exemplary circuit arrangement <b>400</b> that includes a plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> and a controller <b>406</b>. The plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> is arranged in a network and each of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may be coupled to all the other of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>. The controller <b>406</b> is coupled to the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> and is configured to receive measurement results from them. The controller <b>406</b> is further configured to generate an output <b>412</b> in accordance with an evaluation of the measurement results. At least one feedback loop <b>414</b> is coupled to the controller <b>406</b> and the network. The at least one feedback loop <b>414</b> is configured to control a calibration of at least one <b>402</b> of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> in accordance with the output <b>412</b>.

0031Each of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may be configured to measure one or several parameters of the semiconductor chip, as described in connection with <figref idref="DRAWINGS">FIG. 1</figref> earlier herein. The controller <b>406</b> may provide the output <b>412</b> based on a combination of the measurement results received from the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>.

0032In one implementation, one of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may be an on-chip monitor circuit to be calibrated <b>402</b>. The remaining on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> may supervise the calibration of the on-chip monitor circuit to be calibrated <b>402</b>. For example, the on-chip monitor circuit to be calibrated <b>402</b> may be a temperature monitor, the first supervising on-chip monitor circuit <b>404</b> may be a supply voltage monitor, the second supervising on-chip monitor circuit <b>408</b> may be a process monitor and the third supervising on-chip monitor circuit <b>410</b> may be an aging monitor. During a calibration phase of the temperature monitor to be calibrated <b>402</b>, each of the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> may provide measurement results to the controller <b>406</b>. The controller <b>406</b> may combine the measurement results received from the supervising on-chip monitor circuits <b>404</b>. <b>408</b> and <b>410</b>. For example, the controller <b>406</b> may check if the supply voltage deviates from a predetermined voltage range and it may take into account the status of the semiconductor chip with respect to process and aging. Generally, by way of the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b>, the controller <b>406</b> may detect variations of operating conditions during the calibration phase of the temperature monitor to be calibrated <b>402</b>. Depending on the measurement results received, the controller <b>406</b> may denote the calibration of the temperature monitor to be calibrated <b>402</b> as valid or invalid.

0033The controller <b>406</b> may provide a signal at the output <b>412</b> based on a combination of the measurement results received from the supervising on-chip monitor circuits <b>404</b>. <b>408</b> and <b>410</b>. The signal at the output <b>412</b> may be provided to the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> via the feedback loop <b>414</b>. The feedback loop <b>414</b> may control the calibration of the temperature monitor to be calibrated <b>402</b>. For example, the controller <b>406</b> may initiate a re-start of a calibration of the temperature monitor to be calibrated <b>402</b> via the feedback loop <b>414</b>. By combining measurement data obtained from multiple monitor sources <b>404</b>, <b>408</b> and <b>410</b>, the calibration accuracy of the on-chip monitor circuit to be calibrated <b>402</b> may be improved.

0034The circuit arrangement <b>400</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIG. 4</figref> comprises just one feedback loop <b>414</b>. In one implementation, the circuit arrangement <b>400</b> may comprise multiple feedback loops. For example, each of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may be coupled to the controller <b>406</b> via a feedback loop. The controller <b>406</b> may control a calibration of each of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> via the feedback loop and a supervised calibration of some or all of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may be performed consecutively or concurrently.

0035In one implementation, the circuit arrangement <b>400</b> may comprise a network of autonomously working on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>. The controller <b>406</b> may control an operation of the network of autonomously working on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>. The on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may operate independently from each other. For example, the controller <b>406</b> may start or re-start a calibration of the network of autonomously working on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>. The calibration of the network of autonomously working on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may be performed without any further interaction.

0036Referring to <figref idref="DRAWINGS">FIGS. 1 and 4</figref>, a calibration of the on-chip monitor circuit to be calibrated <b>102</b> and <b>104</b> may be performed during production of the semiconductor chip that contains the on-chip monitor circuit to be calibrated <b>102</b> and <b>104</b>. For example, the calibration may be performed before and/or after packaging of the semiconductor chip. Additionally or alternatively, the calibration of the on-chip monitor circuit to be calibrated <b>102</b> and <b>104</b> may be performed during runtime. For example, the calibration may be performed at every set or reset of the semiconductor chip and/or at every change of operating conditions of the semiconductor chip, such as a change of the supply voltage VDD or the clock frequency.

0037Referring to <figref idref="DRAWINGS">FIGS. 1 and 4</figref>, in one implementation, the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>, respectively, may be configured to be operated simultaneously, i.e., they may be configured to measure parameters of the semiconductor chip simultaneously. For example, referring to <figref idref="DRAWINGS">FIG. 4</figref>, during the calibration of the temperature monitor <b>402</b>, the temperature monitor <b>402</b>, the supply voltage monitor <b>404</b>, the process monitor <b>408</b> and the aging monitor <b>410</b> may operate at the same time. The controller <b>406</b> may start the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> at the same time and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may be active at the same time. The on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> may have different measurement times. For example, the aging monitor <b>410</b> may have a longer measurement time than the supply voltage monitor <b>404</b>. Therefore, although the measurement phases of the on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> may start at the same time, the end of the measurement phases may be different.

0038Referring to <figref idref="DRAWINGS">FIGS. 1 and 4</figref>, in one implementation, at least two on-chip monitor circuits of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and of the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>, respectively, may be of the same type. For example, at least two on-chip monitor circuits may measure a same parameter of the semiconductor chip. Additionally or alternatively, at least two on-chip monitor circuits may be constructed in a same or similar manner. For example, on-chip monitor circuits <b>402</b> and <b>404</b> may be temperature monitors and on-chip monitor circuits <b>408</b> and <b>410</b> may be supply voltage monitors located.

0039In one implementation, the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>, respectively, may be arranged in various regions of the semiconductor chip and may form a monitoring system. For example, the at least two on-chip monitor circuits of the same type may be arranged in various regions of the semiconductor chip. At least two on-chip monitor circuits may measure a temperature of the semiconductor chip and they may be placed at different locations on the semiconductor chip as portions of the semiconductor chip may run at different localized temperatures. Additionally or alternatively, at least two on-chip monitor circuits may measure a supply voltage of the semiconductor chip at different locations of the semiconductor chip as parts of the semiconductor chip may be operated at different local supply voltages.

0040Each of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIG. 1</figref> and each on-chip monitor circuit of the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIG. 4</figref> may be implemented in a dedicated circuit block. Additionally or alternatively, the controller <b>106</b> and <b>406</b> may be implemented as a dedicated circuit or it may be implemented in a processor. For example, the controller <b>106</b> and <b>406</b> may be implemented in a programmable microcontroller, a digital signal processor or an application-specific processor that is equipped with a local memory.

0041The plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1 and 4</figref> may be self-calibrating. As described in connection with <figref idref="DRAWINGS">FIGS. 1 and 4</figref>, the controller <b>106</b> and <b>406</b> may start a calibration of a self-calibrating on-chip monitor circuit <b>102</b> and <b>402</b>. If the calibration is invalid, the controller <b>106</b> and <b>406</b> may initiate a re-start of the calibration. Otherwise, the calibration is valid and finished. Except for the start and the re-start, respectively, the controller <b>106</b> and <b>406</b> may not affect the operation of the self-calibrating on-chip monitor circuit <b>102</b> and <b>402</b>.

0042<figref idref="DRAWINGS">FIG. 5</figref> illustrates a schematic circuit diagram of a self-calibrating on-chip monitor circuit <b>502</b>. The self-calibrating on-chip monitor circuit <b>502</b> includes a measurement circuit <b>518</b>, a logic circuit <b>520</b> and a configuration register <b>522</b>. The configuration register <b>522</b> is coupled to the measurement circuit <b>518</b> and may control an operation of the measurement circuit <b>518</b>. The measurement circuit <b>518</b> may receive a control signal <b>514</b> that may be provided by a controller like, e.g., the controller <b>106</b> of <figref idref="DRAWINGS">FIG. 1</figref> or the controller <b>406</b> of <figref idref="DRAWINGS">FIG. 4</figref>. The control signal <b>514</b> may initiate a start or re-start of a calibration by starting or re-starting a measurement of a chip parameter within the measurement circuit <b>518</b>. The logic circuit <b>520</b> is coupled to the measurement circuit <b>518</b> and the configuration register <b>522</b>. The logic circuit <b>520</b> may receive a measurement result of a chip parameter from the measurement circuit <b>518</b> and it may control a setting of the configuration register <b>522</b> responsive to the measurement result received. For example, the measurement circuit <b>518</b> may include an internal delay line and a tapping within the internal delay line may be adjusted in accordance with the setting of the configuration register <b>522</b>. The calibration of the self-calibrating on-chip monitor circuit <b>502</b> may be performed by measuring the chip parameter several times and by adjusting the setting of the configuration register <b>522</b> several times. Generally, after a start or re-start of a calibration of the self-calibrating on-chip monitor circuit <b>502</b>, the calibration may be performed and completed without any inter-action with further circuits outside the self-calibrating on-chip monitor circuit <b>502</b>.

0043Alternatively, the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1 and 4</figref> may be on-chip monitor circuits with external calibration. In contrast to a self-calibrating on-chip monitor circuit, an on-chip monitor circuit with external calibration may inter-act with circuits outside the on-chip monitor circuit several times within a calibration phase.

0044<figref idref="DRAWINGS">FIG. 6</figref> illustrates a schematic circuit diagram of an on-chip monitor circuit with external calibration <b>602</b>. The on-chip monitor circuit with external calibration <b>602</b> includes a measurement circuit <b>618</b> and a configuration register <b>622</b>, herein called calibration control word <b>622</b>. A control signal <b>614</b> may initiate a start or re-start of a calibration by starting or re-starting a measurement of a chip parameter within the measurement circuit <b>618</b>. The measurement circuit <b>618</b> is coupled to the calibration control word <b>622</b> that may configure a setting of the measurement circuit <b>618</b>. A setting of the calibration control word <b>622</b> may be controlled by a signal <b>624</b>. The signal <b>624</b> may be provided by a controller like, e.g., the controller <b>106</b> of <figref idref="DRAWINGS">FIG. 1</figref> or the controller <b>406</b> of <figref idref="DRAWINGS">FIG. 4</figref>. That means, the controller may control the calibration of the on-chip monitor circuit with external calibration <b>602</b> by adapting a setting of the calibration control word <b>622</b>. For example, referring to <figref idref="DRAWINGS">FIG. 4</figref>, the feedback loop <b>414</b> may control the calibration by adapting the calibration control word <b>622</b> in accordance with the output <b>412</b>. During calibration of the on-chip monitor circuit with external calibration <b>602</b>, the calibration control word <b>622</b> may be updated several times.

0045Generally, a calibration of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1-6</figref> may be performed by adapting the monitor functionality by modifying the configuration register <b>522</b> and <b>622</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 5 and 6</figref>. As described in connection with <figref idref="DRAWINGS">FIG. 5</figref> earlier herein, an internal delay line may be adjusted in accordance with the setting of the configuration register <b>522</b> and <b>622</b>. Additionally or alternatively, a measurement range, a measurement resolution, a measurement time, an internal data flow, an internally, locally generated voltage, an internally, locally generated current, an internal, local capacitance, an internal resistance, an internal frequency or an internal phase difference within an on-chip monitor circuit may be adjusted.

0046Each of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1 and 4</figref> may be operated in one of three different modes, a calibration mode, a measurement mode or a disabled mode. In the disabled mode, a power supply of at least one on-chip monitor circuit <b>102</b>, <b>104</b>, <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may be disabled in order to save power.

0047The circuit arrangement <b>100</b> and <b>400</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1 and 4</figref> may be operated in one of two different modes, a supervised calibration mode and a supervised measurement mode. In the supervised calibration mode, the circuit arrangement <b>100</b> and <b>400</b> may operate as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1-6</figref>. The on-chip monitor circuit to be supervised <b>102</b> and <b>402</b> may operate in the calibration mode and the supervising on-chip monitor circuits <b>104</b>, <b>404</b>, <b>408</b> and <b>410</b> may operate in the measurement mode.

0048In the following, the supervised measurement mode will be described in connection with <figref idref="DRAWINGS">FIG. 4</figref>. However, it is to be noted that the supervised measurement mode may also be applied to the circuit arrangement <b>100</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIG. 1</figref>. In the supervised measurement mode, each of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may operate in the measurement mode. During a measurement phase, one <b>402</b> of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>, herein called characterizing on-chip monitor circuit <b>402</b>, may provide measurement results of a chip parameter to be measured or characterized, respectively. The other on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> of the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>, herein called supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b>, may provide measurement results of chip parameters to be supervised during the measurement phase.

0049The controller <b>406</b> may receive the measurement results from the characterizing on-chip monitor circuit <b>402</b> and from the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b>. The controller <b>406</b> may combine the measurement results received from the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b>. For example, the controller <b>406</b> may detect if at least one of the measurement results received from the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> deviates from a predetermined range. The controller <b>406</b> may denote the measurement results received from the characterizing on-chip monitor circuit <b>402</b> as invalid if at least one of the measurement results of the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> deviates from the predetermined range and it may initiate a repeat of the measurement phase. If none of the measurement results of the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> deviates from the predetermined range the measurement results received from the characterizing on-chip monitor circuit <b>402</b> may be denoted as valid and the measurement phase may be finished.

0050The controller <b>406</b> may provide a further output <b>416</b> in accordance with a combined evaluation of the measurement results received from the plurality of one on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>. A signal may be provided at the further output <b>416</b> if the measurement results received from the characterizing on-chip monitor circuit <b>402</b> are denoted as valid. A further circuit may receive the signal provided at the further output <b>416</b> and the further circuit may adapt a parameter of the semiconductor chip responsive to the signal. The parameter to be adapted may be one of the parameters listed in connection with <figref idref="DRAWINGS">FIG. 1</figref> earlier herein. Generally, the controller <b>406</b> is configured to adapt a parameter of the semiconductor chip in accordance with a combination of the measurement results received from the plurality of one on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> if the measurement results received from the characterizing on-chip monitor circuit <b>402</b> are denoted as valid.

0051For example, in the supervised measurement mode, a supervised measurement of a temperature of the semiconductor chip or of a part of the semiconductor chip, respectively, may be performed. The characterizing on-chip monitor circuit <b>402</b> may be a temperature monitor, the supervising on-chip monitor circuit <b>404</b> may be a supply voltage monitor, the supervising on-chip monitor circuit <b>408</b> may be an aging monitor and the supervising on-chip monitor circuit <b>410</b> may be a process monitor. During a measurement phase of the temperature, the controller <b>406</b> may receive measurement results from the characterizing temperature monitor <b>402</b>. In addition, the controller <b>406</b> may collect measurement results from the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b>. The controller <b>406</b> may check for each of the measurement results received from the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> if they deviate from a predetermined range. If none of the measurement results received from the supervising monitor circuits <b>404</b>, <b>408</b> and <b>410</b> deviates from the predetermined range, the measurement results received by the temperature monitor <b>402</b> may be denoted as valid. Otherwise, the measurement results received by the temperature monitor <b>402</b> may be denoted as invalid.

0052For example, by way of the supply voltage monitor <b>404</b>, the controller <b>406</b> may detect a sudden ir-drop that may take place during the measurement phase of the temperature and that may corrupt the measurement performed by the temperature monitor <b>402</b>. In case of a sudden ir-drop, the measurement results received from the temperature monitor <b>402</b> may be denoted as invalid. If the measurement results received from the temperature monitor <b>402</b> are denoted as valid, the controller <b>406</b> may provide a signal at the further output <b>416</b> that may correspond to the temperature measured during the measurement phase. A further circuit may receive the signal provided at the further output <b>416</b> and the further circuit may adapt, e.g., a clock frequency of the semiconductor chip according to the signal. For example, the further circuit may decrease a frequency of a clock of the semiconductor chip if the temperature measured by the temperature monitor <b>402</b> has been increased. If the CMOS circuit performance decreases with decreasing temperature, as for example in modern CMOS technologies with minimum features sizes below 65 nm, i.e. 45 nm node or 28 nm node, or at ultra-low VDD operation with VDD less than 1V, the further circuit may decrease the frequency or may increase the supply voltage in order to prevent a system crash. Generally, the further circuit may initiate a countermeasure in accordance with the signal received from the further output <b>416</b>.

0053Generally, in the supervised measurement mode, the controller <b>406</b> may determine a status of the semiconductor chip based on the measurement results received from the characterizing on-chip monitor circuit <b>402</b> and the supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b>. A signal that is provided at the further output <b>416</b> may correspond to the status of the semiconductor chip. A further circuit may be coupled to the further output <b>416</b> of the semiconductor circuit <b>400</b> and the further circuit may change the status of the semiconductor chip responsive to the signal received from the further output <b>416</b>. By supervising one or several chip parameters during a measurement phase of a chip parameter to be characterized, an accurate measurement of the chip parameter to be characterized may be allowed for. It may be detected if substantial, temporal variations of the chip parameters to be supervised disturb the measurement of the chip parameter to be characterized. Therefore, it may be prevented that the status of the semiconductor chip may be changed erroneously.

0054The controller <b>406</b> may compute the status of the semiconductor chip according to a predefined algorithm. For example, as described in connection with <figref idref="DRAWINGS">FIG. 4</figref> earlier herein, the controller <b>406</b> may check if the measurement results received from supervising on-chip monitor circuits <b>404</b>, <b>408</b> and <b>410</b> deviate from a predetermined range. Additionally or alternatively, the controller <b>406</b> may apply a different algorithm to the measurement results received from the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>. For example, the controller <b>406</b> may perform an averaging of the measurement results and/or it may compare the measurement results to a predetermined threshold value.

0055The further circuit may be implemented on the same semiconductor chip as the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>, i.e., they may be implemented on a same silicon substrate. Alternatively, the further circuit may be implemented on a different semiconductor chip or silicon substrate, respectively. The further circuit may include at least one of a power management circuit, a clock generator, a clock gating circuit, a programmable delay in clock and combinational logic paths and/or a wakeup circuitry of a computational circuit. The further circuit may change the status of the semiconductor chip by changing at least one of a supply voltage, a substrate voltage of an NFET and/or a PFET transistor, a clock frequency and a propagation delay in clock and combinational logic paths. Additionally or alternatively, the further circuit may change the status of the semiconductor chip by blocking the propagation of clock edges into a block and/or by activating an additional computational circuit.

0056As described in connection with <figref idref="DRAWINGS">FIGS. 1 and 4</figref> earlier herein, during a measurement phase or a calibration phase, each on-chip monitor circuit of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may provide several measurement results to the controller <b>106</b> and <b>406</b>. Alternatively, at least one of the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> may provide just one measurement result to the controller <b>106</b> and <b>406</b> during a measurement phase or a calibration phase. The controller <b>106</b> and <b>406</b> may combine the one or several measurement results received from the plurality of on-chip monitor circuits <b>102</b> and <b>104</b> and the network of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b>.

0057<figref idref="DRAWINGS">FIG. 7</figref> shows a further exemplary circuit arrangement <b>700</b> that includes a plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> and a controller <b>706</b>. Additionally, the circuit arrangement <b>700</b> includes a plurality of post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> and a calibration circuit <b>726</b>. Each of the post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> may be coupled to a dedicated on-chip monitor circuit <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b>. Each of the post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> may receive measured raw data <b>726</b>, <b>728</b>, <b>730</b> and <b>732</b> from the dedicated on-chip monitor circuit <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> and may perform a data conversion into a digital data output <b>734</b>, <b>736</b>, <b>738</b> and <b>740</b>. The digital data output <b>734</b>, <b>736</b>, <b>738</b> and <b>740</b> of each of the post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> may be provided to the controller <b>706</b>. The data conversion within the post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> may include at least one of an analog-to-digital conversion, a comparison, a look-up-table functionality and a signal processing functionality, such as filtering, average value computation, minimum and maximum operation or arithmetic-logic operations.

0058The plurality of post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> may be coupled to the controller <b>706</b> and an operation of the plurality of post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> may be controlled by post-processing control signals <b>742</b>, <b>744</b>, <b>746</b> and <b>748</b> provided by the controller <b>706</b>. For example, the controller <b>706</b> may configure a mode of operation of the plurality of post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> via the post-processing control signals <b>742</b>, <b>744</b>, <b>746</b> and <b>748</b>.

0059The controller <b>706</b> may further provide monitor control signals <b>750</b>, <b>752</b>, <b>754</b> and <b>756</b> to the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> and it may control an operation of the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> via the monitor control signals <b>750</b>, <b>752</b>, <b>754</b> and <b>756</b>. For example, the controller <b>706</b> may start, stop or reset the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> or it may set the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> in one of a calibration mode, a measurement and a disabled mode.

0060The controller <b>706</b> may provide an output signal <b>716</b> corresponding to the chip status. Output signal <b>716</b> may be determined by a combined evaluation of the post-processed measurement results <b>734</b>, <b>736</b>, <b>738</b> and <b>740</b> of the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b>.

0061The calibration circuit <b>726</b> may be coupled to the controller <b>706</b> and to the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> and it may control an operation of the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> during a calibration phase. The calibration circuit <b>726</b> may receive a calibration control signal <b>758</b> from the controller <b>706</b> and it may receive information regarding a start or stop of a calibration or a calibration being valid or invalid via the control signal <b>758</b>. At an output <b>712</b>, the calibration circuit <b>726</b> may provide a control signal to the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> via a feedback loop <b>714</b>. The calibration circuit <b>726</b> may initiate a start or re-start of a calibration of at least one of the plurality of on-chip monitor circuits <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> via the feedback loop <b>714</b>.

0062As illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, each of the post-processors <b>718</b>, <b>720</b>, <b>722</b> and <b>724</b> may be coupled to a dedicated on-chip monitor circuit <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b>. Alternatively, at least two of the plurality of on-chip monitor circuit <b>702</b>, <b>704</b>, <b>708</b> and <b>710</b> may be coupled to a common post-processor.

0063Implementations as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1-7</figref> may allow for an accurate calibration of on-chip monitor circuits and an accurate measurement of chip parameters despite of transient variations of operating conditions. The circuit arrangements <b>100</b>, <b>400</b> and <b>700</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1-7</figref> may detect the variations and may repeat the calibration or the measurement, respectively. All or most part of the circuit arrangements <b>100</b>, <b>400</b> and <b>700</b> may be implemented digitally. Therefore, implementations of the circuit arrangements <b>100</b>, <b>400</b> and <b>700</b> may only require a small area and a power consumption of the circuit arrangements <b>100</b>, <b>400</b> and <b>700</b> may be low.

0064Features of the implementations as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1-7</figref> may be combined, unless specifically noted otherwise. For example, in one implementation, the circuit arrangement <b>100</b> of <figref idref="DRAWINGS">FIG. 1</figref> may include more than two on-chip monitor circuits and/or the on-chip monitor circuits of the circuit arrangement <b>100</b> may be linked to each other similar to the circuit arrangement <b>400</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIG. 4</figref>. In a further implementation, the plurality of on-chip monitor circuits <b>402</b>, <b>404</b>, <b>408</b> and <b>410</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIG. 4</figref> may not be linked to each other similar to the circuit arrangement <b>100</b> as illustrated and described in connection with <figref idref="DRAWINGS">FIG. 1</figref>.

0065<figref idref="DRAWINGS">FIG. 8</figref> shows a system <b>858</b> that includes a circuit arrangement <b>800</b>, a functional circuit <b>860</b> and a regulator circuit <b>862</b>. The circuit arrangement <b>800</b> may include one of the circuit arrangements as illustrated and described in connection with <figref idref="DRAWINGS">FIGS. 1-7</figref> earlier herein. The circuit arrangement <b>800</b> may be coupled to the regulator circuit <b>862</b> and it may provide a signal at an output <b>816</b> to the regulator circuit <b>862</b>. As described in connection with <figref idref="DRAWINGS">FIG. 4</figref>, the signal provided at the output <b>816</b> may correspond to a status of a semiconductor chip.

0066As illustrated in <figref idref="DRAWINGS">FIG. 8</figref>, the regulator circuit <b>862</b> may be coupled to the functional circuit <b>860</b> and the functional circuit <b>860</b> may perform at least part of a function of a semiconductor chip. For example, the functional circuit <b>860</b> may perform arithmetic operations or storing operations. The regulator circuit <b>862</b> may include a phase-locked loop (PLL) <b>864</b> and it may provide a clock signal <b>866</b> to the functional circuit <b>860</b>. Additionally or alternatively, the regulator circuit <b>862</b> may include a power management circuit (PMU) <b>868</b> and it may provide a supply voltage signal <b>870</b> to the functional circuit <b>860</b>. The regulator circuit <b>862</b> may adapt a frequency provided via the clock signal <b>866</b> and a voltage level provided via the supply voltage signal <b>870</b> responsive to the signal provided at the output <b>816</b> of the circuit arrangement <b>800</b>.

0067In one implementation, the circuit arrangement <b>800</b> and the functional circuit <b>860</b> may be arranged on a same semiconductor chip, i.e., they may be implemented on a same silicon substrate. During a measurement phase, the circuit arrangement <b>800</b> may determine a current status of the semiconductor chip and it may provide a signal at the output <b>816</b> that corresponds to the current status of the semiconductor chip. The regulator circuit <b>862</b> may regulate a parameter of the semiconductor chip responsive to the signal received from the output <b>816</b> of the circuit arrangement <b>800</b>. The regulator circuit <b>862</b> may adapt the parameter of the semiconductor chip by changing a feature of at least one of the signals <b>866</b> and <b>870</b> provided to the functional circuit <b>860</b> For example, if the circuit arrangement <b>800</b> determines an increase of a temperature, the regulator circuit <b>862</b> may decrease a frequency of the clock signal <b>866</b> provided to the functional circuit <b>860</b>.

0068By placing the circuit arrangement <b>800</b> and the functional circuit <b>860</b> on the same semiconductor chip, the circuit arrangement <b>800</b> and the functional circuit <b>860</b> may both encounter the same operating conditions. In one implementation, the on-chip monitor circuits of the circuit arrangement <b>800</b> may include similar CMOS circuits as the functional circuit <b>860</b> and effects acting on the functional circuit <b>860</b> may also act on the on-chip monitor circuits of the circuit arrangement <b>800</b>. The regulator circuit <b>862</b> may be implemented on the same semiconductor chip as the circuit arrangement <b>800</b> and the functional circuit <b>860</b>. Alternatively, the regulator circuit <b>862</b> may be implemented on a different semiconductor chip.

0069In addition to the signals as illustrated in <figref idref="DRAWINGS">FIG. 8</figref>, the functional circuit <b>860</b> may provide information to the circuit arrangement <b>800</b>. For example, the functional circuit <b>860</b> may provide information concerning running applications and/or performance requirements to the circuit arrangement <b>800</b>. Additionally or alternatively, the regulator circuit <b>862</b> may provide information to the circuit arrangement <b>800</b>. For example, the regulator circuit <b>862</b> may provide information concerning operation conditions, e.g., upper/lower supply voltage range, to the circuit arrangement <b>800</b>. The circuit arrangement <b>800</b> may provide the signal at the output <b>816</b> in accordance with the information received from the functional circuit <b>860</b> and the regulator circuit <b>862</b>. Generally, the circuit arrangement <b>800</b> may be able to account for information provided by the system environment in which it is implemented. Therefore, the circuit arrangement <b>800</b> may be implemented flexibly.

Exemplary Methods

0070<figref idref="DRAWINGS">FIG. 9</figref> illustrates a flow diagram <b>900</b> that includes a number of operations supervising an on-chip monitor circuit. <figref idref="DRAWINGS">FIG. 10</figref> illustrates a flow diagram <b>1000</b> that includes a number of operations calibrating an on-chip monitor circuit. Unless stated otherwise, the order in which the operations are described is not intended to be construed as a limitation. Operations may be repetitive, may be combined in any order and/or may be in parallel to implement the process. In portions of the following discussion, reference may be made to the illustrations of <figref idref="DRAWINGS">FIGS. 1-8</figref> and the subject matter thereof. The procedures described in connection with <figref idref="DRAWINGS">FIGS. 9 and 10</figref> may be realized utilizing the previously described implementations.

0071Referring to <figref idref="DRAWINGS">FIG. 9</figref>, at block <b>902</b>, a measurement of at least one of a plurality of on-chip monitor circuits is started. Each of the plurality of on-chip monitor circuits is configured to measure a parameter of a semiconductor chip. The at least one of a plurality of on-chip monitor circuits is herein called supervising on-chip monitor circuit. The supervising on-chip monitor circuit is configured to measure a parameter of the semiconductor chip, herein called parameter to be supervised.

0072At block <b>904</b>, a measurement of an on-chip monitor circuit to be supervised is started. The on-chip monitor circuit to be supervised is configured to measure a parameter of the semiconductor chip, herein called parameter to be characterized.

0073At block <b>906</b>, at least one measurement result from the supervising on-chip monitor circuit is processed. For example, the processing may include comparing the at least one measurement result from the supervising on-chip monitor circuit to a predetermined range.

0074At block <b>908</b>, a measurement result of the on-chip monitor circuit to be supervised is denoted as invalid if the at least one measurement result from the supervising on-chip monitor circuit deviates from a predetermined range.

0075By supervising the parameter to be supervised during a measurement phase of a parameter to be characterized, an accurate measurement of the parameter to be characterized may be allowed for. It may be detected if variations of the chip parameters to be supervised disturb the measurement of the chip parameter to be characterized.

0076In one implementation, the on-chip monitor circuit to be supervised is configured to measure a parameter that is different from the parameters to be measured by the plurality of on-chip monitor circuits. That means, the parameter to be characterized may differ from the supervising parameters.

0077In a further implementation, the starting of the measurement of the on-chip monitor circuit to be supervised takes place temporally after the starting of the measurement of the supervising on-chip monitor circuit. Therefore, the supervising on-chip monitor circuit may already be measuring the parameter to be supervised at the point of time when the on-chip monitor circuit to be supervised may start measuring the parameter to be characterized.

0078In a further implementation, at least the steps of blocks <b>902</b>-<b>906</b> are repeated if the at least one measurement result of the on-chip monitor circuit to be supervised is denoted as invalid. The steps of blocks <b>902</b>-<b>906</b> may be repeated until the at least one measurement result of the on-chip monitor circuit to be supervised is denoted as valid. As soon as the at least one measurement result of the on-chip monitor circuit to be supervised is denoted as valid, the measurement of the on-chip monitor circuit to be supervised may be finished.

0079In a further implementation, a measurement mode is activated and a parameter of the semiconductor chip is adapted in accordance with the measurement result of the on-chip monitor circuit to be supervised if the measurement result of the on-chip monitor circuit to be supervised is not denoted as invalid. By adapting the parameter of the semiconductor chip, a status of the semiconductor chip may be changed. The status of the semiconductor chip may be changed based on the measurement result of the on-chip monitor circuit to be supervised. For example, a countermeasure may be triggered responsive to the measurement result of the on-chip monitor circuit to be supervised. However, the countermeasure may just be triggered if the measurement result of the on-chip monitor circuit to be supervised is denoted as valid. Therefore, an erroneous update of the status of the semiconductor chip may be prevented.

0080In a further implementation, a plurality of measurement results is received from the supervising on-chip monitor circuit within a predetermined period. The processing of the measurements results at block <b>906</b> includes processing of the plurality of measurement results. By processing a plurality of measurement results, the accuracy of the measurement of the chip parameter to be characterized may be improved.

0081Referring to <figref idref="DRAWINGS">FIG. 10</figref>, at block <b>1002</b>, a plurality of on-chip monitor circuits is activated. The plurality of on-chip monitor circuits is configured to measure at least one parameter of a semiconductor chip and is herein called supervising on-chip monitor circuits.

0082At block <b>1004</b>, an on-chip monitor circuit to be calibrated is activated.

0083At block <b>1006</b>, measurement results from the supervising on-chip monitor circuits are combined. For example, the combining may include checking if each of the measurement results falls within a predetermined range.

0084At block <b>1008</b>, a calibration of the on-chip monitor circuit to be calibrated is controlled in accordance with the combination of the measurement results.

0085By monitoring at least one parameter of the semiconductor chip during a calibration phase of the on-chip monitor circuit to be calibrated, an accurate calibration of the on-chip monitor circuit to be calibrated may be allowed for. It may be detected if substantial, temporal variations of the at least one parameter disturbing the calibration of the on-chip monitor circuit to be calibrated.

0086In one implementation, controlling the calibration includes adapting a setting of the on-chip monitor circuit to be calibrated. By adapting the setting, the functionality of the on-chip monitor circuit to be calibrated may be changed. For example, the functionality of the on-chip monitor circuit to be calibrated may be changed with respect to measurement properties of the on-chip monitor circuit to be calibrated.

0087In a further implementation, controlling the calibration includes repeating the activating steps of blocks <b>1002</b> and <b>1004</b> and the combining step of block <b>1006</b> if at least one of the measurement results deviates from a predetermined range. If at least one of the measurement results deviates from a predetermined range, the calibration of the on-chip monitor circuit to be calibrated may be denoted as invalid. If none of the measurement results from the plurality of on-chip monitor circuits deviated from a predetermined range, the calibration of the on-chip monitor circuit to be calibrated may be denoted as valid and finished. The activating steps of blocks <b>1002</b> and <b>1004</b> and the combining step of block <b>1006</b> may be repeated until the calibration of the on-chip monitor circuit to be calibrated is denoted as valid.

CONCLUSION

0088For the purposes of this disclosure and the claims that follow, the term “coupled” has been used to describe how various elements interface. Such described interfacing of various elements may be either direct or indirect. Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims. It is within the scope of this disclosure to combine various features of the different implementations and claims to produce variations thereof.