Stacked Via Structure For Metal Fuse Applications

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention relates to electronic fuses (e-fuses). More specifically, the present invention relates to stacked via structures for metal fuse applications.

00032. Description of the Related Art

0004In advanced technologies, e-fuses have been implemented at the polycrystalline silicon (PC) level. During programming, a high current pulse of short duration is passed through the structure. This irreversibly migrates silicide on top of the PC, causing a change in resistance and thus acting as a programmable fuse.

0005As scaling progresses, it is becoming harder to implement these e-fuses at the PC level due to drop in maximum allowable currents through the first metal layer or conductor. Also, the collateral damage associated with the event is becoming more difficult to contain. As a result, there is a drive to implement these fuses at the metal interconnect levels and use the phenomenon of electromigration (EM) to program the fuses.

0006The power requirements to cause EM in copper (Cu) interconnects are much larger than the typical PC level fuses. This is partly due to the fact that the liner materials used in Cu interconnects, such as tantalum (Ta) and tantalum nitride (TaN), must be blown along with the Cu in order to achieve proper fuse programming. Hence, there is a need to devise fuse structures that are susceptible to EM without compromising the reliability of the remaining interconnects.

0007In a conventional metal fuse approach, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, a two-level structure comprises conductor <b>11</b> embedded in dielectric layer <b>10</b>, and via <b>21</b> and line <b>22</b> embedded in dielectric layer <b>20</b>. A cap layer <b>23</b> is typically deposited over line <b>22</b> and dielectric layer <b>20</b>. Electron flow is from via <b>21</b> into line <b>22</b>. A high current is applied between the positive current connection (I+) and negative current connection (I−) to induce EM failure. Voltage across the structure is measured using the positive (V+) and negative (V−) voltage connections. The electron flow through the fuse structure is from the lower level metal, conductor <b>11</b>, to the upper level metal, line <b>22</b>.

0008With this design, some of the failures occur in via <b>21</b> while other failures occur in line <b>22</b>, resulting in a lack of control over the failure location and leading to variability in the final resistance of the fuse structure after programming. Moreover, it is not possible to electrically determine whether the failure is in via <b>21</b> or line <b>22</b>. Failures in line <b>22</b> are less desirable because cap layer <b>23</b> may be compromised during the programming process.

0009The programming process with this design may lead to damage in the surrounding dielectric layer <b>20</b>. It is likely that material from the blown fuse area will be present in the damaged dielectric region. If this is the case, then there is concern that the material will migrate throughout the dielectric, causing a short circuit to neighboring lines.

0010Therefore, a structure is needed such that failures occur preferentially in the via and not the line. Also, a detection method is needed to determine whether the programming process causes damage in the via or the line. The structure should allow for determining whether material from the blown fuse area has migrated into the dielectric region. It would also be desirable to prevent further migration of the blown fuse material.

SUMMARY OF THE INVENTION

0011The present invention provides a back end of the line fuse structure. The fuse structure promotes failures in certain areas of a fuse. The present invention further provides a method for detecting where the failures occur in a fuse and a method for detecting damage in a fuse.

0012According to an embodiment of the present invention, a fuse structure is provided. The fuse structure includes: a first dielectric layer having a first conductive via and a first conductive line disposed in a first cavity formed in the first dielectric layer, the first conductive via and the first conductive line having a first liner disposed along at least vertical surfaces of the first cavity; a second dielectric layer above the first dielectric layer, the second dielectric layer having a second conductive via and a second conductive line disposed in a second cavity formed in the second dielectric layer, the second conductive via and the second conductive line being in electrical contact with the first conductive via and the first conductive line, and having a second liner disposed along at least vertical surfaces of the second cavity; wherein at least a portion of the first liner has a thickness less than the second liner.

0013According to a further embodiment of the present invention, another fuse structure is provided. The fuse structure includes: a first dielectric layer having a first conductive via and a first conductive line within a first dual damascene cavity formed in the first dielectric layer, the first conductive via and the first conductive line surrounded laterally by a first liner; a second dielectric layer above the first dielectric layer having a second conductive via and a second conductive line embedded within a second dual damascene cavity formed in the second dielectric layer, the second conductive via and second conductive line in electrical contact with the first conductive via and the first conductive line and surrounded laterally by a second liner; wherein the first liner surrounding laterally the first conductive via and the first conductive line has a thickness of less than about 30 nm, the second liner surrounding laterally the second conductive via and the second conductive line has a thickness of greater than about 30 nm.

0014According to another embodiment of the present invention, a further fuse structure is provided. The fuse structure includes: a first dielectric layer having a first conductive via and a first conductive line disposed in a first cavity formed in the first dielectric layer, the first conductive via and the first conductive line having a first liner disposed along at least vertical surfaces of the first cavity; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having a second conductive via and a second conductive line disposed in a second cavity formed in the second dielectric layer, the second conductive via and the second conductive line being in electrical contact with the first conductive via and the first conductive line, the second conductive line laterally extending around the second conductive via such that the conductive line extends in all directions wider than at least a diameter of an upper portion of the first conductive via, and having a second liner disposed along at least vertical surfaces of the second cavity; wherein the first liner has a thickness less than the second liner.

0015According to a further embodiment of the present invention, a method for electrically detecting failures in a conductive via and a conductive line is provided. The method includes the steps of: forcing current through a fuse structure between a positive current connection and a negative current connection; measuring voltage over each of a first voltage connection and a second voltage connection in the fuse structure; and detecting a failure in one of a conductive via and a conductive line; wherein failure occurs in the conductive via if an open circuit exists at both the first and second voltage connections such that there is no current flow at the voltage connections when current is forced; and wherein a failure occurs in the conductive line if an open circuit exists at only one of the first and second voltage connections such that there is no current flow at one of the voltage connections and an open circuit does not exist at the other when current is forced.

0016According to another embodiment of the present invention, a method for electrically detecting damage in dielectric regions of a fuse is provided. The method includes the steps of: applying voltage between a negative current connection and an positive current connection; measuring current between a positive current connection and a negative current connection; and detecting damage in a dielectric region wherein damage exists and has extended where a short circuit is measured between the positive current connection and the negative current connection.

0017According to a further embodiment of the present invention, a fuse structure for detecting material from damage by a blown fuse is provided. The fuse structure includes: a first dielectric layer disposed on the dielectric material having a first conductive via and a first conductive line disposed in a first cavity formed in the first dielectric layer, the first conductive via and the first conductive line having a first liner disposed along at least vertical surfaces of the first cavity; a second conductive via and a second conductive line disposed in a second cavity formed in the first dielectric layer and having a second liner disposed along at least vertical surfaces of the second cavity, wherein the second conductive via and the second conductive line are not in contact with the first conductive via and the first conductive line; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having a third conductive via and a third conductive line disposed in a third cavity formed in the second dielectric layer, the third conductive via and the third conductive line being in electrical contact with the first conductive via and the first conductive line, the second conductive line laterally extending around the third conductive via such that the third conductive line extends in all directions wider than at least a diameter of an upper portion of the first conductive via, and having a third liner disposed along at least vertical surfaces of the third cavity; wherein the first liner has a thickness less than the second liner.

0018According to another embodiment of the present invention, a method of manufacturing a fuse structure is provided. The method includes the steps of: forming a first cavity in a first dielectric layer, the first dielectric layer disposed on a dielectric material, the dielectric material having a conductor embedded therein, the first cavity in contact with the conductor; depositing a first liner on all surfaces of the first cavity; depositing a seed layer in the first cavity; filling the first cavity with a conductive material forming a first via and a first line; depositing a second dielectric layer laterally disposed on the first cavity; forming a second cavity in the second dielectric layer; depositing a second liner on all surfaces of the first cavity; depositing a second seed layer in the cavity; and filling the second cavity with a conductive material forming a second via and a second line, the second via and the second line being in electrical contact with the first via and the first line.

BRIEF DESCRIPTION OF THE DRAWINGS

0019The features and elements of the present invention are set forth with respect to the appended claims and illustrated in the drawings.

0020<figref idref="DRAWINGS">FIG. 1</figref> illustrates a schematic cross section of a conventional metal fuse structure.

0021<figref idref="DRAWINGS">FIG. 2</figref> illustrates a schematic cross section of the present invention having a stacked via metal fuse structure.

0022<figref idref="DRAWINGS">FIG. 3</figref> illustrates a schematic cross section of the present invention having a stacked via metal fuse structure and an extended conductive line.

0023<figref idref="DRAWINGS">FIG. 4</figref> illustrates a top view of the present invention having a stacked via metal fuse structure and an extended conductive line.

0024<figref idref="DRAWINGS">FIG. 5</figref> illustrates a schematic cross section of the present invention having a stacked via metal fuse structure, an extended conductive line and an adjacent conductive via and conductive line.

0025<figref idref="DRAWINGS">FIGS. 6A-6I</figref> illustrate the method of manufacturing the fuse structure of the present invention.

0026<figref idref="DRAWINGS">FIG. 7</figref> illustrates methods for creating poor liner coverage in the fuse structure of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0027The present invention provides a back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios, which makes liner and seed coverage inside of the vias poorer. This weakness in the liner and seed layers leads to a higher probability of electromigration (EM) failure. The present invention includes a fuse structure to address failures due to poor liner and seed coverage. Design features allow for determining the extent of the damaged region following fuse programming. Other design features make it possible to prevent further propagation of the damaged dielectric region.

0028The following describes embodiments of the present invention with reference to the drawings. The embodiments are illustrations of the invention, which can be embodied in various forms. The present invention is not limited to the embodiments described below, rather representative for teaching one skilled in the art how to make and use it. Some aspects of the drawings repeat from one drawing to the next. The aspects retain their same numbering from their first appearance throughout each of the preceding drawings.

0029With reference now to <figref idref="DRAWINGS">FIG. 2</figref>, a fuse structure in accordance with the present invention is shown. The fuse structure is above and in electrical contact with conductor <b>111</b> embedded in dielectric material <b>110</b>. Dielectric layer <b>120</b> is disposed above dielectric material <b>110</b>. Conductive via <b>122</b> and conductive line <b>123</b> are disposed in cavity <b>121</b> formed in dielectric layer <b>120</b>. Preferably, conductive line <b>123</b> is formed above conductive via <b>122</b>. Liner <b>124</b> is disposed along at least vertical surfaces of cavity <b>121</b>. Preferably, liner <b>124</b> is also disposed along a bottom surface of cavity <b>121</b>. Dielectric layer <b>130</b> is disposed above dielectric layer <b>120</b>. Conductive via <b>132</b> and conductive line <b>133</b> are disposed in cavity <b>131</b> formed in dielectric layer <b>130</b>. Conductive via <b>132</b> and line <b>133</b> are in electrical contact with conductive via <b>122</b> and conductive line <b>123</b>. Liner <b>134</b> is disposed along at least vertical surfaces of cavity <b>131</b>. Preferably, liner <b>134</b> is further disposed along a horizontal surface <b>135</b> beneath line <b>133</b>, a bottom surface of cavity <b>131</b> and vertical surfaces of conductive line <b>133</b>. The electron flow through the fuse structure is from the lower level metal, conductor <b>111</b>, through conductive via <b>122</b>, conductive line <b>123</b> and conductive via <b>132</b>, to the upper level metal, conductive line <b>133</b>.

0030Liner <b>124</b> preferably has poor coverage as compared to at least one portion of liner <b>134</b>. Liner <b>124</b> preferably has a thickness less than the thickness of liner <b>134</b> such that upon application of high current between the positive current connection (I+) and negative voltage connection (I−) to induce electromigration (EM) failure, failure occurs preferentially in conductive via <b>122</b> rather than in conductive via <b>132</b> or conductive line <b>133</b>. Specifically, liner <b>124</b> preferably has a thickness of less than about 30 nm and liner <b>134</b> preferably has a thickness of greater than about 30 nm. In this structure, EM failures are more likely to occur in conductive via <b>122</b> rather than in conductive via <b>132</b> or conductive line <b>133</b>, because relatively lower power is required to cause a failure in conductive via <b>122</b> due to the poor coverage of liner <b>124</b>.

0031Any suitable dielectric material may be used for dielectric material <b>110</b> and dielectric layers <b>120</b> and <b>130</b>. The material used for each of dielectrics <b>110</b>, <b>120</b> and <b>130</b> may be the same or different. Typical dielectric materials include any now known or later developed porous or non-porous dielectric material such as silicon oxide (SiO), silicon nitride (Si₃N₄), hydrogenated silicon oxycarbide (SiCOH), silsesquioxanes, carbon-doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, SiLK™ (a polyarylene ether available from Dow Chemical Corporation), spin-on silicon-carbon contained polymer material available from JSR Corporation, and other low dielectric constant (&lt;3.9) materials or layers thereof.

0032A dielectric barrier layer or capping layer is disposed above each of dielectric material <b>110</b> and dielectric layers <b>120</b> and <b>130</b>. The material used for each capping layer may be the same or different. Typical dielectric materials for the capping layer include any now known or later developed dielectric layer such a silicon carbide (SiC), silicon nitride (Si₃N₄), silicon dioxide (SiO₂), and nitrogen or hydrogen doped silicon carbide (SiC(N,H)).

0033Any suitable liner material may be used for liners <b>124</b> and <b>134</b>, and the material used for each of liners <b>124</b> and <b>134</b> may be the same or different. Typical liner materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), ruthenium (Ru) and ruthenium nitride (RuN).

0034Any suitable conductive material may be used for conductor <b>111</b>, conductive via <b>122</b>, conductive line <b>123</b>, conductive via <b>132</b> and conductive line <b>133</b>. The material used for each of conductor <b>111</b>, conductive via <b>122</b>, conductive line <b>123</b>, conductive via <b>132</b> and conductive line <b>133</b> may be the same or different. Typical conductive materials include copper (Cu), aluminum (Al), silver (Ag), gold (Au) and alloys.

0035Due to the nature of the liner deposition process, liner coverage in the via depends on which via sidewall is being covered. In the case of Ta and TaN, a physical vapor deposition (PVD) process is used such that the line feature above the via will affect the liner coverage in the via. The same holds for the Cu seed layer that is deposited by PVD following liner deposition. In <figref idref="DRAWINGS">FIG. 1</figref>, poor liner coverage occurs on via sidewall <b>24</b> that is opposite to an end <b>25</b> of line <b>22</b> while good liner coverage occurs on the other via sidewall <b>26</b>. This is a result of a dielectric shadowing effect in which the presence of a line end prevents liner material from adequately coating the opposite via sidewall. This represents a less than ideal situation since vias with good liner coverage will require higher power to be blown.

0036In order to combat the shadowing effect, a further embodiment of the present invention permits good liner and seed coverage throughout conductive via <b>132</b>, because failures may still occur in conductive via <b>132</b> and conductive line <b>133</b>. In a preferred embodiment of the present invention, liner coverage can be influenced by the extent to which the line opening extends laterally beyond the via opening. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, conductive line <b>133</b> extends laterally beyond a side <b>136</b> of conductive via <b>132</b>. Conductive line <b>133</b> can also extend laterally around conductive via <b>132</b> by a certain distance in all directions, as seen in <figref idref="DRAWINGS">FIG. 3</figref>. The extension will ensure good liner and seed coverage on sidewalls <b>136</b> and <b>137</b> of conductive via <b>132</b>. Making the width of conductive line <b>133</b> much wider than the diameter of an upper portion of conductive via <b>122</b> in all directions, as seen in <figref idref="DRAWINGS">FIG. 4</figref>, ensures that all sidewalls of conductive via <b>132</b> receive good liner and seed coverage. As the width of conductive line <b>133</b> increases in all directions, liner and seed coverage of conductive via <b>132</b> continues to improve in all directions. The improvement in liner and seed coverage of conductive via <b>132</b> reduces the potential for failures occurring in conductive via <b>132</b> and conductive line <b>133</b> and promotes failures in conductive via <b>122</b>.

0037Extending conductive line <b>133</b> also provides the ability to electrically distinguish between failures in conductive via <b>122</b>, conductive via <b>132</b> and conductive line <b>133</b>. Following fuse programming where a high current is forced through the fuse structure to blow the fuse, current is forced between a positive current connection (I+) at conductive line <b>133</b> and a negative current connection (I−) at conductor <b>111</b>. The voltage across the structure would be measured over a positive voltage connection (V+) along conductive line <b>133</b> and a negative voltage connection (V−) at conductor <b>111</b>. If an open circuit is measured at both of the positive (V+) voltage connections and the negative (V−) voltage connection, then the failure occurred in a conductive via, for example conductive via <b>122</b> in <figref idref="DRAWINGS">FIG. 3</figref>. Thus, there is no current flow at the voltage connections when current is forced. However, if an open circuit exists only at one of the positive voltage connections, then the failure occurs in a conductive line, for example conductive line <b>133</b> in <figref idref="DRAWINGS">FIG. 3</figref>. This testing can be used to screen parts such that only via failures are allowed in a product.

0038Forcing high current through the fuse structure during fuse programming will likely lead to damage in the surrounding dielectric layer. If conductive via <b>122</b> fails, then the resulting damage could be electrically detected by placing vias and lines next to the fuse structure, shown in <figref idref="DRAWINGS">FIG. 5</figref> as conductive via <b>142</b> and conductive line <b>143</b>. Referring to <figref idref="DRAWINGS">FIG. 5</figref>, detection is made by applying a voltage between a negative voltage connection (V−) and positive voltage connection (V+) and then measuring the current between the positive current connection (I+) and a negative current connection (I−). Negative voltage and current connections are located at conductor <b>111</b> and along conductive line <b>133</b>. Positive voltage and current connections are located at conductive via <b>142</b> and conductive line <b>143</b>. If a short circuit is measured, then the damaged region has extended too far and may lead to reliability concerns. The programming conditions would then be adjusted to produce less damage.

0039The fuse structure shown in <figref idref="DRAWINGS">FIG. 2</figref> may be formed using the process shown in <figref idref="DRAWINGS">FIGS. 6A-6I</figref>. First, dielectric layer <b>120</b> is deposited on dielectric material <b>110</b> having conductor <b>111</b> embedded therein. An opening or cavity <b>121</b> for conductive via <b>122</b> and conductive line <b>123</b> is next formed in dielectric layer <b>120</b>. Preferably, cavity <b>121</b> may be a dual damascene cavity to provide openings for conductive via <b>122</b> and conductive line <b>123</b> simultaneously. Liner <b>124</b> is then deposited on at least vertical surfaces of cavity <b>121</b> by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process for example. Preferably, liner <b>124</b> is deposited on the bottom surface of cavity <b>121</b> as well. A Cu seed layer is deposited by PVD in cavity <b>121</b>. Cavity <b>121</b> with liner <b>124</b> is then filled with a conductive material such as Cu using, for example, an electroplating process, to form conductive via <b>122</b> and conductive line <b>123</b>. Via <b>142</b> and line <b>143</b>, as shown in <figref idref="DRAWINGS">FIG. 5</figref>, are also optionally formed by an electroplating process, for example, in dielectric layer <b>120</b>.

0040Next, dielectric layer <b>130</b> is deposited on layer <b>120</b>, an opening or cavity <b>131</b> is formed in dielectric layer <b>130</b>, liner <b>134</b> is deposited on surfaces of cavity <b>131</b>, a Cu seed layer is deposited and cavity <b>131</b> is filled with a conductive material to form conductive via <b>132</b> and conductive line <b>133</b>. Optionally, conductive line <b>133</b> is formed in such a way as to extend in all directions around conductive via <b>132</b>.

0041Dielectric layers <b>120</b> and <b>130</b> can be deposited by a variety of methods. Chemical vapor deposition (CVD) is the preferred method for carbon-doped oxide dielectrics (SiCOH). Spin on processes are the preferred methods for polymer based dielectrics.

0042Cavity <b>121</b> may be formed using any suitable lithographic patterning and etching process. Conductive vias <b>122</b> and <b>132</b> and conductive lines <b>123</b> and <b>133</b> may be formed using a single or dual damascene process. Preferably, a dual damascene process is used.

0043A physical vapor deposition (PVD) process is used to deposit liner materials such as Ta and TaN. Other deposition processes, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), may be used to deposit liner materials as well.

0044To promote a failure in the lower via as opposed to the upper via or line, it is preferred to create poor liner coverage in conductive via <b>122</b> and good liner coverage in conductive via <b>132</b>. Multiple embodiments for creating poor liner coverage are shown in <figref idref="DRAWINGS">FIG. 7</figref>. One embodiment for creating poor liner coverage is to create a higher angle at upper portion <b>125</b> of conductive via <b>122</b>. A further embodiment for creating poor liner coverage is to create a steep bottom sidewall <b>126</b> of conductive via <b>122</b> by creating an angle greater than 87° and a high angle, greater than 87°, at the top sidewall of conductive via <b>122</b>. Another embodiment for creating poor liner coverage is by undercutting sidewalls <b>127</b> and <b>128</b> of conductive via <b>122</b>, preferably such that undercut <b>129</b> is greater than 3 nm.

0045In order to undercut sidewalls <b>127</b> and <b>128</b> of conductive via <b>122</b>, the dielectric layer is reactive ion etched through a hardmask for pattern transfer. This creates a dielectric-hardmask stack where the reactive ion etched conductive via <b>122</b> has a dense hardmask material on top. The dielectric layer is always a less-dense material than the hardmask, which means that it tends to be more deformable and more easily etchable by, for example, reactive ion etch and wet etches. Moreover, it is more easily deformed by, for example, heating, outgassing, and moisture desorption. The result is that the liner and seed deposition is likely to have a hardmask feature on top that has tighter dimensional tolerances for the patterned features than the less-dense dielectric layer that it serves to pattern. An undercut process can be performed using any low-k dielectric; however the effects of the undercut process are more pronounced using an ultra low-k dielectric. Consequently, an undercut is easy to create or engineer, simply on the basis of selection of a wet clean or reactive ion etch that is selective to the ultra low-k dielectric versus the hardmask, or to degas conditions that cause more shrinkage of the ultra low-k dielectric versus the hardmask. An ultra low-k dielectric material has a dielectric constant less than 2.7.

0046The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

0047The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.