Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture

FIELD OF THE INVENTION

0001The invention relates to semiconductor structures and methods of manufacture and, more particularly, to thermal control of thin film resistors using substrate contacts and methods of manufacture.

BACKGROUND

0002Specific structures on silicon-on-insulator (SOI) substrates tend to have problems with heat accumulation from self-heating due to the very low thermal conductivity of the SOI substrate. This presents particular issues with the maximum allowed current density of thermally sensitive structures. The heat accumulation presents particular problems with DC structures such as, for example, some precision resistors (e.g., thin film resistors).

0003Precision resistors are in general use in Si-based microelectronics integrated circuit chips. These resistors are frequently fabricated from polysilicon layers deposited on the chip, but they can also be made from diffused silicon (Si) layers in SOI wafers. These resistors produce heat when current flows through them. In particular, polysilicon and diffused resistors, especially those formed on SOI wafers, heat up rapidly with increasing current density. Although the resistor itself can tolerate relatively high temperatures without suffering damage, wiring on the various metallization levels above and nearby the resistors becomes much more vulnerable to failure by electromigration due to the heating caused by the resistor. Generally, a temperature increase of 5° C. in a metal line can decrease the lifetime of the line by 25 to 30%. The generated heat can also permanently alter the value of the resistance of the resistor by changing the grain size of the polysilicon, by burning out portions (or all) of the film and by redistributing the dopant atoms. Consequently, limiting the current through the resistor protects both the resistor stability and the integrity of the nearby metallization.

0004However, limiting the current through a resistor is at odds with the continued drive toward circuit miniaturization and the trend toward progressively greater current densities for high-performance circuits. The miniaturization of features typically involves reducing the film thickness in which resistors are formed, which tends to increase current density, which causes the resistor to generate more heat.

0005Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

SUMMARY

0006In a first aspect of the invention, a method of forming a semiconductor structure comprises forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.

0007In another aspect of the invention a method of forming a semiconductor structure comprises forming a substrate contact trench through an insulator layer and into a substrate, and forming a core comprising a high thermal conductivity material in the substrate contact trench. The method also comprises forming a capping layer on the core, and forming a resistor on the capping layer and the insulator layer.

0008In yet another aspect of the invention, a semiconductor structure comprises a resistor on an insulator layer over a substrate, and a substrate contact extending through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a liner composed of electrical insulator material and a core composed of a high thermal conductivity material. The liner electrically insulates the resistor from the core.

0009In yet another aspect of the invention, a semiconductor structure comprises a substrate contact extending through an insulator layer and into a substrate. The substrate contact comprises a core composed of a high thermal conductivity material and a capping layer composed of an electrical insulator. The structure also comprises a resistor formed on the capping layer and the insulator layer.

0010In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of a resistor and substrate contact, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the resistor and substrate contact. The method comprises generating a functional representation of the structural elements of the resistor and substrate contact.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

0011The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

0012<figref idref="DRAWINGS">FIGS. 1-14</figref> show processing steps and structures in accordance with aspects of the invention;

0013<figref idref="DRAWINGS">FIG. 15</figref> shows a design diagram in accordance with aspects of the invention;

0014<figref idref="DRAWINGS">FIGS. 16-20</figref> show processing steps and structures in accordance with additional aspects of the invention; and

0015<figref idref="DRAWINGS">FIG. 21</figref> is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.

DETAILED DESCRIPTION

0016The invention relates to semiconductor structures and methods of manufacture and, more particularly, to thermal control of thin film resistors using substrate contacts and methods of manufacture. In accordance with aspects of the invention, a substrate contact is formed through the body of the resistor. In embodiments, the substrate contact is electrically isolated from the resistor and provides a low thermal resistance heat path from the resistor to the substrate. In implementations, the substrate contact comprises a liner composed of an electrical insulator material and a core composed of a high thermal conductivity material. In this manner, implementations of the invention provide a low thermal resistance heat dissipation path from a resistor to a substrate, which enhances the thermal control (e.g., cooling) of the resistor.

0017In accordance with additional aspects of the invention, a metal layer is provided over the resistor and a metal contact is provided between the metal layer and the core of the substrate contact. In this manner, heat that is generated by the resistor and flows upward through the insulator above the resistor is captured by the metal layer and channeled to the substrate through the metal contact and substrate contact.

0018Resistive heating is a physical consequence of electric current passing through the material of a resistor. Polysilicon resistors typically reside on an insulator layer (e.g., SiO₂or similar material) above an Si substrate. Heat generated in the resistor spreads by thermal conduction into the surrounding oxide and from the oxide into the Si substrate. Heat generated during resistive heating may flow directly through the oxide between the resistor and the substrate. The heat may also flow out of the top and the side edges of the resistor. As such, there are top, side, and bottom heat conduction paths from the resistor. Most of the heat generated in a resistor flows into the Si substrate through the underlying shallow trench isolation (STI) and buried oxide (BOX) films. Heat that flows upward is typically dissipated by flowing laterally and then back to the substrate, which constitutes a much more thermally resistive path than simply flowing out beneath the resistor.

0019Implementations of the invention provide a heat dissipation path from the resistor to the substrate by providing a substrate contact through an active area of the resistor and into the substrate. In accordance with aspects of the invention, the substrate contact comprises a high thermal conductivity material having a lower thermal resistance than the STI and/or BOX materials that heat typically flows through when dissipating from a resistor. The substrate contact need not be electrically connected to any other devices in the chip, and may be used primarily as a heat conduction pathway for transferring heat away from the resistor. In embodiments, the substrate contact provides a thermal conduction path from the resistor to the substrate, and thus reduces the resistor temperature significantly. In this manner, a resistor may be cooled more effectively, which advantageously permits the current density in the resistor to be increased.

0020<figref idref="DRAWINGS">FIGS. 1-14</figref> show processing steps and structures in accordance with aspects of the invention. Specifically, <figref idref="DRAWINGS">FIG. 1</figref> shows an exemplary SOI wafer <b>10</b> employed as an intermediate structure in implementations of the invention. The SOI wafer <b>10</b> has a bulk semiconductor substrate <b>15</b>, which is typically a silicon substrate, a buried insulator layer <b>20</b> formed on the substrate <b>15</b>, and a semiconductor layer <b>25</b>, which is typically a silicon layer, formed on the buried insulator layer <b>20</b>. The SOI wafer <b>10</b> may be fabricated using techniques well know to those skilled in the art. For example, the SOI wafer <b>10</b> may be formed by conventional processes including, but not limited to, oxygen implantation (e.g., SIMOX), wafer bonding, etc.

0021The constituent materials of the SOI wafer <b>10</b> may be selected based on the desired end use application of the semiconductor device. For example, the substrate <b>15</b> may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. The buried insulator layer <b>20</b> may be composed of oxide, such as SiO₂, and may be referred to as a buried oxide (BOX) layer <b>20</b>. Moreover, although the SOI wafer is referred to as “silicon on insulator,” the semiconductor layer <b>25</b> is not limited to silicon. Instead, the semiconductor layer <b>25</b> may be comprised of various semiconductor materials, such as, for example, Si, SiGe, SiC, SiGeC, etc.

0022In embodiments, the SOI wafer <b>10</b> has a thickness of about 700 μm, with the BOX layer <b>20</b> having a thickness of about 0.15 μm, and the semiconductor layer <b>25</b> having a thickness of about 0.08 μm. However, the invention is not limited to these dimensions, and the various portions of the SOI wafer may have any desired thicknesses based upon the intended use of the final semiconductor device.

0023As shown in <figref idref="DRAWINGS">FIG. 2</figref>, a shallow trench isolation (STI) structure <b>30</b> is formed in the wafer <b>10</b>, and a resistor <b>35</b> is formed on the STI <b>30</b>. The STI <b>30</b> may be a conventional shallow trench isolation structure formed using conventional semiconductor fabrication processes and materials. For example, the STI <b>30</b> may be formed by arranging a photoresist material on the semiconductor layer <b>25</b>, exposing and developing the photoresist, etching an STI trench in the semiconductor layer <b>25</b> through the patterned photoresist (e.g., using a reactive ion etch (RIE) process), stripping the photoresist, filling the trench with an STI material (e.g., SiO₂), and planarizing the top surface of the structure (e.g., via chemical mechanical polish (CMP)). The STI <b>30</b> locally replaces a portion of the semiconductor layer <b>25</b>.

0024Still referring to <figref idref="DRAWINGS">FIG. 2</figref>, the resistor <b>35</b> may also be formed using conventional semiconductor fabrication processes and materials. For example, the resistor <b>35</b> may comprise electrically conductive doped polysilicon and may be formed by depositing a polysilicon film on the STI <b>30</b> (e.g., using chemical vapor deposition (CVD)), patterning the polysilicon film (e.g., using photolithographic masking and etching), and doping the polysilicon film (e.g., using ion implantation, gas diffusion doping, in-situ doping, etc.).

0025In accordance with aspects of the invention, and as shown in <figref idref="DRAWINGS">FIG. 3</figref>, a substrate contact trench <b>40</b> is formed in the resistor <b>35</b>, the STI <b>30</b>, the BOX layer <b>20</b>, and into the substrate <b>15</b>. In embodiments, the substrate contact trench <b>40</b> is formed using one or more RIE processes. For example, a respective RIE process may be performed for etching each of the resistor <b>35</b>, the STI <b>30</b>, the BOX layer <b>20</b>, and the substrate <b>15</b>, with each respective RIE process being tailored to the material of the layer/feature being etched. Additionally, a single RIE process may be used to etch more than one layer/feature.

0026The substrate contact trench <b>40</b> may have any desired size and shape, and more than one substrate contact trench <b>40</b> may be formed. In accordance with aspects of the invention, the substrate contact trench <b>40</b> may be located anywhere within or overlapping the footprint (e.g., top-down plan view) of the resistor <b>35</b>. In embodiments, the substrate contact trench <b>40</b> creates a hole through the resistor <b>35</b>, but does not bisect the resistor <b>35</b>.

0027As shown in <figref idref="DRAWINGS">FIG. 4</figref>, an insulator film <b>45</b> (e.g., liner) is formed on exposed surfaces of the structure, including a base <b>50</b> and sidewalls <b>55</b> of the substrate contact trench <b>40</b>. In embodiments, the insulator film <b>45</b> is composed of an electrically non-conductive material, such as oxide, nitride, oxynitride, or other dielectric material. The insulator film <b>45</b> may be formed using conventional semiconductor fabrication processes, depending on the material composition of the insulator film <b>45</b>. For example, the insulator film <b>45</b> may be composed of oxide that is thermally grown (e.g., thermal oxidation) on the exposed surfaces of the structure. In another example, the insulator film <b>45</b> may be composed of oxide, nitride, or oxynitride that is deposited using CVD or other suitable conformal deposition process. The insulator film <b>45</b> may have any suitable thickness, as described in greater detail herein.

0028As shown in <figref idref="DRAWINGS">FIG. 5</figref>, and in accordance with aspects of the invention, a portion of the insulator film <b>45</b> is removed from the base <b>50</b> of the substrate contact trench <b>40</b>, while leaving another portion of the insulator film <b>45</b> on the sidewalls <b>55</b> of the substrate contact trench <b>40</b>. In embodiments, a directional RIE process is used to remove the portion of the insulator film <b>45</b> from the base <b>50</b>; however, other suitable removal processes may be used within the scope of the invention. The removal process may also remove the insulator film <b>45</b> from the top of the resistor <b>35</b>, STI <b>30</b>, and semiconductor layer <b>25</b>.

0029As depicted in <figref idref="DRAWINGS">FIG. 6</figref>, a core <b>60</b> is formed in the substrate contact trench <b>40</b> on the insulator film <b>45</b>. In accordance with aspects of the invention, the core <b>60</b> comprises a high thermal conductivity material including, but not limited to, polysilicon, tungsten, copper, aluminum, silver, gold, and combinations thereof. In embodiments, the core <b>60</b> is composed of polysilicon and is formed using a CVD process, although other high thermal conductivity materials may be provided using other formation processes. More specifically, according to aspects of the invention, the core <b>60</b> is composed of any suitable material that has a thermal conductivity that is substantially greater than the thermal conductivity of the material(s) of the BOX layer <b>20</b> and STI <b>30</b> (e.g., SiO₂). Table 1 shows the thermal conductivity of various materials.

0000<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="21pt" align="left" /><colspec colname="1" colwidth="56pt" align="left" /><colspec colname="2" colwidth="140pt" align="center" /><thead><row><entry /><entry namest="offset" nameend="2" rowsep="1">TABLE 1</entry></row><row><entry /><entry namest="offset" nameend="2" align="center" rowsep="1" /></row><row><entry /><entry>Material</entry><entry>Thermal Conductivity (w/m · K)</entry></row><row><entry /><entry namest="offset" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="21pt" align="left" /><colspec colname="1" colwidth="56pt" align="left" /><colspec colname="2" colwidth="140pt" align="char" char="." /><tbody valign="top"><row><entry /><entry>Glass (e.g., SiO₂)</entry><entry>1.1</entry></row><row><entry /><entry>Silicon</entry><entry>149</entry></row><row><entry /><entry>Tungsten</entry><entry>173</entry></row><row><entry /><entry>Aluminum (pure)</entry><entry>237</entry></row><row><entry /><entry>Gold</entry><entry>318</entry></row><row><entry /><entry>Copper</entry><entry>401</entry></row><row><entry /><entry>Silver</entry><entry>429</entry></row><row><entry /><entry namest="offset" nameend="2" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0030As is evident from Table <b>1</b>, polysilicon (e.g., silicon), tungsten, copper, aluminum, silver, and gold each has a thermal conductivity substantially greater than that of SiO₂, and thus may be considered as high thermal conductivity materials. Accordingly, in embodiments, the core <b>60</b> is composed of polysilicon, tungsten, copper, aluminum, silver, gold, or combinations thereof. In accordance with aspects of the invention, the substrate contact trench <b>40</b> that is filled with the insulator film <b>45</b> and the core <b>60</b> constitutes a substrate contact <b>63</b> that provides a heat conduction pathway from the resistor <b>35</b> to the substrate <b>15</b>.

0031The deposition of the core <b>60</b> may result in the formation of excess material on upper surfaces of the structure. The excess material may be removed using a conventional material removal process, such as an endpoint etch or CMP process.

0032As shown in <figref idref="DRAWINGS">FIG. 7</figref>, a first dielectric layer <b>70</b> is formed over the resistor <b>35</b>, the substrate contact <b>63</b>, and portions of the semiconductor layer <b>25</b> and STI <b>30</b>. The first dielectric layer <b>70</b> may be formed using conventional semiconductor fabrication processes and materials. For example, the first dielectric layer <b>70</b> may comprise one or more layers of oxide, nitride, and oxynitride that are formed using, e.g., CVD. In embodiments, the first dielectric layer <b>70</b> comprises a thin oxide film <b>70</b><i>a </i>formed on the resistor <b>35</b> and portions of the semiconductor layer <b>25</b> and STI <b>30</b>, and a nitride layer <b>70</b><i>b </i>deposited on the oxide film <b>70</b><i>a</i>. The oxide film <b>70</b><i>a </i>may have a thickness of about 3 nm, and the nitride layer <b>70</b><i>b </i>may have a thickness of about 20-30 nm, although the invention is not limited to these dimensions and any suitable thicknesses may be employed within the scope of the invention.

0033As shown in <figref idref="DRAWINGS">FIG. 8</figref>, holes <b>75</b> are formed in the first dielectric layer <b>70</b>, and silicide contacts <b>80</b> are formed on the resistor <b>35</b>. The holes <b>75</b> are formed in the first dielectric layer <b>70</b> to define locations for the silicide contacts <b>80</b>. The holes <b>75</b> and silicide contacts <b>80</b> may be formed using conventional semiconductor fabrication processes and materials. For example, the holes <b>75</b> may be formed by photolithographic masking and etching, laser ablation, gas cluster ion beam, etc. The silicide contacts <b>80</b> may be formed by depositing a metal film, such as cobalt, titanium, tungsten, or nickel, on the exposed polysilicon of the resistor <b>35</b> within the holes <b>75</b>, and annealing the structure to create silicide.

0034As shown in <figref idref="DRAWINGS">FIG. 9</figref>, a second dielectric layer <b>85</b> is formed on the exposed surfaces of the structure, and a third dielectric layer <b>90</b> is formed on the second dielectric layer <b>85</b>. The second and third dielectric layers <b>85</b> and <b>90</b> may be composed of any suitable dielectric materials and may be formed using conventional semiconductor fabrication techniques, such as CVD (e.g., a conformal deposition). In embodiments, the second dielectric layer <b>85</b> is composed of nitride, and the third dielectric layer <b>90</b> is composed of silicon dioxide (SiO₂), borophosphosilicate glass (BPSG), or low-k dielectric material; however, the invention is not limited to this configuration and other combinations of materials may be used within the scope of the invention.

0035As shown in <figref idref="DRAWINGS">FIG. 10</figref>, resistor contacts <b>95</b><i>a </i>and thermal contact <b>95</b><i>b </i>are formed in the layers <b>70</b>, <b>85</b>, and <b>90</b>. In accordance with aspects of the invention, the resistor contacts <b>95</b><i>a </i>provide electrical contact to the resistor <b>35</b> by directly contacting the silicide contacts <b>80</b>, and the thermal contact <b>95</b><i>b </i>provides a thermal conduction pathway to the substrate contact <b>63</b>. In embodiments, the resistor contacts <b>95</b><i>a </i>and thermal contact <b>95</b><i>b </i>are formed simultaneously using the same processing steps, e.g., by forming trenches in the dielectric layers <b>70</b>, <b>85</b>, and <b>90</b> and filling the trenches with an electrically conductive material.

0036For example, trenches for the resistor contacts <b>95</b><i>a </i>and thermal contact <b>95</b><i>b </i>may be formed in the dielectric layers <b>70</b>, <b>85</b>, and <b>90</b> by masking the structure and etching unmasked portions of the dielectric layers <b>70</b>, <b>85</b>, and <b>90</b> using one or more conventional etch processes (e.g., RIE). A respective RIE process may be performed for etching each of the dielectric layers <b>70</b>, <b>85</b>, and <b>90</b>, with each respective RIE process being tailored to the material of the layer being etched. Alternatively, a single RIE process may be used to etch more than one layer. The masking defines where the trenches are located, and appropriate masking may be used to form respective trenches over the silicide contacts <b>80</b> (e.g., for the resistor contacts <b>95</b><i>a</i>) and the core <b>60</b> (e.g., for the thermal contact <b>95</b><i>b</i>).

0037The resistor contacts <b>95</b><i>a </i>and thermal contact <b>95</b><i>b</i>, in turn, may be formed by depositing (e.g., using CVD) an electrically conductive material (e.g., tungsten) in the trenches. In embodiments, the resistor contacts <b>95</b><i>a </i>may be in the form of a plurality of vias (e.g., an array of small pillars with a minimum diameter dependent on the technology, for example 0.25 μm in diameter) or in the form of a solid bar.

0038In accordance with aspects of the invention, the use of multiple dielectric layers (e.g., dielectric layers <b>70</b>, <b>85</b>, and <b>90</b>) facilitates the simultaneous creation of the resistor contacts <b>95</b><i>a </i>and thermal contact <b>95</b><i>b</i>. The multiple dielectric layer overlap causes the etch of the contact trenches to self arrest, such that the etch does not etch through the whole nitride stack. Moreover, using nitride in dielectric layers <b>70</b> and <b>85</b> enhances the heat conduction since nitride is generally a better thermal conductor than oxide.

0039As shown in <figref idref="DRAWINGS">FIG. 11</figref>, metal layer <b>100</b> is formed on the third dielectric layer <b>90</b>, and an interlevel dielectric (ILD) <b>105</b> is formed over the entire structure. The metal layer <b>100</b> may be formed in any conventional manner, such as, for example, CVD and patterning (e.g., masking and etching). The metal layer <b>100</b> may be a layer of copper (Cu) or any other desired electrically conductive material. In accordance with aspects of the invention, the metal layer <b>100</b> is patterned to have separate segments <b>100</b><i>a </i>and <b>100</b><i>b</i>. Segments <b>100</b><i>a </i>are connected to the resistor contacts <b>95</b><i>a </i>and provide electrical communication to the resistor <b>35</b>. Segment <b>100</b><i>b </i>is connected to the thermal contact <b>95</b><i>b </i>and is configured to collect heat that dissipates upward from the resistor and channel the collected heat to the substrate <b>15</b> through the thermal contact <b>95</b><i>b </i>and core <b>60</b>. Segment <b>100</b><i>b </i>is electrically insulated from portions <b>100</b><i>a </i>by the ILD <b>105</b>. The ILD <b>105</b> may be formed using conventional semiconductor fabrication techniques, and may be composed of any suitable dielectric material, such as silicon dioxide (SiO₂), tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), hydrogen silsesquioxane (HSQ), etc.

0040In accordance with aspects of the invention, the metal layer segment <b>100</b><i>b</i>, thermal contact <b>95</b><i>b</i>, and substrate contact <b>63</b> are structured and arranged as a heat conduction structure that transfers heat generated by the resistor <b>35</b> to the substrate <b>15</b>. The insulator film <b>45</b> electrically insulates the resistor <b>35</b> from the core <b>60</b>, such that an electrically conductive material may be used as the high thermal conductivity material in the core <b>60</b> without shorting the resistor <b>35</b>. In embodiments, the insulator film <b>45</b> has a thickness that is sufficient to provide electrical insulation between the resistor <b>35</b> and the core <b>60</b>, and that is less than the combined thickness of the STI <b>30</b> and BOX layer <b>20</b>. By being less thick (e.g., thinner) than the STI <b>30</b> and BOX layer <b>20</b>, the insulator film <b>45</b> provides less thermal resistance than the STI <b>30</b> and BOX layer <b>20</b>, such that heat may flow through the insulator film <b>45</b> and core <b>60</b> and into the substrate <b>15</b>. In particular embodiments, the insulator film <b>45</b> has a thickness “t” of about 0.03 μm to about 0.1 μm, although the invention is not limited to this range and any suitable thickness may be used.

0041In implementations, the resistor <b>35</b> and the substrate contact <b>63</b> may be of any desired size and shape. For example, the resistor <b>35</b> may be substantially rectangular with a width of about 10 μm (e.g., perpendicular to the direction of current flow between the silicide contacts <b>80</b>) and a length of about 2 μm (e.g., parallel to the direction of current flow between the silicide contacts <b>80</b>), and the substrate contact <b>63</b> may have a width of about 0.5 μm and a length of about 0.5 μm. However, the invention is not limited to this exemplary configuration, and any suitable size and shape may be used for the resistor <b>35</b> and the substrate contact <b>63</b>. Moreover, the respective sizes and shapes of the resistor <b>35</b> and the substrate contact(s) <b>63</b> may be tailored to achieve a particular electrical resistance and heat transfer for the resistor <b>35</b>.

0042For example, <figref idref="DRAWINGS">FIGS. 12-14</figref> show an implementation comprising two substrate contacts <b>63</b>′ having an elongated shape parallel to the direction of current flow in the resistor <b>35</b>′. More specifically, <figref idref="DRAWINGS">FIG. 12</figref> shows a plan view of the substrate contacts <b>63</b>′ and thermal contacts <b>95</b><i>b</i>′ extending parallel to the direction of current flow between resistor contacts <b>95</b><i>a</i>′. <figref idref="DRAWINGS">FIG. 13</figref> shows a cross section along line XIII-XIII of <figref idref="DRAWINGS">FIG. 12</figref>, and <figref idref="DRAWINGS">FIG. 14</figref> shows a cross section along line XIV-XIV of <figref idref="DRAWINGS">FIG. 12</figref>. As can be seen in <figref idref="DRAWINGS">FIGS. 12-14</figref>, the liners <b>45</b>′ insulate the cores <b>60</b>′ from the resistor <b>35</b>′, and the ILD <b>105</b>′ insulates metal layer segment <b>100</b><i>b</i>′ from segments <b>100</b><i>a</i>′. In accordance with aspects of the invention, the metal layer segment <b>100</b><i>b</i>′ covers substantially the entire resistor <b>35</b>′. In this manner, the metal layer segment <b>100</b><i>b</i>′ contacts both thermal contacts <b>95</b><i>b</i>′ and captures substantially all of the heat that dissipates upward from the resistor, and conducts this heat to the substrate <b>15</b>′ via the thermal contacts <b>95</b><i>b</i>′ and cores <b>60</b>′.

0043<figref idref="DRAWINGS">FIG. 15</figref> shows an exemplary design detail for the structures shown in <figref idref="DRAWINGS">FIGS. 1-14</figref> in accordance with aspects of the invention. As shown in <figref idref="DRAWINGS">FIG. 15</figref>, the minimum spacing between the resistor <b>35</b> and the core <b>60</b> may be about 0.105 μm in both the width and length direction. The minimum spacing between the edges of the core <b>60</b> and the edges of the thermal contact <b>95</b><i>b </i>may be about 0.13 μm in both the width and length directions. The minimum lengthwise spacing between edges of the thermal contact <b>95</b><i>b </i>may be about 0.69 μm, and the minimum widthwise spacing between edges of the thermal contact <b>95</b><i>b </i>may be about 0.23 μm. The minimum widthwise spacing between edges of the core <b>60</b> may be about 0.49 μm. The minimum widthwise spacing between edges of the resistor <b>35</b>, e.g., bounding the substrate contact, may be about 0.70 μm. The minimum spacing between the metal layer segment <b>100</b><i>a </i>and segment <b>100</b><i>b </i>may be about 0.3 μm. The minimal lengthwise spacing between the thermal contact <b>95</b><i>b </i>and the silicide contacts <b>50</b> may be about 0.5 μm. It is understood that these values are merely exemplary, and other spacings may be used within the scope of the invention.

0044<figref idref="DRAWINGS">FIGS. 16-20</figref> show processing steps and structure in accordance with additional aspects of the invention in which like reference characters refer to the same features already described herein. In particular, <figref idref="DRAWINGS">FIG. 16</figref> shows a substrate contact trench <b>150</b> formed in the STI <b>30</b> and BOX layer <b>20</b> and into the substrate <b>15</b>. The substrate contact trench <b>150</b> may be formed using, for example, masking (e.g., photolithography) and etching (e.g., RIE). In embodiments, the substrate contact trench <b>150</b> is formed prior to the resistor.

0045As shown in <figref idref="DRAWINGS">FIG. 17</figref>, the substrate contact trench <b>150</b> is filled with a core <b>155</b> comprising a high thermal conductivity material. The core <b>155</b> may be formed in the same manner (e.g., CVD) and with the same materials (e.g., tungsten, polysilicon, etc.) as core <b>60</b> described with respect to <figref idref="DRAWINGS">FIG. 6</figref>. The top surface of the structure may be planarized using, e.g., CMP or an etch, following the formation of the core <b>155</b>.

0046As shown in <figref idref="DRAWINGS">FIG. 18</figref>, the core <b>155</b> is recessed to form a trench <b>160</b>. The trench <b>160</b> may be formed using any suitable technique, such as a timed etch of the core <b>155</b> material. In embodiments, the trench <b>160</b> has a depth of about 0.03 to 0.1 μm, although the trench <b>160</b> may be formed to any suitable depth.

0047As shown in <figref idref="DRAWINGS">FIG. 19</figref>, an electrically insulating capping layer <b>165</b> is formed in the trench <b>160</b> on the core <b>155</b>. The capping layer <b>165</b> may be formed using conventional semiconductor fabrication processes and materials. For example, the capping layer <b>165</b> may be composed of any desired electrical insulator, such as oxide, nitride, oxynitride, or other dielectric materials. Moreover, the capping layer <b>165</b> may be formed using, for example, thermal oxidation, CVD, etc. After forming the capping layer <b>165</b>, the structure may be planarized, e.g., using CMP.

0048As shown in <figref idref="DRAWINGS">FIG. 20</figref>, a resistor <b>35</b> is formed on the STI <b>30</b> and the capping layer <b>165</b>. Additionally, a first dielectric layer <b>70</b> is formed on the resistor <b>35</b>, silicide contacts <b>80</b> are formed on the resistor <b>35</b>, a second dielectric layer <b>85</b> is formed over the first dielectric layer <b>70</b>, a third dielectric layer <b>90</b> is formed on the second dielectric layer <b>85</b>, resistor contacts <b>95</b><i>a </i>are formed in the dielectric layers, metal layer segments <b>100</b><i>a </i>are formed in contact with the resistor contacts <b>95</b><i>a</i>, and ILD <b>105</b> is formed over the metal layer segments <b>100</b><i>a</i>. The resistor <b>35</b>, dielectric layers <b>70</b>, <b>85</b>, and <b>90</b>, silicide contacts <b>80</b>, resistor contacts <b>95</b><i>a</i>, metal layer segments <b>100</b><i>a</i>, and ILD <b>105</b> may be formed in the same manner as described with respect to <figref idref="DRAWINGS">FIGS. 2-11</figref>.

0049In accordance with aspects of the invention, the capping layer <b>165</b> electrically insulates the resistor <b>35</b> from the core <b>155</b>. In embodiments, the capping layer <b>165</b> has a thickness less than the combined thickness of the STI <b>30</b> and BOX layer <b>20</b>. In this manner, a heat conduction path from the resistor <b>35</b> to the substrate <b>15</b> through the capping layer <b>165</b> and the high thermal conductivity core <b>155</b> has a lower thermal resistance than a heat conduction path from the resistor <b>35</b> to the substrate <b>15</b> through the STI <b>30</b> and BOX layer <b>20</b>.

0050Aspects of the invention have been described with respect to a polysilicon resistor formed on an SOI wafer. The invention is not limited to this particular type of resistor, however, and implementations of the invention may be used with any type of resistor. For example, a substrate contact in accordance with aspects of the invention may be formed through a diffused resistor (e.g., formed directly on the BOX layer of an SOI wafer) or a refractory metal resistor (e.g., formed on an ILD layer). Moreover, the invention is not limited to use with SOI wafers. Instead, aspects of the invention could be used with any type of wafer, including resistors formed in or on a bulk semiconductor material (e.g., silicon) substrate. For example, the resistor used in implementations of the invention may be formed on an insulator layer (e.g., an STI) formed in a bulk silicon substrate.

0051<figref idref="DRAWINGS">FIG. 21</figref> is a flow diagram of a design process used in semiconductor design, manufacture, and/or test. <figref idref="DRAWINGS">FIG. 21</figref> shows a block diagram of an exemplary design flow <b>900</b> used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow <b>900</b> includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown in <figref idref="DRAWINGS">FIGS. 1-20</figref>. The design structures processed and/or generated by design flow <b>900</b> may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).

0052Design flow <b>900</b> may vary depending on the type of representation being designed. For example, a design flow <b>900</b> for building an application specific IC (ASIC) may differ from a design flow <b>900</b> for designing a standard component or from a design flow <b>900</b> for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

0053<figref idref="DRAWINGS">FIG. 21</figref> illustrates multiple such design structures including an input design structure <b>920</b> that is preferably processed by a design process <b>910</b>. Design structure <b>920</b> may be a logical simulation design structure generated and processed by design process <b>910</b> to produce a logically equivalent functional representation of a hardware device. Design structure <b>920</b> may also or alternatively comprise data and/or program instructions that when processed by design process <b>910</b>, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure <b>920</b> may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure <b>920</b> may be accessed and processed by one or more hardware and/or software modules within design process <b>910</b> to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in <figref idref="DRAWINGS">FIGS. 1-20</figref>. As such, design structure <b>920</b> may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

0054Design process <b>910</b> preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in <figref idref="DRAWINGS">FIGS. 1-20</figref> to generate a netlist <b>980</b> which may contain design structures such as design structure <b>920</b>. Netlist <b>980</b> may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist <b>980</b> may be synthesized using an iterative process in which netlist <b>980</b> is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist <b>980</b> may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.

0055Design process <b>910</b> may include hardware and software modules for processing a variety of input data structure types including netlist <b>980</b>. Such data structure types may reside, for example, within library elements <b>630</b> and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications <b>940</b>, characterization data <b>950</b>, verification data <b>960</b>, design rules <b>970</b>, and test data files <b>985</b> which may include input test patterns, output test results, and other testing information. Design process <b>910</b> may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process <b>910</b> without deviating from the scope and spirit of the invention. Design process <b>910</b> may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

0056Design process <b>910</b> employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure <b>920</b> together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure <b>990</b>.

0057Design structure <b>990</b> resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure <b>920</b>, design structure <b>990</b> preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in <figref idref="DRAWINGS">FIGS. 1-20</figref>. In one embodiment, design structure <b>990</b> may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in <figref idref="DRAWINGS">FIGS. 1-20</figref>.

0058Design structure <b>990</b> may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure <b>990</b> may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in <figref idref="DRAWINGS">FIGS. 1-20</figref>. Design structure <b>990</b> may then proceed to a stage <b>995</b> where, for example, design structure <b>990</b>: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

0059The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

0060The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

0061The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims, if applicable, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principals of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Accordingly, while the invention has been described in terms of embodiments, those of skill in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.